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phy: rockchip: naneng-combphy: Add SoC prefix to register definitions
All supported variants of naneng-combphy follow a register layout similar to the RK3568 variant with some exceptions of SoC-specific registers. Add RK3568 prefix for the common set of registers and the corresponding SoC prefix for SoC-specific registers, making usage of definitions clear and preparing for future COMBPHY variants with a different register layout. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250728102947.38984-6-ziyao@disroot.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Yao Zi
Vinod Koul
parent
b6c02cba32
commit
b3bbc6afcf
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@ -21,78 +21,80 @@
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#define REF_CLOCK_100MHz (100 * HZ_PER_MHZ)
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/* COMBO PHY REG */
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#define PHYREG6 0x14
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#define PHYREG6_PLL_DIV_MASK GENMASK(7, 6)
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#define PHYREG6_PLL_DIV_SHIFT 6
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#define PHYREG6_PLL_DIV_2 1
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#define RK3568_PHYREG6 0x14
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#define RK3568_PHYREG6_PLL_DIV_MASK GENMASK(7, 6)
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#define RK3568_PHYREG6_PLL_DIV_SHIFT 6
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#define RK3568_PHYREG6_PLL_DIV_2 1
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#define PHYREG7 0x18
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#define PHYREG7_TX_RTERM_MASK GENMASK(7, 4)
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#define PHYREG7_TX_RTERM_SHIFT 4
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#define PHYREG7_TX_RTERM_50OHM 8
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#define PHYREG7_RX_RTERM_MASK GENMASK(3, 0)
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#define PHYREG7_RX_RTERM_SHIFT 0
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#define PHYREG7_RX_RTERM_44OHM 15
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#define RK3568_PHYREG7 0x18
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#define RK3568_PHYREG7_TX_RTERM_MASK GENMASK(7, 4)
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#define RK3568_PHYREG7_TX_RTERM_SHIFT 4
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#define RK3568_PHYREG7_TX_RTERM_50OHM 8
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#define RK3568_PHYREG7_RX_RTERM_MASK GENMASK(3, 0)
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#define RK3568_PHYREG7_RX_RTERM_SHIFT 0
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#define RK3568_PHYREG7_RX_RTERM_44OHM 15
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#define PHYREG8 0x1C
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#define PHYREG8_SSC_EN BIT(4)
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#define RK3568_PHYREG8 0x1C
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#define RK3568_PHYREG8_SSC_EN BIT(4)
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#define PHYREG10 0x24
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#define PHYREG10_SSC_PCM_MASK GENMASK(3, 0)
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#define PHYREG10_SSC_PCM_3500PPM 7
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#define RK3568_PHYREG11 0x28
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#define RK3568_PHYREG11_SU_TRIM_0_7 0xF0
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#define PHYREG11 0x28
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#define PHYREG11_SU_TRIM_0_7 0xF0
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#define RK3568_PHYREG12 0x2C
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#define RK3568_PHYREG12_PLL_LPF_ADJ_VALUE 4
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#define PHYREG12 0x2C
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#define PHYREG12_PLL_LPF_ADJ_VALUE 4
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#define RK3568_PHYREG13 0x30
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#define RK3568_PHYREG13_RESISTER_MASK GENMASK(5, 4)
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#define RK3568_PHYREG13_RESISTER_SHIFT 0x4
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#define RK3568_PHYREG13_RESISTER_HIGH_Z 3
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#define RK3568_PHYREG13_CKRCV_AMP0 BIT(7)
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#define PHYREG13 0x30
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#define PHYREG13_RESISTER_MASK GENMASK(5, 4)
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#define PHYREG13_RESISTER_SHIFT 0x4
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#define PHYREG13_RESISTER_HIGH_Z 3
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#define PHYREG13_CKRCV_AMP0 BIT(7)
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#define RK3568_PHYREG14 0x34
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#define RK3568_PHYREG14_CKRCV_AMP1 BIT(0)
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#define PHYREG14 0x34
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#define PHYREG14_CKRCV_AMP1 BIT(0)
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#define RK3568_PHYREG15 0x38
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#define RK3568_PHYREG15_CTLE_EN BIT(0)
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#define RK3568_PHYREG15_SSC_CNT_MASK GENMASK(7, 6)
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#define RK3568_PHYREG15_SSC_CNT_SHIFT 6
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#define RK3568_PHYREG15_SSC_CNT_VALUE 1
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#define PHYREG15 0x38
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#define PHYREG15_CTLE_EN BIT(0)
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#define PHYREG15_SSC_CNT_MASK GENMASK(7, 6)
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#define PHYREG15_SSC_CNT_SHIFT 6
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#define PHYREG15_SSC_CNT_VALUE 1
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#define RK3568_PHYREG16 0x3C
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#define RK3568_PHYREG16_SSC_CNT_VALUE 0x5f
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#define PHYREG16 0x3C
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#define PHYREG16_SSC_CNT_VALUE 0x5f
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#define RK3568_PHYREG18 0x44
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#define RK3568_PHYREG18_PLL_LOOP 0x32
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#define PHYREG17 0x40
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#define RK3568_PHYREG32 0x7C
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#define RK3568_PHYREG32_SSC_MASK GENMASK(7, 4)
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#define RK3568_PHYREG32_SSC_DIR_MASK GENMASK(5, 4)
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#define RK3568_PHYREG32_SSC_DIR_SHIFT 4
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#define RK3568_PHYREG32_SSC_UPWARD 0
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#define RK3568_PHYREG32_SSC_DOWNWARD 1
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#define RK3568_PHYREG32_SSC_OFFSET_MASK GENMASK(7, 6)
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#define RK3568_PHYREG32_SSC_OFFSET_SHIFT 6
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#define RK3568_PHYREG32_SSC_OFFSET_500PPM 1
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#define PHYREG18 0x44
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#define PHYREG18_PLL_LOOP 0x32
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#define RK3568_PHYREG33 0x80
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#define RK3568_PHYREG33_PLL_KVCO_MASK GENMASK(4, 2)
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#define RK3568_PHYREG33_PLL_KVCO_SHIFT 2
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#define RK3568_PHYREG33_PLL_KVCO_VALUE 2
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#define RK3576_PHYREG33_PLL_KVCO_VALUE 4
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#define PHYREG21 0x50
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#define PHYREG21_RX_SQUELCH_VAL 0x0D
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/* RK3588 COMBO PHY registers */
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#define RK3588_PHYREG27 0x6C
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#define RK3588_PHYREG27_RX_TRIM 0x4C
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#define PHYREG27 0x6C
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#define PHYREG27_RX_TRIM_RK3588 0x4C
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/* RK3576 COMBO PHY registers */
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#define RK3576_PHYREG10 0x24
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#define RK3576_PHYREG10_SSC_PCM_MASK GENMASK(3, 0)
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#define RK3576_PHYREG10_SSC_PCM_3500PPM 7
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#define PHYREG30 0x74
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#define RK3576_PHYREG17 0x40
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#define PHYREG32 0x7C
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#define PHYREG32_SSC_MASK GENMASK(7, 4)
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#define PHYREG32_SSC_DIR_MASK GENMASK(5, 4)
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#define PHYREG32_SSC_DIR_SHIFT 4
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#define PHYREG32_SSC_UPWARD 0
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#define PHYREG32_SSC_DOWNWARD 1
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#define PHYREG32_SSC_OFFSET_MASK GENMASK(7, 6)
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#define PHYREG32_SSC_OFFSET_SHIFT 6
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#define PHYREG32_SSC_OFFSET_500PPM 1
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#define RK3576_PHYREG21 0x50
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#define RK3576_PHYREG21_RX_SQUELCH_VAL 0x0D
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#define PHYREG33 0x80
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#define PHYREG33_PLL_KVCO_MASK GENMASK(4, 2)
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#define PHYREG33_PLL_KVCO_SHIFT 2
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#define PHYREG33_PLL_KVCO_VALUE 2
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#define PHYREG33_PLL_KVCO_VALUE_RK3576 4
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#define RK3576_PHYREG30 0x74
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struct rockchip_combphy_priv;
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@ -407,9 +409,8 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
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switch (priv->type) {
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case PHY_TYPE_PCIE:
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/* Set SSC downward spread spectrum */
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rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
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PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
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PHYREG32);
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val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
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rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
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rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
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rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
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@ -418,29 +419,30 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
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break;
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case PHY_TYPE_USB3:
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/* Set SSC downward spread spectrum */
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rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
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PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
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PHYREG32);
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val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
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rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
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RK3568_PHYREG32);
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/* Enable adaptive CTLE for USB3.0 Rx */
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rockchip_combphy_updatel(priv, PHYREG15_CTLE_EN,
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PHYREG15_CTLE_EN, PHYREG15);
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rockchip_combphy_updatel(priv, RK3568_PHYREG15_CTLE_EN,
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RK3568_PHYREG15_CTLE_EN, RK3568_PHYREG15);
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/* Set PLL KVCO fine tuning signals */
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rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, BIT(3), PHYREG33);
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rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
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BIT(3), RK3568_PHYREG33);
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/* Set PLL LPF R1 to su_trim[10:7]=1001 */
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writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
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writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
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/* Set PLL input clock divider 1/2 */
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val = FIELD_PREP(PHYREG6_PLL_DIV_MASK, PHYREG6_PLL_DIV_2);
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rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, val, PHYREG6);
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val = FIELD_PREP(RK3568_PHYREG6_PLL_DIV_MASK, RK3568_PHYREG6_PLL_DIV_2);
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rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, val, RK3568_PHYREG6);
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/* Set PLL loop divider */
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writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
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writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
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/* Set PLL KVCO to min and set PLL charge pump current to max */
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writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
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writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
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rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
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rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
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@ -458,11 +460,12 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
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case REF_CLOCK_24MHz:
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if (priv->type == PHY_TYPE_USB3) {
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/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
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val = FIELD_PREP(PHYREG15_SSC_CNT_MASK, PHYREG15_SSC_CNT_VALUE);
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rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
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val, PHYREG15);
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val = FIELD_PREP(RK3568_PHYREG15_SSC_CNT_MASK,
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RK3568_PHYREG15_SSC_CNT_VALUE);
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rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
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val, RK3568_PHYREG15);
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writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
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writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
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}
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break;
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case REF_CLOCK_25MHz:
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@ -472,19 +475,20 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
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rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
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if (priv->type == PHY_TYPE_PCIE) {
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/* PLL KVCO tuning fine */
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val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE);
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rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
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val, PHYREG33);
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val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
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RK3568_PHYREG33_PLL_KVCO_VALUE);
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rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
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val, RK3568_PHYREG33);
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/* Enable controlling random jitter, aka RMJ */
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writel(0x4, priv->mmio + PHYREG12);
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writel(0x4, priv->mmio + RK3568_PHYREG12);
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val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
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rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
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val, PHYREG6);
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val = RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT;
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rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
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val, RK3568_PHYREG6);
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writel(0x32, priv->mmio + PHYREG18);
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writel(0xf0, priv->mmio + PHYREG11);
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writel(0x32, priv->mmio + RK3568_PHYREG18);
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writel(0xf0, priv->mmio + RK3568_PHYREG11);
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}
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break;
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default:
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@ -495,20 +499,21 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
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if (priv->ext_refclk) {
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rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
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if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
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val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
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val |= PHYREG13_CKRCV_AMP0;
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rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
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val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT;
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val |= RK3568_PHYREG13_CKRCV_AMP0;
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rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val,
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RK3568_PHYREG13);
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val = readl(priv->mmio + PHYREG14);
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val |= PHYREG14_CKRCV_AMP1;
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writel(val, priv->mmio + PHYREG14);
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val = readl(priv->mmio + RK3568_PHYREG14);
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val |= RK3568_PHYREG14_CKRCV_AMP1;
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writel(val, priv->mmio + RK3568_PHYREG14);
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}
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}
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if (priv->enable_ssc) {
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val = readl(priv->mmio + PHYREG8);
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val |= PHYREG8_SSC_EN;
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writel(val, priv->mmio + PHYREG8);
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val = readl(priv->mmio + RK3568_PHYREG8);
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val |= RK3568_PHYREG8_SSC_EN;
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writel(val, priv->mmio + RK3568_PHYREG8);
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}
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return 0;
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@ -555,9 +560,9 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
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switch (priv->type) {
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case PHY_TYPE_PCIE:
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/* Set SSC downward spread spectrum. */
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rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
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PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
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PHYREG32);
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val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
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rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
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rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
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rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
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@ -567,30 +572,28 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
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case PHY_TYPE_USB3:
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/* Set SSC downward spread spectrum. */
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rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
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PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
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PHYREG32);
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val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT,
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rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
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/* Enable adaptive CTLE for USB3.0 Rx. */
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val = readl(priv->mmio + PHYREG15);
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val |= PHYREG15_CTLE_EN;
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writel(val, priv->mmio + PHYREG15);
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val = readl(priv->mmio + RK3568_PHYREG15);
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val |= RK3568_PHYREG15_CTLE_EN;
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writel(val, priv->mmio + RK3568_PHYREG15);
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/* Set PLL KVCO fine tuning signals. */
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rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
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PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
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PHYREG33);
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val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT;
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rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, val, RK3568_PHYREG33);
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/* Enable controlling random jitter. */
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writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
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writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
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/* Set PLL input clock divider 1/2. */
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rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
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PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
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PHYREG6);
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rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
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RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT,
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RK3568_PHYREG6);
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writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
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writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
|
||||
writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
|
||||
writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
|
||||
|
||||
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
|
||||
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
|
||||
|
|
@ -608,16 +611,16 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|||
|
||||
case PHY_TYPE_SATA:
|
||||
/* Enable adaptive CTLE for SATA Rx. */
|
||||
val = readl(priv->mmio + PHYREG15);
|
||||
val |= PHYREG15_CTLE_EN;
|
||||
writel(val, priv->mmio + PHYREG15);
|
||||
val = readl(priv->mmio + RK3568_PHYREG15);
|
||||
val |= RK3568_PHYREG15_CTLE_EN;
|
||||
writel(val, priv->mmio + RK3568_PHYREG15);
|
||||
/*
|
||||
* Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
|
||||
* 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
|
||||
*/
|
||||
val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
|
||||
val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
|
||||
writel(val, priv->mmio + PHYREG7);
|
||||
val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT;
|
||||
val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT;
|
||||
writel(val, priv->mmio + RK3568_PHYREG7);
|
||||
|
||||
rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
|
||||
rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
|
||||
|
|
@ -652,11 +655,11 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|||
case REF_CLOCK_24MHz:
|
||||
if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
|
||||
/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
|
||||
val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
|
||||
rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
|
||||
val, PHYREG15);
|
||||
val = RK3568_PHYREG15_SSC_CNT_VALUE << RK3568_PHYREG15_SSC_CNT_SHIFT;
|
||||
rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
|
||||
val, RK3568_PHYREG15);
|
||||
|
||||
writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
|
||||
writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
@ -668,24 +671,26 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|||
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
|
||||
if (priv->type == PHY_TYPE_PCIE) {
|
||||
/* PLL KVCO fine tuning. */
|
||||
val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT;
|
||||
rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
|
||||
val, PHYREG33);
|
||||
val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT;
|
||||
rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
|
||||
val, RK3568_PHYREG33);
|
||||
|
||||
/* Enable controlling random jitter. */
|
||||
writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
|
||||
writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
|
||||
|
||||
val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
|
||||
rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
|
||||
val, PHYREG6);
|
||||
val = RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT;
|
||||
rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
|
||||
val, RK3568_PHYREG6);
|
||||
|
||||
writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
|
||||
writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
|
||||
writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
|
||||
writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
|
||||
} else if (priv->type == PHY_TYPE_SATA) {
|
||||
/* downward spread spectrum +500ppm */
|
||||
val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
|
||||
val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
|
||||
rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
|
||||
val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
|
||||
val |= RK3568_PHYREG32_SSC_OFFSET_500PPM <<
|
||||
RK3568_PHYREG32_SSC_OFFSET_SHIFT;
|
||||
rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
|
||||
RK3568_PHYREG32);
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
@ -697,20 +702,21 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|||
if (priv->ext_refclk) {
|
||||
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
|
||||
if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
|
||||
val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
|
||||
val |= PHYREG13_CKRCV_AMP0;
|
||||
rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
|
||||
val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT;
|
||||
val |= RK3568_PHYREG13_CKRCV_AMP0;
|
||||
rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val,
|
||||
RK3568_PHYREG13);
|
||||
|
||||
val = readl(priv->mmio + PHYREG14);
|
||||
val |= PHYREG14_CKRCV_AMP1;
|
||||
writel(val, priv->mmio + PHYREG14);
|
||||
val = readl(priv->mmio + RK3568_PHYREG14);
|
||||
val |= RK3568_PHYREG14_CKRCV_AMP1;
|
||||
writel(val, priv->mmio + RK3568_PHYREG14);
|
||||
}
|
||||
}
|
||||
|
||||
if (priv->enable_ssc) {
|
||||
val = readl(priv->mmio + PHYREG8);
|
||||
val |= PHYREG8_SSC_EN;
|
||||
writel(val, priv->mmio + PHYREG8);
|
||||
val = readl(priv->mmio + RK3568_PHYREG8);
|
||||
val |= RK3568_PHYREG8_SSC_EN;
|
||||
writel(val, priv->mmio + RK3568_PHYREG8);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -771,8 +777,8 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|||
switch (priv->type) {
|
||||
case PHY_TYPE_PCIE:
|
||||
/* Set SSC downward spread spectrum */
|
||||
val = FIELD_PREP(PHYREG32_SSC_MASK, PHYREG32_SSC_DOWNWARD);
|
||||
rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
|
||||
val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD);
|
||||
rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
|
||||
|
||||
rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
|
||||
rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
|
||||
|
|
@ -782,32 +788,33 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|||
|
||||
case PHY_TYPE_USB3:
|
||||
/* Set SSC downward spread spectrum */
|
||||
val = FIELD_PREP(PHYREG32_SSC_MASK, PHYREG32_SSC_DOWNWARD);
|
||||
rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
|
||||
val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD);
|
||||
rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
|
||||
|
||||
/* Enable adaptive CTLE for USB3.0 Rx */
|
||||
val = readl(priv->mmio + PHYREG15);
|
||||
val |= PHYREG15_CTLE_EN;
|
||||
writel(val, priv->mmio + PHYREG15);
|
||||
val = readl(priv->mmio + RK3568_PHYREG15);
|
||||
val |= RK3568_PHYREG15_CTLE_EN;
|
||||
writel(val, priv->mmio + RK3568_PHYREG15);
|
||||
|
||||
/* Set PLL KVCO fine tuning signals */
|
||||
rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, BIT(3), PHYREG33);
|
||||
rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, BIT(3),
|
||||
RK3568_PHYREG33);
|
||||
|
||||
/* Set PLL LPF R1 to su_trim[10:7]=1001 */
|
||||
writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
|
||||
writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
|
||||
|
||||
/* Set PLL input clock divider 1/2 */
|
||||
val = FIELD_PREP(PHYREG6_PLL_DIV_MASK, PHYREG6_PLL_DIV_2);
|
||||
rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, val, PHYREG6);
|
||||
val = FIELD_PREP(RK3568_PHYREG6_PLL_DIV_MASK, RK3568_PHYREG6_PLL_DIV_2);
|
||||
rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, val, RK3568_PHYREG6);
|
||||
|
||||
/* Set PLL loop divider */
|
||||
writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
|
||||
writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
|
||||
|
||||
/* Set PLL KVCO to min and set PLL charge pump current to max */
|
||||
writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
|
||||
writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
|
||||
|
||||
/* Set Rx squelch input filler bandwidth */
|
||||
writel(PHYREG21_RX_SQUELCH_VAL, priv->mmio + PHYREG21);
|
||||
writel(RK3576_PHYREG21_RX_SQUELCH_VAL, priv->mmio + RK3576_PHYREG21);
|
||||
|
||||
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
|
||||
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
|
||||
|
|
@ -816,14 +823,14 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|||
|
||||
case PHY_TYPE_SATA:
|
||||
/* Enable adaptive CTLE for SATA Rx */
|
||||
val = readl(priv->mmio + PHYREG15);
|
||||
val |= PHYREG15_CTLE_EN;
|
||||
writel(val, priv->mmio + PHYREG15);
|
||||
val = readl(priv->mmio + RK3568_PHYREG15);
|
||||
val |= RK3568_PHYREG15_CTLE_EN;
|
||||
writel(val, priv->mmio + RK3568_PHYREG15);
|
||||
|
||||
/* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */
|
||||
val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
|
||||
val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
|
||||
writel(val, priv->mmio + PHYREG7);
|
||||
val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT;
|
||||
val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT;
|
||||
writel(val, priv->mmio + RK3568_PHYREG7);
|
||||
|
||||
rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
|
||||
rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
|
||||
|
|
@ -845,19 +852,21 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|||
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
|
||||
if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
|
||||
/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
|
||||
val = FIELD_PREP(PHYREG15_SSC_CNT_MASK, PHYREG15_SSC_CNT_VALUE);
|
||||
rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
|
||||
val, PHYREG15);
|
||||
val = FIELD_PREP(RK3568_PHYREG15_SSC_CNT_MASK,
|
||||
RK3568_PHYREG15_SSC_CNT_VALUE);
|
||||
rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
|
||||
val, RK3568_PHYREG15);
|
||||
|
||||
writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
|
||||
writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
|
||||
} else if (priv->type == PHY_TYPE_PCIE) {
|
||||
/* PLL KVCO tuning fine */
|
||||
val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576);
|
||||
rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
|
||||
val, PHYREG33);
|
||||
val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
|
||||
RK3576_PHYREG33_PLL_KVCO_VALUE);
|
||||
rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
|
||||
val, RK3568_PHYREG33);
|
||||
|
||||
/* Set up rx_pck invert and rx msb to disable */
|
||||
writel(0x00, priv->mmio + PHYREG27);
|
||||
writel(0x00, priv->mmio + RK3588_PHYREG27);
|
||||
|
||||
/*
|
||||
* Set up SU adjust signal:
|
||||
|
|
@ -865,11 +874,11 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|||
* su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b011
|
||||
* su_trim[31:24], CKDRV adjust
|
||||
*/
|
||||
writel(0x90, priv->mmio + PHYREG11);
|
||||
writel(0x02, priv->mmio + PHYREG12);
|
||||
writel(0x57, priv->mmio + PHYREG14);
|
||||
writel(0x90, priv->mmio + RK3568_PHYREG11);
|
||||
writel(0x02, priv->mmio + RK3568_PHYREG12);
|
||||
writel(0x57, priv->mmio + RK3568_PHYREG14);
|
||||
|
||||
writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
|
||||
writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
@ -881,15 +890,16 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|||
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
|
||||
if (priv->type == PHY_TYPE_PCIE) {
|
||||
/* gate_tx_pck_sel length select work for L1SS */
|
||||
writel(0xc0, priv->mmio + PHYREG30);
|
||||
writel(0xc0, priv->mmio + RK3576_PHYREG30);
|
||||
|
||||
/* PLL KVCO tuning fine */
|
||||
val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576);
|
||||
rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
|
||||
val, PHYREG33);
|
||||
val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
|
||||
RK3576_PHYREG33_PLL_KVCO_VALUE);
|
||||
rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
|
||||
val, RK3568_PHYREG33);
|
||||
|
||||
/* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
|
||||
writel(0x4c, priv->mmio + PHYREG27);
|
||||
writel(0x4c, priv->mmio + RK3588_PHYREG27);
|
||||
|
||||
/*
|
||||
* Set up SU adjust signal:
|
||||
|
|
@ -899,20 +909,23 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|||
* su_trim[23:16], CKRCV adjust
|
||||
* su_trim[31:24], CKDRV adjust
|
||||
*/
|
||||
writel(0x90, priv->mmio + PHYREG11);
|
||||
writel(0x43, priv->mmio + PHYREG12);
|
||||
writel(0x88, priv->mmio + PHYREG13);
|
||||
writel(0x56, priv->mmio + PHYREG14);
|
||||
writel(0x90, priv->mmio + RK3568_PHYREG11);
|
||||
writel(0x43, priv->mmio + RK3568_PHYREG12);
|
||||
writel(0x88, priv->mmio + RK3568_PHYREG13);
|
||||
writel(0x56, priv->mmio + RK3568_PHYREG14);
|
||||
} else if (priv->type == PHY_TYPE_SATA) {
|
||||
/* downward spread spectrum +500ppm */
|
||||
val = FIELD_PREP(PHYREG32_SSC_DIR_MASK, PHYREG32_SSC_DOWNWARD);
|
||||
val |= FIELD_PREP(PHYREG32_SSC_OFFSET_MASK, PHYREG32_SSC_OFFSET_500PPM);
|
||||
rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
|
||||
val = FIELD_PREP(RK3568_PHYREG32_SSC_DIR_MASK,
|
||||
RK3568_PHYREG32_SSC_DOWNWARD);
|
||||
val |= FIELD_PREP(RK3568_PHYREG32_SSC_OFFSET_MASK,
|
||||
RK3568_PHYREG32_SSC_OFFSET_500PPM);
|
||||
rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
|
||||
RK3568_PHYREG32);
|
||||
|
||||
/* ssc ppm adjust to 3500ppm */
|
||||
rockchip_combphy_updatel(priv, PHYREG10_SSC_PCM_MASK,
|
||||
PHYREG10_SSC_PCM_3500PPM,
|
||||
PHYREG10);
|
||||
rockchip_combphy_updatel(priv, RK3576_PHYREG10_SSC_PCM_MASK,
|
||||
RK3576_PHYREG10_SSC_PCM_3500PPM,
|
||||
RK3576_PHYREG10);
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
@ -924,12 +937,13 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|||
if (priv->ext_refclk) {
|
||||
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
|
||||
if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
|
||||
val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576);
|
||||
rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
|
||||
val, PHYREG33);
|
||||
val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
|
||||
RK3576_PHYREG33_PLL_KVCO_VALUE);
|
||||
rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
|
||||
val, RK3568_PHYREG33);
|
||||
|
||||
/* Set up rx_trim: PLL LPF C1 85pf R1 2.5kohm */
|
||||
writel(0x0c, priv->mmio + PHYREG27);
|
||||
writel(0x0c, priv->mmio + RK3588_PHYREG27);
|
||||
|
||||
/*
|
||||
* Set up SU adjust signal:
|
||||
|
|
@ -939,25 +953,25 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|||
* su_trim[23:16], CKRCV adjust
|
||||
* su_trim[31:24], CKDRV adjust
|
||||
*/
|
||||
writel(0x90, priv->mmio + PHYREG11);
|
||||
writel(0x43, priv->mmio + PHYREG12);
|
||||
writel(0x88, priv->mmio + PHYREG13);
|
||||
writel(0x56, priv->mmio + PHYREG14);
|
||||
writel(0x90, priv->mmio + RK3568_PHYREG11);
|
||||
writel(0x43, priv->mmio + RK3568_PHYREG12);
|
||||
writel(0x88, priv->mmio + RK3568_PHYREG13);
|
||||
writel(0x56, priv->mmio + RK3568_PHYREG14);
|
||||
}
|
||||
}
|
||||
|
||||
if (priv->enable_ssc) {
|
||||
val = readl(priv->mmio + PHYREG8);
|
||||
val |= PHYREG8_SSC_EN;
|
||||
writel(val, priv->mmio + PHYREG8);
|
||||
val = readl(priv->mmio + RK3568_PHYREG8);
|
||||
val |= RK3568_PHYREG8_SSC_EN;
|
||||
writel(val, priv->mmio + RK3568_PHYREG8);
|
||||
|
||||
if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) {
|
||||
/* Set PLL loop divider */
|
||||
writel(0x00, priv->mmio + PHYREG17);
|
||||
writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
|
||||
writel(0x00, priv->mmio + RK3576_PHYREG17);
|
||||
writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
|
||||
|
||||
/* Set up rx_pck invert and rx msb to disable */
|
||||
writel(0x00, priv->mmio + PHYREG27);
|
||||
writel(0x00, priv->mmio + RK3588_PHYREG27);
|
||||
|
||||
/*
|
||||
* Set up SU adjust signal:
|
||||
|
|
@ -966,16 +980,17 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|||
* su_trim[23:16], CKRCV adjust
|
||||
* su_trim[31:24], CKDRV adjust
|
||||
*/
|
||||
writel(0x90, priv->mmio + PHYREG11);
|
||||
writel(0x02, priv->mmio + PHYREG12);
|
||||
writel(0x08, priv->mmio + PHYREG13);
|
||||
writel(0x57, priv->mmio + PHYREG14);
|
||||
writel(0x40, priv->mmio + PHYREG15);
|
||||
writel(0x90, priv->mmio + RK3568_PHYREG11);
|
||||
writel(0x02, priv->mmio + RK3568_PHYREG12);
|
||||
writel(0x08, priv->mmio + RK3568_PHYREG13);
|
||||
writel(0x57, priv->mmio + RK3568_PHYREG14);
|
||||
writel(0x40, priv->mmio + RK3568_PHYREG15);
|
||||
|
||||
writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
|
||||
writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
|
||||
|
||||
val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576);
|
||||
writel(val, priv->mmio + PHYREG33);
|
||||
val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
|
||||
RK3576_PHYREG33_PLL_KVCO_VALUE);
|
||||
writel(val, priv->mmio + RK3568_PHYREG33);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1045,30 +1060,28 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|||
break;
|
||||
case PHY_TYPE_USB3:
|
||||
/* Set SSC downward spread spectrum */
|
||||
rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
|
||||
PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
|
||||
PHYREG32);
|
||||
val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
|
||||
rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
|
||||
|
||||
/* Enable adaptive CTLE for USB3.0 Rx. */
|
||||
val = readl(priv->mmio + PHYREG15);
|
||||
val |= PHYREG15_CTLE_EN;
|
||||
writel(val, priv->mmio + PHYREG15);
|
||||
val = readl(priv->mmio + RK3568_PHYREG15);
|
||||
val |= RK3568_PHYREG15_CTLE_EN;
|
||||
writel(val, priv->mmio + RK3568_PHYREG15);
|
||||
|
||||
/* Set PLL KVCO fine tuning signals. */
|
||||
rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
|
||||
PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
|
||||
PHYREG33);
|
||||
val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT,
|
||||
rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, val, RK3568_PHYREG33);
|
||||
|
||||
/* Enable controlling random jitter. */
|
||||
writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
|
||||
writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
|
||||
|
||||
/* Set PLL input clock divider 1/2. */
|
||||
rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
|
||||
PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
|
||||
PHYREG6);
|
||||
rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
|
||||
RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT,
|
||||
RK3568_PHYREG6);
|
||||
|
||||
writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
|
||||
writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
|
||||
writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
|
||||
writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
|
||||
|
||||
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
|
||||
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
|
||||
|
|
@ -1076,16 +1089,16 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|||
break;
|
||||
case PHY_TYPE_SATA:
|
||||
/* Enable adaptive CTLE for SATA Rx. */
|
||||
val = readl(priv->mmio + PHYREG15);
|
||||
val |= PHYREG15_CTLE_EN;
|
||||
writel(val, priv->mmio + PHYREG15);
|
||||
val = readl(priv->mmio + RK3568_PHYREG15);
|
||||
val |= RK3568_PHYREG15_CTLE_EN;
|
||||
writel(val, priv->mmio + RK3568_PHYREG15);
|
||||
/*
|
||||
* Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
|
||||
* 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
|
||||
*/
|
||||
val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
|
||||
val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
|
||||
writel(val, priv->mmio + PHYREG7);
|
||||
val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT;
|
||||
val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT;
|
||||
writel(val, priv->mmio + RK3568_PHYREG7);
|
||||
|
||||
rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
|
||||
rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
|
||||
|
|
@ -1107,11 +1120,11 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|||
case REF_CLOCK_24MHz:
|
||||
if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
|
||||
/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
|
||||
val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
|
||||
rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
|
||||
val, PHYREG15);
|
||||
val = RK3568_PHYREG15_SSC_CNT_VALUE << RK3568_PHYREG15_SSC_CNT_SHIFT;
|
||||
rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
|
||||
val, RK3568_PHYREG15);
|
||||
|
||||
writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
|
||||
writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
@ -1122,23 +1135,25 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|||
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
|
||||
if (priv->type == PHY_TYPE_PCIE) {
|
||||
/* PLL KVCO fine tuning. */
|
||||
val = 4 << PHYREG33_PLL_KVCO_SHIFT;
|
||||
rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
|
||||
val, PHYREG33);
|
||||
val = 4 << RK3568_PHYREG33_PLL_KVCO_SHIFT;
|
||||
rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
|
||||
val, RK3568_PHYREG33);
|
||||
|
||||
/* Enable controlling random jitter. */
|
||||
writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
|
||||
writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
|
||||
|
||||
/* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
|
||||
writel(PHYREG27_RX_TRIM_RK3588, priv->mmio + PHYREG27);
|
||||
writel(RK3588_PHYREG27_RX_TRIM, priv->mmio + RK3588_PHYREG27);
|
||||
|
||||
/* Set up su_trim: */
|
||||
writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
|
||||
writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
|
||||
} else if (priv->type == PHY_TYPE_SATA) {
|
||||
/* downward spread spectrum +500ppm */
|
||||
val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
|
||||
val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
|
||||
rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
|
||||
val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
|
||||
val |= RK3568_PHYREG32_SSC_OFFSET_500PPM <<
|
||||
RK3568_PHYREG32_SSC_OFFSET_SHIFT;
|
||||
rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
|
||||
RK3568_PHYREG32);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
|
|
@ -1149,20 +1164,21 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|||
if (priv->ext_refclk) {
|
||||
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
|
||||
if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
|
||||
val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
|
||||
val |= PHYREG13_CKRCV_AMP0;
|
||||
rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
|
||||
val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT;
|
||||
val |= RK3568_PHYREG13_CKRCV_AMP0;
|
||||
rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val,
|
||||
RK3568_PHYREG13);
|
||||
|
||||
val = readl(priv->mmio + PHYREG14);
|
||||
val |= PHYREG14_CKRCV_AMP1;
|
||||
writel(val, priv->mmio + PHYREG14);
|
||||
val = readl(priv->mmio + RK3568_PHYREG14);
|
||||
val |= RK3568_PHYREG14_CKRCV_AMP1;
|
||||
writel(val, priv->mmio + RK3568_PHYREG14);
|
||||
}
|
||||
}
|
||||
|
||||
if (priv->enable_ssc) {
|
||||
val = readl(priv->mmio + PHYREG8);
|
||||
val |= PHYREG8_SSC_EN;
|
||||
writel(val, priv->mmio + PHYREG8);
|
||||
val = readl(priv->mmio + RK3568_PHYREG8);
|
||||
val |= RK3568_PHYREG8_SSC_EN;
|
||||
writel(val, priv->mmio + RK3568_PHYREG8);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user