From 55a43c346d24434e46ef7fcc09a9df8179c346e4 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sun, 16 Feb 2025 16:27:42 +0100 Subject: [PATCH 01/52] arm64: dts: rockchip: change rng reset id back to its constant value With the binding header now providing the SCMI_SRST_H_TRNG_NS constant, switch back to it from the temporary numeric value. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 1e18ad93ba0e..1401d9fecfc4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1970,7 +1970,7 @@ rng@fe378000 { reg = <0x0 0xfe378000 0x0 0x200>; interrupts = ; clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; - resets = <&scmi_reset 48>; + resets = <&scmi_reset SCMI_SRST_H_TRNG_NS>; }; i2s0_8ch: i2s@fe470000 { From 530f2bebc0918efe6deac1e2c92ce4a13e0c12e1 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Wed, 5 Mar 2025 21:16:26 +0800 Subject: [PATCH 02/52] arm64: dts: rockchip: Enable ufshc on rk3576 evb1 board RK3576 evb1 board supports UFS, so enable it. Signed-off-by: Shawn Lin Link: https://lore.kernel.org/r/1741180586-140422-1-git-send-email-shawn.lin@rock-chips.com [the core device node went into the driver tree, hence this being later] Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts index e368691fd28e..08c188445931 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -747,6 +747,10 @@ &uart0 { status = "okay"; }; +&ufshc { + status = "okay"; +}; + &usbdp_phy { rockchip,dp-lane-mux = <2 3>; status = "okay"; From fc1f5f5bcac7df327a20f4bfbd4872e17d38601d Mon Sep 17 00:00:00 2001 From: Marcin Juszkiewicz Date: Tue, 25 Mar 2025 20:51:46 +0100 Subject: [PATCH 03/52] arm64: dts: rockchip: enable HDMI1 on FriendlyElec NanoPC-T6 Time to get second video output working. Signed-off-by: Marcin Juszkiewicz Link: https://lore.kernel.org/r/20250325-nanopc-t6-hdmi-v1-1-299a2ed45878@redhat.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi index bbe500cc924b..8542d9ebb6c0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -52,6 +52,17 @@ hdmi0_con_in: endpoint { }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; @@ -360,10 +371,31 @@ hdmi0_out_con: endpoint { }; }; + +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + &hdptxphy0 { status = "okay"; }; +&hdptxphy1 { + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; @@ -1126,3 +1158,10 @@ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = ; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; From c0898e6881f964ca831c407c7019cd7f307d4368 Mon Sep 17 00:00:00 2001 From: Marcin Juszkiewicz Date: Tue, 25 Mar 2025 20:51:47 +0100 Subject: [PATCH 04/52] arm64: dts: rockchip: enable HDMI sound on FriendlyElec NanoPC-T6 We have both video outputs showing pixels, time to play some noise. Signed-off-by: Marcin Juszkiewicz Link: https://lore.kernel.org/r/20250325-nanopc-t6-hdmi-v1-2-299a2ed45878@redhat.com Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi index 8542d9ebb6c0..cecfb788bf9e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -371,6 +371,9 @@ hdmi0_out_con: endpoint { }; }; +&hdmi0_sound { + status = "okay"; +}; &hdmi1 { status = "okay"; @@ -388,6 +391,10 @@ hdmi1_out_con: endpoint { }; }; +&hdmi1_sound { + status = "okay"; +}; + &hdptxphy0 { status = "okay"; }; @@ -563,6 +570,14 @@ i2s0_8ch_p0_0: endpoint { }; }; +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + &pcie2x1l0 { reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc_3v3_pcie20>; From 831263a4164e189c47e3a9ea189cb4b5bc078b1e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 18 Mar 2025 22:08:45 +0100 Subject: [PATCH 05/52] arm64: dts: rockchip: Correct gmac phy address on QNAP TS433 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Motorcomm Phy can be talked to on mdio broadcast address 0, but the actuall address is 3. Adapt the reg property and node name accordingly. Signed-off-by: Uwe Kleine-König Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/6b8ef7e37e646f4cd399ceb2f46017644d76da9d.1742331667.git.ukleinek@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts index 7bd32d230ad2..70e88769e21c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts @@ -481,9 +481,10 @@ eeprom@56 { }; &mdio0 { - rgmii_phy0: ethernet-phy@0 { + rgmii_phy0: ethernet-phy@3 { + /* Motorcomm YT8521 phy */ compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; + reg = <0x3>; }; }; From d01e09a9f7cd4fb5a947e3dc718242b51b581615 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 18 Mar 2025 22:08:46 +0100 Subject: [PATCH 06/52] arm64: dts: rockchip: Add gmac phy reset GPIO to QNAP TS433 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While looking through the vendor U-Boot code Heiko spotted that a SoC GPIO is connected to the ethernet phy's reset pin. Add the respective reset-gpios property with pinmuxing for the GPIO to the phy node. Signed-off-by: Uwe Kleine-König Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/49f66206fccc714a8745b9ac35247615ad5cc369.1742331667.git.ukleinek@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts index 70e88769e21c..411f8ac7994b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts @@ -485,6 +485,10 @@ rgmii_phy0: ethernet-phy@3 { /* Motorcomm YT8521 phy */ compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x3>; + pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <10000>; + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; }; }; @@ -557,6 +561,12 @@ &pcie3x2 { }; &pinctrl { + gmac0 { + eth_phy0_reset_pin: eth-phy0-reset-pin { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + keys { copy_button_pin: copy-button-pin { rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; From b6490faab67c4436abeddb5c9e1fb0e8791d58ad Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sat, 21 Dec 2024 18:49:07 +0800 Subject: [PATCH 07/52] arm64: dts: rockchip: aliase sdhci as mmc0 for rk3566 box demo Follow most others rk356x based boards, and u-boot only use mmc0/1 as mmc boot targets, so aliase sdhci as mmc0. Signed-off-by: Andy Yan [demo-board only used internally by Rockchip, so changing the alias order does not affect public users] Link: https://lore.kernel.org/r/20241221104920.4193034-1-andyshrk@163.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts b/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts index 7d4680933823..decc6deeef4e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts @@ -19,9 +19,9 @@ / { aliases { ethernet0 = &gmac1; - mmc0 = &sdmmc0; - mmc1 = &sdmmc1; - mmc2 = &sdhci; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; }; chosen: chosen { From 392275203af1b384fd12df2cef6fb6ee8b3f2b68 Mon Sep 17 00:00:00 2001 From: Jianfeng Liu Date: Tue, 18 Mar 2025 00:32:21 +0800 Subject: [PATCH 08/52] arm64: dts: rockchip: Enable HDMI ports on ArmSoM W3 Enable the two HDMI ports on ArmSoM W3. And audio output of these two ports are also enabled. Signed-off-by: Jianfeng Liu Link: https://lore.kernel.org/r/20250317163240.3083908-1-liujianfeng1994@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-armsom-w3.dts | 101 ++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts index 779cd1b1798c..6ad2759ddcca 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts @@ -4,6 +4,7 @@ #include #include +#include #include "rk3588-armsom-lm7.dtsi" / { @@ -32,6 +33,28 @@ analog-sound { pinctrl-0 = <&hp_detect>; }; + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -138,6 +161,54 @@ &combphy2_psu { status = "okay"; }; +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + &i2c6 { status = "okay"; @@ -192,6 +263,14 @@ i2s0_8ch_p0_0: endpoint { }; }; +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + &package_thermal { polling-delay = <1000>; @@ -406,3 +485,25 @@ &usb_host1_xhci { &usb_host2_xhci { status = "okay"; }; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = ; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; From f46705afd1aafd843e28e981447c92469e846673 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 17 Mar 2025 13:07:26 +0100 Subject: [PATCH 09/52] arm64: dts: rockchip: Enable HDMI audio output for RK3588 Jaguar HDMI audio is available on the RK3588 Jaguar HDMI TX port, so let's enable it. Signed-off-by: Quentin Schulz Link: https://lore.kernel.org/r/20250317-tsd-rk3588-hdmi-audio-v1-1-0b8ceb9597a6@cherry.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts index 9fceea6c1398..ebe77cdd24e8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -303,6 +303,10 @@ hdmi0_out_con: endpoint { }; }; +&hdmi0_sound { + status = "okay"; +}; + &hdptxphy0 { status = "okay"; }; @@ -512,6 +516,10 @@ regulator-state-mem { }; }; +&i2s5_8ch { + status = "okay"; +}; + &mdio0 { rgmii_phy: ethernet-phy@6 { /* KSZ9031 or KSZ9131 */ From 200b3fa574c9377ff0b4e69a6ca4668939bf0cad Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 17 Mar 2025 13:07:27 +0100 Subject: [PATCH 10/52] arm64: dts: rockchip: Enable HDMI audio output for RK3588 Tiger Haikou HDMI audio is available on the RK3588 Tiger Haikou HDMI TX port, so let's enable it. Signed-off-by: Quentin Schulz Link: https://lore.kernel.org/r/20250317-tsd-rk3588-hdmi-audio-v1-2-0b8ceb9597a6@cherry.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts index a3d8ff647839..caa43d1abf17 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts @@ -189,6 +189,10 @@ hdmi0_out_con: endpoint { }; }; +&hdmi0_sound { + status = "okay"; +}; + &hdptxphy0 { status = "okay"; }; @@ -228,6 +232,10 @@ &i2s3_2ch { status = "okay"; }; +&i2s5_8ch { + status = "okay"; +}; + &pcie30phy { status = "okay"; }; From cdba8e71599a1a1cf9ca6e9573c243c9a21f899c Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Tue, 8 Apr 2025 10:31:15 +0800 Subject: [PATCH 11/52] arm64: dts: rockchip: Rename vcc3v3_pcie0 to vcc3v3_pcie1 for rk3576-evb1-v10 It's for pcie1, correct the name. Signed-off-by: Shawn Lin Link: https://lore.kernel.org/r/1744079475-211962-1-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts index 08c188445931..ac397ac00a9e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -128,7 +128,7 @@ vcc3v3_lcd_n: regulator-vcc3v3-lcd0-n { vin-supply = <&vcc_3v3_s0>; }; - vcc3v3_pcie0: regulator-vcc3v3-pcie0 { + vcc3v3_pcie1: regulator-vcc3v3-pcie1 { compatible = "regulator-fixed"; regulator-name = "vcc3v3_pcie1"; regulator-min-microvolt = <3300000>; From a37d21a9b45e47ed6bc1f94e738096c07db78a07 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Tue, 1 Apr 2025 18:00:18 +0800 Subject: [PATCH 12/52] arm64: dts: rockchip: Add missing uart3 interrupt for RK3528 The interrupt of uart3 node on rk3528 is missing, fix it. Fixes: 7983e6c379a9 ("arm64: dts: rockchip: Add base DT for rk3528 SoC") Reviewed-by: Yao Zi Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20250401100020.944658-2-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index 26c3559d6a6d..7f1ffd6003f5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -404,9 +404,10 @@ uart2: serial@ffa00000 { uart3: serial@ffa08000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; + reg = <0x0 0xffa08000 0x0 0x100>; clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; - reg = <0x0 0xffa08000 0x0 0x100>; + interrupts = ; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; From 762b1f6503340b4729bc8a5fa6a5780712012cd8 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Tue, 1 Apr 2025 18:00:19 +0800 Subject: [PATCH 13/52] arm64: dts: rockchip: Add DMA controller for RK3528 Add DMA controller dt node for RK3528 SoC. Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20250401100020.944658-3-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index 7f1ffd6003f5..9c60bb414638 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -493,6 +493,24 @@ sdhci: mmc@ffbf0000 { status = "disabled"; }; + dmac: dma-controller@ffd60000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xffd60000 0x0 0x4000>; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + interrupts = , + , + , + , + , + , + , + , + ; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3528-pinctrl"; rockchip,grf = <&ioc_grf>; From ab6fcb58aedf7df1d146b47d5fedd844a7c346e2 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Tue, 1 Apr 2025 18:00:20 +0800 Subject: [PATCH 14/52] arm64: dts: rockchip: Add UART DMA support for RK3528 The UART ports on RK3528 have DMA capability, describe it. Flow control is optional, so dma-names are not added. Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20250401100020.944658-4-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index 9c60bb414638..826f9be0be19 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -375,6 +375,7 @@ uart0: serial@ff9f0000 { clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; interrupts = ; + dmas = <&dmac 8>, <&dmac 9>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -386,6 +387,7 @@ uart1: serial@ff9f8000 { clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; interrupts = ; + dmas = <&dmac 10>, <&dmac 11>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -397,6 +399,7 @@ uart2: serial@ffa00000 { clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; interrupts = ; + dmas = <&dmac 12>, <&dmac 13>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -408,6 +411,7 @@ uart3: serial@ffa08000 { clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; interrupts = ; + dmas = <&dmac 14>, <&dmac 15>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -419,6 +423,7 @@ uart4: serial@ffa10000 { clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; clock-names = "baudclk", "apb_pclk"; interrupts = ; + dmas = <&dmac 16>, <&dmac 17>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -430,6 +435,7 @@ uart5: serial@ffa18000 { clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; clock-names = "baudclk", "apb_pclk"; interrupts = ; + dmas = <&dmac 18>, <&dmac 19>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -441,6 +447,7 @@ uart6: serial@ffa20000 { clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; clock-names = "baudclk", "apb_pclk"; interrupts = ; + dmas = <&dmac 20>, <&dmac 21>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -452,6 +459,7 @@ uart7: serial@ffa28000 { clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; clock-names = "baudclk", "apb_pclk"; interrupts = ; + dmas = <&dmac 22>, <&dmac 23>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; From 8ecd096d018be8a6bd3bd930f3a41a85db66a67d Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Tue, 1 Apr 2025 17:00:09 +0800 Subject: [PATCH 15/52] arm64: dts: rockchip: Move SHMEM memory to reserved memory on rk3588 0x0 to 0xf0000000 are SDRAM memory areas where 0x10f000 is located. So move the SHMEM memory of arm_scmi to the reserved memory node. Fixes: c9211fa2602b ("arm64: dts: rockchip: Add base DT for rk3588 SoC") Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20250401090009.733771-2-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 1401d9fecfc4..4e3c28d99459 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -439,16 +439,15 @@ xin32k: clock-2 { #clock-cells = <0>; }; - pmu_sram: sram@10f000 { - compatible = "mmio-sram"; - reg = <0x0 0x0010f000 0x0 0x100>; - ranges = <0 0x0 0x0010f000 0x100>; - #address-cells = <1>; - #size-cells = <1>; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; - scmi_shmem: sram@0 { + scmi_shmem: shmem@10f000 { compatible = "arm,scmi-shmem"; - reg = <0x0 0x100>; + reg = <0x0 0x0010f000 0x0 0x100>; + no-map; }; }; From dc79d3d5e7c7b2c177b4a4ca84d20d271fb68da0 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Mon, 10 Mar 2025 18:41:13 +0800 Subject: [PATCH 16/52] arm64: dts: rockchip: Add eDP0 node for RK3588 Add support for the eDP0 output on RK3588 SoC. Signed-off-by: Damon Ding Link: https://lore.kernel.org/r/20250310104114.2608063-13-damon.ding@rock-chips.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 4e3c28d99459..064235253dab 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1453,6 +1453,34 @@ hdmi0_out: port@1 { }; }; + edp0: edp@fdec0000 { + compatible = "rockchip,rk3588-edp"; + reg = <0x0 0xfdec0000 0x0 0x1000>; + clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>; + clock-names = "dp", "pclk"; + interrupts = ; + phys = <&hdptxphy0>; + phy-names = "dp"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>; + reset-names = "dp", "apb"; + rockchip,grf = <&vo1_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + edp0_in: port@0 { + reg = <0>; + }; + + edp0_out: port@1 { + reg = <1>; + }; + }; + }; + qos_gpu_m0: qos@fdf35000 { compatible = "rockchip,rk3588-qos", "syscon"; reg = <0x0 0xfdf35000 0x0 0x20>; From 53862b991e79d8816d5ff54b5954d6a0fe1dcd4c Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Mon, 10 Mar 2025 18:41:14 +0800 Subject: [PATCH 17/52] arm64: dts: rockchip: Enable eDP0 display on RK3588S EVB1 board Add the necessary DT changes to enable eDP0 on RK3588S EVB1 board: - Set pinctrl of pwm12 for backlight - Enable edp0/hdptxphy0/vp2 - Assign the parent of DCLK_VOP2_SRC to PLL_V0PLL - Add aux-bus/panel nodes For RK3588, the PLL_V0PLL is specifically designed for the VOP2. This means the clock rate of PLL_V0PLL can be adjusted according to the dclk rate of relevant VP. It is typically assigned as the dclk source of a specific VP when the clock of relevant display mode is unusual, such as the eDP panel 'lg,lp079qx1-sp0v' paired with RK3588S EVB1, which has a clock rate of 202.02MHz. Additionally, the 'force-hpd' is set for edp0 because the HPD pin on the panel side is not connected to the eDP HPD pin on the SoC side according to the RK3588S EVB1 hardware design. Signed-off-by: Damon Ding Link: https://lore.kernel.org/r/20250310104114.2608063-14-damon.ding@rock-chips.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588s-evb1-v10.dts | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts index 9f4aca9c2e3f..0df3e80f2dd9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "rk3588s.dtsi" @@ -238,6 +239,42 @@ &combphy2_psu { status = "okay"; }; +&edp0 { + force-hpd; + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd_edp>; + no-hpd; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + }; +}; + +&edp0_in { + edp0_in_vp2: endpoint { + remote-endpoint = <&vp2_out_edp0>; + }; +}; + +&edp0_out { + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; +}; + +&hdptxphy0 { + status = "okay"; +}; + &i2c3 { status = "okay"; @@ -403,6 +440,7 @@ usbc0_int: usbc0-int { }; &pwm12 { + pinctrl-0 = <&pwm12m1_pins>; status = "okay"; }; @@ -1172,3 +1210,20 @@ usbdp_phy0_dp_altmode_mux: endpoint@1 { }; }; }; + +&vop_mmu { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP2_SRC>; + assigned-clock-parents = <&cru PLL_V0PLL>; + status = "okay"; +}; + +&vp2 { + vp2_out_edp0: endpoint@ROCKCHIP_VOP2_EP_EDP0 { + reg = ; + remote-endpoint = <&edp0_in_vp2>; + }; +}; From 99685162462c2c70f9e2fbe06481a84a5d0220ca Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sat, 19 Apr 2025 20:13:16 +0800 Subject: [PATCH 18/52] arm64: dts: rockchip: Rename hdmi-con to hdmi0-con for Cool Pi CM5 EVB There are two hdmi connector on Cool Pi CM5 EVB, the current supported is hdmi0, assign corresponding index to it. It will be convenient for us to add support for another one. Signed-off-by: Andy Yan Link: https://lore.kernel.org/r/20250419121326.388298-1-andyshrk@163.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts index 9eda69722665..56ff58c67f97 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts @@ -23,12 +23,12 @@ backlight: backlight { pwms = <&pwm2 0 25000 0>; }; - hdmi-con { + hdmi0-con { compatible = "hdmi-connector"; type = "a"; port { - hdmi_con_in: endpoint { + hdmi0_con_in: endpoint { remote-endpoint = <&hdmi0_out_con>; }; }; @@ -125,7 +125,7 @@ hdmi0_in_vp0: endpoint { &hdmi0_out { hdmi0_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; + remote-endpoint = <&hdmi0_con_in>; }; }; From 85e3fd37204a79e0cd3105176081439ddefbd3b2 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sat, 19 Apr 2025 20:13:17 +0800 Subject: [PATCH 19/52] arm64: dts: rockchip: Enable HDMI1 on Cool Pi CM5 EVB Enable the second HDMI output port on Cool Pi CM5 EVB Signed-off-by: Andy Yan Link: https://lore.kernel.org/r/20250419121326.388298-2-andyshrk@163.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3588-coolpi-cm5-evb.dts | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts index 56ff58c67f97..54c279399f9a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts @@ -34,6 +34,17 @@ hdmi0_con_in: endpoint { }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + leds: leds { compatible = "gpio-leds"; @@ -129,10 +140,32 @@ hdmi0_out_con: endpoint { }; }; +&hdmi1 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>; + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + &hdptxphy0 { status = "okay"; }; +&hdptxphy1 { + status = "okay"; +}; + /* M.2 E-Key */ &pcie2x1l1 { reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; @@ -261,3 +294,10 @@ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = ; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; From abfe411af85aa6ecde580b1f75b9c8145b635fa7 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sat, 19 Apr 2025 20:13:18 +0800 Subject: [PATCH 20/52] arm64: dts: rockchip: Enable HDMI audio outputs for Cool Pi CM5 EVB Enable audio outputs for two HDMI ports on Cool Pi CM5 EVB Signed-off-by: Andy Yan Link: https://lore.kernel.org/r/20250419121326.388298-3-andyshrk@163.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts index 54c279399f9a..3d5c8b753208 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts @@ -128,6 +128,10 @@ &hdmi0 { status = "okay"; }; +&hdmi0_sound { + status = "okay"; +}; + &hdmi0_in { hdmi0_in_vp0: endpoint { remote-endpoint = <&vp0_out_hdmi0>; @@ -158,6 +162,10 @@ hdmi1_out_con: endpoint { }; }; +&hdmi1_sound { + status = "okay"; +}; + &hdptxphy0 { status = "okay"; }; @@ -166,6 +174,14 @@ &hdptxphy1 { status = "okay"; }; +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + /* M.2 E-Key */ &pcie2x1l1 { reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; From d4b9fc2af45d2b91b1654c4aaa1edcb4dd8f4918 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Mon, 14 Apr 2025 22:51:10 +0800 Subject: [PATCH 21/52] arm64: dts: rockchip: Add rk3576 pcie nodes rk3576 has two pcie controllers, both are pcie2x1 work with naneng-combphy. Signed-off-by: Kever Yang Tested-by: Shawn Lin Reviewed-by: Nicolas Frattaroli Tested-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20250414145110.11275-3-kever.yang@rock-chips.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 108 +++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index ebb5fc8bb8b1..a6bfef82d50b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1240,6 +1240,114 @@ qos_npu_m1ro: qos@27f22100 { reg = <0x0 0x27f22100 0x0 0x20>; }; + pcie0: pcie@2a200000 { + compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; + reg = <0x0 0x22000000 0x0 0x00400000>, + <0x0 0x2a200000 0x0 0x00010000>, + <0x0 0x20000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x0 0xf>; + clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>, + <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>, + <&cru CLK_PCIE0_AUX>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux"; + device_type = "pci"; + interrupts = , + , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; + linux,pci-domain = <0>; + max-link-speed = <2>; + num-ib-windows = <8>; + num-viewport = <8>; + num-ob-windows = <2>; + num-lanes = <1>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3576_PD_PHP>; + ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000 + 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000 + 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie0_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pcie1: pcie@2a210000 { + compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; + reg = <0x0 0x22400000 0x0 0x00400000>, + <0x0 0x2a210000 0x0 0x00010000>, + <0x0 0x21000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x20 0x2f>; + clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>, + <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>, + <&cru CLK_PCIE1_AUX>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux"; + device_type = "pci"; + interrupts = , + , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + linux,pci-domain = <0>; + max-link-speed = <2>; + num-ib-windows = <8>; + num-viewport = <8>; + num-ob-windows = <2>; + num-lanes = <1>; + phys = <&combphy1_psu PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3576_PD_SUBPHP>; + ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000 + 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000 + 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>; + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + gmac0: ethernet@2a220000 { compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; reg = <0x0 0x2a220000 0x0 0x10000>; From 2e177b85541d1a5c28a4d64dabec8bdce0461a79 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 26 Feb 2025 15:09:40 +0100 Subject: [PATCH 22/52] arm64: dts: rockchip: add mipi dcphy nodes to rk3588 Add the two MIPI-DC-phy nodes to the RK3588, that will be used by the DSI2 controllers and hopefully in some future also for camera input. Signed-off-by: Heiko Stuebner Reviewed-by: Sebastian Reichel Tested-by: Sebastian Reichel # RK3588 EVB1 Link: https://lore.kernel.org/r/20250226140942.3825223-2-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 064235253dab..944721f314b1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -589,6 +589,16 @@ sys_grf: syscon@fd58c000 { reg = <0x0 0xfd58c000 0x0 0x1000>; }; + mipidcphy0_grf: syscon@fd5e8000 { + compatible = "rockchip,rk3588-dcphy-grf", "syscon"; + reg = <0x0 0xfd5e8000 0x0 0x4000>; + }; + + mipidcphy1_grf: syscon@fd5ec000 { + compatible = "rockchip,rk3588-dcphy-grf", "syscon"; + reg = <0x0 0xfd5ec000 0x0 0x4000>; + }; + vop_grf: syscon@fd5a4000 { compatible = "rockchip,rk3588-vop-grf", "syscon"; reg = <0x0 0xfd5a4000 0x0 0x2000>; @@ -2962,6 +2972,38 @@ usbdp_phy0: phy@fed80000 { status = "disabled"; }; + mipidcphy0: phy@feda0000 { + compatible = "rockchip,rk3588-mipi-dcphy"; + reg = <0x0 0xfeda0000 0x0 0x10000>; + rockchip,grf = <&mipidcphy0_grf>; + clocks = <&cru PCLK_MIPI_DCPHY0>, + <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; + clock-names = "pclk", "ref"; + resets = <&cru SRST_M_MIPI_DCPHY0>, + <&cru SRST_P_MIPI_DCPHY0>, + <&cru SRST_P_MIPI_DCPHY0_GRF>, + <&cru SRST_S_MIPI_DCPHY0>; + reset-names = "m_phy", "apb", "grf", "s_phy"; + #phy-cells = <1>; + status = "disabled"; + }; + + mipidcphy1: phy@fedb0000 { + compatible = "rockchip,rk3588-mipi-dcphy"; + reg = <0x0 0xfedb0000 0x0 0x10000>; + rockchip,grf = <&mipidcphy1_grf>; + clocks = <&cru PCLK_MIPI_DCPHY1>, + <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; + clock-names = "pclk", "ref"; + resets = <&cru SRST_M_MIPI_DCPHY1>, + <&cru SRST_P_MIPI_DCPHY1>, + <&cru SRST_P_MIPI_DCPHY1_GRF>, + <&cru SRST_S_MIPI_DCPHY1>; + reset-names = "m_phy", "apb", "grf", "s_phy"; + #phy-cells = <1>; + status = "disabled"; + }; + combphy0_ps: phy@fee00000 { compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee00000 0x0 0x100>; From 0d0947766d877b63729dbef502e75827bf4ebca9 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 26 Feb 2025 15:09:41 +0100 Subject: [PATCH 23/52] arm64: dts: rockchip: add dsi controller nodes on rk3588 The RK3588 comes with two DSI2 controllers based on a new Synopsis IP. Add the necessary nodes for them. Signed-off-by: Heiko Stuebner Reviewed-by: Sebastian Reichel Tested-by: Sebastian Reichel # RK3588 EVB1 Link: https://lore.kernel.org/r/20250226140942.3825223-3-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 944721f314b1..548677de9a53 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -1421,6 +1422,62 @@ i2s9_8ch: i2s@fddfc000 { status = "disabled"; }; + dsi0: dsi@fde20000 { + compatible = "rockchip,rk3588-mipi-dsi2"; + reg = <0x0 0xfde20000 0x0 0x10000>; + interrupts = ; + clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>; + clock-names = "pclk", "sys"; + resets = <&cru SRST_P_DSIHOST0>; + reset-names = "apb"; + power-domains = <&power RK3588_PD_VOP>; + phys = <&mipidcphy0 PHY_TYPE_DPHY>; + phy-names = "dcphy"; + rockchip,grf = <&vop_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi0_in: port@0 { + reg = <0>; + }; + + dsi0_out: port@1 { + reg = <1>; + }; + }; + }; + + dsi1: dsi@fde30000 { + compatible = "rockchip,rk3588-mipi-dsi2"; + reg = <0x0 0xfde30000 0x0 0x10000>; + interrupts = ; + clocks = <&cru PCLK_DSIHOST1>, <&cru CLK_DSIHOST1>; + clock-names = "pclk", "sys"; + resets = <&cru SRST_P_DSIHOST1>; + reset-names = "apb"; + power-domains = <&power RK3588_PD_VOP>; + phys = <&mipidcphy1 PHY_TYPE_DPHY>; + phy-names = "dcphy"; + rockchip,grf = <&vop_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi1_in: port@0 { + reg = <0>; + }; + + dsi1_out: port@1 { + reg = <1>; + }; + }; + }; + hdmi0: hdmi@fde80000 { compatible = "rockchip,rk3588-dw-hdmi-qp"; reg = <0x0 0xfde80000 0x0 0x20000>; From 777055e02f739b5df943366323f58eeb68d90e67 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 26 Feb 2025 15:09:42 +0100 Subject: [PATCH 24/52] arm64: dts: rockchip: add overlay for tiger-haikou video-demo adapter This adds support for the video-demo-adapter DEVKIT ADDON CAM-TS-A01 (https://embedded.cherry.de/product/development-kit/) for the Haikou devkit with Tiger RK3588 SoM. The Video Demo adapter is an adapter connected to the fake PCIe slot labeled "Video Connector" on the Haikou devkit. It's main feature is a Leadtek DSI-display with touchscreen and a camera (that is not supported yet). To drive these components a number of additional regulators are grouped on the adapter as well as a PCA9670 gpio-expander to provide the needed additional gpio-lines. Signed-off-by: Heiko Stuebner Reviewed-by: Dragan Simic # Makefile Tested-by: Quentin Schulz Link: https://lore.kernel.org/r/20250226140942.3825223-4-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 5 + .../rk3588-tiger-haikou-video-demo.dtso | 153 ++++++++++++++++++ 2 files changed, 158 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou-video-demo.dtso diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 3e8771ef69ba..61158c75f332 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -165,6 +165,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou-video-demo.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-coolpi-4b.dtb @@ -233,3 +234,7 @@ rk3588-rock-5b-pcie-ep-dtbs := rk3588-rock-5b.dtb \ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtb rk3588-rock-5b-pcie-srns-dtbs := rk3588-rock-5b.dtb \ rk3588-rock-5b-pcie-srns.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou-haikou-video-demo.dtb +rk3588-tiger-haikou-haikou-video-demo-dtbs := rk3588-tiger-haikou.dtb \ + rk3588-tiger-haikou-video-demo.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou-video-demo.dtso b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou-video-demo.dtso new file mode 100644 index 000000000000..b8636fcb4f39 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou-video-demo.dtso @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Cherry Embedded Solutions GmbH + * + * DEVKIT ADDON CAM-TS-A01 + * https://embedded.cherry.de/product/development-kit/ + * + * DT-overlay for the camera / DSI demo appliance for Haikou boards. + * In the flavour for use with a Tiger system-on-module. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&dc_12v>; + pwms = <&pwm0 0 25000 0>; + }; + + vcc1v8_video: regulator-vcc1v8-video { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8-video"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc2v8_video: regulator-vcc2v8-video { + compatible = "regulator-fixed"; + regulator-name = "vcc2v8-video"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc3v3_baseboard>; + }; + + video-adapter-leds { + compatible = "gpio-leds"; + + video-adapter-led { + color = ; + gpios = <&pca9670 7 GPIO_ACTIVE_HIGH>; + label = "video-adapter-led"; + linux,default-trigger = "none"; + }; + }; +}; + +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "leadtek,ltk050h3148w"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc1v8_video>; + reset-gpios = <&pca9670 0 GPIO_ACTIVE_LOW>; + vci-supply = <&vcc2v8_video>; + + port { + mipi_panel_in: endpoint { + remote-endpoint = <&dsi0_out_panel>; + }; + }; + }; +}; + +&dsi0_in { + dsi0_in_vp3: endpoint { + remote-endpoint = <&vp3_out_dsi0>; + }; +}; + +&dsi0_out { + dsi0_out_panel: endpoint { + remote-endpoint = <&mipi_panel_in>; + }; +}; + +&i2c6 { + /* OV5675, GT911, DW9714 are limited to 400KHz */ + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + interrupt-parent = <&gpio3>; + interrupts = ; + irq-gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_int>; + reset-gpios = <&pca9670 1 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&vcc2v8_video>; + VDDIO-supply = <&vcc3v3_baseboard>; + }; + + pca9670: gpio@27 { + compatible = "nxp,pca9670"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pca9670_resetn>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; + }; +}; + +&mipidcphy0 { + status = "okay"; +}; + +&pinctrl { + pca9670 { + pca9670_resetn: pca9670-resetn { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_int: touch-int { + rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&vp3 { + #address-cells = <1>; + #size-cells = <0>; + + vp3_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 { + reg = ; + remote-endpoint = <&dsi0_in_vp3>; + }; +}; From 8454ad4e4a9bfc9cae560da54bc8ecc1cf87f002 Mon Sep 17 00:00:00 2001 From: Jacobe Zang Date: Thu, 24 Apr 2025 18:14:40 +0800 Subject: [PATCH 25/52] arm64: dts: rockchip: Add bluetooth support to Khadas Edge2 This commit adds the RTS signal, specifies the compatible Broadcom chip, its clock source, interrupts, GPIOs for wakeup and shutdown, maximum speed, pinctrl settings, and power supplies. Signed-off-by: Muhammed Efe Cetin Signed-off-by: Jacobe Zang Link: https://lore.kernel.org/r/20250424-edge-v1-1-314aad01d9ab@wesion.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588s-khadas-edge2.dts | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts index 88a5e822ed17..afa16aacee00 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -697,8 +697,24 @@ &uart2 { &uart9 { pinctrl-names = "default"; - pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; + pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn &uart9m2_rtsn>; status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&hym8563>; + clock-names = "lpo"; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wakeup"; + device-wakeup-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_wake_host_irq &bt_wake_pin &bt_reset_pin>; + vbat-supply = <&vcc_3v3_s3>; + vddio-supply = <&vcc_1v8_s3>; + }; }; &u2phy2 { From 169f17bbbeaf8c71f2d001f2d0109dd26270ed24 Mon Sep 17 00:00:00 2001 From: Jacobe Zang Date: Thu, 24 Apr 2025 18:14:41 +0800 Subject: [PATCH 26/52] arm64: dts: rockchip: Add HDMI & VOP2 to Khadas Edge2 Enable HDMI display output on Khadas Edge2. Signed-off-by: Muhammed Efe Cetin Signed-off-by: Jacobe Zang Link: https://lore.kernel.org/r/20250424-edge-v1-2-314aad01d9ab@wesion.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3588s-khadas-edge2.dts | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts index afa16aacee00..7aa93ab3bc4b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -6,6 +6,7 @@ #include #include #include +#include #include "rk3588s.dtsi" / { @@ -42,6 +43,17 @@ ir-receiver { pinctrl-0 = <&ir_receiver_pin>; }; + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + leds { compatible = "pwm-leds"; @@ -181,6 +193,30 @@ &gpu { status = "okay"; }; +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; @@ -754,3 +790,18 @@ &usb_host1_ohci { &usb_host2_xhci { status = "okay"; }; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; From 932bcd2131df776411dc26314f9455620909d4af Mon Sep 17 00:00:00 2001 From: Jacobe Zang Date: Thu, 24 Apr 2025 18:14:42 +0800 Subject: [PATCH 27/52] arm64: dts: rockchip: enable HDMI out audio on Khadas Edge2 Enable HDMI out audio on the Khadas Edge2. Signed-off-by: Jacobe Zang Link: https://lore.kernel.org/r/20250424-edge-v1-3-314aad01d9ab@wesion.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts index 7aa93ab3bc4b..2c22abaf40a8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -217,6 +217,10 @@ &hdptxphy0 { status = "okay"; }; +&hdmi0_sound { + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; @@ -269,6 +273,10 @@ hym8563: rtc@51 { }; }; +&i2s5_8ch { + status = "okay"; +}; + &pd_gpu { domain-supply = <&vdd_gpu_s0>; }; From a481bb0b1ad936c976679f9de25a709b98f9dcc3 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sat, 26 Apr 2025 15:15:40 +0800 Subject: [PATCH 28/52] arm64: dts: rockchip: Add eDP1 dt node for rk3588 Add eDP1 dt node for RK3588 SoC Signed-off-by: Andy Yan Link: https://lore.kernel.org/r/20250426071554.1305042-1-andyshrk@163.com Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3588-extra.dtsi | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi index 099edb3fd0f6..9d81d3b9444e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -252,6 +252,34 @@ hdmi1_out: port@1 { }; }; + edp1: edp@fded0000 { + compatible = "rockchip,rk3588-edp"; + reg = <0x0 0xfded0000 0x0 0x1000>; + clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>, <&cru CLK_EDP1_200M>; + clock-names = "dp", "pclk", "spdif"; + interrupts = ; + phys = <&hdptxphy1>; + phy-names = "dp"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_EDP1_24M>, <&cru SRST_P_EDP1>; + reset-names = "dp", "apb"; + rockchip,grf = <&vo1_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + edp1_in: port@0 { + reg = <0>; + }; + + edp1_out: port@1 { + reg = <1>; + }; + }; + }; + hdmi_receiver: hdmi_receiver@fdee0000 { compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; reg = <0x0 0xfdee0000 0x0 0x6000>; From 281bc0c595d3d4ea9997205830cf99c65eff931a Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sat, 26 Apr 2025 15:15:41 +0800 Subject: [PATCH 29/52] arm64: dts: rockchip: Enable eDP display for Cool Pi GenBook Cool Pi CM5 GenBook equipped with a 1080P eDP panel, the panel connected on board with 30/40 pin connector. There is no hpd hooked up on the board, so we need to set hpd-absent-delay-ms in dts. Signed-off-by: Andy Yan Link: https://lore.kernel.org/r/20250426071554.1305042-2-andyshrk@163.com Signed-off-by: Heiko Stuebner --- .../rockchip/rk3588-coolpi-cm5-genbook.dts | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts index 6dc10da5215f..738637ecaf55 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts @@ -148,6 +148,40 @@ vcc5v0_usb_host0: vcc5v0_usb30_host: regulator-vcc5v0-usb-host { }; }; +&edp1 { + force-hpd; + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + hpd-absent-delay-ms = <200>; + no-hpd; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd>; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + }; +}; + +&edp1_in { + edp1_in_vp2: endpoint { + remote-endpoint = <&vp2_out_edp1>; + }; +}; + +&edp1_out { + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; +}; + + /* HDMI CEC is not used */ &hdmi0 { pinctrl-0 = <&hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>; @@ -170,6 +204,10 @@ &hdptxphy0 { status = "okay"; }; +&hdptxphy1 { + status = "okay"; +}; + &i2c4 { status = "okay"; pinctrl-names = "default"; @@ -383,6 +421,8 @@ &usb_host1_xhci { }; &vop { + assigned-clocks = <&cru DCLK_VOP2_SRC>; + assigned-clock-parents = <&cru PLL_V0PLL>; status = "okay"; }; @@ -396,3 +436,10 @@ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp2 { + vp2_out_edp1: endpoint@ROCKCHIP_VOP2_EP_EDP1 { + reg = ; + remote-endpoint = <&edp1_in_vp2>; + }; +}; From faebc6375bbf4e30b3ef3870b7879228ad7b2ada Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Wed, 23 Apr 2025 09:22:39 +0800 Subject: [PATCH 30/52] arm64: dts: rockchip: Add pcie1 slot for rk3576 evb1 board PCIe1 and usb_drd1_dwc3 is sharing the same PHY on RK3576 platform. For pcie1 slot and USB interface, there is a swich IC labelled as Dial_Switch_1 on evb1 board. If we need to make pcie1 slot work for this board, we should first disable usb_drd1_dwc3 and then set Dial_Switch_1 to low state. Signed-off-by: Shawn Lin Link: https://lore.kernel.org/r/1745371359-30443-1-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts index ac397ac00a9e..0902d694cef4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -691,6 +691,17 @@ rgmii_phy1: phy@1 { }; }; +&pcie1 { + reset-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie1>; + + /* + * Disable usb_drd1_dwc3 if enabling pcie1 and set Dial_Switch_1 + * to low state according to the schematic of page 17. + */ + status = "disabled"; +}; + &pinctrl { usb { usb_host_pwren: usb-host-pwren { From b3610f20905fbc95afb61370df02bf1bfbb538c0 Mon Sep 17 00:00:00 2001 From: Chaoyi Chen Date: Fri, 18 Apr 2025 09:47:56 +0800 Subject: [PATCH 31/52] dt-bindings: arm: rockchip: Add rk3588 evb2 board Add devicetree binding for the rk3588 evb2 board. Signed-off-by: Chaoyi Chen Acked-by: "Rob Herring (Arm)" Link: https://lore.kernel.org/r/20250418014757.336-2-kernel@airkyi.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 650fb833d96e..455fbb290b77 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1074,7 +1074,9 @@ properties: - description: Rockchip RK3588 Evaluation board items: - - const: rockchip,rk3588-evb1-v10 + - enum: + - rockchip,rk3588-evb1-v10 + - rockchip,rk3588-evb2-v10 - const: rockchip,rk3588 - description: Rockchip RK3588S Evaluation board From 2acfe31a8ce57f9ecc06c0a0b860dc25e29cf92b Mon Sep 17 00:00:00 2001 From: Chaoyi Chen Date: Fri, 18 Apr 2025 09:47:57 +0800 Subject: [PATCH 32/52] arm64: dts: rockchip: Add rk3588 evb2 board General features for rk3588 evb2 board: - Rockchip RK3588 - LPDDR4/4X - eMMC5.1 - RK806-2x2pcs + DiscretePower - 1x HDMI2.1 TX / HDMI2.0 RX - 1x full size DisplayPort - 3x USB3.0 Host - 1x USB2.0 Host - WIFI/BT Tested with HDMI/GPU/USB2.0/USB3.0/WIFI module. Signed-off-by: Chaoyi Chen Link: https://lore.kernel.org/r/20250418014757.336-3-kernel@airkyi.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588-evb2-v10.dts | 931 ++++++++++++++++++ 2 files changed, 932 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 61158c75f332..7948522cb225 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -147,6 +147,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb2-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-firefly-itx-3588j.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-friendlyelec-cm3588-nas.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h96-max-v58.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts new file mode 100644 index 000000000000..91fe810d38d8 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts @@ -0,0 +1,931 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "rk3588.dtsi" + +/ { + model = "Rockchip RK3588 EVB2 V10 Board"; + compatible = "rockchip,rk3588-evb2-v10", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_LOW>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: regulator-vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + sram-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&sdio { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom0_pins>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + max-frequency = <150000000>; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + non-removable; + no-sd; + sd-uhs-sdr104; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio2>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-0 = <&wifi_host_wake_irq>; + pinctrl-names = "default"; + }; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <2>; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc5v0_sys>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + + regulators { + vdd_gpu_s0: dcdc-reg1 { + /* regulator coupling requires always-on */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-coupled-with = <&vdd_gpu_mem_s0>; + regulator-coupled-max-spread = <10000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vdd_gpu_mem_s0: dcdc-reg5 { + /* regulator coupling requires always-on */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + regulator-name = "vdd_gpu_mem_s0"; + regulator-coupled-with = <&vdd_gpu_s0>; + regulator-coupled-max-spread = <10000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vdd_npu_mem_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vdd_vdenc_mem_s0: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v1_nldo_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1100000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd1_1v8_ddr_s3: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd1_1v8_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_codec_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avcc_1v8_codec_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s3: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_1v8_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd2l_0v9_ddr_s3: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd2l_0v9_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_0v75_hdmi_edp_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_hdmi_edp_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v75_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + pmic@1 { + compatible = "rockchip,rk806"; + reg = <0x01>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, + <&rk806_slave_dvs3_null>; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_2v0_pldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_slave_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_slave_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_slave_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_cpu_big1_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big1_mem_s0>; + regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big0_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big0_mem_s0>; + regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_lit_mem_s0>; + regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_mem_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big1_s0>; + regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big1_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + + vdd_cpu_big0_mem_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big0_s0>; + regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big0_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_mem_s0: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_lit_s0>; + regulator-coupled-max-spread = <10000>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_cam_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v8_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd1v8_ddr_pll_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd1v8_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_1v8_pll_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_1v8_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_sd_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_2v8_cam_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_2v8_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_pll_s0: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_0v75_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v85_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_cam_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_1v2_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; From f50181bb033b941c623bd727988bdab890139158 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Tue, 15 Apr 2025 12:47:11 -0500 Subject: [PATCH 33/52] arm64: dts: rockchip: Enable HDMI0 audio output for Indiedroid Nova Make available HDMI audio for the HDMI0 port. Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20250415174711.72891-1-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts index 4189a88ecf40..4ec7bc4a9e96 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts @@ -278,6 +278,10 @@ hdmi0_out_con: endpoint { }; }; +&hdmi0_sound { + status = "okay"; +}; + &hdptxphy0 { status = "okay"; }; @@ -449,6 +453,10 @@ i2s0_8ch_p0_0: endpoint { }; }; +&i2s5_8ch { + status = "okay"; +}; + &pcie2x1l2 { pinctrl-0 = <&rtl8111_perstb>; pinctrl-names = "default"; From b022a48d8d6c0e701196c98c23f261512e6ab4c2 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 14 Apr 2025 20:37:45 +0200 Subject: [PATCH 34/52] arm64: dts: rockchip: Add HDMI support for roc-rk3576-pc Enable HDMI and VOP nodes for the roc-rk3576-pc board. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250414183745.1352470-1-heiko@sntech.de --- .../arm64/boot/dts/rockchip/rk3576-roc-pc.dts | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts index 612b7bb0b749..d4e437ea6cd8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts @@ -10,6 +10,7 @@ #include #include #include +#include #include #include "rk3576.dtsi" @@ -54,6 +55,17 @@ button-recovery { }; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + vbus5v0_typec: regulator-vbus5v0-typec { compatible = "regulator-fixed"; enable-active-high; @@ -258,6 +270,26 @@ ð0m0_rgmii_bus status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdptxphy { + status = "okay"; +}; + &mdio0 { status = "okay"; @@ -734,3 +766,18 @@ &uart6 { pinctrl-0 = <&uart6m3_xfer>; status = "okay"; }; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; From 34b69113ab975e8718b24b9b2cd4b1ea8dc107d8 Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Mon, 14 Apr 2025 20:37:38 +0200 Subject: [PATCH 35/52] arm64: dts: rockchip: enable pcie on Sige5 The ArmSoM Sige5 board exposes PCIe controller 0 on its M.2 slot on the bottom of the board. Enable the necessary nodes for it, and also add the correct pins for both the power enable GPIO and the PCIe reset GPIO. Signed-off-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20250414-rk3576-sige5-pcie-v1-1-0e950a96f392@collabora.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3576-armsom-sige5.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts index 828bde7fab68..964ee351d3b6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -117,6 +117,8 @@ vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { vcc_3v3_pcie: regulator-vcc-3v3-pcie { compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwr_en>; regulator-name = "vcc_3v3_pcie"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -177,6 +179,10 @@ vcc_3v3_ufs_s0: regulator-vcc-ufs-s0 { }; }; +&combphy0_ps { + status = "okay"; +}; + &cpu_l0 { cpu-supply = <&vdd_cpu_lit_s0>; }; @@ -634,6 +640,14 @@ rgmii_phy1: phy@1 { }; }; +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset>; + reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie>; + status = "okay"; +}; + &pinctrl { headphone { hp_det: hp-det { @@ -655,6 +669,15 @@ led_rgb_g: led-green-en { rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + pcie { + pcie_pwr_en: pcie-pwr-en { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + pcie_reset: pcie-reset { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; }; &sdhci { From b0657f9a8cdd1a8075de60e1b7c1977515b2a8f4 Mon Sep 17 00:00:00 2001 From: Markus Reichl Date: Fri, 11 Apr 2025 16:02:21 +0200 Subject: [PATCH 36/52] arm64: dts: rockchip: Add vcc supply to spi flash on rk3399-roc-pc Add vcc supply to the spi-nor flash chip on rk3399-roc-pc boards according to the board schematics ROC-3399-PC-V10-A-20180804 to avoid warnings in dmesg output. Signed-off-by: Markus Reichl Link: https://lore.kernel.org/r/20250411140223.1069-1-m.reichl@fivetechno.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi index 0393da25cdfb..fc9279627ef6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi @@ -736,6 +736,7 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <30000000>; + vcc-supply = <&vcc3v3_sys>; }; }; From 2339bc6b42a6bb89a90b050b0ee3e1020249c750 Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Fri, 25 Apr 2025 10:44:41 +0200 Subject: [PATCH 37/52] arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3328-rock64 As described on page 6 of the Rock64 schematics for both v2.0 and v3.0 the SPI Flash's VCC connector is connected to the VCC_IO power source. This fixes the following warning: spi-nor spi0.0: supply vcc not found, using dummy regulator Signed-off-by: Diederik de Haas Link: https://lore.kernel.org/r/20250425092601.56549-2-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts index e550b6eeeff3..5367e5fa9232 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts @@ -343,6 +343,7 @@ flash@0 { /* maximum speed for Rockchip SPI */ spi-max-frequency = <50000000>; + vcc-supply = <&vcc_io>; }; }; From b7b045de0bb80c2922344a18894a6a2e6c425f91 Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Fri, 25 Apr 2025 10:44:42 +0200 Subject: [PATCH 38/52] arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3399-rockpro64 As described on page 16 of the RockPro64 schematics for both v2.0 and v2.1, the SPI Flash's VCC connector is connected to the VCC_3V0 power source. This fixes the following warning: spi-nor spi1.0: supply vcc not found, using dummy regulator Signed-off-by: Diederik de Haas Link: https://lore.kernel.org/r/20250425092601.56549-3-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi index 51c6aa26d828..a7e4adf87e7a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi @@ -850,6 +850,7 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <10000000>; + vcc-supply = <&vcc_3v0>; }; }; From 2c99a9ce2ccdb095de88028269913833dd2e984d Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Fri, 25 Apr 2025 10:44:43 +0200 Subject: [PATCH 39/52] arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3566-pinetab2 As described on page 37 of PineTab2 Schematic-20230417, the SPI Flash's VCC connector is connected to VCCIO_FLASH and according to page 6 of that same schematic, that belongs to the VCC_1V8 power source. This fixes the following warning: spi-nor spi4.0: supply vcc not found, using dummy regulator Signed-off-by: Diederik de Haas Link: https://lore.kernel.org/r/20250425092601.56549-4-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi index 26cf765a7297..3473b1eef5cd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi @@ -867,6 +867,7 @@ flash@0 { spi-max-frequency = <100000000>; spi-rx-bus-width = <2>; spi-tx-bus-width = <1>; + vcc-supply = <&vcc_1v8>; }; }; From 425af91c58023a8924cc2330384e040d388adc4e Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Fri, 25 Apr 2025 10:44:44 +0200 Subject: [PATCH 40/52] arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3588-rock-5b The Radxa Rock 5B component placement document identifies the SPI Nor Flash chip as 'U4300' which is described on page 25 of the Schematic v1.45. There we can see that the VCC connector is connected to the VCC_3V3_S3 power source. This fixes the following warning: spi-nor spi5.0: supply vcc not found, using dummy regulator Signed-off-by: Diederik de Haas Link: https://lore.kernel.org/r/20250425092601.56549-5-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index d22068475c5d..17f4fd054cd3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -562,6 +562,7 @@ flash@0 { spi-max-frequency = <104000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; + vcc-supply = <&vcc_3v3_s3>; }; }; From 24d8127d801560c8fa811d554e8ab5db7e51511c Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Thu, 24 Apr 2025 20:52:23 +0200 Subject: [PATCH 41/52] arm64: dts: rockchip: add SATA nodes to RK3576 The Rockchip RK3576 features two SATA nodes. The first, sata0, is behind combphy0, which muxes between pcie0 and sata0. The second, sata1, is behind combphy1, which muxes between pcie1, sata1 and usb_drd1_dwc3. I've only been able to test sata0 on my board, but it appears to work just fine. Signed-off-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20250424-rk3576-sata-v1-2-23ee89c939fe@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 30 ++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index a6bfef82d50b..ddc92ccc530d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1442,6 +1442,36 @@ gmac1_mtl_tx_setup: tx-queues-config { }; }; + sata0: sata@2a240000 { + compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci"; + reg = <0x0 0x2a240000 0x0 0x1000>; + clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, + <&cru CLK_RXOOB0>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + power-domains = <&power RK3576_PD_SUBPHP>; + phys = <&combphy0_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + dma-coherent; + status = "disabled"; + }; + + sata1: sata@2a250000 { + compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci"; + reg = <0x0 0x2a250000 0x0 0x1000>; + clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, + <&cru CLK_RXOOB1>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + power-domains = <&power RK3576_PD_SUBPHP>; + phys = <&combphy1_psu PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + dma-coherent; + status = "disabled"; + }; + ufshc: ufshc@2a2d0000 { compatible = "rockchip,rk3576-ufshc"; reg = <0x0 0x2a2d0000 0x0 0x10000>, From db1fefec31e79e59459c2c14fe4d42e303ef8ba3 Mon Sep 17 00:00:00 2001 From: Jimmy Hon Date: Sun, 27 Apr 2025 13:20:19 -0500 Subject: [PATCH 42/52] arm64: dts: rockchip: Enable bluetooth of AP6611s on OrangePI5 Max/Ultra Orange Pi 5 Max and Ultra has onboard AP6611s with Bluetooth 5.3 connected via UART7. The chip reports as: [ 3.747864] Bluetooth: hci0: BCM: chip id 3 [ 3.750021] Bluetooth: hci0: BCM: features 0x0f [ 3.775923] Bluetooth: hci0: SYN43711A0 [ 3.775930] Bluetooth: hci0: BCM (001.001.030) build 0000 Signed-off-by: Jimmy Hon Link: https://lore.kernel.org/r/20250427182019.1862-1-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner --- .../rockchip/rk3588-orangepi-5-compact.dtsi | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-compact.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-compact.dtsi index f748c6f760d8..9343dfc86941 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-compact.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-compact.dtsi @@ -87,6 +87,20 @@ usb_host_pwren: usb-host-pwren { rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + wireless-bluetooth { + bt_reg_on: bt-reg-on { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt: host-wake-bt { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pwm4 { @@ -120,6 +134,28 @@ &u2phy1_otg { phy-supply = <&vcc5v0_usb20>; }; +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7m0_xfer &uart7m0_ctsn &uart7m0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&hym8563>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wakeup"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on>, <&host_wake_bt>, <&bt_wake_host>; + shutdown-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + vbat-supply = <&vcc_3v3_s3>; + vddio-supply = <&vcc_1v8_s3>; + }; +}; + &usb_host0_xhci { dr_mode = "host"; }; From 60087bcbd1206a546c570c453dee5f5d961ef5b3 Mon Sep 17 00:00:00 2001 From: John Clark Date: Tue, 22 Apr 2025 17:03:45 -0400 Subject: [PATCH 43/52] arm64: dts: rockchip: fix usb-c port functionality on rk3588-nanopc-t6 The USB-C port on the NanoPC-T6 was not providing VBUS (vbus5v0_typec regulator disabled, gpio-58 out lo) due to misconfiguration. The original setup with regulator-always-on and regulator-boot-on forced the port on, masking the issue, but removing these properties revealed that the fusb302 driver was not enabling the regulator dynamically. Changes: - Removed regulator-always-on and regulator-boot-on from vbus5v0_typec and vbus5v0_usb to allow driver control. - Changed power-role from "source" to "dual" in the usb-c-connector to support OTG functionality. - Added pd-revision = /bits/ 8 <0x2 0x0 0x1 0x2> to the FUSB302MPX node to specify USB Power Delivery (PD) Revision 2.0, Version 1.2, ensuring the driver correctly advertises PD capabilities and negotiates power roles (source/sink). - Added op-sink-microwatt and sink-pdos for proper sink mode configuration (1W min, 15W max). - Added typec-power-opmode = "1.5A" to enable 1.5A fallback for non-PD USB-C devices, aligning with the 5V/2A hardware limit. - Set try-power-role to "source" to prioritize VBUS enablement. - Adjusted usb_host0_xhci dr_mode from "host" to "otg" and added usb-role-switch for dual-role support. Testing: - Verified VBUS (5V) delivery to a sink device (USB thumb drive). - Confirmed USB host mode with lsusb detecting connected devices. - Validated USB device mode with adb devices when connected to a PC. - Tested dual-role (OTG) functionality with try-power-role set to "source" and "sink"; "source" prioritizes faster VBUS activation. - Validated functionality with a mobile device, including USB Power Delivery, file transfer, USB tethering, MIDI, and image transfer. - Tested USB-C Ethernet adapter compatibility in host mode. - Tested USB-C hub compatibility in host mode. Signed-off-by: John Clark Link: https://lore.kernel.org/r/20250422210345.196050-1-inindev@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 21 ++++++++++--------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi index cecfb788bf9e..3d8b6f0c5541 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -174,8 +174,6 @@ vbus5v0_typec: regulator-vbus5v0-typec { gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&typec5v_pwren>; - regulator-always-on; - regulator-boot-on; regulator-name = "vbus5v0_typec"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -188,8 +186,6 @@ vbus5v0_usb: regulator-vbus5v0-usb { gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb5v_pwren>; - regulator-always-on; - regulator-boot-on; regulator-name = "vbus5v0_usb"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -465,24 +461,30 @@ regulator-state-mem { }; &i2c6 { - clock-frequency = <200000>; status = "okay"; - fusb302: typec-portc@22 { + usbc0: usb-typec@22 { compatible = "fcs,fusb302"; reg = <0x22>; interrupt-parent = <&gpio0>; interrupts = ; - pinctrl-0 = <&usbc0_int>; pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; vbus-supply = <&vbus5v0_typec>; + status = "okay"; connector { compatible = "usb-c-connector"; data-role = "dual"; label = "USB-C"; - power-role = "source"; + op-sink-microwatt = <1000000>; + /* fusb302 supports PD Rev 2.0 Ver 1.2 */ + pd-revision = /bits/ 8 <0x2 0x0 0x1 0x2>; + power-role = "dual"; + sink-pdos = ; source-pdos = ; + try-power-role = "source"; + typec-power-opmode = "1.5A"; ports { #address-cells = <1>; @@ -1135,9 +1137,8 @@ &usb_host0_ohci { }; &usb_host0_xhci { - dr_mode = "host"; - status = "okay"; usb-role-switch; + status = "okay"; port { usb_host0_xhci_drd_sw: endpoint { From fdc68be8a8acbea9630c3bca560b7a1cf3a952e2 Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Sat, 3 May 2025 17:22:18 +0200 Subject: [PATCH 44/52] arm64: dts: rockchip: Add phy-supply to gmac0 on NanoPi R5S According to paragraph "7.16. Power" of the RTL8211F-CG datasheet, gmac0 needs to have a 3.3V power supply. On page 22 of the NanoPi R5S version 2204, that is identified as VCC_GEPHY_3V3 which is connected to the VCC_3V3 power source. This fixes the following warning: rk_gmac-dwmac fe2a0000.ethernet: supply phy not found, using dummy regulator Signed-off-by: Diederik de Haas Link: https://lore.kernel.org/r/20250503152917.138648-2-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts index b6ad8328c7eb..4cb8df1129c0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts @@ -58,6 +58,7 @@ &gmac0 { clock_in_out = "output"; phy-handle = <&rgmii_phy0>; phy-mode = "rgmii"; + phy-supply = <&vcc_3v3>; pinctrl-names = "default"; pinctrl-0 = <&gmac0_miim &gmac0_tx_bus2 From ec79aee752c6b5c7695cd82a57a8a9249d09316d Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Sat, 3 May 2025 17:22:19 +0200 Subject: [PATCH 45/52] arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3566-quartz64-b The Quartz64 Model B has a Winbound 25Q64DWZPIG SPI flash chip, identified as 'U13' on the component placement schematic. In the Quartz 64 Model-B Schematic from 20220124 on page 17, we can see that the VCC connector is connected to VCCIO_FLASH and page 4 shows that that in turn is connected to the VCCIO2 domain. That domain uses vcc_1v8 as its power source. This fixes the following warning: spi-nor spi4.0: supply vcc not found, using dummy regulator Signed-off-by: Diederik de Haas Link: https://lore.kernel.org/r/20250503152917.138648-3-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts index 5707321a1144..f8cf03380636 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts @@ -648,6 +648,7 @@ flash@0 { spi-max-frequency = <24000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; + vcc-supply = <&vcc_1v8>; }; }; From ec169727bf7365f7475f335116e1bb5896dd3603 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 1 May 2025 18:02:09 +0200 Subject: [PATCH 46/52] arm64: dts: rockchip: Switch to undeprecated qcom,calibration-variant on RK3399 The property qcom,ath10k-calibration-variant was deprecated in favor of recently introduced generic qcom,calibration-variant, common to all Qualcomm Atheros WiFi bindings. Change will affect out of tree users, like other projects, of this DTS. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250501160208.96451-2-krzysztof.kozlowski@linaro.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-dumo.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-dumo.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-dumo.dts index 9e4b12ed62cb..be3ae473e562 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-dumo.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-dumo.dts @@ -36,6 +36,6 @@ wifi@0,0 { compatible = "qcom,ath10k"; reg = <0x00000000 0x0 0x00000000 0x0 0x00000000>, <0x03000010 0x0 0x00000000 0x0 0x00200000>; - qcom,ath10k-calibration-variant = "GO_DUMO"; + qcom,calibration-variant = "GO_DUMO"; }; }; From 5268f3b5d29887480011b44567bcbf0d422cda94 Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Wed, 30 Apr 2025 18:16:36 +0200 Subject: [PATCH 47/52] arm64: dts: rockchip: add RK3576 RNG node The RK3576 has a hardware random number generator IP built into the SoC. Add it to the SoC's .dtsi, now that there's a binding and driver for it. Signed-off-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20250430-rk3576-hwrng-v1-3-480c15b5843e@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index ddc92ccc530d..d7c6495e18c0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1557,6 +1557,14 @@ sfc0: spi@2a340000 { status = "disabled"; }; + rng: rng@2a410000 { + compatible = "rockchip,rk3576-rng"; + reg = <0x0 0x2a410000 0x0 0x200>; + clocks = <&cru HCLK_TRNG_NS>; + interrupts = ; + resets = <&cru SRST_H_TRNG_NS>; + }; + otp: otp@2a580000 { compatible = "rockchip,rk3576-otp"; reg = <0x0 0x2a580000 0x0 0x400>; From d3a05f490d048808968df1e0d3240ab01fe82211 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Thu, 17 Apr 2025 12:01:18 +0000 Subject: [PATCH 48/52] arm64: dts: rockchip: Add I2C controllers for RK3528 Describe I2C controllers shipped by RK3528 in devicetree. For I2C-2, I2C-4 and I2C-7 which come with only a set of possible pins, a default pin configuration is included. Signed-off-by: Yao Zi Reviewed-by: Jonas Karlman Link: https://lore.kernel.org/r/20250417120118.17610-5-ziyao@disroot.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 110 +++++++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index 826f9be0be19..2c9780069af9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -24,6 +24,14 @@ aliases { gpio2 = &gpio2; gpio3 = &gpio3; gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -465,6 +473,108 @@ uart7: serial@ffa28000 { status = "disabled"; }; + i2c0: i2c@ffa50000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa50000 0x0 0x1000>; + clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@ffa58000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa58000 0x0 0x1000>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@ffa60000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa60000 0x0 0x1000>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@ffa68000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa68000 0x0 0x1000>; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@ffa70000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa70000 0x0 0x1000>; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@ffa78000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa78000 0x0 0x1000>; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@ffa80000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa80000 0x0 0x1000>; + clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; + clock-names = "i2c", "pclk"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@ffa88000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa88000 0x0 0x1000>; + clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + saradc: adc@ffae0000 { compatible = "rockchip,rk3528-saradc"; reg = <0x0 0xffae0000 0x0 0x10000>; From 101fe8b5627c68b3f2f941266e26ac355131e2fe Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Thu, 17 Apr 2025 12:01:19 +0000 Subject: [PATCH 49/52] arm64: dts: rockchip: Add onboard EEPROM for Radxa E20C Radxa E20C ships an onboard I2C EEPROM for storing production information. Enable it in devicetree. Signed-off-by: Yao Zi Reviewed-by: Jonas Karlman Link: https://lore.kernel.org/r/20250417120118.17610-6-ziyao@disroot.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts index 57a446b5cbd6..6e77f7753ff7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts @@ -110,6 +110,20 @@ vcc5v0_sys: regulator-5v0-vcc-sys { }; }; +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m0_xfer>; + status = "okay"; + + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v3>; + }; +}; + &pinctrl { gpio-keys { user_key: user-key { From 9e701ad7c3551b3ab87ed5fa439569696ddf42e4 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Tue, 1 Apr 2025 20:00:19 +0800 Subject: [PATCH 50/52] arm64: dts: rockchip: Add pwm nodes for RK3528 Add pwm nodes for RK3528. The PWM core on RK3528 is the same as RK3328, but the driver does not support interrupts yet. Signed-off-by: Chukun Pan Reviewed-by: Jonas Karlman Link: https://lore.kernel.org/r/20250401120020.976343-2-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 80 ++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index 2c9780069af9..923cff6bb103 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -575,6 +575,86 @@ i2c7: i2c@ffa88000 { status = "disabled"; }; + pwm0: pwm@ffa90000 { + compatible = "rockchip,rk3528-pwm", + "rockchip,rk3328-pwm"; + reg = <0x0 0xffa90000 0x0 0x10>; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@ffa90010 { + compatible = "rockchip,rk3528-pwm", + "rockchip,rk3328-pwm"; + reg = <0x0 0xffa90010 0x0 0x10>; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@ffa90020 { + compatible = "rockchip,rk3528-pwm", + "rockchip,rk3328-pwm"; + reg = <0x0 0xffa90020 0x0 0x10>; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@ffa90030 { + compatible = "rockchip,rk3528-pwm", + "rockchip,rk3328-pwm"; + reg = <0x0 0xffa90030 0x0 0x10>; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm4: pwm@ffa98000 { + compatible = "rockchip,rk3528-pwm", + "rockchip,rk3328-pwm"; + reg = <0x0 0xffa98000 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm5: pwm@ffa98010 { + compatible = "rockchip,rk3528-pwm", + "rockchip,rk3328-pwm"; + reg = <0x0 0xffa98010 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm6: pwm@ffa98020 { + compatible = "rockchip,rk3528-pwm", + "rockchip,rk3328-pwm"; + reg = <0x0 0xffa98020 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm7: pwm@ffa98030 { + compatible = "rockchip,rk3528-pwm", + "rockchip,rk3328-pwm"; + reg = <0x0 0xffa98030 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + saradc: adc@ffae0000 { compatible = "rockchip,rk3528-saradc"; reg = <0x0 0xffae0000 0x0 0x10000>; From c6599944af5a09029259ff8c533d22754f2b1ba4 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Tue, 1 Apr 2025 20:00:20 +0800 Subject: [PATCH 51/52] arm64: dts: rockchip: Enable regulators for Radxa E20C Enable pwm and fixed regulators for Radxa E20C. The pwm regulator is used to power the CPU and GPU. Note that the LPDDR4 voltage is 1.1V. Signed-off-by: Chukun Pan Reviewed-by: Jonas Karlman Link: https://lore.kernel.org/r/20250401120020.976343-3-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3528-radxa-e20c.dts | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts index 6e77f7753ff7..0942baba6b8f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts @@ -9,6 +9,7 @@ #include #include +#include #include "rk3528.dtsi" / { @@ -80,6 +81,26 @@ led-wan { }; }; + vdd_0v9: regulator-0v9-vdd { + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_ddr: regulator-1v1-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + vcc_1v8: regulator-1v8-vcc { compatible = "regulator-fixed"; regulator-name = "vcc_1v8"; @@ -108,6 +129,46 @@ vcc5v0_sys: regulator-5v0-vcc-sys { regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + vdd_arm: regulator-vdd-arm { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <746000>; + regulator-max-microvolt = <1201000>; + regulator-settling-time-up-us = <250>; + }; + + vdd_logic: regulator-vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1006000>; + regulator-settling-time-up-us = <250>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; }; &i2c1 { @@ -146,6 +207,18 @@ wan_led_g: wan-led-g { }; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1m0_pins>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m0_pins>; + status = "okay"; +}; + &saradc { vref-supply = <&vcc_1v8>; status = "okay"; From a706a593cb19796f31d3a888423ef1a71885ae72 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 6 May 2025 20:56:55 +0100 Subject: [PATCH 52/52] arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3566-rock3c As described in the radxa_rock_3c_v1400_schematic.pdf, the SPI Flash's VCC connector is connected to VCCIO_FLASH and according to the that same schematic, that belongs to the VCC_1V8 power source. This fixes the following warning: spi-nor spi4.0: supply vcc not found, using dummy regulator Fixes: ee219017ddb5 ("arm64: dts: rockchip: Add Radxa ROCK 3C") Signed-off-by: Peter Robinson Link: https://lore.kernel.org/r/20250506195702.593044-1-pbrobinson@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts index 53e71528e4c4..6224d72813e5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts @@ -636,6 +636,7 @@ flash@0 { spi-max-frequency = <104000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; + vcc-supply = <&vcc_1v8>; }; };