- New boards: rk3588-evb2, rk3588-tiger-haikou-video-demo-overlay

- New peripherals: RNG+PCIe+SATA on rk3576; eDP on rk3588;
   DMA+I2C+PWM on rk3528; DSI on rk3588
 - SPI-flash binding got a supply-property, so a number of boards add
   this supply.
 - RK3588 wrongly declared the shared memory with SCMI in the peripheral
   space - moved to the correct reserved-memory structure now.
 - The rest is peripheral enablement accross many boards - like hdmi
   output for a big number of boards, regulators, eeprom, etc.
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Merge tag 'v6.16-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt

- New boards: rk3588-evb2, rk3588-tiger-haikou-video-demo-overlay
- New peripherals: RNG+PCIe+SATA on rk3576; eDP on rk3588;
  DMA+I2C+PWM on rk3528; DSI on rk3588
- SPI-flash binding got a supply-property, so a number of boards add
  this supply.
- RK3588 wrongly declared the shared memory with SCMI in the peripheral
  space - moved to the correct reserved-memory structure now.
- The rest is peripheral enablement accross many boards - like hdmi
  output for a big number of boards, regulators, eeprom, etc.

* tag 'v6.16-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (52 commits)
  arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3566-rock3c
  arm64: dts: rockchip: Enable regulators for Radxa E20C
  arm64: dts: rockchip: Add pwm nodes for RK3528
  arm64: dts: rockchip: Add onboard EEPROM for Radxa E20C
  arm64: dts: rockchip: Add I2C controllers for RK3528
  arm64: dts: rockchip: add RK3576 RNG node
  arm64: dts: rockchip: Switch to undeprecated qcom,calibration-variant on RK3399
  arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3566-quartz64-b
  arm64: dts: rockchip: Add phy-supply to gmac0 on NanoPi R5S
  arm64: dts: rockchip: fix usb-c port functionality on rk3588-nanopc-t6
  arm64: dts: rockchip: Enable bluetooth of AP6611s on OrangePI5 Max/Ultra
  arm64: dts: rockchip: add SATA nodes to RK3576
  arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3588-rock-5b
  arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3566-pinetab2
  arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3399-rockpro64
  arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3328-rock64
  arm64: dts: rockchip: Add vcc supply to spi flash on rk3399-roc-pc
  arm64: dts: rockchip: enable pcie on Sige5
  arm64: dts: rockchip: Add HDMI support for roc-rk3576-pc
  arm64: dts: rockchip: Enable HDMI0 audio output for Indiedroid Nova
  ...

Link: https://lore.kernel.org/r/2307187.iZASKD2KPV@diego
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-05-09 22:56:20 +02:00
commit b386d064c8
33 changed files with 2281 additions and 32 deletions

View File

@ -1074,7 +1074,9 @@ properties:
- description: Rockchip RK3588 Evaluation board
items:
- const: rockchip,rk3588-evb1-v10
- enum:
- rockchip,rk3588-evb1-v10
- rockchip,rk3588-evb2-v10
- const: rockchip,rk3588
- description: Rockchip RK3588S Evaluation board

View File

@ -147,6 +147,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb2-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-firefly-itx-3588j.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-friendlyelec-cm3588-nas.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h96-max-v58.dtb
@ -165,6 +166,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou-video-demo.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-coolpi-4b.dtb
@ -233,3 +235,7 @@ rk3588-rock-5b-pcie-ep-dtbs := rk3588-rock-5b.dtb \
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtb
rk3588-rock-5b-pcie-srns-dtbs := rk3588-rock-5b.dtb \
rk3588-rock-5b-pcie-srns.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou-haikou-video-demo.dtb
rk3588-tiger-haikou-haikou-video-demo-dtbs := rk3588-tiger-haikou.dtb \
rk3588-tiger-haikou-video-demo.dtbo

View File

@ -343,6 +343,7 @@ flash@0 {
/* maximum speed for Rockchip SPI */
spi-max-frequency = <50000000>;
vcc-supply = <&vcc_io>;
};
};

View File

@ -36,6 +36,6 @@ wifi@0,0 {
compatible = "qcom,ath10k";
reg = <0x00000000 0x0 0x00000000 0x0 0x00000000>,
<0x03000010 0x0 0x00000000 0x0 0x00200000>;
qcom,ath10k-calibration-variant = "GO_DUMO";
qcom,calibration-variant = "GO_DUMO";
};
};

View File

@ -736,6 +736,7 @@ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <30000000>;
vcc-supply = <&vcc3v3_sys>;
};
};

View File

@ -850,6 +850,7 @@ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
vcc-supply = <&vcc_3v0>;
};
};

View File

@ -9,6 +9,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pwm/pwm.h>
#include "rk3528.dtsi"
/ {
@ -80,6 +81,26 @@ led-wan {
};
};
vdd_0v9: regulator-0v9-vdd {
compatible = "regulator-fixed";
regulator-name = "vdd_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&vcc5v0_sys>;
};
vcc_ddr: regulator-1v1-vcc-ddr {
compatible = "regulator-fixed";
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
vin-supply = <&vcc5v0_sys>;
};
vcc_1v8: regulator-1v8-vcc {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
@ -108,6 +129,60 @@ vcc5v0_sys: regulator-5v0-vcc-sys {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vdd_arm: regulator-vdd-arm {
compatible = "pwm-regulator";
pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>;
pwm-supply = <&vcc5v0_sys>;
regulator-name = "vdd_arm";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <746000>;
regulator-max-microvolt = <1201000>;
regulator-settling-time-up-us = <250>;
};
vdd_logic: regulator-vdd-logic {
compatible = "pwm-regulator";
pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>;
pwm-supply = <&vcc5v0_sys>;
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <705000>;
regulator-max-microvolt = <1006000>;
regulator-settling-time-up-us = <250>;
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&cpu1 {
cpu-supply = <&vdd_arm>;
};
&cpu2 {
cpu-supply = <&vdd_arm>;
};
&cpu3 {
cpu-supply = <&vdd_arm>;
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1m0_xfer>;
status = "okay";
eeprom@50 {
compatible = "belling,bl24c16a", "atmel,24c16";
reg = <0x50>;
pagesize = <16>;
read-only;
vcc-supply = <&vcc_3v3>;
};
};
&pinctrl {
@ -132,6 +207,18 @@ wan_led_g: wan-led-g {
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pwm1m0_pins>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pwm2m0_pins>;
status = "okay";
};
&saradc {
vref-supply = <&vcc_1v8>;
status = "okay";

View File

@ -24,6 +24,14 @@ aliases {
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &gpio4;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@ -375,6 +383,7 @@ uart0: serial@ff9f0000 {
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 8>, <&dmac 9>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@ -386,6 +395,7 @@ uart1: serial@ff9f8000 {
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 10>, <&dmac 11>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@ -397,6 +407,7 @@ uart2: serial@ffa00000 {
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 12>, <&dmac 13>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@ -404,9 +415,11 @@ uart2: serial@ffa00000 {
uart3: serial@ffa08000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xffa08000 0x0 0x100>;
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
reg = <0x0 0xffa08000 0x0 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 14>, <&dmac 15>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@ -418,6 +431,7 @@ uart4: serial@ffa10000 {
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 16>, <&dmac 17>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@ -429,6 +443,7 @@ uart5: serial@ffa18000 {
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 18>, <&dmac 19>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@ -440,6 +455,7 @@ uart6: serial@ffa20000 {
clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 20>, <&dmac 21>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@ -451,11 +467,194 @@ uart7: serial@ffa28000 {
clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 22>, <&dmac 23>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
i2c0: i2c@ffa50000 {
compatible = "rockchip,rk3528-i2c",
"rockchip,rk3399-i2c";
reg = <0x0 0xffa50000 0x0 0x1000>;
clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@ffa58000 {
compatible = "rockchip,rk3528-i2c",
"rockchip,rk3399-i2c";
reg = <0x0 0xffa58000 0x0 0x1000>;
clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@ffa60000 {
compatible = "rockchip,rk3528-i2c",
"rockchip,rk3399-i2c";
reg = <0x0 0xffa60000 0x0 0x1000>;
clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2m1_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@ffa68000 {
compatible = "rockchip,rk3528-i2c",
"rockchip,rk3399-i2c";
reg = <0x0 0xffa68000 0x0 0x1000>;
clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@ffa70000 {
compatible = "rockchip,rk3528-i2c",
"rockchip,rk3399-i2c";
reg = <0x0 0xffa70000 0x0 0x1000>;
clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@ffa78000 {
compatible = "rockchip,rk3528-i2c",
"rockchip,rk3399-i2c";
reg = <0x0 0xffa78000 0x0 0x1000>;
clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c6: i2c@ffa80000 {
compatible = "rockchip,rk3528-i2c",
"rockchip,rk3399-i2c";
reg = <0x0 0xffa80000 0x0 0x1000>;
clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c7: i2c@ffa88000 {
compatible = "rockchip,rk3528-i2c",
"rockchip,rk3399-i2c";
reg = <0x0 0xffa88000 0x0 0x1000>;
clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c7_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pwm0: pwm@ffa90000 {
compatible = "rockchip,rk3528-pwm",
"rockchip,rk3328-pwm";
reg = <0x0 0xffa90000 0x0 0x10>;
clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
#pwm-cells = <3>;
status = "disabled";
};
pwm1: pwm@ffa90010 {
compatible = "rockchip,rk3528-pwm",
"rockchip,rk3328-pwm";
reg = <0x0 0xffa90010 0x0 0x10>;
clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
#pwm-cells = <3>;
status = "disabled";
};
pwm2: pwm@ffa90020 {
compatible = "rockchip,rk3528-pwm",
"rockchip,rk3328-pwm";
reg = <0x0 0xffa90020 0x0 0x10>;
clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
#pwm-cells = <3>;
status = "disabled";
};
pwm3: pwm@ffa90030 {
compatible = "rockchip,rk3528-pwm",
"rockchip,rk3328-pwm";
reg = <0x0 0xffa90030 0x0 0x10>;
clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
#pwm-cells = <3>;
status = "disabled";
};
pwm4: pwm@ffa98000 {
compatible = "rockchip,rk3528-pwm",
"rockchip,rk3328-pwm";
reg = <0x0 0xffa98000 0x0 0x10>;
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
#pwm-cells = <3>;
status = "disabled";
};
pwm5: pwm@ffa98010 {
compatible = "rockchip,rk3528-pwm",
"rockchip,rk3328-pwm";
reg = <0x0 0xffa98010 0x0 0x10>;
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
#pwm-cells = <3>;
status = "disabled";
};
pwm6: pwm@ffa98020 {
compatible = "rockchip,rk3528-pwm",
"rockchip,rk3328-pwm";
reg = <0x0 0xffa98020 0x0 0x10>;
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
#pwm-cells = <3>;
status = "disabled";
};
pwm7: pwm@ffa98030 {
compatible = "rockchip,rk3528-pwm",
"rockchip,rk3328-pwm";
reg = <0x0 0xffa98030 0x0 0x10>;
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
#pwm-cells = <3>;
status = "disabled";
};
saradc: adc@ffae0000 {
compatible = "rockchip,rk3528-saradc";
reg = <0x0 0xffae0000 0x0 0x10000>;
@ -492,6 +691,24 @@ sdhci: mmc@ffbf0000 {
status = "disabled";
};
dmac: dma-controller@ffd60000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xffd60000 0x0 0x4000>;
clocks = <&cru ACLK_DMAC>;
clock-names = "apb_pclk";
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-periph-burst;
};
pinctrl: pinctrl {
compatible = "rockchip,rk3528-pinctrl";
rockchip,grf = <&ioc_grf>;

View File

@ -19,9 +19,9 @@ / {
aliases {
ethernet0 = &gmac1;
mmc0 = &sdmmc0;
mmc1 = &sdmmc1;
mmc2 = &sdhci;
mmc0 = &sdhci;
mmc1 = &sdmmc0;
mmc2 = &sdmmc1;
};
chosen: chosen {

View File

@ -867,6 +867,7 @@ flash@0 {
spi-max-frequency = <100000000>;
spi-rx-bus-width = <2>;
spi-tx-bus-width = <1>;
vcc-supply = <&vcc_1v8>;
};
};

View File

@ -648,6 +648,7 @@ flash@0 {
spi-max-frequency = <24000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
vcc-supply = <&vcc_1v8>;
};
};

View File

@ -636,6 +636,7 @@ flash@0 {
spi-max-frequency = <104000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
vcc-supply = <&vcc_1v8>;
};
};

View File

@ -58,6 +58,7 @@ &gmac0 {
clock_in_out = "output";
phy-handle = <&rgmii_phy0>;
phy-mode = "rgmii";
phy-supply = <&vcc_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2

View File

@ -481,9 +481,14 @@ eeprom@56 {
};
&mdio0 {
rgmii_phy0: ethernet-phy@0 {
rgmii_phy0: ethernet-phy@3 {
/* Motorcomm YT8521 phy */
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
reg = <0x3>;
pinctrl-0 = <&eth_phy0_reset_pin>;
pinctrl-names = "default";
reset-assert-us = <10000>;
reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>;
};
};
@ -556,6 +561,12 @@ &pcie3x2 {
};
&pinctrl {
gmac0 {
eth_phy0_reset_pin: eth-phy0-reset-pin {
rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
keys {
copy_button_pin: copy-button-pin {
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;

View File

@ -117,6 +117,8 @@ vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 {
vcc_3v3_pcie: regulator-vcc-3v3-pcie {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pcie_pwr_en>;
regulator-name = "vcc_3v3_pcie";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@ -177,6 +179,10 @@ vcc_3v3_ufs_s0: regulator-vcc-ufs-s0 {
};
};
&combphy0_ps {
status = "okay";
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
@ -634,6 +640,14 @@ rgmii_phy1: phy@1 {
};
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset>;
reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3_pcie>;
status = "okay";
};
&pinctrl {
headphone {
hp_det: hp-det {
@ -655,6 +669,15 @@ led_rgb_g: led-green-en {
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie_pwr_en: pcie-pwr-en {
rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down>;
};
pcie_reset: pcie-reset {
rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&sdhci {

View File

@ -128,7 +128,7 @@ vcc3v3_lcd_n: regulator-vcc3v3-lcd0-n {
vin-supply = <&vcc_3v3_s0>;
};
vcc3v3_pcie0: regulator-vcc3v3-pcie0 {
vcc3v3_pcie1: regulator-vcc3v3-pcie1 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie1";
regulator-min-microvolt = <3300000>;
@ -691,6 +691,17 @@ rgmii_phy1: phy@1 {
};
};
&pcie1 {
reset-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie1>;
/*
* Disable usb_drd1_dwc3 if enabling pcie1 and set Dial_Switch_1
* to low state according to the schematic of page 17.
*/
status = "disabled";
};
&pinctrl {
usb {
usb_host_pwren: usb-host-pwren {
@ -747,6 +758,10 @@ &uart0 {
status = "okay";
};
&ufshc {
status = "okay";
};
&usbdp_phy {
rockchip,dp-lane-mux = <2 3>;
status = "okay";

View File

@ -10,6 +10,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include <dt-bindings/usb/pd.h>
#include "rk3576.dtsi"
@ -54,6 +55,17 @@ button-recovery {
};
};
hdmi-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
vbus5v0_typec: regulator-vbus5v0-typec {
compatible = "regulator-fixed";
enable-active-high;
@ -258,6 +270,26 @@ &eth0m0_rgmii_bus
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_in {
hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;
};
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdptxphy {
status = "okay";
};
&mdio0 {
status = "okay";
@ -734,3 +766,18 @@ &uart6 {
pinctrl-0 = <&uart6m3_xfer>;
status = "okay";
};
&vop {
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi_in_vp0>;
};
};

View File

@ -1240,6 +1240,114 @@ qos_npu_m1ro: qos@27f22100 {
reg = <0x0 0x27f22100 0x0 0x20>;
};
pcie0: pcie@2a200000 {
compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
reg = <0x0 0x22000000 0x0 0x00400000>,
<0x0 0x2a200000 0x0 0x00010000>,
<0x0 0x20000000 0x0 0x00100000>;
reg-names = "dbi", "apb", "config";
bus-range = <0x0 0xf>;
clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
<&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
<&cru CLK_PCIE0_AUX>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk",
"aux";
device_type = "pci";
interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie0_intc 0>,
<0 0 0 2 &pcie0_intc 1>,
<0 0 0 3 &pcie0_intc 2>,
<0 0 0 4 &pcie0_intc 3>;
linux,pci-domain = <0>;
max-link-speed = <2>;
num-ib-windows = <8>;
num-viewport = <8>;
num-ob-windows = <2>;
num-lanes = <1>;
phys = <&combphy0_ps PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = <&power RK3576_PD_PHP>;
ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000
0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000
0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>;
resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
reset-names = "pwr", "pipe";
#address-cells = <3>;
#size-cells = <2>;
status = "disabled";
pcie0_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
};
};
pcie1: pcie@2a210000 {
compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
reg = <0x0 0x22400000 0x0 0x00400000>,
<0x0 0x2a210000 0x0 0x00010000>,
<0x0 0x21000000 0x0 0x00100000>;
reg-names = "dbi", "apb", "config";
bus-range = <0x20 0x2f>;
clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>,
<&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>,
<&cru CLK_PCIE1_AUX>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk",
"aux";
device_type = "pci";
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie1_intc 0>,
<0 0 0 2 &pcie1_intc 1>,
<0 0 0 3 &pcie1_intc 2>,
<0 0 0 4 &pcie1_intc 3>;
linux,pci-domain = <0>;
max-link-speed = <2>;
num-ib-windows = <8>;
num-viewport = <8>;
num-ob-windows = <2>;
num-lanes = <1>;
phys = <&combphy1_psu PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = <&power RK3576_PD_SUBPHP>;
ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000
0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000
0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>;
resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
reset-names = "pwr", "pipe";
#address-cells = <3>;
#size-cells = <2>;
status = "disabled";
pcie1_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
};
};
gmac0: ethernet@2a220000 {
compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
reg = <0x0 0x2a220000 0x0 0x10000>;
@ -1334,6 +1442,36 @@ gmac1_mtl_tx_setup: tx-queues-config {
};
};
sata0: sata@2a240000 {
compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci";
reg = <0x0 0x2a240000 0x0 0x1000>;
clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
<&cru CLK_RXOOB0>;
clock-names = "sata", "pmalive", "rxoob";
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&power RK3576_PD_SUBPHP>;
phys = <&combphy0_ps PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
dma-coherent;
status = "disabled";
};
sata1: sata@2a250000 {
compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci";
reg = <0x0 0x2a250000 0x0 0x1000>;
clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
<&cru CLK_RXOOB1>;
clock-names = "sata", "pmalive", "rxoob";
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&power RK3576_PD_SUBPHP>;
phys = <&combphy1_psu PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
dma-coherent;
status = "disabled";
};
ufshc: ufshc@2a2d0000 {
compatible = "rockchip,rk3576-ufshc";
reg = <0x0 0x2a2d0000 0x0 0x10000>,
@ -1419,6 +1557,14 @@ sfc0: spi@2a340000 {
status = "disabled";
};
rng: rng@2a410000 {
compatible = "rockchip,rk3576-rng";
reg = <0x0 0x2a410000 0x0 0x200>;
clocks = <&cru HCLK_TRNG_NS>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
resets = <&cru SRST_H_TRNG_NS>;
};
otp: otp@2a580000 {
compatible = "rockchip,rk3576-otp";
reg = <0x0 0x2a580000 0x0 0x400>;

View File

@ -4,6 +4,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3588-armsom-lm7.dtsi"
/ {
@ -32,6 +33,28 @@ analog-sound {
pinctrl-0 = <&hp_detect>;
};
hdmi0-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi0_con_in: endpoint {
remote-endpoint = <&hdmi0_out_con>;
};
};
};
hdmi1-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi1_con_in: endpoint {
remote-endpoint = <&hdmi1_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@ -138,6 +161,54 @@ &combphy2_psu {
status = "okay";
};
&hdmi0 {
status = "okay";
};
&hdmi0_in {
hdmi0_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi0>;
};
};
&hdmi0_out {
hdmi0_out_con: endpoint {
remote-endpoint = <&hdmi0_con_in>;
};
};
&hdmi0_sound {
status = "okay";
};
&hdmi1 {
status = "okay";
};
&hdmi1_in {
hdmi1_in_vp1: endpoint {
remote-endpoint = <&vp1_out_hdmi1>;
};
};
&hdmi1_out {
hdmi1_out_con: endpoint {
remote-endpoint = <&hdmi1_con_in>;
};
};
&hdmi1_sound {
status = "okay";
};
&hdptxphy0 {
status = "okay";
};
&hdptxphy1 {
status = "okay";
};
&i2c6 {
status = "okay";
@ -192,6 +263,14 @@ i2s0_8ch_p0_0: endpoint {
};
};
&i2s5_8ch {
status = "okay";
};
&i2s6_8ch {
status = "okay";
};
&package_thermal {
polling-delay = <1000>;
@ -406,3 +485,25 @@ &usb_host1_xhci {
&usb_host2_xhci {
status = "okay";
};
&vop {
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi0_in_vp0>;
};
};
&vp1 {
vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 {
reg = <ROCKCHIP_VOP2_EP_HDMI1>;
remote-endpoint = <&hdmi1_in_vp1>;
};
};

View File

@ -6,6 +6,7 @@
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/rk3588-power.h>
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
#include <dt-bindings/phy/phy.h>
@ -439,16 +440,15 @@ xin32k: clock-2 {
#clock-cells = <0>;
};
pmu_sram: sram@10f000 {
compatible = "mmio-sram";
reg = <0x0 0x0010f000 0x0 0x100>;
ranges = <0 0x0 0x0010f000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
scmi_shmem: sram@0 {
scmi_shmem: shmem@10f000 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x100>;
reg = <0x0 0x0010f000 0x0 0x100>;
no-map;
};
};
@ -590,6 +590,16 @@ sys_grf: syscon@fd58c000 {
reg = <0x0 0xfd58c000 0x0 0x1000>;
};
mipidcphy0_grf: syscon@fd5e8000 {
compatible = "rockchip,rk3588-dcphy-grf", "syscon";
reg = <0x0 0xfd5e8000 0x0 0x4000>;
};
mipidcphy1_grf: syscon@fd5ec000 {
compatible = "rockchip,rk3588-dcphy-grf", "syscon";
reg = <0x0 0xfd5ec000 0x0 0x4000>;
};
vop_grf: syscon@fd5a4000 {
compatible = "rockchip,rk3588-vop-grf", "syscon";
reg = <0x0 0xfd5a4000 0x0 0x2000>;
@ -1412,6 +1422,62 @@ i2s9_8ch: i2s@fddfc000 {
status = "disabled";
};
dsi0: dsi@fde20000 {
compatible = "rockchip,rk3588-mipi-dsi2";
reg = <0x0 0xfde20000 0x0 0x10000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>;
clock-names = "pclk", "sys";
resets = <&cru SRST_P_DSIHOST0>;
reset-names = "apb";
power-domains = <&power RK3588_PD_VOP>;
phys = <&mipidcphy0 PHY_TYPE_DPHY>;
phy-names = "dcphy";
rockchip,grf = <&vop_grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
dsi0_in: port@0 {
reg = <0>;
};
dsi0_out: port@1 {
reg = <1>;
};
};
};
dsi1: dsi@fde30000 {
compatible = "rockchip,rk3588-mipi-dsi2";
reg = <0x0 0xfde30000 0x0 0x10000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru PCLK_DSIHOST1>, <&cru CLK_DSIHOST1>;
clock-names = "pclk", "sys";
resets = <&cru SRST_P_DSIHOST1>;
reset-names = "apb";
power-domains = <&power RK3588_PD_VOP>;
phys = <&mipidcphy1 PHY_TYPE_DPHY>;
phy-names = "dcphy";
rockchip,grf = <&vop_grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
dsi1_in: port@0 {
reg = <0>;
};
dsi1_out: port@1 {
reg = <1>;
};
};
};
hdmi0: hdmi@fde80000 {
compatible = "rockchip,rk3588-dw-hdmi-qp";
reg = <0x0 0xfde80000 0x0 0x20000>;
@ -1454,6 +1520,34 @@ hdmi0_out: port@1 {
};
};
edp0: edp@fdec0000 {
compatible = "rockchip,rk3588-edp";
reg = <0x0 0xfdec0000 0x0 0x1000>;
clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>;
clock-names = "dp", "pclk";
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
phys = <&hdptxphy0>;
phy-names = "dp";
power-domains = <&power RK3588_PD_VO1>;
resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>;
reset-names = "dp", "apb";
rockchip,grf = <&vo1_grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
edp0_in: port@0 {
reg = <0>;
};
edp0_out: port@1 {
reg = <1>;
};
};
};
qos_gpu_m0: qos@fdf35000 {
compatible = "rockchip,rk3588-qos", "syscon";
reg = <0x0 0xfdf35000 0x0 0x20>;
@ -1970,7 +2064,7 @@ rng@fe378000 {
reg = <0x0 0xfe378000 0x0 0x200>;
interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>;
resets = <&scmi_reset 48>;
resets = <&scmi_reset SCMI_SRST_H_TRNG_NS>;
};
i2s0_8ch: i2s@fe470000 {
@ -2935,6 +3029,38 @@ usbdp_phy0: phy@fed80000 {
status = "disabled";
};
mipidcphy0: phy@feda0000 {
compatible = "rockchip,rk3588-mipi-dcphy";
reg = <0x0 0xfeda0000 0x0 0x10000>;
rockchip,grf = <&mipidcphy0_grf>;
clocks = <&cru PCLK_MIPI_DCPHY0>,
<&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
clock-names = "pclk", "ref";
resets = <&cru SRST_M_MIPI_DCPHY0>,
<&cru SRST_P_MIPI_DCPHY0>,
<&cru SRST_P_MIPI_DCPHY0_GRF>,
<&cru SRST_S_MIPI_DCPHY0>;
reset-names = "m_phy", "apb", "grf", "s_phy";
#phy-cells = <1>;
status = "disabled";
};
mipidcphy1: phy@fedb0000 {
compatible = "rockchip,rk3588-mipi-dcphy";
reg = <0x0 0xfedb0000 0x0 0x10000>;
rockchip,grf = <&mipidcphy1_grf>;
clocks = <&cru PCLK_MIPI_DCPHY1>,
<&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
clock-names = "pclk", "ref";
resets = <&cru SRST_M_MIPI_DCPHY1>,
<&cru SRST_P_MIPI_DCPHY1>,
<&cru SRST_P_MIPI_DCPHY1_GRF>,
<&cru SRST_S_MIPI_DCPHY1>;
reset-names = "m_phy", "apb", "grf", "s_phy";
#phy-cells = <1>;
status = "disabled";
};
combphy0_ps: phy@fee00000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee00000 0x0 0x100>;

View File

@ -23,17 +23,28 @@ backlight: backlight {
pwms = <&pwm2 0 25000 0>;
};
hdmi-con {
hdmi0-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
hdmi0_con_in: endpoint {
remote-endpoint = <&hdmi0_out_con>;
};
};
};
hdmi1-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi1_con_in: endpoint {
remote-endpoint = <&hdmi1_out_con>;
};
};
};
leds: leds {
compatible = "gpio-leds";
@ -117,6 +128,10 @@ &hdmi0 {
status = "okay";
};
&hdmi0_sound {
status = "okay";
};
&hdmi0_in {
hdmi0_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi0>;
@ -125,14 +140,48 @@ hdmi0_in_vp0: endpoint {
&hdmi0_out {
hdmi0_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
remote-endpoint = <&hdmi0_con_in>;
};
};
&hdmi1 {
pinctrl-names = "default";
pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>;
status = "okay";
};
&hdmi1_in {
hdmi1_in_vp1: endpoint {
remote-endpoint = <&vp1_out_hdmi1>;
};
};
&hdmi1_out {
hdmi1_out_con: endpoint {
remote-endpoint = <&hdmi1_con_in>;
};
};
&hdmi1_sound {
status = "okay";
};
&hdptxphy0 {
status = "okay";
};
&hdptxphy1 {
status = "okay";
};
&i2s5_8ch {
status = "okay";
};
&i2s6_8ch {
status = "okay";
};
/* M.2 E-Key */
&pcie2x1l1 {
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
@ -261,3 +310,10 @@ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
remote-endpoint = <&hdmi0_in_vp0>;
};
};
&vp1 {
vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 {
reg = <ROCKCHIP_VOP2_EP_HDMI1>;
remote-endpoint = <&hdmi1_in_vp1>;
};
};

View File

@ -148,6 +148,40 @@ vcc5v0_usb_host0: vcc5v0_usb30_host: regulator-vcc5v0-usb-host {
};
};
&edp1 {
force-hpd;
status = "okay";
aux-bus {
panel {
compatible = "edp-panel";
hpd-absent-delay-ms = <200>;
no-hpd;
backlight = <&backlight>;
power-supply = <&vcc3v3_lcd>;
port {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
};
};
};
};
&edp1_in {
edp1_in_vp2: endpoint {
remote-endpoint = <&vp2_out_edp1>;
};
};
&edp1_out {
edp_out_panel: endpoint {
remote-endpoint = <&panel_in_edp>;
};
};
/* HDMI CEC is not used */
&hdmi0 {
pinctrl-0 = <&hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>;
@ -170,6 +204,10 @@ &hdptxphy0 {
status = "okay";
};
&hdptxphy1 {
status = "okay";
};
&i2c4 {
status = "okay";
pinctrl-names = "default";
@ -383,6 +421,8 @@ &usb_host1_xhci {
};
&vop {
assigned-clocks = <&cru DCLK_VOP2_SRC>;
assigned-clock-parents = <&cru PLL_V0PLL>;
status = "okay";
};
@ -396,3 +436,10 @@ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
remote-endpoint = <&hdmi0_in_vp0>;
};
};
&vp2 {
vp2_out_edp1: endpoint@ROCKCHIP_VOP2_EP_EDP1 {
reg = <ROCKCHIP_VOP2_EP_EDP1>;
remote-endpoint = <&edp1_in_vp2>;
};
};

View File

@ -0,0 +1,931 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3588.dtsi"
/ {
model = "Rockchip RK3588 EVB2 V10 Board";
compatible = "rockchip,rk3588-evb2-v10", "rockchip,rk3588";
aliases {
mmc0 = &sdhci;
serial2 = &uart2;
};
chosen {
stdout-path = "serial2:1500000n8";
};
hdmi-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi0_out_con>;
};
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&hym8563>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
post-power-on-delay-ms = <200>;
reset-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_LOW>;
};
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc5v0_host: vcc5v0-host {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_usb>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
};
vcc5v0_usb: regulator-vcc5v0-usb {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_usbdcin>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usbdcin: regulator-vcc5v0-usbdcin {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usbdcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
};
&gpu {
mali-supply = <&vdd_gpu_s0>;
sram-supply = <&vdd_gpu_mem_s0>;
status = "okay";
};
&hdmi0 {
status = "okay";
};
&hdmi0_in {
hdmi0_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi0>;
};
};
&hdmi0_out {
hdmi0_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdptxphy0 {
status = "okay";
};
&i2c2 {
status = "okay";
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-output-names = "hym8563";
interrupt-parent = <&gpio0>;
interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hym8563_int>;
wakeup-source;
};
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pinctrl {
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wifi {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
};
wifi_host_wake_irq: wifi-host-wake-irq {
rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
&sdhci {
bus-width = <8>;
max-frequency = <200000000>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
&sdio {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&sdiom0_pins>;
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
disable-wp;
keep-power-in-suspend;
max-frequency = <150000000>;
mmc-pwrseq = <&sdio_pwrseq>;
no-mmc;
non-removable;
no-sd;
sd-uhs-sdr104;
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio2>;
interrupts = <RK_PB4 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-0 = <&wifi_host_wake_irq>;
pinctrl-names = "default";
};
};
&spi2 {
status = "okay";
assigned-clocks = <&cru CLK_SPI2>;
assigned-clock-rates = <200000000>;
num-cs = <2>;
pmic@0 {
compatible = "rockchip,rk806";
reg = <0x0>;
#gpio-cells = <2>;
gpio-controller;
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
pinctrl-names = "default";
spi-max-frequency = <1000000>;
system-power-controller;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc5v0_sys>;
vcc6-supply = <&vcc5v0_sys>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc5v0_sys>;
vcc9-supply = <&vcc5v0_sys>;
vcc10-supply = <&vcc5v0_sys>;
vcc11-supply = <&vcc_2v0_pldo_s3>;
vcc12-supply = <&vcc5v0_sys>;
vcc13-supply = <&vcc5v0_sys>;
vcc14-supply = <&vcc_1v1_nldo_s3>;
vcca-supply = <&vcc5v0_sys>;
rk806_dvs1_null: dvs1-null-pins {
pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
rk806_dvs2_null: dvs2-null-pins {
pins = "gpio_pwrctrl2";
function = "pin_fun0";
};
rk806_dvs3_null: dvs3-null-pins {
pins = "gpio_pwrctrl3";
function = "pin_fun0";
};
regulators {
vdd_gpu_s0: dcdc-reg1 {
/* regulator coupling requires always-on */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_gpu_s0";
regulator-enable-ramp-delay = <400>;
regulator-coupled-with = <&vdd_gpu_mem_s0>;
regulator-coupled-max-spread = <10000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_npu_s0: dcdc-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_npu_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_log_s0: dcdc-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <750000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_log_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <750000>;
};
};
vdd_vdenc_s0: dcdc-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_vdenc_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu_mem_s0: dcdc-reg5 {
/* regulator coupling requires always-on */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <400>;
regulator-name = "vdd_gpu_mem_s0";
regulator-coupled-with = <&vdd_gpu_s0>;
regulator-coupled-max-spread = <10000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_npu_mem_s0: dcdc-reg6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_npu_mem_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_2v0_pldo_s3: dcdc-reg7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_2v0_pldo_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <2000000>;
};
};
vdd_vdenc_mem_s0: dcdc-reg8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_vdenc_mem_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd2_ddr_s3: dcdc-reg9 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd2_ddr_s3";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_1v1_nldo_s3: dcdc-reg10 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-ramp-delay = <12500>;
regulator-name = "vcc_1v1_nldo_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1100000>;
};
};
avcc_1v8_s0: pldo-reg1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <12500>;
regulator-name = "avcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd1_1v8_ddr_s3: pldo-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd1_1v8_ddr_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
avcc_1v8_codec_s0: pldo-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <12500>;
regulator-name = "avcc_1v8_codec_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3_s3: pldo-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
regulator-name = "vcc_3v3_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vccio_sd_s0: pldo-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
regulator-name = "vccio_sd_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_1v8_s3: pldo-reg6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <12500>;
regulator-name = "vccio_1v8_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_0v75_s3: nldo-reg1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_0v75_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <750000>;
};
};
vdd2l_0v9_ddr_s3: nldo-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdd2l_0v9_ddr_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vdd_0v75_hdmi_edp_s0: nldo-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "vdd_0v75_hdmi_edp_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
avdd_0v75_s0: nldo-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "avdd_0v75_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_0v85_s0: nldo-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-name = "vdd_0v85_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
pmic@1 {
compatible = "rockchip,rk806";
reg = <0x01>;
#gpio-cells = <2>;
gpio-controller;
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>,
<&rk806_slave_dvs3_null>;
pinctrl-names = "default";
spi-max-frequency = <1000000>;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc5v0_sys>;
vcc6-supply = <&vcc5v0_sys>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc5v0_sys>;
vcc9-supply = <&vcc5v0_sys>;
vcc10-supply = <&vcc5v0_sys>;
vcc11-supply = <&vcc_2v0_pldo_s3>;
vcc12-supply = <&vcc5v0_sys>;
vcc13-supply = <&vcc_1v1_nldo_s3>;
vcc14-supply = <&vcc_2v0_pldo_s3>;
vcca-supply = <&vcc5v0_sys>;
rk806_slave_dvs1_null: dvs1-null-pins {
pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
rk806_slave_dvs2_null: dvs2-null-pins {
pins = "gpio_pwrctrl2";
function = "pin_fun0";
};
rk806_slave_dvs3_null: dvs3-null-pins {
pins = "gpio_pwrctrl3";
function = "pin_fun0";
};
regulators {
vdd_cpu_big1_s0: dcdc-reg1 {
regulator-always-on;
regulator-boot-on;
regulator-coupled-with = <&vdd_cpu_big1_mem_s0>;
regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_cpu_big1_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_big0_s0: dcdc-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-coupled-with = <&vdd_cpu_big0_mem_s0>;
regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_cpu_big0_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_lit_s0: dcdc-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-coupled-with = <&vdd_cpu_lit_mem_s0>;
regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_cpu_lit_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3_s0: dcdc-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
regulator-name = "vcc_3v3_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_big1_mem_s0: dcdc-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-coupled-with = <&vdd_cpu_big1_s0>;
regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_cpu_big1_mem_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_big0_mem_s0: dcdc-reg6 {
regulator-always-on;
regulator-boot-on;
regulator-coupled-with = <&vdd_cpu_big0_s0>;
regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_cpu_big0_mem_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8_s0: dcdc-reg7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <12500>;
regulator-name = "vcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_lit_mem_s0: dcdc-reg8 {
regulator-always-on;
regulator-boot-on;
regulator-coupled-with = <&vdd_cpu_lit_s0>;
regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_cpu_lit_mem_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vddq_ddr_s0: dcdc-reg9 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vddq_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_ddr_s0: dcdc-reg10 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <900000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8_cam_s0: pldo-reg1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <12500>;
regulator-name = "vcc_1v8_cam_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
avdd1v8_ddr_pll_s0: pldo-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <12500>;
regulator-name = "avdd1v8_ddr_pll_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_1v8_pll_s0: pldo-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_1v8_pll_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3_sd_s0: pldo-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
regulator-name = "vcc_3v3_sd_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_2v8_cam_s0: pldo-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-ramp-delay = <12500>;
regulator-name = "vcc_2v8_cam_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
pldo6_s3: pldo-reg6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "pldo6_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_0v75_pll_s0: nldo-reg1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_0v75_pll_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_ddr_pll_s0: nldo-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-name = "vdd_ddr_pll_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
avdd_0v85_s0: nldo-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-ramp-delay = <12500>;
regulator-name = "avdd_0v85_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
avdd_1v2_cam_s0: nldo-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-ramp-delay = <12500>;
regulator-name = "avdd_1v2_cam_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
avdd_1v2_s0: nldo-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-ramp-delay = <12500>;
regulator-name = "avdd_1v2_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&u2phy0 {
status = "okay";
};
&u2phy0_otg {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&u2phy1 {
status = "okay";
};
&u2phy1_otg {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&u2phy2 {
status = "okay";
};
&u2phy2_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&u2phy3 {
status = "okay";
};
&u2phy3_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
&usbdp_phy0 {
rockchip,dp-lane-mux = <2 3>;
status = "okay";
};
&usbdp_phy1 {
rockchip,dp-lane-mux = <2 3>;
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host1_xhci {
dr_mode = "host";
status = "okay";
};
&vop {
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi0_in_vp0>;
};
};

View File

@ -252,6 +252,34 @@ hdmi1_out: port@1 {
};
};
edp1: edp@fded0000 {
compatible = "rockchip,rk3588-edp";
reg = <0x0 0xfded0000 0x0 0x1000>;
clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>, <&cru CLK_EDP1_200M>;
clock-names = "dp", "pclk", "spdif";
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
phys = <&hdptxphy1>;
phy-names = "dp";
power-domains = <&power RK3588_PD_VO1>;
resets = <&cru SRST_EDP1_24M>, <&cru SRST_P_EDP1>;
reset-names = "dp", "apb";
rockchip,grf = <&vo1_grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
edp1_in: port@0 {
reg = <0>;
};
edp1_out: port@1 {
reg = <1>;
};
};
};
hdmi_receiver: hdmi_receiver@fdee0000 {
compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx";
reg = <0x0 0xfdee0000 0x0 0x6000>;

View File

@ -303,6 +303,10 @@ hdmi0_out_con: endpoint {
};
};
&hdmi0_sound {
status = "okay";
};
&hdptxphy0 {
status = "okay";
};
@ -512,6 +516,10 @@ regulator-state-mem {
};
};
&i2s5_8ch {
status = "okay";
};
&mdio0 {
rgmii_phy: ethernet-phy@6 {
/* KSZ9031 or KSZ9131 */

View File

@ -52,6 +52,17 @@ hdmi0_con_in: endpoint {
};
};
hdmi1-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi1_con_in: endpoint {
remote-endpoint = <&hdmi1_out_con>;
};
};
};
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>;
@ -163,8 +174,6 @@ vbus5v0_typec: regulator-vbus5v0-typec {
gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&typec5v_pwren>;
regulator-always-on;
regulator-boot-on;
regulator-name = "vbus5v0_typec";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@ -177,8 +186,6 @@ vbus5v0_usb: regulator-vbus5v0-usb {
gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb5v_pwren>;
regulator-always-on;
regulator-boot-on;
regulator-name = "vbus5v0_usb";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@ -360,10 +367,38 @@ hdmi0_out_con: endpoint {
};
};
&hdmi0_sound {
status = "okay";
};
&hdmi1 {
status = "okay";
};
&hdmi1_in {
hdmi1_in_vp1: endpoint {
remote-endpoint = <&vp1_out_hdmi1>;
};
};
&hdmi1_out {
hdmi1_out_con: endpoint {
remote-endpoint = <&hdmi1_con_in>;
};
};
&hdmi1_sound {
status = "okay";
};
&hdptxphy0 {
status = "okay";
};
&hdptxphy1 {
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
@ -426,24 +461,30 @@ regulator-state-mem {
};
&i2c6 {
clock-frequency = <200000>;
status = "okay";
fusb302: typec-portc@22 {
usbc0: usb-typec@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&usbc0_int>;
pinctrl-names = "default";
pinctrl-0 = <&usbc0_int>;
vbus-supply = <&vbus5v0_typec>;
status = "okay";
connector {
compatible = "usb-c-connector";
data-role = "dual";
label = "USB-C";
power-role = "source";
op-sink-microwatt = <1000000>;
/* fusb302 supports PD Rev 2.0 Ver 1.2 */
pd-revision = /bits/ 8 <0x2 0x0 0x1 0x2>;
power-role = "dual";
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
try-power-role = "source";
typec-power-opmode = "1.5A";
ports {
#address-cells = <1>;
@ -531,6 +572,14 @@ i2s0_8ch_p0_0: endpoint {
};
};
&i2s5_8ch {
status = "okay";
};
&i2s6_8ch {
status = "okay";
};
&pcie2x1l0 {
reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3_pcie20>;
@ -1088,9 +1137,8 @@ &usb_host0_ohci {
};
&usb_host0_xhci {
dr_mode = "host";
status = "okay";
usb-role-switch;
status = "okay";
port {
usb_host0_xhci_drd_sw: endpoint {
@ -1126,3 +1174,10 @@ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
remote-endpoint = <&hdmi0_in_vp0>;
};
};
&vp1 {
vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 {
reg = <ROCKCHIP_VOP2_EP_HDMI1>;
remote-endpoint = <&hdmi1_in_vp1>;
};
};

View File

@ -87,6 +87,20 @@ usb_host_pwren: usb-host-pwren {
rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-bluetooth {
bt_reg_on: bt-reg-on {
rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_host: bt-wake-host {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
};
host_wake_bt: host-wake-bt {
rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm4 {
@ -120,6 +134,28 @@ &u2phy1_otg {
phy-supply = <&vcc5v0_usb20>;
};
&uart7 {
pinctrl-names = "default";
pinctrl-0 = <&uart7m0_xfer &uart7m0_ctsn &uart7m0_rtsn>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&hym8563>;
clock-names = "lpo";
device-wakeup-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA0 IRQ_TYPE_EDGE_FALLING>;
interrupt-names = "host-wakeup";
pinctrl-names = "default";
pinctrl-0 = <&bt_reg_on>, <&host_wake_bt>, <&bt_wake_host>;
shutdown-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
vbat-supply = <&vcc_3v3_s3>;
vddio-supply = <&vcc_1v8_s3>;
};
};
&usb_host0_xhci {
dr_mode = "host";
};

View File

@ -562,6 +562,7 @@ flash@0 {
spi-max-frequency = <104000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
vcc-supply = <&vcc_3v3_s3>;
};
};

View File

@ -0,0 +1,153 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2024 Cherry Embedded Solutions GmbH
*
* DEVKIT ADDON CAM-TS-A01
* https://embedded.cherry.de/product/development-kit/
*
* DT-overlay for the camera / DSI demo appliance for Haikou boards.
* In the flavour for use with a Tiger system-on-module.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
&{/} {
backlight: backlight {
compatible = "pwm-backlight";
power-supply = <&dc_12v>;
pwms = <&pwm0 0 25000 0>;
};
vcc1v8_video: regulator-vcc1v8-video {
compatible = "regulator-fixed";
regulator-name = "vcc1v8-video";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc3v3_baseboard>;
};
vcc2v8_video: regulator-vcc2v8-video {
compatible = "regulator-fixed";
regulator-name = "vcc2v8-video";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
vin-supply = <&vcc3v3_baseboard>;
};
video-adapter-leds {
compatible = "gpio-leds";
video-adapter-led {
color = <LED_COLOR_ID_BLUE>;
gpios = <&pca9670 7 GPIO_ACTIVE_HIGH>;
label = "video-adapter-led";
linux,default-trigger = "none";
};
};
};
&dsi0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
panel@0 {
compatible = "leadtek,ltk050h3148w";
reg = <0>;
backlight = <&backlight>;
iovcc-supply = <&vcc1v8_video>;
reset-gpios = <&pca9670 0 GPIO_ACTIVE_LOW>;
vci-supply = <&vcc2v8_video>;
port {
mipi_panel_in: endpoint {
remote-endpoint = <&dsi0_out_panel>;
};
};
};
};
&dsi0_in {
dsi0_in_vp3: endpoint {
remote-endpoint = <&vp3_out_dsi0>;
};
};
&dsi0_out {
dsi0_out_panel: endpoint {
remote-endpoint = <&mipi_panel_in>;
};
};
&i2c6 {
/* OV5675, GT911, DW9714 are limited to 400KHz */
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
touchscreen@14 {
compatible = "goodix,gt911";
reg = <0x14>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
irq-gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&touch_int>;
reset-gpios = <&pca9670 1 GPIO_ACTIVE_HIGH>;
AVDD28-supply = <&vcc2v8_video>;
VDDIO-supply = <&vcc3v3_baseboard>;
};
pca9670: gpio@27 {
compatible = "nxp,pca9670";
reg = <0x27>;
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pca9670_resetn>;
reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>;
};
};
&mipidcphy0 {
status = "okay";
};
&pinctrl {
pca9670 {
pca9670_resetn: pca9670-resetn {
rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
touch {
touch_int: touch-int {
rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm0 {
status = "okay";
};
&vp3 {
#address-cells = <1>;
#size-cells = <0>;
vp3_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 {
reg = <ROCKCHIP_VOP2_EP_MIPI0>;
remote-endpoint = <&dsi0_in_vp3>;
};
};

View File

@ -189,6 +189,10 @@ hdmi0_out_con: endpoint {
};
};
&hdmi0_sound {
status = "okay";
};
&hdptxphy0 {
status = "okay";
};
@ -228,6 +232,10 @@ &i2s3_2ch {
status = "okay";
};
&i2s5_8ch {
status = "okay";
};
&pcie30phy {
status = "okay";
};

View File

@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include <dt-bindings/usb/pd.h>
#include "rk3588s.dtsi"
@ -238,6 +239,42 @@ &combphy2_psu {
status = "okay";
};
&edp0 {
force-hpd;
status = "okay";
aux-bus {
panel {
compatible = "edp-panel";
backlight = <&backlight>;
power-supply = <&vcc3v3_lcd_edp>;
no-hpd;
port {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
};
};
};
};
&edp0_in {
edp0_in_vp2: endpoint {
remote-endpoint = <&vp2_out_edp0>;
};
};
&edp0_out {
edp_out_panel: endpoint {
remote-endpoint = <&panel_in_edp>;
};
};
&hdptxphy0 {
status = "okay";
};
&i2c3 {
status = "okay";
@ -403,6 +440,7 @@ usbc0_int: usbc0-int {
};
&pwm12 {
pinctrl-0 = <&pwm12m1_pins>;
status = "okay";
};
@ -1172,3 +1210,20 @@ usbdp_phy0_dp_altmode_mux: endpoint@1 {
};
};
};
&vop_mmu {
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_VOP2_SRC>;
assigned-clock-parents = <&cru PLL_V0PLL>;
status = "okay";
};
&vp2 {
vp2_out_edp0: endpoint@ROCKCHIP_VOP2_EP_EDP0 {
reg = <ROCKCHIP_VOP2_EP_EDP0>;
remote-endpoint = <&edp0_in_vp2>;
};
};

View File

@ -278,6 +278,10 @@ hdmi0_out_con: endpoint {
};
};
&hdmi0_sound {
status = "okay";
};
&hdptxphy0 {
status = "okay";
};
@ -449,6 +453,10 @@ i2s0_8ch_p0_0: endpoint {
};
};
&i2s5_8ch {
status = "okay";
};
&pcie2x1l2 {
pinctrl-0 = <&rtl8111_perstb>;
pinctrl-names = "default";

View File

@ -6,6 +6,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3588s.dtsi"
/ {
@ -42,6 +43,17 @@ ir-receiver {
pinctrl-0 = <&ir_receiver_pin>;
};
hdmi0-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi0_con_in: endpoint {
remote-endpoint = <&hdmi0_out_con>;
};
};
};
leds {
compatible = "pwm-leds";
@ -181,6 +193,34 @@ &gpu {
status = "okay";
};
&hdmi0 {
status = "okay";
};
&hdmi0_in {
hdmi0_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi0>;
};
};
&hdmi0_out {
hdmi0_out_con: endpoint {
remote-endpoint = <&hdmi0_con_in>;
};
};
&hdmi0_sound {
status = "okay";
};
&hdptxphy0 {
status = "okay";
};
&hdmi0_sound {
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
@ -233,6 +273,10 @@ hym8563: rtc@51 {
};
};
&i2s5_8ch {
status = "okay";
};
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
@ -697,8 +741,24 @@ &uart2 {
&uart9 {
pinctrl-names = "default";
pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>;
pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn &uart9m2_rtsn>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&hym8563>;
clock-names = "lpo";
interrupt-parent = <&gpio0>;
interrupts = <RK_PD5 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wakeup";
device-wakeup-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
max-speed = <1500000>;
pinctrl-names = "default";
pinctrl-0 = <&bt_wake_host_irq &bt_wake_pin &bt_reset_pin>;
vbat-supply = <&vcc_3v3_s3>;
vddio-supply = <&vcc_1v8_s3>;
};
};
&u2phy2 {
@ -738,3 +798,18 @@ &usb_host1_ohci {
&usb_host2_xhci {
status = "okay";
};
&vop {
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi0_in_vp0>;
};
};