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cpufreq/amd-pstate: Cache EPP value and use that everywhere
Cache the value in cpudata->epp_cached, and use that for all callers. As all callers use cached value merge amd_pstate_get_energy_pref_index() into show_energy_performance_preference(). Check if the EPP value is changed before writing it to MSR or shared memory region. Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com> Link: https://lore.kernel.org/r/20241209185248.16301-12-mario.limonciello@amd.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
This commit is contained in:
Mario Limonciello
parent
3f7b835fa4
commit
b3781f30bf
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@ -186,29 +186,28 @@ static inline int get_mode_idx_from_str(const char *str, size_t size)
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static DEFINE_MUTEX(amd_pstate_limits_lock);
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static DEFINE_MUTEX(amd_pstate_driver_lock);
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static s16 msr_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached)
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static s16 msr_get_epp(struct amd_cpudata *cpudata)
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{
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u64 value;
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int ret;
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if (!cppc_req_cached) {
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ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &cppc_req_cached);
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if (ret < 0) {
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pr_debug("Could not retrieve energy perf value (%d)\n", ret);
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return ret;
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}
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ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value);
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if (ret < 0) {
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pr_debug("Could not retrieve energy perf value (%d)\n", ret);
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return ret;
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}
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return FIELD_GET(AMD_CPPC_EPP_PERF_MASK, cppc_req_cached);
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return FIELD_GET(AMD_CPPC_EPP_PERF_MASK, value);
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}
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DEFINE_STATIC_CALL(amd_pstate_get_epp, msr_get_epp);
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static inline s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached)
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static inline s16 amd_pstate_get_epp(struct amd_cpudata *cpudata)
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{
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return static_call(amd_pstate_get_epp)(cpudata, cppc_req_cached);
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return static_call(amd_pstate_get_epp)(cpudata);
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}
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static s16 shmem_get_epp(struct amd_cpudata *cpudata, u64 dummy)
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static s16 shmem_get_epp(struct amd_cpudata *cpudata)
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{
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u64 epp;
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int ret;
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@ -222,35 +221,6 @@ static s16 shmem_get_epp(struct amd_cpudata *cpudata, u64 dummy)
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return (s16)(epp & 0xff);
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}
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static int amd_pstate_get_energy_pref_index(struct amd_cpudata *cpudata)
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{
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s16 epp;
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int index = -EINVAL;
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epp = amd_pstate_get_epp(cpudata, 0);
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if (epp < 0)
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return epp;
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switch (epp) {
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case AMD_CPPC_EPP_PERFORMANCE:
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index = EPP_INDEX_PERFORMANCE;
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break;
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case AMD_CPPC_EPP_BALANCE_PERFORMANCE:
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index = EPP_INDEX_BALANCE_PERFORMANCE;
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break;
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case AMD_CPPC_EPP_BALANCE_POWERSAVE:
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index = EPP_INDEX_BALANCE_POWERSAVE;
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break;
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case AMD_CPPC_EPP_POWERSAVE:
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index = EPP_INDEX_POWERSAVE;
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break;
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default:
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break;
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}
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return index;
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}
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static int msr_update_perf(struct amd_cpudata *cpudata, u32 min_perf,
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u32 des_perf, u32 max_perf, bool fast_switch)
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{
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@ -275,19 +245,23 @@ static inline int amd_pstate_update_perf(struct amd_cpudata *cpudata,
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static int msr_set_epp(struct amd_cpudata *cpudata, u32 epp)
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{
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u64 value = READ_ONCE(cpudata->cppc_req_cached);
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u64 value, prev;
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int ret;
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value = prev = READ_ONCE(cpudata->cppc_req_cached);
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value &= ~AMD_CPPC_EPP_PERF_MASK;
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value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp);
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if (value == prev)
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return 0;
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ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
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if (ret) {
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pr_err("failed to set energy perf value (%d)\n", ret);
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return ret;
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}
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cpudata->epp_cached = epp;
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WRITE_ONCE(cpudata->epp_cached, epp);
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WRITE_ONCE(cpudata->cppc_req_cached, value);
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return ret;
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@ -305,13 +279,16 @@ static int shmem_set_epp(struct amd_cpudata *cpudata, u32 epp)
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int ret;
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struct cppc_perf_ctrls perf_ctrls;
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if (epp == cpudata->epp_cached)
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return 0;
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perf_ctrls.energy_perf = epp;
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ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1);
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if (ret) {
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pr_debug("failed to set energy perf value (%d)\n", ret);
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return ret;
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}
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cpudata->epp_cached = epp;
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WRITE_ONCE(cpudata->epp_cached, epp);
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return ret;
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}
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@ -1214,9 +1191,22 @@ static ssize_t show_energy_performance_preference(
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struct amd_cpudata *cpudata = policy->driver_data;
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int preference;
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preference = amd_pstate_get_energy_pref_index(cpudata);
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if (preference < 0)
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return preference;
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switch (cpudata->epp_cached) {
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case AMD_CPPC_EPP_PERFORMANCE:
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preference = EPP_INDEX_PERFORMANCE;
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break;
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case AMD_CPPC_EPP_BALANCE_PERFORMANCE:
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preference = EPP_INDEX_BALANCE_PERFORMANCE;
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break;
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case AMD_CPPC_EPP_BALANCE_POWERSAVE:
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preference = EPP_INDEX_BALANCE_POWERSAVE;
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break;
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case AMD_CPPC_EPP_POWERSAVE:
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preference = EPP_INDEX_POWERSAVE;
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break;
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default:
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return -EINVAL;
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}
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return sysfs_emit(buf, "%s\n", energy_perf_strings[preference]);
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}
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@ -1501,7 +1491,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy)
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policy->driver_data = cpudata;
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cpudata->epp_cached = cpudata->epp_default = amd_pstate_get_epp(cpudata, 0);
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cpudata->epp_cached = cpudata->epp_default = amd_pstate_get_epp(cpudata);
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policy->min = policy->cpuinfo.min_freq;
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policy->max = policy->cpuinfo.max_freq;
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@ -1555,35 +1545,26 @@ static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy)
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{
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struct amd_cpudata *cpudata = policy->driver_data;
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u64 value;
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s16 epp;
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amd_pstate_update_min_max_limit(policy);
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value = READ_ONCE(cpudata->cppc_req_cached);
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value &= ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK |
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AMD_CPPC_DES_PERF_MASK);
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AMD_CPPC_DES_PERF_MASK | AMD_CPPC_EPP_PERF_MASK);
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value |= FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, cpudata->max_limit_perf);
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value |= FIELD_PREP(AMD_CPPC_DES_PERF_MASK, 0);
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value |= FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, cpudata->min_limit_perf);
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/* Get BIOS pre-defined epp value */
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epp = amd_pstate_get_epp(cpudata, value);
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if (epp < 0) {
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/**
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* This return value can only be negative for shared_memory
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* systems where EPP register read/write not supported.
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*/
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return epp;
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}
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if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE)
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epp = 0;
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WRITE_ONCE(cpudata->epp_cached, 0);
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value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, cpudata->epp_cached);
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WRITE_ONCE(cpudata->cppc_req_cached, value);
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if (trace_amd_pstate_epp_perf_enabled()) {
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trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, epp,
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trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf,
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cpudata->epp_cached,
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cpudata->min_limit_perf,
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cpudata->max_limit_perf,
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policy->boost_enabled);
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@ -1592,7 +1573,7 @@ static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy)
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amd_pstate_update_perf(cpudata, cpudata->min_limit_perf, 0U,
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cpudata->max_limit_perf, false);
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return amd_pstate_set_epp(cpudata, epp);
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return amd_pstate_set_epp(cpudata, READ_ONCE(cpudata->epp_cached));
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}
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static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy)
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