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KVM: x86: Allow setting CR4.CET if IBT or SHSTK is supported
Drop X86_CR4_CET from CR4_RESERVED_BITS and instead mark CET as reserved if and only if IBT *and* SHSTK are unsupported, i.e. allow CR4.CET to be set if IBT or SHSTK is supported. This creates a virtualization hole if the CPU supports both IBT and SHSTK, but the kernel or vCPU model only supports one of the features. However, it's entirely legal for a CPU to have only one of IBT or SHSTK, i.e. the hole is a flaw in the architecture, not in KVM. More importantly, so long as KVM is careful to initialize and context switch both IBT and SHSTK state (when supported in hardware) if either feature is exposed to the guest, a misbehaving guest can only harm itself. E.g. VMX initializes host CET VMCS fields based solely on hardware capabilities. Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> Signed-off-by: Mathias Krause <minipli@grsecurity.net> Tested-by: Mathias Krause <minipli@grsecurity.net> Tested-by: John Allen <john.allen@amd.com> Tested-by: Rick Edgecombe <rick.p.edgecombe@intel.com> Signed-off-by: Chao Gao <chao.gao@intel.com> [sean: split to separate patch, write changelog] Reviewed-by: Binbin Wu <binbin.wu@linux.intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Link: https://lore.kernel.org/r/20250919223258.1604852-24-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
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@ -142,7 +142,7 @@
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| X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \
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| X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \
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| X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP \
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| X86_CR4_LAM_SUP))
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| X86_CR4_LAM_SUP | X86_CR4_CET))
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#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
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@ -680,6 +680,9 @@ static inline bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
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__reserved_bits |= X86_CR4_PCIDE; \
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if (!__cpu_has(__c, X86_FEATURE_LAM)) \
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__reserved_bits |= X86_CR4_LAM_SUP; \
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if (!__cpu_has(__c, X86_FEATURE_SHSTK) && \
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!__cpu_has(__c, X86_FEATURE_IBT)) \
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__reserved_bits |= X86_CR4_CET; \
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__reserved_bits; \
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})
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