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ufs-host: qcom: Fix clock scaling error

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Following error is seen:
"devfreq 1d84000.ufshc: dvfs failed with (-22) error"

Following entries need to support 403Mhz, 201.5Mhz and 100Mhz:
- SYS1CLK_1US_REG
- DME_VS_CORE_CLK_CTRL.MAX_CORE_CLK_1US_CYCLES
- PA_VS_CORE_CLK_40NS_CYCLES.

Enable clock scaling.

Change-Id: I61d16f55d57d27e6884dc1e00eb8f70120082976
Signed-off-by: Asutosh Das <quic_asutoshd@quicinc.com>
This commit is contained in:
Asutosh Das 2022-11-07 13:02:08 -08:00
parent 71694d1b47
commit b348b14d2f
2 changed files with 19 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/ufs/host/ufs-qcom.c
View File

@ -940,17 +940,30 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_max_freq_mode(struct ufs_hba *hba)
}
switch (max_freq) {
case 403000000:
err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 403, 16);
break;
case 300000000:
err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 300, 12);
break;
case 201500000:
err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 202, 8);
break;
case 150000000:
err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150, 6);
break;
case 100000000:
err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 100, 4);
break;
default:
err = -EINVAL;
break;
}
if (err) {
dev_err(hba->dev, "unipro max_freq=%u entry missing\n", max_freq);
dump_stack();
}
return err;
}
@ -2078,6 +2091,7 @@ static void ufs_qcom_set_caps(struct ufs_hba *hba)
hba->caps |= UFSHCD_CAP_CLK_GATING |
UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
hba->caps |= UFSHCD_CAP_WB_EN;
hba->caps |= UFSHCD_CAP_CLK_SCALING;
}
hba->caps |= UFSHCD_CAP_CRYPTO;
@ -3514,8 +3528,12 @@ static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
case 75000000:
err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75, 3);
break;
case 100000000:
err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 100, 4);
break;
default:
err = -EINVAL;
dev_err(hba->dev, "unipro curr_freq=%u entry missing\n", curr_freq);
break;
}

2
drivers/ufs/host/ufs-qcom.h
View File

@ -218,7 +218,7 @@ enum ufs_qcom_phy_init_type {
#define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_OFFSET_V4 0x10
#define PA_VS_CORE_CLK_40NS_CYCLES 0x9007
#define PA_VS_CORE_CLK_40NS_CYCLES_MASK 0xF
#define PA_VS_CORE_CLK_40NS_CYCLES_MASK 0x3F
#define DL_VS_CLK_CFG 0xA00B
#define DL_VS_CLK_CFG_MASK 0x3FF