- Reject async flips when PSR's selective fetch is enabled (Ville)

-----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCgAdFiEEbSBwaO7dZQkcLOKj+mJfZA7rE8oFAmknIDwACgkQ+mJfZA7r
 E8qZkQgAsLGliDOMLEw1hFrs+QSDy0uEXaKiIKSjnJ5xrJxFFtQB0a5MWPCEuzRb
 fgkCdIThW0JrCN8c00ayPS5lT9HbeTqcOMnh1PKchbfWrCSkVDns5A9rGQACgvpr
 r5IsgP7eRnyvkfykYXcCkAXk2EHrmn1N620MLsiOp88HnR5YPji3Fetho5Ba9Cx9
 KJfATrjJqn6hcRvhRydZJQ4dhdkMYjXtYMcHF3rkwiowRKReW7LpRgeONqIKfTeL
 40vYVvut1/XK5p82vELc8aZUxzdCQN+SEsezF7ycA5z5f/MJV5UPtw6Z+cB4bm0f
 dpQvqYpp2Lw+3NU633uPoN6IprDBgg==
 =j1e/
 -----END PGP SIGNATURE-----

Merge tag 'drm-intel-fixes-2025-11-26' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-fixes

- Reject async flips when PSR's selective fetch is enabled (Ville)

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/aScgY8QMjmyJRBX2@intel.com

drivers/gpu/drm/i915/display/intel_display.c

@@ -5964,6 +5964,14 @@ static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
 		return -EINVAL;
 	}
 
+	/* FIXME: selective fetch should be disabled for async flips */
+	if (new_crtc_state->enable_psr2_sel_fetch) {
+		drm_dbg_kms(display->drm,
+			    "[CRTC:%d:%s] async flip disallowed with PSR2 selective fetch\n",
+			    crtc->base.base.id, crtc->base.name);
+		return -EINVAL;
+	}
+
 	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
 					     new_plane_state, i) {
 		if (plane->pipe != crtc->pipe)

drivers/gpu/drm/i915/display/intel_psr.c

@@ -1256,12 +1256,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	if (crtc_state->uapi.async_flip) {
-		drm_dbg_kms(display->drm,
-			    "PSR2 sel fetch not enabled, async flip enabled\n");
-		return false;
-	}
-
 	return crtc_state->enable_psr2_sel_fetch = true;
 }