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iommu/amd: Rearrange GCR3 table setup code
Consolidate GCR3 table related code in one place so that its easy to maintain. Note that this patch doesn't move __set_gcr3/__clear_gcr3. We are moving GCR3 table from per domain to per device. Following series will rework these functions. During that time I will move these functions as well. No functional changes intended. Signed-off-by: Vasant Hegde <vasant.hegde@amd.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Link: https://lore.kernel.org/r/20240205115615.6053-9-vasant.hegde@amd.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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@ -1714,6 +1714,38 @@ static int setup_gcr3_table(struct protection_domain *domain, int pasids)
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return 0;
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}
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static u64 *__get_gcr3_pte(u64 *root, int level, u32 pasid, bool alloc)
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{
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int index;
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u64 *pte;
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while (true) {
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index = (pasid >> (9 * level)) & 0x1ff;
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pte = &root[index];
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if (level == 0)
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break;
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if (!(*pte & GCR3_VALID)) {
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if (!alloc)
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return NULL;
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root = (void *)get_zeroed_page(GFP_ATOMIC);
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if (root == NULL)
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return NULL;
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*pte = iommu_virt_to_phys(root) | GCR3_VALID;
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}
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root = iommu_phys_to_virt(*pte & PAGE_MASK);
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level -= 1;
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}
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return pte;
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}
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static void set_dte_entry(struct amd_iommu *iommu,
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struct iommu_dev_data *dev_data)
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{
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@ -2737,38 +2769,6 @@ int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid)
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return ret;
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}
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static u64 *__get_gcr3_pte(u64 *root, int level, u32 pasid, bool alloc)
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{
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int index;
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u64 *pte;
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while (true) {
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index = (pasid >> (9 * level)) & 0x1ff;
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pte = &root[index];
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if (level == 0)
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break;
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if (!(*pte & GCR3_VALID)) {
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if (!alloc)
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return NULL;
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root = (void *)get_zeroed_page(GFP_ATOMIC);
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if (root == NULL)
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return NULL;
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*pte = iommu_virt_to_phys(root) | GCR3_VALID;
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}
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root = iommu_phys_to_virt(*pte & PAGE_MASK);
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level -= 1;
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}
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return pte;
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}
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static int __set_gcr3(struct protection_domain *domain, u32 pasid,
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unsigned long cr3)
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{
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