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arm64: dts: rockchip: add core dts file for rk3399pro npu
Add rk3399pro_npu.dtsi for RK3399Pro-npu. - A35 *2/ arm-pmu/ timer/ pdma/ xin24m - grf/ pmugrf/ cru/ rktimer - qos/ pmu - usb3 - tsadc - i2c0 - uart2 - pinctrl Change-Id: I2a692826274d6c66c728716865ceb0c27e35719c Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This commit is contained in:
Jianqun Xu
Tao Huang
parent
a79ff0ae89
commit
b2da189521
522
arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi
Normal file
522
arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi
Normal file
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@ -0,0 +1,522 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
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#include <dt-bindings/clock/rk1808-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/power/rk1808-power.h>
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/ {
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compatible = "rockchip,rk3399pro-npu";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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i2c0 = &i2c0;
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serial2 = &uart2;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a35", "arm,armv8";
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reg = <0x0 0x0>;
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clocks = <&cru ARMCLK>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a35", "arm,armv8";
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reg = <0x0 0x1>;
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clocks = <&cru ARMCLK>;
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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arm,no-tick-in-suspend;
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};
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xin24m: xin24m {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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usbdrd3: usb@fd000000 {
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compatible = "rockchip,rk1808-dwc3";
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clocks = <&cru SCLK_USB3_OTG0_REF>, <&cru ACLK_USB3OTG>,
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<&cru SCLK_USB3_OTG0_SUSPEND>;
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clock-names = "ref_clk", "bus_clk",
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"suspend_clk";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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usbdrd_dwc3: dwc3@fd000000 {
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compatible = "snps,dwc3";
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reg = <0x0 0xfd000000 0x0 0x200000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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dr_mode = "otg";
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phys = <&u2phy_otg>;
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phy-names = "usb2-phy";
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phy_type = "utmi_wide";
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snps,dis_enblslpm_quirk;
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snps,dis-u2-freeclk-exists-quirk;
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snps,dis_u2_susphy_quirk;
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snps,dis-del-phy-power-chg-quirk;
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snps,tx-ipgap-linecheck-dis-quirk;
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status = "disabled";
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};
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};
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grf: syscon@fe000000 {
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compatible = "rockchip,rk1808-grf", "syscon", "simple-mfd";
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reg = <0x0 0xfe000000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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io_domains: io-domains {
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compatible = "rockchip,rk1808-io-voltage-domain";
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status = "disabled";
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};
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};
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usb2phy_grf: syscon@fe010000 {
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compatible = "rockchip,rk1808-usb2phy-grf", "syscon",
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"simple-mfd";
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reg = <0x0 0xfe010000 0x0 0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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u2phy: usb2-phy@100 {
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compatible = "rockchip,rk1808-usb2phy";
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reg = <0x100 0x10>;
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clocks = <&cru SCLK_USBPHY_REF>;
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clock-names = "phyclk";
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#clock-cells = <0>;
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assigned-clocks = <&cru USB480M>;
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assigned-clock-parents = <&u2phy>;
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clock-output-names = "usb480m_phy";
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status = "disabled";
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u2phy_host: host-port {
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#phy-cells = <0>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "linestate";
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status = "disabled";
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};
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u2phy_otg: otg-port {
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#phy-cells = <0>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "otg-bvalid", "otg-id",
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"linestate";
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status = "disabled";
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};
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};
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};
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pmugrf: syscon@fe410000 {
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compatible = "rockchip,rk1808-pmugrf", "syscon", "simple-mfd";
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reg = <0x0 0xfe410000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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pmu_io_domains: io-domains {
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compatible = "rockchip,rk1808-pmu-io-voltage-domain";
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status = "disabled";
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};
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};
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qos_npu: qos@fe850000 {
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compatible = "syscon";
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reg = <0x0 0xfe850000 0x0 0x20>;
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};
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qos_pcie: qos@fe880000 {
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compatible = "syscon";
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reg = <0x0 0xfe880000 0x0 0x20>;
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};
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qos_isp: qos@fe8a0000 {
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compatible = "syscon";
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reg = <0x0 0xfe8a0000 0x0 0x20>;
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};
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qos_rga_rd: qos@fe8a0080 {
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compatible = "syscon";
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reg = <0x0 0xfe8a0080 0x0 0x20>;
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};
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qos_rga_wr: qos@fe8a0100 {
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compatible = "syscon";
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reg = <0x0 0xfe8a0100 0x0 0x20>;
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};
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qos_vip: qos@fe8a0180 {
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compatible = "syscon";
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reg = <0x0 0xfe8a0180 0x0 0x20>;
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};
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qos_vop_dma: qos@fe8b0000 {
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compatible = "syscon";
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reg = <0x0 0xfe8b0000 0x0 0x20>;
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};
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qos_vop_lite: qos@fe8b0080 {
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compatible = "syscon";
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reg = <0x0 0xfe8b0080 0x0 0x20>;
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};
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qos_vpu: qos@fe8cc000 {
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compatible = "syscon";
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reg = <0x0 0xfe8c000 0x0 0x20>;
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};
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gic: interrupt-controller@ff100000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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reg = <0x0 0xff100000 0 0x10000>, /* GICD */
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<0x0 0xff140000 0 0xc0000>, /* GICR */
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<0x0 0xff300000 0 0x10000>, /* GICC */
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<0x0 0xff310000 0 0x10000>, /* GICH */
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<0x0 0xff320000 0 0x10000>; /* GICV */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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its: interrupt-controller@ff120000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x0 0xff120000 0x0 0x20000>;
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};
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};
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cru: clock-controller@ff350000 {
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compatible = "rockchip,rk1808-cru";
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reg = <0x0 0xff350000 0x0 0x5000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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assigned-clocks =
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<&cru PLL_GPLL>, <&cru PLL_CPLL>,
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<&cru PLL_PPLL>, <&cru ARMCLK>,
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<&cru MSCLK_PERI>, <&cru LSCLK_PERI>,
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<&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>,
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<&cru LSCLK_BUS_PRE>;
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assigned-clock-rates =
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<1200000000>, <1000000000>,
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<416000000>, <816000000>,
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<200000000>, <100000000>,
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<300000000>, <200000000>,
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<100000000>;
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};
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tsadc: tsadc@ff3a0000 {
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compatible = "rockchip,rk1808-tsadc";
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reg = <0x0 0xff3a0000 0x0 0x100>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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rockchip,grf = <&grf>;
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clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
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clock-names = "tsadc", "apb_pclk";
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assigned-clocks = <&cru SCLK_TSADC>;
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assigned-clock-rates = <50000>;
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resets = <&cru SRST_TSADC>;
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reset-names = "tsadc-apb";
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#thermal-sensor-cells = <1>;
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rockchip,hw-tshut-temp = <120000>;
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status = "disabled";
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};
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pmu: power-management@ff3e0000 {
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compatible = "rockchip,rk1808-pmu", "syscon", "simple-mfd";
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reg = <0x0 0xff3e0000 0x0 0x1000>;
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power: power-controller {
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compatible = "rockchip,rk1808-power-controller";
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#power-domain-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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/* These power domains are grouped by VD_NPU */
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pd_npu@RK1808_VD_NPU {
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reg = <RK1808_VD_NPU>;
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clocks = <&cru SCLK_NPU>,
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<&cru ACLK_NPU>,
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<&cru HCLK_NPU>;
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pm_qos = <&qos_npu>;
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};
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/* These power domains are grouped by VD_LOGIC */
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pd_pcie@RK1808_PD_PCIE {
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reg = <RK1808_PD_PCIE>;
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clocks = <&cru HSCLK_PCIE>,
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<&cru LSCLK_PCIE>,
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<&cru ACLK_PCIE>,
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<&cru ACLK_PCIE_MST>,
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<&cru ACLK_PCIE_SLV>,
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<&cru PCLK_PCIE>,
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<&cru SCLK_PCIE_AUX>;
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pm_qos = <&qos_pcie>;
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};
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pd_vpu@RK1808_PD_VPU {
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reg = <RK1808_PD_VPU>;
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clocks = <&cru ACLK_VPU>,
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<&cru HCLK_VPU>;
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pm_qos = <&qos_vpu>;
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};
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pd_vio@RK1808_PD_VIO {
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reg = <RK1808_PD_VIO>;
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clocks = <&cru HSCLK_VIO>,
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<&cru LSCLK_VIO>,
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<&cru ACLK_VOPRAW>,
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<&cru HCLK_VOPRAW>,
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<&cru ACLK_VOPLITE>,
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<&cru HCLK_VOPLITE>,
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<&cru PCLK_DSI_TX>,
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<&cru PCLK_CSI_TX>,
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<&cru ACLK_RGA>,
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<&cru HCLK_RGA>,
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<&cru ACLK_ISP>,
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<&cru HCLK_ISP>,
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<&cru ACLK_CIF>,
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<&cru HCLK_CIF>,
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<&cru PCLK_CSI2HOST>,
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<&cru DCLK_VOPRAW>,
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<&cru DCLK_VOPLITE>;
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pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
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<&qos_isp>, <&qos_vip>,
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<&qos_vop_dma>, <&qos_vop_lite>;
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};
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};
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};
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i2c0: i2c@ff410000 {
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compatible = "rockchip,rk3399-i2c";
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reg = <0x0 0xff410000 0x0 0x1000>;
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clocks = <&cru SCLK_PMU_I2C0>, <&cru PCLK_I2C0_PMU>;
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clock-names = "i2c", "pclk";
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_xfer>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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pdma: pdma@ff4e0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x0 0xff4e0000 0x0 0x4000>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_DMAC>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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peripherals-req-type-burst;
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};
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uart2: serial@ff550000 {
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compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff550000 0x0 0x100>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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dmas = <&pdma 4>, <&pdma 5>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&uart2m0_xfer>;
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status = "disabled";
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};
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rktimer: rktimer@ff700000 {
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compatible = "rockchip,rk3288-timer";
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reg = <0x0 0xff700000 0x0 0x1000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
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clock-names = "pclk", "timer";
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};
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npu: npu@ffbc0000 {
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compatible = "rockchip,npu";
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reg = <0x0 0xffbc0000 0x0 0x1000>;
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clocks = <&cru SCLK_NPU>, <&cru HCLK_NPU>;
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clock-names = "sclk_npu", "hclk_npu";
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rk1808-pinctrl";
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rockchip,grf = <&grf>;
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rockchip,pmu = <&pmugrf>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio0: gpio0@ff4c0000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xff4c0000 0x0 0x100>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_PMU_GPIO0>, <&cru PCLK_GPIO0_PMU>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio1@ff690000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xff690000 0x0 0x100>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_GPIO1>, <&cru PCLK_GPIO1>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
|
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#interrupt-cells = <2>;
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};
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gpio2: gpio2@ff6a0000 {
|
||||
compatible = "rockchip,gpio-bank";
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reg = <0x0 0xff6a0000 0x0 0x100>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_GPIO2>, <&cru PCLK_GPIO2>;
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||||
gpio-controller;
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#gpio-cells = <2>;
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||||
|
||||
interrupt-controller;
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#interrupt-cells = <2>;
|
||||
};
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||||
|
||||
gpio3: gpio3@ff6b0000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xff6b0000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_GPIO3>, <&cru PCLK_GPIO3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
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||||
|
||||
gpio4: gpio4@ff6c0000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xff6c0000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_GPIO4>, <&cru PCLK_GPIO4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pcfg_pull_none: pcfg-pull-none {
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pcfg_pull_none_smt: pcfg-pull-none-smt {
|
||||
bias-disable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
i2c0 {
|
||||
i2c0_xfer: i2c0-xfer {
|
||||
rockchip,pins =
|
||||
/* i2c0_sda */
|
||||
<0 RK_PB1 1 &pcfg_pull_none_smt>,
|
||||
/* i2c0_scl */
|
||||
<0 RK_PB0 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
};
|
||||
|
||||
pciusb {
|
||||
pciusb_pins: pciusb-pins {
|
||||
rockchip,pins =
|
||||
/* pciusb_debug0 */
|
||||
<4 RK_PB4 3 &pcfg_pull_none>,
|
||||
/* pciusb_debug1 */
|
||||
<4 RK_PB5 3 &pcfg_pull_none>,
|
||||
/* pciusb_debug2 */
|
||||
<4 RK_PB6 3 &pcfg_pull_none>,
|
||||
/* pciusb_debug3 */
|
||||
<4 RK_PB7 3 &pcfg_pull_none>,
|
||||
/* pciusb_debug4 */
|
||||
<4 RK_PC0 3 &pcfg_pull_none>,
|
||||
/* pciusb_debug5 */
|
||||
<4 RK_PC1 3 &pcfg_pull_none>,
|
||||
/* pciusb_debug6 */
|
||||
<4 RK_PC2 3 &pcfg_pull_none>,
|
||||
/* pciusb_debug7 */
|
||||
<4 RK_PC3 3 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
uart2m0_xfer: uart2m0-xfer {
|
||||
rockchip,pins =
|
||||
/* uart2_rxm0 */
|
||||
<4 RK_PA3 2 &pcfg_pull_none>,
|
||||
/* uart2_txm0 */
|
||||
<4 RK_PA2 2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart2m1_xfer: uart2m1-xfer {
|
||||
rockchip,pins =
|
||||
/* uart2_rxm1 */
|
||||
<2 RK_PD1 2 &pcfg_pull_none>,
|
||||
/* uart2_txm1 */
|
||||
<2 RK_PD0 2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart2m2_xfer: uart2m2-xfer {
|
||||
rockchip,pins =
|
||||
/* uart2_rxm2 */
|
||||
<3 RK_PA4 2 &pcfg_pull_none>,
|
||||
/* uart2_txm2 */
|
||||
<3 RK_PA3 2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
tsadc {
|
||||
tsadc_otp_gpio: tsadc-otp-gpio {
|
||||
rockchip,pins =
|
||||
<0 RK_PA6 0 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
tsadc_otp_out: tsadc-otp-out {
|
||||
rockchip,pins =
|
||||
<0 RK_PA6 2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user