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mtd: rawnand: atmel: Fix pulse read timing for certain flash chips

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Prevent PMECC errors when reading from AMD/Spansion S34ML02G1 flash on
SAM9X60 SoC, after switching to ONFI timing mode 3.

From reading the S34ML02G1 and the SAM9X60 datasheets again, it seems
like we have to wait tREA after rising RE# before sampling the data.
Thus pulse must be at least tREA.

The previous approach to set this timing worked on sam9g20 and sama5d2
with the same flash (S34ML02G1), probably because those have a slower
mck clock rate and thus the resolution of the timings setup is not as
tight as with sam9x60.

The approach to fix the issue was carried over from u-boot, which itself
got it from at91bootstrap.  It has been successfully tested in
at91bootstrap, U-Boot and Linux on sam9x60 and sama5d2, for several
months here.

Link: https://github.com/linux4sam/at91bootstrap/issues/174
Link: e2dfd8141d
Link: https://lore.kernel.org/u-boot/20240415075755.780653-1-ada@thorsis.com/
Link: 344e2f2cd4
Cc: Li Bin <bin.li@microchip.com>
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
This commit is contained in:
Alexander Dahl 2025-09-04 11:14:41 +02:00 committed by Miquel Raynal
parent dfea8f7183
commit b2d2c2b8af
1 changed files with 9 additions and 4 deletions
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13
drivers/mtd/nand/raw/atmel/nand-controller.c
View File

@ -1240,7 +1240,7 @@ static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
const struct nand_interface_config *conf,
struct atmel_smc_cs_conf *smcconf)
{
u32 ncycles, totalcycles, timeps, mckperiodps;
u32 ncycles, totalcycles, timeps, mckperiodps, pulse;
struct atmel_nand_controller *nc;
int ret;
@ -1366,11 +1366,16 @@ static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
/*
* Read pulse timing directly matches tRP:
* Read pulse timing would directly match tRP,
* but some NAND flash chips (S34ML01G2 and W29N02KVxxAF)
* do not work properly in timing mode 3.
* The workaround is to extend the SMC NRD pulse to meet tREA
* timing.
*
* NRD_PULSE = tRP
* NRD_PULSE = max(tRP, tREA)
*/
ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
pulse = max(conf->timings.sdr.tRP_min, conf->timings.sdr.tREA_max);
ncycles = DIV_ROUND_UP(pulse, mckperiodps);
totalcycles += ncycles;
ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
ncycles);