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Merge remote-tracking branch 'origin/develop-3.0' into develop-3.0-jb

Browse Source 
Conflicts:
	include/net/cfg80211.h
This commit is contained in:
黄涛 2012-08-21 14:14:24 +08:00
commit b2be450f10
489 changed files with 240850 additions and 4943 deletions
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2
Makefile
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@ -1230,7 +1230,7 @@ rpm: include/config/kernel.release FORCE
# Brief documentation of the typical targets used
# ---------------------------------------------------------------------------
boards := $(wildcard $(srctree)/arch/$(SRCARCH)/configs/*_defconfig)
boards := $(wildcard $(srctree)/arch/$(SRCARCH)/configs/rk*_defconfig)
boards := $(notdir $(boards))
board-dirs := $(dir $(wildcard $(srctree)/arch/$(SRCARCH)/configs/*/*_defconfig))
board-dirs := $(sort $(notdir $(board-dirs:/=)))

25
arch/arm/Kconfig
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@ -871,6 +871,17 @@ config ARCH_RK29
help
Support for Rockchip's RK29xx SoCs.
config ARCH_RK2928
bool "Rockchip RK2928"
select PLAT_RK
select CPU_V7
select ARM_GIC
select RK_PL330_DMA
select MIGHT_HAVE_CACHE_L2X0
select ARM_ERRATA_754322
help
Support for Rockchip's RK2928 SoCs.
config ARCH_RK30
bool "Rockchip RK30xx"
select PLAT_RK
@ -884,6 +895,19 @@ config ARCH_RK30
help
Support for Rockchip's RK30xx SoCs.
config ARCH_RK31
bool "Rockchip RK31xx"
select PLAT_RK
select CPU_V7
select ARM_GIC
select RK_PL330_DMA
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
select ARM_ERRATA_764369
select ARM_ERRATA_754322
help
Support for Rockchip's RK31xx SoCs.
config PLAT_SPEAR
bool "ST SPEAr"
select ARM_AMBA
@ -986,6 +1010,7 @@ source "arch/arm/mach-realview/Kconfig"
source "arch/arm/plat-rk/Kconfig"
source "arch/arm/mach-rk29/Kconfig"
source "arch/arm/mach-rk2928/Kconfig"
source "arch/arm/mach-rk30/Kconfig"
source "arch/arm/mach-sa1100/Kconfig"

2
arch/arm/Makefile
View File

@ -172,7 +172,9 @@ machine-$(CONFIG_ARCH_PNX4008) := pnx4008
machine-$(CONFIG_ARCH_PXA) := pxa
machine-$(CONFIG_ARCH_REALVIEW) := realview
machine-$(CONFIG_ARCH_RK29) := rk29
machine-$(CONFIG_ARCH_RK2928) := rk2928
machine-$(CONFIG_ARCH_RK30) := rk30
machine-$(CONFIG_ARCH_RK31) := rk30
machine-$(CONFIG_ARCH_RPC) := rpc
machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443
machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0

6
arch/arm/common/pl330.c
View File

@ -379,11 +379,11 @@ static inline u32 get_id(struct pl330_info *pi, u32 off)
void __iomem *regs = pi->base;
u32 id = 0;
#ifdef CONFIG_ARCH_RK30
#ifdef CONFIG_PLAT_RK
id |= ((readl(regs + off + 0x0) & 0xff) << 0);
id |= ((readl(regs + off + 0x4) & 0xff)<< 8);
id |= ((readl(regs + off + 0x4) & 0xff) << 8);
id |= ((readl(regs + off + 0x8) & 0xff) << 16);
id |= ((readl(regs + off + 0xc) & 0xff)<< 24);
id |= ((readl(regs + off + 0xc) & 0xff) << 24);
#else
id |= (readb(regs + off + 0x0) << 0);
id |= (readb(regs + off + 0x4) << 8);

398
arch/arm/configs/rk2928_a720_defconfig Normal file
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@ -0,0 +1,398 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_KERNEL_LZO=y
CONFIG_LOG_BUF_SHIFT=19
CONFIG_CGROUPS=y
CONFIG_CGROUP_DEBUG=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_RESOURCE_COUNTERS=y
CONFIG_CGROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_PANIC_TIMEOUT=1
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_ELF_CORE is not set
CONFIG_ASHMEM=y
# CONFIG_AIO is not set
CONFIG_EMBEDDED=y
# CONFIG_SLUB_DEBUG is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_ARCH_RK2928=y
CONFIG_RK_CLOCK_PROC=y
CONFIG_RK_DEBUG_UART=0
CONFIG_MACH_RK2928_A720=y
CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
CONFIG_FIQ_DEBUGGER_CONSOLE=y
CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_HIGHMEM=y
CONFIG_COMPACTION=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_IDLE=y
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_WAKELOCK=y
CONFIG_PM_RUNTIME=y
CONFIG_SUSPEND_TIME=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_INET_ESP=y
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_INET6_AH=y
CONFIG_INET6_ESP=y
CONFIG_INET6_IPCOMP=y
CONFIG_IPV6_MIP6=y
CONFIG_IPV6_TUNNEL=y
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_NETFILTER=y
CONFIG_NF_CONNTRACK=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=y
CONFIG_NF_CONNTRACK_FTP=y
CONFIG_NF_CONNTRACK_H323=y
CONFIG_NF_CONNTRACK_IRC=y
CONFIG_NF_CONNTRACK_NETBIOS_NS=y
CONFIG_NF_CONNTRACK_PPTP=y
CONFIG_NF_CONNTRACK_SANE=y
CONFIG_NF_CONNTRACK_SIP=y
CONFIG_NF_CONNTRACK_TFTP=y
CONFIG_NF_CT_NETLINK=y
CONFIG_NETFILTER_TPROXY=y
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
CONFIG_NETFILTER_XT_TARGET_MARK=y
CONFIG_NETFILTER_XT_TARGET_NFLOG=y
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
CONFIG_NETFILTER_XT_TARGET_TPROXY=y
CONFIG_NETFILTER_XT_TARGET_TRACE=y
CONFIG_NETFILTER_XT_MATCH_COMMENT=y
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
CONFIG_NETFILTER_XT_MATCH_HELPER=y
CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
CONFIG_NETFILTER_XT_MATCH_LENGTH=y
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
CONFIG_NETFILTER_XT_MATCH_MAC=y
CONFIG_NETFILTER_XT_MATCH_MARK=y
CONFIG_NETFILTER_XT_MATCH_POLICY=y
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
CONFIG_NETFILTER_XT_MATCH_QUOTA=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
CONFIG_NETFILTER_XT_MATCH_SOCKET=y
CONFIG_NETFILTER_XT_MATCH_STATE=y
CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
CONFIG_NETFILTER_XT_MATCH_STRING=y
CONFIG_NETFILTER_XT_MATCH_TIME=y
CONFIG_NETFILTER_XT_MATCH_U32=y
CONFIG_NF_CONNTRACK_IPV4=y
CONFIG_IP_NF_IPTABLES=y
CONFIG_IP_NF_MATCH_AH=y
CONFIG_IP_NF_MATCH_ECN=y
CONFIG_IP_NF_MATCH_TTL=y
CONFIG_IP_NF_FILTER=y
CONFIG_IP_NF_TARGET_REJECT=y
CONFIG_IP_NF_TARGET_REJECT_SKERR=y
CONFIG_IP_NF_TARGET_LOG=y
CONFIG_NF_NAT=y
CONFIG_IP_NF_TARGET_MASQUERADE=y
CONFIG_IP_NF_TARGET_NETMAP=y
CONFIG_IP_NF_TARGET_REDIRECT=y
CONFIG_IP_NF_MANGLE=y
CONFIG_IP_NF_RAW=y
CONFIG_IP_NF_ARPTABLES=y
CONFIG_IP_NF_ARPFILTER=y
CONFIG_IP_NF_ARP_MANGLE=y
CONFIG_NF_CONNTRACK_IPV6=y
CONFIG_IP6_NF_IPTABLES=y
CONFIG_IP6_NF_TARGET_LOG=y
CONFIG_IP6_NF_FILTER=y
CONFIG_IP6_NF_TARGET_REJECT=y
CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
CONFIG_IP6_NF_MANGLE=y
CONFIG_IP6_NF_RAW=y
CONFIG_BRIDGE=y
# CONFIG_BRIDGE_IGMP_SNOOPING is not set
CONFIG_PHONET=y
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=y
CONFIG_NET_SCH_INGRESS=y
CONFIG_NET_CLS_U32=y
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_U32=y
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=y
CONFIG_NET_ACT_GACT=y
CONFIG_NET_ACT_MIRRED=y
CONFIG_BT=y
CONFIG_BT_L2CAP=y
CONFIG_BT_SCO=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=y
CONFIG_BT_HIDP=y
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIBCM4325=y
CONFIG_BT_AUTOSLEEP=y
CONFIG_CFG80211=y
CONFIG_MAC80211=y
CONFIG_RFKILL=y
CONFIG_RFKILL_RK=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_FIRMWARE_IN_KERNEL is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND_IDS=y
CONFIG_MTD_RKNAND=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_MISC_DEVICES=y
CONFIG_UID_STAT=y
CONFIG_APANIC=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_MULTI_LUN=y
CONFIG_MD=y
CONFIG_BLK_DEV_DM=y
CONFIG_DM_CRYPT=y
CONFIG_DM_UEVENT=y
CONFIG_NETDEVICES=y
CONFIG_PHYLIB=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
CONFIG_WLAN_80211=y
CONFIG_RTL8188EU=y
CONFIG_USB_USBNET=y
CONFIG_PPP=y
CONFIG_PPP_MULTILINK=y
CONFIG_PPP_FILTER=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_SYNC_TTY=y
CONFIG_PPP_DEFLATE=y
CONFIG_PPP_BSDCOMP=y
CONFIG_PPP_MPPE=y
CONFIG_PPPOLAC=y
CONFIG_PPPOPNS=y
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_KEYRESET=y
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_JOYSTICK=y
CONFIG_INPUT_TABLET=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_SITRONIX_A720=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_KEYCHORD=y
CONFIG_INPUT_UINPUT=y
CONFIG_GS_MMA7660=y
CONFIG_SENSOR_DEVICE=y
CONFIG_GSENSOR_DEVICE=y
# CONFIG_SERIO is not set
# CONFIG_CONSOLE_TRANSLATIONS is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C0_CONTROLLER_RK30=y
CONFIG_I2C1_CONTROLLER_RK30=y
CONFIG_I2C2_CONTROLLER_RK30=y
CONFIG_I2C3_CONTROLLER_RK30=y
CONFIG_ADC_RK30=y
CONFIG_EXPANDED_GPIO_NUM=0
CONFIG_EXPANDED_GPIO_IRQ_NUM=0
CONFIG_SPI_FPGA_GPIO_NUM=0
CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
CONFIG_POWER_SUPPLY=y
CONFIG_TEST_POWER=y
# CONFIG_HWMON is not set
CONFIG_MFD_TPS65910=y
CONFIG_MFD_TPS65090=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_TPS65910=y
CONFIG_RK30_PWM_REGULATOR=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_VIDEO_DEV=y
CONFIG_SOC_CAMERA=y
CONFIG_SOC_CAMERA_OV2659=y
CONFIG_VIDEO_RK29=y
CONFIG_VIDEO_RK29_CAMMEM_ION=y
CONFIG_ION=y
CONFIG_ION_ROCKCHIP=y
CONFIG_FB=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_DISPLAY_SUPPORT=y
CONFIG_LCD_RK2928_A720=y
CONFIG_FB_ROCKCHIP=y
CONFIG_LCDC_RK2928=y
CONFIG_RGA_RK30=y
CONFIG_RK_LVDS=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_BMP is not set
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_ARM is not set
CONFIG_SND_SOC=y
CONFIG_SND_RK29_SOC=y
CONFIG_SND_I2S_DMA_EVENT_STATIC=y
CONFIG_SND_RK_SOC_RK2928=y
CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
CONFIG_HID_A4TECH=y
CONFIG_HID_ACRUX=y
CONFIG_HID_ACRUX_FF=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
CONFIG_HID_CHERRY=y
CONFIG_HID_CHICONY=y
CONFIG_HID_CYPRESS=y
CONFIG_HID_DRAGONRISE=y
CONFIG_DRAGONRISE_FF=y
CONFIG_HID_EMS_FF=y
CONFIG_HID_ELECOM=y
CONFIG_HID_EZKEY=y
CONFIG_HID_KEYTOUCH=y
CONFIG_HID_KYE=y
CONFIG_HID_UCLOGIC=y
CONFIG_HID_WALTOP=y
CONFIG_HID_GYRATION=y
CONFIG_HID_TWINHAN=y
CONFIG_HID_KENSINGTON=y
CONFIG_HID_LCPOWER=y
CONFIG_HID_LOGITECH=y
CONFIG_LOGITECH_FF=y
CONFIG_LOGIRUMBLEPAD2_FF=y
CONFIG_LOGIG940_FF=y
CONFIG_LOGIWII_FF=y
CONFIG_HID_MAGICMOUSE=y
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
CONFIG_HID_MULTITOUCH=y
CONFIG_HID_NTRIG=y
CONFIG_HID_ORTEK=y
CONFIG_HID_PANTHERLORD=y
CONFIG_PANTHERLORD_FF=y
CONFIG_HID_PETALYNX=y
CONFIG_HID_PICOLCD=y
CONFIG_HID_QUANTA=y
CONFIG_HID_ROCCAT_ARVO=y
CONFIG_HID_ROCCAT_KONE=y
CONFIG_HID_ROCCAT_KONEPLUS=y
CONFIG_HID_ROCCAT_KOVAPLUS=y
CONFIG_HID_ROCCAT_PYRA=y
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SONY=y
CONFIG_HID_SUNPLUS=y
CONFIG_HID_GREENASIA=y
CONFIG_GREENASIA_FF=y
CONFIG_HID_SMARTJOYPLUS=y
CONFIG_SMARTJOYPLUS_FF=y
CONFIG_HID_TOPSEED=y
CONFIG_HID_THRUSTMASTER=y
CONFIG_THRUSTMASTER_FF=y
CONFIG_HID_WACOM=y
CONFIG_HID_ZEROPLUS=y
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=y
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_OTG_BLACKLIST_HUB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_OPTION=y
CONFIG_USB_GADGET=y
CONFIG_USB20_HOST=y
CONFIG_USB20_OTG=y
CONFIG_MMC=y
CONFIG_MMC_UNSAFE_RESUME=y
CONFIG_MMC_EMBEDDED_SDIO=y
CONFIG_MMC_PARANOID_SD_INIT=y
CONFIG_SDMMC_RK29=y
# CONFIG_SDMMC1_RK29 is not set
CONFIG_SWITCH=y
CONFIG_SWITCH_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_TPS65910_RTC=y
CONFIG_STAGING=y
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_ANDROID_LOGGER=y
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
# CONFIG_CMMB is not set
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set
CONFIG_EXT4_FS=y
# CONFIG_EXT4_FS_XATTR is not set
# CONFIG_DNOTIFY is not set
CONFIG_FUSE_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_EFI_PARTITION=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set
CONFIG_CRYPTO_TWOFISH=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set

119
arch/arm/configs/rk2928_fpga_defconfig Normal file
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@ -0,0 +1,119 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_KERNEL_LZO=y
CONFIG_LOG_BUF_SHIFT=19
CONFIG_CGROUPS=y
CONFIG_CGROUP_DEBUG=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_RESOURCE_COUNTERS=y
CONFIG_CGROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="root"
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_PANIC_TIMEOUT=1
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_ELF_CORE is not set
CONFIG_ASHMEM=y
# CONFIG_AIO is not set
CONFIG_EMBEDDED=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_ARCH_RK2928=y
# CONFIG_DDR_TEST is not set
# CONFIG_RK29_LAST_LOG is not set
CONFIG_RK_DEBUG_UART=0
CONFIG_MACH_RK2928_FPGA=y
# CONFIG_CACHE_L2X0 is not set
CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
CONFIG_FIQ_DEBUGGER_CONSOLE=y
CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_HIGHMEM=y
CONFIG_COMPACTION=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init debug"
CONFIG_CPU_IDLE=y
CONFIG_VFP=y
CONFIG_WAKELOCK=y
CONFIG_PM_RUNTIME=y
CONFIG_SUSPEND_TIME=y
CONFIG_NET=y
CONFIG_UNIX=y
# CONFIG_NET_ACTIVITY_STATS is not set
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_FIRMWARE_IN_KERNEL is not set
CONFIG_MTD=y
CONFIG_MISC_DEVICES=y
# CONFIG_ANDROID_PMEM is not set
CONFIG_INPUT_POLLDEV=y
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_CONSOLE_TRANSLATIONS is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C0_CONTROLLER_RK30=y
CONFIG_I2C2_CONTROLLER_RK30=y
# CONFIG_I2C3_RK30 is not set
# CONFIG_ADC is not set
CONFIG_EXPANDED_GPIO_NUM=0
CONFIG_EXPANDED_GPIO_IRQ_NUM=0
CONFIG_SPI_FPGA_GPIO_NUM=0
CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
# CONFIG_HWMON is not set
# CONFIG_MFD_SUPPORT is not set
CONFIG_MEDIA_SUPPORT=y
CONFIG_VIDEO_DEV=y
CONFIG_SOC_CAMERA=y
CONFIG_SOC_CAMERA_OV2659=y
CONFIG_SOC_CAMERA_OV5642=y
CONFIG_VIDEO_RK29=y
CONFIG_VIDEO_RK29_CAMMEM_ION=y
CONFIG_ION=y
CONFIG_ION_ROCKCHIP=y
CONFIG_FB=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
CONFIG_DISPLAY_SUPPORT=y
CONFIG_LCD_TD043MGEA1=y
CONFIG_FB_ROCKCHIP=y
CONFIG_LCDC_RK2928=y
# CONFIG_THREE_FB_BUFFER is not set
CONFIG_RGA_RK30=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_RTC_CLASS=y
# CONFIG_CMMB is not set
# CONFIG_DNOTIFY is not set
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
CONFIG_SLUB_DEBUG_ON=y
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set

398
arch/arm/configs/rk2928_sdk_defconfig Executable file
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@ -0,0 +1,398 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_KERNEL_LZO=y
CONFIG_LOG_BUF_SHIFT=19
CONFIG_CGROUPS=y
CONFIG_CGROUP_DEBUG=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_RESOURCE_COUNTERS=y
CONFIG_CGROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_PANIC_TIMEOUT=1
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_ELF_CORE is not set
CONFIG_ASHMEM=y
# CONFIG_AIO is not set
CONFIG_EMBEDDED=y
# CONFIG_SLUB_DEBUG is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_ARCH_RK2928=y
CONFIG_WIFI_CONTROL_FUNC=y
CONFIG_RK_DEBUG_UART=2
CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
CONFIG_FIQ_DEBUGGER_CONSOLE=y
CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_HIGHMEM=y
CONFIG_COMPACTION=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init"
CONFIG_CPU_IDLE=y
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_WAKELOCK=y
CONFIG_PM_RUNTIME=y
CONFIG_SUSPEND_TIME=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_INET_ESP=y
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_INET6_AH=y
CONFIG_INET6_ESP=y
CONFIG_INET6_IPCOMP=y
CONFIG_IPV6_MIP6=y
CONFIG_IPV6_TUNNEL=y
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_NETFILTER=y
CONFIG_NF_CONNTRACK=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=y
CONFIG_NF_CONNTRACK_FTP=y
CONFIG_NF_CONNTRACK_H323=y
CONFIG_NF_CONNTRACK_IRC=y
CONFIG_NF_CONNTRACK_NETBIOS_NS=y
CONFIG_NF_CONNTRACK_PPTP=y
CONFIG_NF_CONNTRACK_SANE=y
CONFIG_NF_CONNTRACK_SIP=y
CONFIG_NF_CONNTRACK_TFTP=y
CONFIG_NF_CT_NETLINK=y
CONFIG_NETFILTER_TPROXY=y
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
CONFIG_NETFILTER_XT_TARGET_MARK=y
CONFIG_NETFILTER_XT_TARGET_NFLOG=y
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
CONFIG_NETFILTER_XT_TARGET_TPROXY=y
CONFIG_NETFILTER_XT_TARGET_TRACE=y
CONFIG_NETFILTER_XT_MATCH_COMMENT=y
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
CONFIG_NETFILTER_XT_MATCH_HELPER=y
CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
CONFIG_NETFILTER_XT_MATCH_LENGTH=y
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
CONFIG_NETFILTER_XT_MATCH_MAC=y
CONFIG_NETFILTER_XT_MATCH_MARK=y
CONFIG_NETFILTER_XT_MATCH_POLICY=y
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
CONFIG_NETFILTER_XT_MATCH_QUOTA=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
CONFIG_NETFILTER_XT_MATCH_SOCKET=y
CONFIG_NETFILTER_XT_MATCH_STATE=y
CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
CONFIG_NETFILTER_XT_MATCH_STRING=y
CONFIG_NETFILTER_XT_MATCH_TIME=y
CONFIG_NETFILTER_XT_MATCH_U32=y
CONFIG_NF_CONNTRACK_IPV4=y
CONFIG_IP_NF_IPTABLES=y
CONFIG_IP_NF_MATCH_AH=y
CONFIG_IP_NF_MATCH_ECN=y
CONFIG_IP_NF_MATCH_TTL=y
CONFIG_IP_NF_FILTER=y
CONFIG_IP_NF_TARGET_REJECT=y
CONFIG_IP_NF_TARGET_REJECT_SKERR=y
CONFIG_IP_NF_TARGET_LOG=y
CONFIG_NF_NAT=y
CONFIG_IP_NF_TARGET_MASQUERADE=y
CONFIG_IP_NF_TARGET_NETMAP=y
CONFIG_IP_NF_TARGET_REDIRECT=y
CONFIG_IP_NF_MANGLE=y
CONFIG_IP_NF_RAW=y
CONFIG_IP_NF_ARPTABLES=y
CONFIG_IP_NF_ARPFILTER=y
CONFIG_IP_NF_ARP_MANGLE=y
CONFIG_NF_CONNTRACK_IPV6=y
CONFIG_IP6_NF_IPTABLES=y
CONFIG_IP6_NF_TARGET_LOG=y
CONFIG_IP6_NF_FILTER=y
CONFIG_IP6_NF_TARGET_REJECT=y
CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
CONFIG_IP6_NF_MANGLE=y
CONFIG_IP6_NF_RAW=y
CONFIG_BRIDGE=y
# CONFIG_BRIDGE_IGMP_SNOOPING is not set
CONFIG_PHONET=y
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=y
CONFIG_NET_SCH_INGRESS=y
CONFIG_NET_CLS_U32=y
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_U32=y
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=y
CONFIG_NET_ACT_GACT=y
CONFIG_NET_ACT_MIRRED=y
CONFIG_BT=y
CONFIG_BT_L2CAP=y
CONFIG_BT_SCO=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=y
CONFIG_BT_HIDP=y
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIBCM4325=y
CONFIG_BT_AUTOSLEEP=y
CONFIG_RFKILL=y
CONFIG_RFKILL_RK=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_FIRMWARE_IN_KERNEL is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND_IDS=y
CONFIG_MTD_RKNAND=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_MISC_DEVICES=y
CONFIG_UID_STAT=y
CONFIG_APANIC=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_MULTI_LUN=y
CONFIG_MD=y
CONFIG_BLK_DEV_DM=y
CONFIG_DM_CRYPT=y
CONFIG_DM_UEVENT=y
CONFIG_NETDEVICES=y
CONFIG_PHYLIB=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
CONFIG_WLAN_80211=y
CONFIG_RKWIFI=y
CONFIG_USB_USBNET=y
CONFIG_PPP=y
CONFIG_PPP_MULTILINK=y
CONFIG_PPP_FILTER=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_SYNC_TTY=y
CONFIG_PPP_DEFLATE=y
CONFIG_PPP_BSDCOMP=y
CONFIG_PPP_MPPE=y
CONFIG_PPPOLAC=y
CONFIG_PPPOPNS=y
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_KEYRESET=y
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_JOYSTICK=y
CONFIG_INPUT_TABLET=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_EETI_EGALAX=y
CONFIG_EETI_EGALAX_MAX_X=1087
CONFIG_EETI_EGALAX_MAX_Y=800
CONFIG_INPUT_MISC=y
CONFIG_INPUT_KEYCHORD=y
CONFIG_INPUT_UINPUT=y
CONFIG_COMPASS_AK8975=y
CONFIG_GS_MMA8452=y
CONFIG_GYRO_L3G4200D=y
CONFIG_LS_CM3217=y
CONFIG_SENSOR_DEVICE=y
CONFIG_GSENSOR_DEVICE=y
CONFIG_COMPASS_DEVICE=y
CONFIG_GYROSCOPE_DEVICE=y
CONFIG_LIGHT_DEVICE=y
# CONFIG_SERIO is not set
# CONFIG_CONSOLE_TRANSLATIONS is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_RK29=y
CONFIG_UART0_RK29=y
CONFIG_UART0_CTS_RTS_RK29=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C0_CONTROLLER_RK30=y
CONFIG_I2C1_CONTROLLER_RK30=y
CONFIG_I2C2_CONTROLLER_RK30=y
CONFIG_I2C3_CONTROLLER_RK30=y
CONFIG_ADC_RK30=y
CONFIG_EXPANDED_GPIO_NUM=0
CONFIG_EXPANDED_GPIO_IRQ_NUM=0
CONFIG_SPI_FPGA_GPIO_NUM=0
CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
CONFIG_POWER_SUPPLY=y
CONFIG_TEST_POWER=y
# CONFIG_HWMON is not set
CONFIG_MFD_TPS65910=y
CONFIG_MFD_TPS65090=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_TPS65910=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_VIDEO_DEV=y
CONFIG_SOC_CAMERA=y
CONFIG_SOC_CAMERA_OV2659=y
CONFIG_SOC_CAMERA_OV5642=y
CONFIG_VIDEO_RK29=y
CONFIG_VIDEO_RK29_CAMMEM_ION=y
CONFIG_ION=y
CONFIG_ION_ROCKCHIP=y
CONFIG_FB=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_DISPLAY_SUPPORT=y
CONFIG_LCD_HSD100PXN=y
CONFIG_FB_ROCKCHIP=y
CONFIG_LCDC_RK2928=y
CONFIG_RK_HDMI=y
CONFIG_RGA_RK30=y
CONFIG_RK_LVDS=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_BMP is not set
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_ARM is not set
CONFIG_SND_SOC=y
CONFIG_SND_RK29_SOC=y
CONFIG_SND_I2S_DMA_EVENT_STATIC=y
CONFIG_SND_RK_SOC_RK2928=y
CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
CONFIG_HID_A4TECH=y
CONFIG_HID_ACRUX=y
CONFIG_HID_ACRUX_FF=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
CONFIG_HID_CHERRY=y
CONFIG_HID_CHICONY=y
CONFIG_HID_CYPRESS=y
CONFIG_HID_DRAGONRISE=y
CONFIG_DRAGONRISE_FF=y
CONFIG_HID_EMS_FF=y
CONFIG_HID_ELECOM=y
CONFIG_HID_EZKEY=y
CONFIG_HID_KEYTOUCH=y
CONFIG_HID_KYE=y
CONFIG_HID_UCLOGIC=y
CONFIG_HID_WALTOP=y
CONFIG_HID_GYRATION=y
CONFIG_HID_TWINHAN=y
CONFIG_HID_KENSINGTON=y
CONFIG_HID_LCPOWER=y
CONFIG_HID_LOGITECH=y
CONFIG_LOGITECH_FF=y
CONFIG_LOGIRUMBLEPAD2_FF=y
CONFIG_LOGIG940_FF=y
CONFIG_LOGIWII_FF=y
CONFIG_HID_MAGICMOUSE=y
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
CONFIG_HID_MULTITOUCH=y
CONFIG_HID_NTRIG=y
CONFIG_HID_ORTEK=y
CONFIG_HID_PANTHERLORD=y
CONFIG_PANTHERLORD_FF=y
CONFIG_HID_PETALYNX=y
CONFIG_HID_PICOLCD=y
CONFIG_HID_QUANTA=y
CONFIG_HID_ROCCAT_ARVO=y
CONFIG_HID_ROCCAT_KONE=y
CONFIG_HID_ROCCAT_KONEPLUS=y
CONFIG_HID_ROCCAT_KOVAPLUS=y
CONFIG_HID_ROCCAT_PYRA=y
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SONY=y
CONFIG_HID_SUNPLUS=y
CONFIG_HID_GREENASIA=y
CONFIG_GREENASIA_FF=y
CONFIG_HID_SMARTJOYPLUS=y
CONFIG_SMARTJOYPLUS_FF=y
CONFIG_HID_TOPSEED=y
CONFIG_HID_THRUSTMASTER=y
CONFIG_THRUSTMASTER_FF=y
CONFIG_HID_WACOM=y
CONFIG_HID_ZEROPLUS=y
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=y
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_OTG_BLACKLIST_HUB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_OPTION=y
CONFIG_USB_GADGET=y
CONFIG_USB20_HOST=y
CONFIG_USB20_OTG=y
CONFIG_MMC=y
CONFIG_MMC_UNSAFE_RESUME=y
CONFIG_MMC_EMBEDDED_SDIO=y
CONFIG_MMC_PARANOID_SD_INIT=y
CONFIG_SDMMC_RK29=y
CONFIG_SWITCH=y
CONFIG_SWITCH_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_TPS65910_RTC=y
CONFIG_STAGING=y
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_ANDROID_LOGGER=y
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
# CONFIG_CMMB is not set
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set
CONFIG_EXT4_FS=y
# CONFIG_EXT4_FS_XATTR is not set
# CONFIG_DNOTIFY is not set
CONFIG_FUSE_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_EFI_PARTITION=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set
CONFIG_CRYPTO_TWOFISH=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set

31
arch/arm/configs/rk3066_sdk_defconfig
View File

@ -10,7 +10,6 @@ CONFIG_RESOURCE_COUNTERS=y
CONFIG_CGROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_PANIC_TIMEOUT=1
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_ELF_CORE is not set
@ -22,10 +21,8 @@ CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_ARCH_RK30=y
CONFIG_WIFI_CONTROL_FUNC=y
CONFIG_MACH_RK3066_SDK=y
CONFIG_CLK_SWITCH_TO_32K=y
# CONFIG_SWP_EMULATE is not set
CONFIG_MACH_RK3066_SDK=y
CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
CONFIG_FIQ_DEBUGGER_CONSOLE=y
@ -57,10 +54,12 @@ CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_WAKELOCK=y
CONFIG_PM_RUNTIME=y
CONFIG_PM_DEBUG=y
CONFIG_SUSPEND_TIME=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
@ -80,6 +79,7 @@ CONFIG_IPV6_MIP6=y
CONFIG_IPV6_TUNNEL=y
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_NETFILTER=y
# CONFIG_BRIDGE_NETFILTER is not set
CONFIG_NF_CONNTRACK=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CT_PROTO_DCCP=y
@ -98,6 +98,7 @@ CONFIG_NF_CT_NETLINK=y
CONFIG_NETFILTER_TPROXY=y
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
CONFIG_NETFILTER_XT_TARGET_MARK=y
CONFIG_NETFILTER_XT_TARGET_NFLOG=y
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
@ -224,7 +225,16 @@ CONFIG_INPUT_KEYRESET=y
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_JOYSTICK=y
CONFIG_JOYSTICK_XPAD=y
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
CONFIG_INPUT_TABLET=y
CONFIG_TABLET_USB_ACECAD=y
CONFIG_TABLET_USB_AIPTEK=y
CONFIG_TABLET_USB_GTCO=y
CONFIG_TABLET_USB_HANWANG=y
CONFIG_TABLET_USB_KBTAB=y
CONFIG_TABLET_USB_WACOM=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_GT8XX=y
CONFIG_INPUT_MISC=y
@ -255,6 +265,7 @@ CONFIG_I2C1_CONTROLLER_RK30=y
CONFIG_I2C2_CONTROLLER_RK30=y
CONFIG_I2C3_CONTROLLER_RK30=y
CONFIG_I2C4_CONTROLLER_RK30=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_WM831X=y
CONFIG_EXPANDED_GPIO_NUM=0
CONFIG_EXPANDED_GPIO_IRQ_NUM=0
@ -284,11 +295,12 @@ CONFIG_DISPLAY_SUPPORT=y
CONFIG_LCD_B101EW05=y
CONFIG_FB_ROCKCHIP=y
CONFIG_LCDC_RK30=y
CONFIG_HDMI_RK30=y
CONFIG_RK_HDMI=y
CONFIG_RGA_RK30=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_BMP is not set
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_SUPPORT_OLD_API is not set
@ -356,8 +368,8 @@ CONFIG_HID_WACOM=y
CONFIG_HID_ZEROPLUS=y
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=y
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_DEVICEFS=y
CONFIG_USB_OTG_BLACKLIST_HUB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_SERIAL=y
@ -402,13 +414,12 @@ CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set
# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set
CONFIG_ENABLE_DEFAULT_TRACERS=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_TWOFISH=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set

143
arch/arm/configs/rk3066b_sdk_defconfig Normal file
View File

@ -0,0 +1,143 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_KERNEL_LZO=y
CONFIG_LOG_BUF_SHIFT=19
CONFIG_CGROUPS=y
CONFIG_CGROUP_DEBUG=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_RESOURCE_COUNTERS=y
CONFIG_CGROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="root"
CONFIG_INITRAMFS_COMPRESSION_GZIP=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_PANIC_TIMEOUT=1
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_ELF_CORE is not set
CONFIG_ASHMEM=y
# CONFIG_AIO is not set
CONFIG_EMBEDDED=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_ARCH_RK31=y
# CONFIG_DDR_TEST is not set
# CONFIG_RK29_LAST_LOG is not set
CONFIG_RK_DEBUG_UART=1
CONFIG_MACH_RK3066B_SDK=y
# CONFIG_CACHE_L2X0 is not set
CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
CONFIG_FIQ_DEBUGGER_CONSOLE=y
CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_HIGHMEM=y
CONFIG_COMPACTION=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init debug"
CONFIG_VFP=y
CONFIG_WAKELOCK=y
CONFIG_PM_RUNTIME=y
CONFIG_SUSPEND_TIME=y
CONFIG_NET=y
CONFIG_UNIX=y
# CONFIG_NET_ACTIVITY_STATS is not set
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_FIRMWARE_IN_KERNEL is not set
CONFIG_MTD=y
CONFIG_MISC_DEVICES=y
# CONFIG_ANDROID_PMEM is not set
CONFIG_INPUT_POLLDEV=y
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_CONSOLE_TRANSLATIONS is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C0_CONTROLLER_RK30=y
CONFIG_I2C1_CONTROLLER_RK30=y
CONFIG_I2C2_CONTROLLER_RK30=y
# CONFIG_I2C3_RK30 is not set
# CONFIG_ADC is not set
CONFIG_EXPANDED_GPIO_NUM=0
CONFIG_EXPANDED_GPIO_IRQ_NUM=0
CONFIG_SPI_FPGA_GPIO_NUM=0
CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
# CONFIG_HWMON is not set
# CONFIG_MFD_SUPPORT is not set
CONFIG_MEDIA_SUPPORT=y
CONFIG_VIDEO_DEV=y
CONFIG_SOC_CAMERA=y
CONFIG_SOC_CAMERA_OV2659=y
CONFIG_VIDEO_RK29=y
CONFIG_VIDEO_RK29_CAMMEM_ION=y
CONFIG_ION=y
CONFIG_ION_ROCKCHIP=y
CONFIG_FB=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_DISPLAY_SUPPORT=y
CONFIG_LCD_TD043MGEA1=y
CONFIG_FB_ROCKCHIP=y
CONFIG_LCDC_RK31=y
CONFIG_LCDC1_RK31=y
# CONFIG_THREE_FB_BUFFER is not set
CONFIG_RGA_RK30=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_ARM is not set
CONFIG_SND_SOC=y
CONFIG_SND_RK29_SOC=y
CONFIG_SND_RK29_SOC_I2S_2CH=y
CONFIG_SND_I2S_DMA_EVENT_STATIC=y
CONFIG_SND_RK29_SOC_RK1000=y
CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_UNSAFE_RESUME=y
CONFIG_MMC_PARANOID_SD_INIT=y
CONFIG_SDMMC_RK29=y
# CONFIG_SDMMC1_RK29 is not set
CONFIG_RTC_CLASS=y
# CONFIG_CMMB is not set
# CONFIG_DNOTIFY is not set
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
CONFIG_SLUB_DEBUG_ON=y
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set

2
arch/arm/configs/rk30_ds1001b_defconfig
View File

@ -288,7 +288,7 @@ CONFIG_DISPLAY_SUPPORT=y
CONFIG_LCD_B101EW05=y
CONFIG_FB_ROCKCHIP=y
CONFIG_LCDC_RK30=y
CONFIG_HDMI_RK30=y
CONFIG_RK_HDMI=y
CONFIG_RGA_RK30=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set

6
arch/arm/configs/rk30_phone_defconfig
View File

@ -23,9 +23,9 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_ARCH_RK30=y
CONFIG_DDR_SDRAM_FREQ=300
CONFIG_CLK_SWITCH_TO_32K=y
CONFIG_WIFI_CONTROL_FUNC=y
CONFIG_MACH_RK30_PHONE=y
CONFIG_CLK_SWITCH_TO_32K=y
# CONFIG_SWP_EMULATE is not set
CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
@ -234,13 +234,17 @@ CONFIG_INPUT_TWL6030_PWRBUTTON=y
CONFIG_INPUT_UINPUT=y
CONFIG_COMPASS_AK8975=y
CONFIG_GS_MMA8452=y
CONFIG_GS_LIS3DH=y
CONFIG_GYRO_L3G4200D=y
CONFIG_LS_CM3217=y
CONFIG_SENSOR_DEVICE=y
CONFIG_GSENSOR_DEVICE=y
CONFIG_GS_KXTIK=y
CONFIG_COMPASS_DEVICE=y
CONFIG_GYROSCOPE_DEVICE=y
CONFIG_LIGHT_DEVICE=y
CONFIG_LS_AL3006=y
CONFIG_LS_STK3171=y
# CONFIG_SERIO is not set
# CONFIG_CONSOLE_TRANSLATIONS is not set
# CONFIG_LEGACY_PTYS is not set

53
arch/arm/configs/rk30_phonepad_defconfig Normal file → Executable file
View File

@ -22,8 +22,10 @@ CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_ARCH_RK30=y
CONFIG_DDR_SDRAM_FREQ=300
CONFIG_CLK_SWITCH_TO_32K=y
CONFIG_WIFI_CONTROL_FUNC=y
CONFIG_RK30_I2C_INSRAM=y
CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC=y
CONFIG_MACH_RK30_PHONE_PAD=y
# CONFIG_SWP_EMULATE is not set
CONFIG_FIQ_DEBUGGER=y
@ -172,14 +174,14 @@ CONFIG_BT_SCO=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=y
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=y
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIBCM4325=y
CONFIG_BT_AUTOSLEEP=y
CONFIG_CFG80211=y
CONFIG_NL80211_TESTMODE=y
CONFIG_MAC80211=y
CONFIG_RFKILL=y
CONFIG_RFKILL_RK=y
CONFIG_RFKILL_INPUT=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_FIRMWARE_IN_KERNEL is not set
@ -207,7 +209,7 @@ CONFIG_PHYLIB=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
CONFIG_WLAN_80211=y
CONFIG_RKWIFI=y
CONFIG_MT6620=y
CONFIG_USB_USBNET=y
CONFIG_PPP=y
CONFIG_PPP_MULTILINK=y
@ -233,19 +235,19 @@ CONFIG_INPUT_KEYCHORD=y
CONFIG_INPUT_UINPUT=y
CONFIG_COMPASS_AK8975=y
CONFIG_GS_MMA8452=y
CONFIG_GS_LIS3DH=y
CONFIG_GYRO_L3G4200D=y
CONFIG_LS_CM3217=y
CONFIG_SENSOR_DEVICE=y
CONFIG_GSENSOR_DEVICE=y
CONFIG_GS_KXTIK=y
CONFIG_COMPASS_DEVICE=y
CONFIG_GYROSCOPE_DEVICE=y
CONFIG_LIGHT_DEVICE=y
# CONFIG_SERIO is not set
# CONFIG_CONSOLE_TRANSLATIONS is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_RK29=y
CONFIG_UART0_RK29=y
CONFIG_UART0_CTS_RTS_RK29=y
CONFIG_UART0_DMA_RK29=3
CONFIG_UART3_RK29=y
CONFIG_UART3_CTS_RTS_RK29=y
# CONFIG_HW_RANDOM is not set
@ -257,21 +259,30 @@ CONFIG_I2C2_CONTROLLER_RK30=y
CONFIG_I2C3_CONTROLLER_RK30=y
CONFIG_I2C4_CONTROLLER_RK30=y
CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET=y
CONFIG_GPIO_WM831X=y
CONFIG_EXPANDED_GPIO_NUM=0
CONFIG_EXPANDED_GPIO_IRQ_NUM=0
CONFIG_SPI_FPGA_GPIO_NUM=0
CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
CONFIG_POWER_SUPPLY=y
CONFIG_TEST_POWER=y
CONFIG_WM831X_BACKUP=y
CONFIG_BATTERY_RK30_ADC=y
CONFIG_BATTERY_RK30_AC_CHARGE=y
CONFIG_BATTERY_RK30_VOL3V8=y
CONFIG_POWER_ON_CHARGER_DISPLAY=y
CONFIG_WM8326_VBAT_LOW_DETECTION=y
# CONFIG_HWMON is not set
CONFIG_MFD_TPS65910=y
CONFIG_MFD_WM831X_I2C=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_TPS65910=y
CONFIG_REGULATOR_WM831X=y
CONFIG_RK30_PWM_REGULATOR=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_VIDEO_DEV=y
CONFIG_SOC_CAMERA=y
CONFIG_SOC_CAMERA_OV2659=y
CONFIG_SOC_CAMERA_OV5642=y
CONFIG_SOC_CAMERA_SIV121D=y
CONFIG_SOC_CAMERA_SID130B=y
CONFIG_VIDEO_RK29=y
CONFIG_VIDEO_RK29_CAMMEM_ION=y
CONFIG_ION=y
@ -285,7 +296,7 @@ CONFIG_DISPLAY_SUPPORT=y
CONFIG_LCD_HV070WSA100=y
CONFIG_FB_ROCKCHIP=y
CONFIG_LCDC_RK30=y
CONFIG_HDMI_RK30=y
CONFIG_RK_HDMI=y
CONFIG_RGA_RK30=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
@ -298,6 +309,7 @@ CONFIG_SND=y
# CONFIG_SND_ARM is not set
CONFIG_SND_SOC=y
CONFIG_SND_RK29_SOC=y
CONFIG_SND_RK_SOC_I2S2_2CH=y
CONFIG_SND_I2S_DMA_EVENT_STATIC=y
CONFIG_SND_RK29_SOC_RT5623=y
CONFIG_SND_RK29_SOC_RT3261=y
@ -374,12 +386,14 @@ CONFIG_MMC_UNSAFE_RESUME=y
CONFIG_MMC_EMBEDDED_SDIO=y
CONFIG_MMC_PARANOID_SD_INIT=y
CONFIG_SDMMC_RK29=y
CONFIG_RK29_SDIO_IRQ_FROM_GPIO=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_SWITCH=y
CONFIG_SWITCH_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_WM831X=y
CONFIG_TPS65910_RTC=y
CONFIG_STAGING=y
CONFIG_ANDROID=y
@ -388,6 +402,15 @@ CONFIG_ANDROID_LOGGER=y
CONFIG_ANDROID_TIMED_GPIO=y
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
# CONFIG_CMMB is not set
CONFIG_MTK_COMBO=y
CONFIG_MTK_COMBO_PLAT_PATH="rockchip"
CONFIG_MTK_COMBO_COMM=m
CONFIG_MTK_COMBO_BT_HW_TEST=m
CONFIG_MTK_COMBO_BT_HCI=m
CONFIG_MTK_COMBO_FM=m
CONFIG_MTK_COMBO_WIFI=m
CONFIG_MTK_GPS=m
CONFIG_MTK_COMBO_GPS=m
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set
CONFIG_EXT4_FS=y

9
arch/arm/configs/rk30_sdk_defconfig
View File

@ -240,13 +240,20 @@ CONFIG_INPUT_KEYCHORD=y
CONFIG_INPUT_UINPUT=y
CONFIG_COMPASS_AK8975=y
CONFIG_GS_MMA8452=y
CONFIG_GS_LIS3DH=y
CONFIG_GYRO_L3G4200D=y
CONFIG_LS_CM3217=y
CONFIG_SENSOR_DEVICE=y
CONFIG_GSENSOR_DEVICE=y
CONFIG_GS_KXTIK=y
CONFIG_COMPASS_DEVICE=y
CONFIG_GYROSCOPE_DEVICE=y
CONFIG_LIGHT_DEVICE=y
CONFIG_LS_AL3006=y
CONFIG_LS_STK3171=y
CONFIG_PROXIMITY_DEVICE=y
CONFIG_PS_AL3006=y
CONFIG_PS_STK3171=y
# CONFIG_SERIO is not set
# CONFIG_CONSOLE_TRANSLATIONS is not set
# CONFIG_LEGACY_PTYS is not set
@ -293,7 +300,7 @@ CONFIG_DISPLAY_SUPPORT=y
CONFIG_LCD_B101EW05=y
CONFIG_FB_ROCKCHIP=y
CONFIG_LCDC_RK30=y
CONFIG_HDMI_RK30=y
CONFIG_RK_HDMI=y
CONFIG_RGA_RK30=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set

142
arch/arm/configs/rk31_fpga_defconfig Normal file
View File

@ -0,0 +1,142 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_KERNEL_LZO=y
CONFIG_LOG_BUF_SHIFT=19
CONFIG_CGROUPS=y
CONFIG_CGROUP_DEBUG=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_RESOURCE_COUNTERS=y
CONFIG_CGROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="root"
CONFIG_INITRAMFS_COMPRESSION_GZIP=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_PANIC_TIMEOUT=1
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_ELF_CORE is not set
CONFIG_ASHMEM=y
# CONFIG_AIO is not set
CONFIG_EMBEDDED=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_ARCH_RK31=y
# CONFIG_DDR_TEST is not set
# CONFIG_RK29_LAST_LOG is not set
CONFIG_RK_DEBUG_UART=1
# CONFIG_CACHE_L2X0 is not set
CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
CONFIG_FIQ_DEBUGGER_CONSOLE=y
CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_HIGHMEM=y
CONFIG_COMPACTION=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init debug"
CONFIG_VFP=y
CONFIG_WAKELOCK=y
CONFIG_PM_RUNTIME=y
CONFIG_SUSPEND_TIME=y
CONFIG_NET=y
CONFIG_UNIX=y
# CONFIG_NET_ACTIVITY_STATS is not set
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_FIRMWARE_IN_KERNEL is not set
CONFIG_MTD=y
CONFIG_MISC_DEVICES=y
# CONFIG_ANDROID_PMEM is not set
CONFIG_INPUT_POLLDEV=y
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_CONSOLE_TRANSLATIONS is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C0_CONTROLLER_RK30=y
CONFIG_I2C1_CONTROLLER_RK30=y
CONFIG_I2C2_CONTROLLER_RK30=y
# CONFIG_I2C3_RK30 is not set
# CONFIG_ADC is not set
CONFIG_EXPANDED_GPIO_NUM=0
CONFIG_EXPANDED_GPIO_IRQ_NUM=0
CONFIG_SPI_FPGA_GPIO_NUM=0
CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
# CONFIG_HWMON is not set
# CONFIG_MFD_SUPPORT is not set
CONFIG_MEDIA_SUPPORT=y
CONFIG_VIDEO_DEV=y
CONFIG_SOC_CAMERA=y
CONFIG_SOC_CAMERA_OV2659=y
CONFIG_VIDEO_RK29=y
CONFIG_VIDEO_RK29_CAMMEM_ION=y
CONFIG_ION=y
CONFIG_ION_ROCKCHIP=y
CONFIG_FB=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_DISPLAY_SUPPORT=y
CONFIG_LCD_TD043MGEA1=y
CONFIG_FB_ROCKCHIP=y
CONFIG_LCDC_RK31=y
CONFIG_LCDC1_RK31=y
# CONFIG_THREE_FB_BUFFER is not set
CONFIG_RGA_RK30=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_ARM is not set
CONFIG_SND_SOC=y
CONFIG_SND_RK29_SOC=y
CONFIG_SND_RK29_SOC_I2S_2CH=y
CONFIG_SND_I2S_DMA_EVENT_STATIC=y
CONFIG_SND_RK29_SOC_RK1000=y
CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_UNSAFE_RESUME=y
CONFIG_MMC_PARANOID_SD_INIT=y
CONFIG_SDMMC_RK29=y
# CONFIG_SDMMC1_RK29 is not set
CONFIG_RTC_CLASS=y
# CONFIG_CMMB is not set
# CONFIG_DNOTIFY is not set
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
CONFIG_SLUB_DEBUG_ON=y
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set

13
arch/arm/kernel/vmlinux.lds.S
View File

@ -271,12 +271,6 @@ SECTIONS
__sram_code_start = .;
}
/*
* Link these to the ITCM RAM
* Put VMA to the TCM address and LMA to the common RAM
* and we'll upload the contents from RAM to TCM and free
* the used RAM after that.
*/
.text_sram_code SRAM_CODE_OFFSET : AT(__sram_code_start)
{
__ssram_code_text = .;
@ -288,7 +282,7 @@ SECTIONS
/*
* Reset the dot pointer, this is needed to create the
* relative __dtcm_start below (to be used as extern in code).
* relative __sram_data_start below (to be used as extern in code).
*/
. = ADDR(.sram_start) + SIZEOF(.sram_start) + SIZEOF(.text_sram_code);
@ -297,7 +291,7 @@ SECTIONS
}
/* TODO: add remainder of ITCM as well, that can be used for data! */
.data_sram SRAM_DATA_OFFSET : AT(__sram_data_start)
.data_sram SRAM_CODE_OFFSET + SIZEOF(.text_sram_code) : AT(__sram_data_start)
{
. = ALIGN(4);
__ssram_data = .;
@ -311,9 +305,10 @@ SECTIONS
/* End marker for freeing TCM copy in linked object */
.sram_end : AT(ADDR(.sram_data_start) + SIZEOF(.data_sram)){
. = ALIGN(PAGE_SIZE);
__sram_end = .;
}
. = ALIGN(PAGE_SIZE);
#endif
NOTES

0
arch/arm/mach-rk29/include/mach/loader.h Normal file → Executable file
View File

19
arch/arm/mach-rk29/include/mach/rk29_camera.h
View File

@ -25,4 +25,23 @@
#include <plat/rk_camera.h>
#define CONFIG_CAMERA_SCALE_CROP_MACHINE RK_CAM_SCALE_CROP_IPP
#if (CONFIG_CAMERA_SCALE_CROP_MACHINE==RK_CAM_SCALE_CROP_ARM)
#define CAMERA_SCALE_CROP_MACHINE "arm"
#elif (CONFIG_CAMERA_SCALE_CROP_MACHINE==RK_CAM_SCALE_CROP_IPP)
#define CAMERA_SCALE_CROP_MACHINE "ipp"
#elif (CONFIG_CAMERA_SCALE_CROP_MACHINE==RK_CAM_SCALE_CROP_RGA)
#define CAMERA_SCALE_CROP_MACHINE "rga"
#elif (CONFIG_CAMERA_SCALE_CROP_MACHINE==RK_CAM_SCALE_CROP_PP)
#define CAMERA_SCALE_CROP_MACHINE "pp"
#endif
#if (CONFIG_CAMERA_SCALE_CROP_MACHINE == RK_CAM_SCALE_CROP_ARM)
#define CAMERA_VIDEOBUF_ARM_ACCESS 1
#else
#define CAMERA_VIDEOBUF_ARM_ACCESS 0
#endif
#endif

17
arch/arm/mach-rk2928/Kconfig Normal file
View File

@ -0,0 +1,17 @@
if ARCH_RK2928
choice
prompt "RK2928 Board Type"
default MACH_RK2928_SDK
config MACH_RK2928_FPGA
bool "RK2928 FPGA board"
config MACH_RK2928_SDK
bool "RK2928 SDK board"
config MACH_RK2928_A720
bool "RK2928 A720 board"
endchoice
endif

16
arch/arm/mach-rk2928/Makefile Normal file
View File

@ -0,0 +1,16 @@
obj-y += common.o
obj-y += io.o
obj-y += reset.o
obj-y += timer.o
obj-y += devices.o
obj-y += iomux.o
obj-y += clock.o
obj-y += clock_data.o
obj-$(CONFIG_CPU_FREQ) += cpufreq.o
obj-$(CONFIG_DVFS) += dvfs.o
obj-$(CONFIG_PM) += pm.o
CFLAGS_pm.o += -Os -mthumb
obj-$(CONFIG_MACH_RK2928_FPGA) += board-rk2928-fpga.o
obj-$(CONFIG_MACH_RK2928_SDK) += board-rk2928-sdk.o
obj-$(CONFIG_MACH_RK2928_A720) += board-rk2928-a720.o

3
arch/arm/mach-rk2928/Makefile.boot Normal file
View File

@ -0,0 +1,3 @@
zreladdr-y := 0x60408000
params_phys-y := 0x60088000
initrd_phys-y := 0x60800000

448
arch/arm/mach-rk2928/board-rk2928-a720-camera.c Normal file
View File

@ -0,0 +1,448 @@
#ifdef CONFIG_VIDEO_RK29
/*---------------- Camera Sensor Macro Define Begin ------------------------*/
/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */
#define CONFIG_SENSOR_IIC_ADDR_0 0
#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 0
#define CONFIG_SENSOR_CIF_INDEX_0 0
#define CONFIG_SENSOR_ORIENTATION_0 90
#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_0 INVALID_GPIO//RK2928_PIN3_PB3
#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
#define CONFIG_SENSOR_IIC_ADDR_01 0x00
#define CONFIG_SENSOR_CIF_INDEX_01 0
#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
#define CONFIG_SENSOR_ORIENTATION_01 90
#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_01 INVALID_GPIO//RK2928_PIN3_PB3
#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
#define CONFIG_SENSOR_IIC_ADDR_02 0x00
#define CONFIG_SENSOR_CIF_INDEX_02 0
#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
#define CONFIG_SENSOR_ORIENTATION_02 90
#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO//RK2928_PIN3_PB3
#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */
#define CONFIG_SENSOR_IIC_ADDR_1 0x60
#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
#define CONFIG_SENSOR_CIF_INDEX_1 0
#define CONFIG_SENSOR_ORIENTATION_1 270
#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_1 RK2928_PIN3_PB3
#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
#define CONFIG_SENSOR_IIC_ADDR_11 0x00
#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
#define CONFIG_SENSOR_CIF_INDEX_11 0
#define CONFIG_SENSOR_ORIENTATION_11 270
#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO
#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
#define CONFIG_SENSOR_IIC_ADDR_12 0x00
#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
#define CONFIG_SENSOR_CIF_INDEX_12 0
#define CONFIG_SENSOR_ORIENTATION_12 270
#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO
#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
#endif //#ifdef CONFIG_VIDEO_RK29
/*---------------- Camera Sensor Configuration Macro End------------------------*/
#include "../../../drivers/media/video/rk2928_camera.c"
/*---------------- Camera Sensor Macro Define End ---------*/
#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
/*****************************************************************************************
* camera devices
* author: ddl@rock-chips.com
*****************************************************************************************/
#ifdef CONFIG_VIDEO_RK29
#define CONFIG_SENSOR_POWER_IOCTL_USR 0 //define this refer to your board layout
#define CONFIG_SENSOR_RESET_IOCTL_USR 0
#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
static void rk_cif_power(int on)
{
struct regulator *ldo_18,*ldo_28;
ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
printk("get cif ldo failed!\n");
return;
}
if(on == 0){
regulator_disable(ldo_28);
regulator_put(ldo_28);
regulator_disable(ldo_18);
regulator_put(ldo_18);
mdelay(500);
}
else{
regulator_set_voltage(ldo_28, 2800000, 2800000);
regulator_enable(ldo_28);
// printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
regulator_put(ldo_28);
regulator_set_voltage(ldo_18, 1800000, 1800000);
// regulator_set_suspend_voltage(ldo, 1800000);
regulator_enable(ldo_18);
// printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
regulator_put(ldo_18);
}
}
#if CONFIG_SENSOR_POWER_IOCTL_USR
static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
{
//#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
rk_cif_power(on);
}
#endif
#if CONFIG_SENSOR_RESET_IOCTL_USR
static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
{
#error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
}
#endif
#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
{
#error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
}
#endif
#if CONFIG_SENSOR_FLASH_IOCTL_USR
static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
{
#error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
}
#endif
static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
#if CONFIG_SENSOR_POWER_IOCTL_USR
.sensor_power_cb = sensor_power_usr_cb,
#else
.sensor_power_cb = NULL,
#endif
#if CONFIG_SENSOR_RESET_IOCTL_USR
.sensor_reset_cb = sensor_reset_usr_cb,
#else
.sensor_reset_cb = NULL,
#endif
#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
.sensor_powerdown_cb = sensor_powerdown_usr_cb,
#else
.sensor_powerdown_cb = NULL,
#endif
#if CONFIG_SENSOR_FLASH_IOCTL_USR
.sensor_flash_cb = sensor_flash_usr_cb,
#else
.sensor_flash_cb = NULL,
#endif
};
#if CONFIG_SENSOR_IIC_ADDR_0
static struct reginfo_t rk_init_data_sensor_reg_0[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_1
static struct reginfo_t rk_init_data_sensor_reg_1[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
{
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_01
static struct reginfo_t rk_init_data_sensor_reg_01[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
{
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_02
static struct reginfo_t rk_init_data_sensor_reg_02[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
{
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_11
static struct reginfo_t rk_init_data_sensor_reg_11[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
{
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_12
static struct reginfo_t rk_init_data_sensor_reg_12[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
{
{0x0000, 0x00,0,0}
};
#endif
static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
{
#if CONFIG_SENSOR_IIC_ADDR_0
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_0,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_1
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_1,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_01
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_01,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_02
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_02,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_11
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_11,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_12
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_12,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
};
#include "../../../drivers/media/video/rk2928_camera.c"
#endif /* CONFIG_VIDEO_RK29 */

39
arch/arm/mach-rk2928/board-rk2928-a720-key.c Executable file
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@ -0,0 +1,39 @@
#include <mach/gpio.h>
#include <plat/key.h>
#define EV_ENCALL KEY_F4
#define EV_MENU KEY_F1
#define PRESS_LEV_LOW 1
#define PRESS_LEV_HIGH 0
static struct rk29_keys_button key_button[] = {
{
.desc = "play",
.code = KEY_POWER,
.gpio = RK2928_PIN1_PA4,
.active_low = PRESS_LEV_LOW,
//.code_long_press = EV_ENCALL,
.wakeup = 1,
},
{
.desc = "vol+",
.code = KEY_VOLUMEUP,
.gpio = INVALID_GPIO,
.adc_value = 1,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "vol-",
.code = KEY_VOLUMEDOWN,
.gpio = INVALID_GPIO,
.adc_value = 512,
.active_low = PRESS_LEV_LOW,
},
};
struct rk29_keys_platform_data rk29_keys_pdata = {
.buttons = key_button,
.nbuttons = ARRAY_SIZE(key_button),
.chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
};

618
arch/arm/mach-rk2928/board-rk2928-a720-tps65910.c Executable file
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#include <linux/regulator/machine.h>
#include <linux/i2c/twl.h>
#include <linux/mfd/tps65910.h>
#include <mach/sram.h>
#include <linux/platform_device.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#define gpio_readl(offset) readl_relaxed(RK2928_GPIO1_BASE + offset)
#define gpio_writel(v, offset) do { writel_relaxed(v, RK2928_GPIO1_BASE + offset); dsb(); } while (0)
#define GPIO_SWPORTA_DR 0x0000
#define GPIO_SWPORTA_DDR 0x0004
#define GPIO1_A1_OUTPUT (1<<1)
#define GPIO1_A1_OUTPUT_HIGH (1<<1)
#define GPIO1_A1_OUTPUT_LOW (~(1<<1))
#ifdef CONFIG_MFD_TPS65910
#define PMU_POWER_SLEEP RK2928_PIN1_PA1
extern int platform_device_register(struct platform_device *pdev);
int tps65910_pre_init(struct tps65910 *tps65910){
int val = 0;
int i = 0;
int err = -1;
printk("%s,line=%d\n", __func__,__LINE__);
gpio_request(PMU_POWER_SLEEP, "NULL");
gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW);
val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL2);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DEVCTRL2 reg\n");
return val;
}
/* Set sleep state active high and allow device turn-off after PWRON long press */
val |= (DEVCTRL2_SLEEPSIG_POL_MASK | DEVCTRL2_PWON_LP_OFF_MASK);
err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL2, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_DEVCTRL2 reg\n");
return err;
}
#if 1
/* set PSKIP=0 */
val = tps65910_reg_read(tps65910, TPS65910_DCDCCTRL);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val &= ~DEVCTRL_DEV_OFF_MASK;
val &= ~DEVCTRL_DEV_SLP_MASK;
err = tps65910_reg_write(tps65910, TPS65910_DCDCCTRL, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_DCDCCTRL reg\n");
return err;
}
#endif
/* Set the maxinum load current */
/* VDD1 */
val = tps65910_reg_read(tps65910, TPS65910_VDD1);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_VDD1 reg\n");
return val;
}
val |= (1<<5); //when 1: 1.5 A
val |= (0x07<<2); //TSTEP[2:0] = 111 : 2.5 mV/|¨¬s(sampling 3 Mhz/5)
err = tps65910_reg_write(tps65910, TPS65910_VDD1, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_VDD1 reg\n");
return err;
}
/* VDD2 */
val = tps65910_reg_read(tps65910, TPS65910_VDD2);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_VDD2 reg\n");
return val;
}
val |= (1<<5); //when 1: 1.5 A
err = tps65910_reg_write(tps65910, TPS65910_VDD2, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_VDD2 reg\n");
return err;
}
/* VIO */
val = tps65910_reg_read(tps65910, TPS65910_VIO);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_VIO reg\n");
return -EIO;
}
val |= (1<<6); //when 01: 1.0 A
err = tps65910_reg_write(tps65910, TPS65910_VIO, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_VIO reg\n");
return err;
}
#if 1
/* Mask ALL interrupts */
err = tps65910_reg_write(tps65910,TPS65910_INT_MSK, 0xFF);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_INT_MSK reg\n");
return err;
}
err = tps65910_reg_write(tps65910, TPS65910_INT_MSK2, 0x03);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_INT_MSK2 reg\n");
return err;
}
/* Set RTC Power, disable Smart Reflex in DEVCTRL_REG */
#if 1
val = 0;
val |= (DEVCTRL_SR_CTL_I2C_SEL_MASK);
err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_DEVCTRL reg\n");
return err;
}
printk(KERN_INFO "TPS65910 Set default voltage.\n");
#endif
#if 0
//read sleep control register for debug
for(i=0; i<6; i++)
{
err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
if (err) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return -EIO;
}
else
printk("%s.......is 0x%04x\n",__FUNCTION__,val);
}
#endif
#if 1
//sleep control register
/*set func when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val |= (1 << 1);
err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
/* open ldo when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_LDO_ON);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val &= 0;
err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_LDO_ON, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
/*set dc mode when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_RES_ON);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val |= 0xff;
err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_RES_ON, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
/*close ldo when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_SLEEP_SET_LDO_OFF);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val |= 0x9B;
err = tps65910_reg_write(tps65910, TPS65910_SLEEP_SET_LDO_OFF, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
#endif
#if 0
//read sleep control register for debug
for(i=0; i<6; i++)
{
err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
if (err) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return -EIO;
}
else
printk("%s.......is 0x%4x\n",__FUNCTION__,val);
}
#endif
#endif
printk("%s,line=%d\n", __func__,__LINE__);
return 0;
}
int tps65910_post_init(struct tps65910 *tps65910)
{
struct regulator *dcdc;
struct regulator *ldo;
printk("%s,line=%d\n", __func__,__LINE__);
#ifdef CONFIG_RK30_PWM_REGULATOR
platform_device_register(&pwm_regulator_device[0]);
#endif
dcdc = regulator_get(NULL, "vio"); //vcc_io
regulator_set_voltage(dcdc, 3300000, 3300000);
regulator_enable(dcdc);
printk("%s set vio vcc_io=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
/*
ldo = regulator_get(NULL, "vpll"); // vcc25
regulator_set_voltage(ldo, 2500000, 2500000);
regulator_enable(ldo);
printk("%s set vpll vcc25=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
*/
ldo = regulator_get(NULL, "vdig2"); // vdd12
regulator_set_voltage(ldo, 1200000, 1200000);
regulator_enable(ldo);
printk("%s set vdig2 vdd12=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "vaux33"); //vcc_tp
regulator_set_voltage(ldo, 3300000, 3300000);
regulator_enable(ldo);
printk("%s set vaux33 vcc_tp=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
dcdc = regulator_get(NULL, "vdd_cpu"); //vdd_cpu
regulator_set_voltage(dcdc, 1200000, 1200000);
regulator_enable(dcdc);
printk("%s set vdd1 vdd_cpu=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
dcdc = regulator_get(NULL, "vdd2"); //vcc_ddr
regulator_set_voltage(dcdc, 1200000, 1200000); // 1.5*4/5 = 1.2 and Vout=1.5v
regulator_enable(dcdc);
printk("%s set vdd2 vcc_ddr=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
ldo = regulator_get(NULL, "vdig1"); //vcc18_cif
regulator_set_voltage(ldo, 1500000, 1500000);
regulator_enable(ldo);
printk("%s set vdig1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
dcdc = regulator_get(NULL, "vaux1"); //vcc28_cif
regulator_set_voltage(dcdc,2800000,2800000);
regulator_enable(dcdc);
printk("%s set vaux1 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
ldo = regulator_get(NULL, "vaux2"); //vcca33
regulator_set_voltage(ldo, 3300000, 3300000);
regulator_enable(ldo);
printk("%s set vaux2 vcca33=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
/*
ldo = regulator_get(NULL, "vdac"); // vccio_wl
regulator_set_voltage(ldo,1800000,1800000);
regulator_enable(ldo);
printk("%s set vdac vccio_wl=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
*/
ldo = regulator_get(NULL, "vmmc"); //vccio_wl
regulator_set_voltage(ldo,3300000,3300000);
regulator_enable(ldo);
printk("%s set vmmc vccio_wl=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
printk("%s,line=%d END\n", __func__,__LINE__);
return 0;
}
static struct regulator_consumer_supply tps65910_smps1_supply[] = {
{
.supply = "vdd1",
},
{
.supply = "vdd_cpu",
},
};
static struct regulator_consumer_supply tps65910_smps2_supply[] = {
{
.supply = "vdd2",
},
};
static struct regulator_consumer_supply tps65910_smps3_supply[] = {
{
.supply = "vdd3",
},
};
static struct regulator_consumer_supply tps65910_smps4_supply[] = {
{
.supply = "vio",
},
};
static struct regulator_consumer_supply tps65910_ldo1_supply[] = {
{
.supply = "vdig1",
},
};
static struct regulator_consumer_supply tps65910_ldo2_supply[] = {
{
.supply = "vdig2",
},
};
static struct regulator_consumer_supply tps65910_ldo3_supply[] = {
{
.supply = "vaux1",
},
};
static struct regulator_consumer_supply tps65910_ldo4_supply[] = {
{
.supply = "vaux2",
},
};
static struct regulator_consumer_supply tps65910_ldo5_supply[] = {
{
.supply = "vaux33",
},
};
static struct regulator_consumer_supply tps65910_ldo6_supply[] = {
{
.supply = "vmmc",
},
};
static struct regulator_consumer_supply tps65910_ldo7_supply[] = {
{
.supply = "vdac",
},
};
static struct regulator_consumer_supply tps65910_ldo8_supply[] = {
{
.supply = "vpll",
},
};
static struct regulator_init_data tps65910_smps1 = {
.constraints = {
.name = "VDD1",
.min_uV = 600000,
.max_uV = 1500000,
.apply_uV = 1,
.always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_smps1_supply),
.consumer_supplies = tps65910_smps1_supply,
};
/* */
static struct regulator_init_data tps65910_smps2 = {
.constraints = {
.name = "VDD2",
.min_uV = 600000,
.max_uV = 1500000,
.apply_uV = 1,
.always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_smps2_supply),
.consumer_supplies = tps65910_smps2_supply,
};
/* */
static struct regulator_init_data tps65910_smps3 = {
.constraints = {
.name = "VDD3",
.min_uV = 1000000,
.max_uV = 1400000,
.apply_uV = 1,
.always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_smps3_supply),
.consumer_supplies = tps65910_smps3_supply,
};
static struct regulator_init_data tps65910_smps4 = {
.constraints = {
.name = "VIO",
.min_uV = 1800000,
.max_uV = 3300000,
.apply_uV = 1,
.always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_smps4_supply),
.consumer_supplies = tps65910_smps4_supply,
};
static struct regulator_init_data tps65910_ldo1 = {
.constraints = {
.name = "VDIG1",
.min_uV = 1200000,
.max_uV = 2700000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo1_supply),
.consumer_supplies = tps65910_ldo1_supply,
};
/* */
static struct regulator_init_data tps65910_ldo2 = {
.constraints = {
.name = "VDIG2",
.min_uV = 1000000,
.max_uV = 1800000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo2_supply),
.consumer_supplies = tps65910_ldo2_supply,
};
/* */
static struct regulator_init_data tps65910_ldo3 = {
.constraints = {
.name = "VAUX1",
.min_uV = 1800000,
.max_uV = 3300000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo3_supply),
.consumer_supplies = tps65910_ldo3_supply,
};
/* */
static struct regulator_init_data tps65910_ldo4 = {
.constraints = {
.name = "VAUX2",
.min_uV = 1800000,
.max_uV = 3300000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo4_supply),
.consumer_supplies = tps65910_ldo4_supply,
};
/* */
static struct regulator_init_data tps65910_ldo5 = {
.constraints = {
.name = "VAUX33",
.min_uV = 1800000,
.max_uV = 3300000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo5_supply),
.consumer_supplies = tps65910_ldo5_supply,
};
/* */
static struct regulator_init_data tps65910_ldo6 = {
.constraints = {
.name = "VMMC",
.min_uV = 1800000,
.max_uV = 3300000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo6_supply),
.consumer_supplies = tps65910_ldo6_supply,
};
/* */
static struct regulator_init_data tps65910_ldo7 = {
.constraints = {
.name = "VDAC",
.min_uV = 1800000,
.max_uV = 2850000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo7_supply),
.consumer_supplies = tps65910_ldo7_supply,
};
/* */
static struct regulator_init_data tps65910_ldo8 = {
.constraints = {
.name = "VPLL",
.min_uV = 1000000,
.max_uV = 2500000,
.apply_uV = 1,
.always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo8_supply),
.consumer_supplies = tps65910_ldo8_supply,
};
void __sramfunc board_pmu_suspend(void)
{
int ret;
ret = gpio_readl(GPIO_SWPORTA_DDR);
gpio_writel(ret | GPIO1_A1_OUTPUT, GPIO_SWPORTA_DDR);
ret = gpio_readl(GPIO_SWPORTA_DR);
gpio_writel(ret | GPIO1_A1_OUTPUT_HIGH, GPIO_SWPORTA_DR); //set pmu_sleep output high
}
void __sramfunc board_pmu_resume(void)
{
int ret;
ret = gpio_readl(GPIO_SWPORTA_DDR);
gpio_writel(ret | GPIO1_A1_OUTPUT, GPIO_SWPORTA_DDR);
ret = gpio_readl(GPIO_SWPORTA_DR);
gpio_writel(ret & GPIO1_A1_OUTPUT_LOW, GPIO_SWPORTA_DR); //set pmu_sleep output low
sram_udelay(2000);
}
static struct tps65910_board tps65910_data = {
.irq = (unsigned)TPS65910_HOST_IRQ,
.irq_base = NR_GIC_IRQS + NR_GPIO_IRQS,
.gpio_base = TPS65910_GPIO_EXPANDER_BASE,
.pre_init = tps65910_pre_init,
.post_init = tps65910_post_init,
//TPS65910_NUM_REGS = 13
// Regulators
.tps65910_pmic_init_data[TPS65910_REG_VRTC] = NULL,
.tps65910_pmic_init_data[TPS65910_REG_VIO] = &tps65910_smps4,
.tps65910_pmic_init_data[TPS65910_REG_VDD1] = &tps65910_smps1,
.tps65910_pmic_init_data[TPS65910_REG_VDD2] = &tps65910_smps2,
.tps65910_pmic_init_data[TPS65910_REG_VDD3] = &tps65910_smps3,
.tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &tps65910_ldo1,
.tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &tps65910_ldo2,
.tps65910_pmic_init_data[TPS65910_REG_VPLL] = &tps65910_ldo8,
.tps65910_pmic_init_data[TPS65910_REG_VDAC] = &tps65910_ldo7,
.tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &tps65910_ldo3,
.tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &tps65910_ldo4,
.tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &tps65910_ldo5,
.tps65910_pmic_init_data[TPS65910_REG_VMMC] = &tps65910_ldo6,
};
#endif

665
arch/arm/mach-rk2928/board-rk2928-a720.c Executable file
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@ -0,0 +1,665 @@
/* arch/arm/mach-rk2928/board-rk2928-fpga.c
*
* Copyright (C) 2012 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/skbuff.h>
#include <linux/spi/spi.h>
#include <linux/mmc/host.h>
#include <linux/ion.h>
#include <linux/cpufreq.h>
#include <linux/clk.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
#include <asm/hardware/gic.h>
#include <mach/dvfs.h>
#include <mach/board.h>
#include <mach/hardware.h>
#include <mach/io.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <linux/fb.h>
#include <linux/regulator/machine.h>
#include <linux/rfkill-rk.h>
#include <linux/sensor-dev.h>
#include <linux/mfd/tps65910.h>
#include <linux/regulator/rk29-pwm-regulator.h>
#if defined(CONFIG_HDMI_RK30)
#include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
#endif
#if defined(CONFIG_SPIM_RK29)
#include "../../../drivers/spi/rk29_spim.h"
#endif
#include "board-rk2928-a720-camera.c"
#include "board-rk2928-a720-key.c"
#ifdef CONFIG_THREE_FB_BUFFER
#define RK30_FB0_MEM_SIZE 12*SZ_1M
#else
#define RK30_FB0_MEM_SIZE 8*SZ_1M
#endif
static struct spi_board_info board_spi_devices[] = {
};
/***********************************************************
* rk30 backlight
************************************************************/
#ifdef CONFIG_BACKLIGHT_RK29_BL
#define PWM_ID 0
#define PWM_MUX_NAME GPIO0D2_PWM_0_NAME
#define PWM_MUX_MODE GPIO0D_PWM_0
#define PWM_MUX_MODE_GPIO GPIO0D_GPIO0D2
#define PWM_GPIO RK2928_PIN0_PD2
#define PWM_EFFECT_VALUE 0
#define LCD_DISP_ON_PIN
#ifdef LCD_DISP_ON_PIN
#define BL_EN_PIN RK2928_PIN1_PB0
#define BL_EN_VALUE GPIO_HIGH
#endif
static int rk29_backlight_io_init(void)
{
int ret = 0;
rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
#ifdef LCD_DISP_ON_PIN
// rk30_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
ret = gpio_request(BL_EN_PIN, NULL);
if (ret != 0) {
gpio_free(BL_EN_PIN);
}
gpio_direction_output(BL_EN_PIN, 0);
gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
#endif
return ret;
}
static int rk29_backlight_io_deinit(void)
{
int ret = 0;
#ifdef LCD_DISP_ON_PIN
gpio_free(BL_EN_PIN);
#endif
rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
return ret;
}
static int rk29_backlight_pwm_suspend(void)
{
int ret = 0;
rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
if (gpio_request(PWM_GPIO, NULL)) {
printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
return -1;
}
gpio_direction_output(PWM_GPIO, GPIO_LOW);
#ifdef LCD_DISP_ON_PIN
gpio_direction_output(BL_EN_PIN, 0);
gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
#endif
return ret;
}
static int rk29_backlight_pwm_resume(void)
{
gpio_free(PWM_GPIO);
rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
#ifdef LCD_DISP_ON_PIN
msleep(30);
gpio_direction_output(BL_EN_PIN, 1);
gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
#endif
return 0;
}
static struct rk29_bl_info rk29_bl_info = {
.pwm_id = PWM_ID,
.bl_ref = PWM_EFFECT_VALUE,
.io_init = rk29_backlight_io_init,
.io_deinit = rk29_backlight_io_deinit,
.pwm_suspend = rk29_backlight_pwm_suspend,
.pwm_resume = rk29_backlight_pwm_resume,
};
static struct platform_device rk29_device_backlight = {
.name = "rk29_backlight",
.id = -1,
.dev = {
.platform_data = &rk29_bl_info,
}
};
#endif
#ifdef CONFIG_FB_ROCKCHIP
#define LCD_MUX_NAME GPIO0C2_UART0_RTSN_NAME
#define LCD_GPIO_MODE GPIO0C_GPIO0C2
#define LCD_EN RK2928_PIN0_PC2
#define LCD_EN_VALUE GPIO_LOW
static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
{
int ret = 0;
rk30_mux_api_set(LCD_MUX_NAME, LCD_GPIO_MODE);
ret = gpio_request(LCD_EN, NULL);
if (ret != 0)
{
gpio_free(LCD_EN);
printk(KERN_ERR "request lcd en pin fail!\n");
return -1;
}
else
{
gpio_direction_output(LCD_EN, LCD_EN_VALUE); //disable
}
return 0;
}
static int rk_fb_io_disable(void)
{
gpio_set_value(LCD_EN, !LCD_EN_VALUE);
return 0;
}
static int rk_fb_io_enable(void)
{
gpio_set_value(LCD_EN, LCD_EN_VALUE);
return 0;
}
#if defined(CONFIG_LCDC_RK2928)
struct rk29fb_info lcdc_screen_info = {
.prop = PRMRY, //primary display device
.io_init = rk_fb_io_init,
.io_disable = rk_fb_io_disable,
.io_enable = rk_fb_io_enable,
.set_screen_info = set_lcd_info,
};
#endif
static struct resource resource_fb[] = {
[0] = {
.name = "fb0 buf",
.start = 0,
.end = 0,//RK30_FB0_MEM_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = "ipp buf", //for rotate
.start = 0,
.end = 0,//RK30_FB0_MEM_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[2] = {
.name = "fb2 buf",
.start = 0,
.end = 0,//RK30_FB0_MEM_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device device_fb = {
.name = "rk-fb",
.id = -1,
.num_resources = ARRAY_SIZE(resource_fb),
.resource = resource_fb,
};
#endif
#ifdef CONFIG_ION
#define ION_RESERVE_SIZE (80 * SZ_1M)
static struct ion_platform_data rk30_ion_pdata = {
.nr = 1,
.heaps = {
{
.type = ION_HEAP_TYPE_CARVEOUT,
.id = ION_NOR_HEAP_ID,
.name = "norheap",
.size = ION_RESERVE_SIZE,
}
},
};
static struct platform_device device_ion = {
.name = "ion-rockchip",
.id = 0,
.dev = {
.platform_data = &rk30_ion_pdata,
},
};
#endif
#if defined(CONFIG_TOUCHSCREEN_SITRONIX_A720)
#define TOUCH_RESET_PIN RK2928_PIN1_PA3
#define TOUCH_INT_PIN RK2928_PIN1_PB3
int ft5306_init_platform_hw(void)
{
//printk("ft5306_init_platform_hw\n");
if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
gpio_free(TOUCH_RESET_PIN);
printk("ft5306_init_platform_hw gpio_request error\n");
return -EIO;
}
if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
gpio_free(TOUCH_INT_PIN);
printk("ift5306_init_platform_hw gpio_request error\n");
return -EIO;
}
gpio_direction_output(TOUCH_RESET_PIN, GPIO_HIGH);
mdelay(10);
gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
mdelay(10);
gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
msleep(300);
return 0;
}
struct ft5x0x_platform_data sitronix_info = {
.model = 5007,
.init_platform_hw= ft5306_init_platform_hw,
};
#endif
/*MMA7660 gsensor*/
#if defined (CONFIG_GS_MMA7660)
#define MMA7660_INT_PIN RK2928_PIN1_PB1
static int mma7660_init_platform_hw(void)
{
rk30_mux_api_set(GPIO1B1_SPI_TXD_UART1_SOUT_NAME, GPIO1B_GPIO1B1);
return 0;
}
static struct sensor_platform_data mma7660_info = {
.type = SENSOR_TYPE_ACCEL,
.irq_enable = 1,
.poll_delay_ms = 30,
.init_platform_hw = mma7660_init_platform_hw,
.orientation = {-1, 0, 0, 0, 0, 1, 0, -1, 0},
};
#endif
#if CONFIG_RK30_PWM_REGULATOR
const static int pwm_voltage_map[] = {
1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
};
static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
{
.supply = "vdd_core",
}
};
struct regulator_init_data pwm_regulator_init_dcdc[1] =
{
{
.constraints = {
.name = "PWM_DCDC1",
.min_uV = 600000,
.max_uV = 1800000, //0.6-1.8V
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
.consumer_supplies = pwm_dcdc1_consumers,
},
};
static struct pwm_platform_data pwm_regulator_info[1] = {
{
.pwm_id = 2,
.pwm_gpio = RK2928_PIN0_PD4,
.pwm_iomux_name = GPIO0D4_PWM_2_NAME,
.pwm_iomux_pwm = GPIO0D_PWM_2,
.pwm_iomux_gpio = GPIO0D_GPIO0D4,
.pwm_voltage = 1200000,
.suspend_voltage = 1050000,
.min_uV = 1000000,
.max_uV = 1400000,
.coefficient = 455, //45.5%
.pwm_voltage_map = pwm_voltage_map,
.init_data = &pwm_regulator_init_dcdc[0],
},
};
struct platform_device pwm_regulator_device[1] = {
{
.name = "pwm-voltage-regulator",
.id = 0,
.dev = {
.platform_data = &pwm_regulator_info[0],
}
},
};
#endif
/**************************************************************************************************
* SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
**************************************************************************************************/
#ifdef CONFIG_SDMMC_RK29
#include "board-rk2928-sdk-sdmmc.c"
#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
#define SDMMC0_WRITE_PROTECT_PIN RK2928_PIN1_PA7 //According to your own project to set the value of write-protect-pin.
#endif
#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
#define SDMMC1_WRITE_PROTECT_PIN RK2928_PIN0_PD5 //According to your own project to set the value of write-protect-pin.
#endif
#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK2928_PIN0_PB2
#endif //endif ---#ifdef CONFIG_SDMMC_RK29
#ifdef CONFIG_SDMMC0_RK29
static int rk29_sdmmc0_cfg_gpio(void)
{
rk29_sdmmc_set_iomux(0, 0xFFFF);
rk30_mux_api_set(GPIO1C1_MMC0_DETN_NAME, GPIO1C_MMC0_DETN);
#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
#endif
return 0;
}
#define CONFIG_SDMMC0_USE_DMA
struct rk29_sdmmc_platform_data default_sdmmc0_data = {
.host_ocr_avail =
(MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
.host_caps =
(MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
.io_init = rk29_sdmmc0_cfg_gpio,
#if !defined(CONFIG_SDMMC_RK29_OLD)
.set_iomux = rk29_sdmmc_set_iomux,
#endif
.dma_name = "sd_mmc",
#ifdef CONFIG_SDMMC0_USE_DMA
.use_dma = 1,
#else
.use_dma = 0,
#endif
.detect_irq = RK2928_PIN1_PC1, // INVALID_GPIO
.enable_sd_wakeup = 0,
#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
.write_prt = SDMMC0_WRITE_PROTECT_PIN,
#else
.write_prt = INVALID_GPIO,
#endif
};
#endif // CONFIG_SDMMC0_RK29
#ifdef CONFIG_SND_SOC_RK2928
static struct resource resources_acodec[] = {
{
.start = RK2928_ACODEC_PHYS,
.end = RK2928_ACODEC_PHYS + RK2928_ACODEC_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = RK2928_PIN1_PA0,
.end = RK2928_PIN1_PA0,
.flags = IORESOURCE_IO,
},
};
static struct platform_device device_acodec = {
.name = "rk2928-codec",
.id = -1,
.num_resources = ARRAY_SIZE(resources_acodec),
.resource = resources_acodec,
};
#endif
static struct platform_device *devices[] __initdata = {
#ifdef CONFIG_BACKLIGHT_RK29_BL
&rk29_device_backlight,
#endif
#ifdef CONFIG_FB_ROCKCHIP
&device_fb,
#endif
#ifdef CONFIG_ION
&device_ion,
#endif
#ifdef CONFIG_SND_SOC_RK2928
&device_acodec,
#endif
};
//i2c
#ifdef CONFIG_I2C0_RK30
#ifdef CONFIG_MFD_TPS65910
#define TPS65910_HOST_IRQ RK2928_PIN1_PB2
#include "board-rk2928-a720-tps65910.c"
#endif
static struct i2c_board_info __initdata i2c0_info[] = {
#if defined (CONFIG_MFD_TPS65910)
{
.type = "tps65910",
.addr = TPS65910_I2C_ID0,
.flags = 0,
.irq = TPS65910_HOST_IRQ,
.platform_data = &tps65910_data,
},
#endif
};
#endif
#ifdef CONFIG_I2C1_RK30
static struct i2c_board_info __initdata i2c1_info[] = {
#if defined (CONFIG_GS_MMA7660)
{
.type = "gs_mma7660",
.addr = 0x4c,
.flags = 0,
.irq = MMA7660_INT_PIN,
.platform_data = &mma7660_info,
},
#endif
};
#endif
#ifdef CONFIG_I2C2_RK30
static struct i2c_board_info __initdata i2c2_info[] = {
#if defined (CONFIG_TOUCHSCREEN_SITRONIX_A720)
{
.type ="sitronix",
.addr = 0x38,
.flags = 0,
.irq = TOUCH_INT_PIN,
.platform_data = &sitronix_info,
},
#endif
};
#endif
#ifdef CONFIG_I2C3_RK30
static struct i2c_board_info __initdata i2c3_info[] = {
};
#endif
#ifdef CONFIG_I2C_GPIO_RK30
#define I2C_SDA_PIN INVALID_GPIO //set sda_pin here
#define I2C_SCL_PIN INVALID_GPIO //set scl_pin here
static int rk30_i2c_io_init(void)
{
//set iomux (gpio) here
return 0;
}
struct i2c_gpio_platform_data default_i2c_gpio_data = {
.sda_pin = I2C_SDA_PIN,
.scl_pin = I2C_SCL_PIN,
.udelay = 5, // clk = 500/udelay = 100Khz
.timeout = 100,//msecs_to_jiffies(100),
.bus_num = 5,
.io_init = rk30_i2c_io_init,
};
static struct i2c_board_info __initdata i2c_gpio_info[] = {
};
#endif
static void __init rk30_i2c_register_board_info(void)
{
#ifdef CONFIG_I2C0_RK30
i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
#endif
#ifdef CONFIG_I2C1_RK30
i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
#endif
#ifdef CONFIG_I2C2_RK30
i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
#endif
#ifdef CONFIG_I2C3_RK30
i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
#endif
#ifdef CONFIG_I2C_GPIO_RK30
i2c_register_board_info(4, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
#endif
}
//end of i2c
#define POWER_ON_PIN RK2928_PIN1_PA2 //power_hold
static void rk2928_pm_power_off(void)
{
printk(KERN_ERR "rk2928_pm_power_off start...\n");
#if defined(CONFIG_MFD_TPS65910)
tps65910_device_shutdown();//tps65910 shutdown
#endif
gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
};
static void __init rk2928_board_init(void)
{
gpio_request(POWER_ON_PIN, "poweronpin");
gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
gpio_free(POWER_ON_PIN);
pm_power_off = rk2928_pm_power_off;
rk30_i2c_register_board_info();
spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
platform_add_devices(devices, ARRAY_SIZE(devices));
}
static void __init rk2928_reserve(void)
{
#ifdef CONFIG_ION
rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
#endif
#ifdef CONFIG_FB_ROCKCHIP
resource_fb[0].start = board_mem_reserve_add("fb0", RK30_FB0_MEM_SIZE);
resource_fb[0].end = resource_fb[0].start + RK30_FB0_MEM_SIZE - 1;
#endif
#ifdef CONFIG_VIDEO_RK29
rk30_camera_request_reserve_mem();
#endif
board_mem_reserved();
}
/**
* dvfs_cpu_logic_table: table for arm and logic dvfs
* @frequency : arm frequency
* @cpu_volt : arm voltage depend on frequency
* @logic_volt : logic voltage arm requests depend on frequency
* comments : min arm/logic voltage
*/
static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
{.frequency = 216 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},//0.975V/1.000V
{.frequency = 312 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},//0.975V/1.000V
{.frequency = 408 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},//1.000V/1.025V
{.frequency = 504 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},//1.000V/1.025V
{.frequency = 600 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},//1.025V/1.050V
{.frequency = 696 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.000V/1.025V
{.frequency = 816 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
//{.frequency = 912 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
//{.frequency = 1008 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
#if 0
{.frequency = 1104 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
{.frequency = 1200 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
{.frequency = 1104 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
{.frequency = 1248 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
#endif
//{.frequency = 1000 * 1000, .cpu_volt = 1225 * 1000, .logic_volt = 1200 * 1000},//1.150V/1.100V
{.frequency = CPUFREQ_TABLE_END},
};
static struct cpufreq_frequency_table dvfs_gpu_table[] = {
{.frequency = 266 * 1000, .index = 1050 * 1000},
{.frequency = 400 * 1000, .index = 1275 * 1000},
{.frequency = CPUFREQ_TABLE_END},
};
static struct cpufreq_frequency_table dvfs_ddr_table[] = {
{.frequency = 300 * 1000, .index = 1050 * 1000},
{.frequency = 400 * 1000, .index = 1125 * 1000},
{.frequency = CPUFREQ_TABLE_END},
};
#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
void __init board_clock_init(void)
{
rk2928_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
//dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
printk("%s end\n", __func__);
}
MACHINE_START(RK2928, "RK2928board")
.boot_params = PLAT_PHYS_OFFSET + 0x800,
.fixup = rk2928_fixup,
.reserve = &rk2928_reserve,
.map_io = rk2928_map_io,
.init_irq = rk2928_init_irq,
.timer = &rk2928_timer,
.init_machine = rk2928_board_init,
MACHINE_END

53
arch/arm/mach-rk2928/board-rk2928-fpga-key.c Executable file
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#include <mach/gpio.h>
#include <plat/key.h>
#define EV_ENCALL KEY_F4
#define EV_MENU KEY_F1
#define PRESS_LEV_LOW 1
#define PRESS_LEV_HIGH 0
static struct rk29_keys_button key_button[] = {
{
.desc = "menu",
.code = EV_MENU,
.gpio = RK2928_PIN3_PB2,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "vol+",
.code = KEY_VOLUMEUP,
.gpio = RK2928_PIN3_PB1,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "vol-",
.code = KEY_VOLUMEDOWN,
.gpio = RK2928_PIN3_PB0,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "home",
.code = KEY_HOME,
.gpio = RK2928_PIN3_PB3,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "esc",
.code = KEY_BACK,
.gpio = RK2928_PIN3_PB4,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "key6",
.code = KEY_CAMERA,
.gpio = RK2928_PIN3_PB5,
.active_low = PRESS_LEV_LOW,
},
};
struct rk29_keys_platform_data rk29_keys_pdata = {
.buttons = key_button,
.nbuttons = ARRAY_SIZE(key_button),
.chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1
};

909
arch/arm/mach-rk2928/board-rk2928-fpga.c Executable file
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/* arch/arm/mach-rk2928/board-rk2928-fpga.c
*
* Copyright (C) 2012 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/skbuff.h>
#include <linux/spi/spi.h>
#include <linux/mmc/host.h>
#include <linux/ion.h>
#include <linux/cpufreq.h>
#include <linux/clk.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
#include <asm/hardware/gic.h>
#include <mach/board.h>
#include <mach/hardware.h>
#include <mach/io.h>
#include <mach/gpio.h>
#include <linux/fb.h>
#include <linux/regulator/machine.h>
#include <linux/rfkill-rk.h>
#include <linux/sensor-dev.h>
#ifdef CONFIG_VIDEO_RK29
/*---------------- Camera Sensor Macro Define Begin ------------------------*/
/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */
#define CONFIG_SENSOR_IIC_ADDR_0 0
#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 4
#define CONFIG_SENSOR_CIF_INDEX_0 0
#define CONFIG_SENSOR_ORIENTATION_0 90
#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_0 RK2928_PIN1_PD6
#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
#define CONFIG_SENSOR_IIC_ADDR_01 0x00
#define CONFIG_SENSOR_CIF_INDEX_01 0
#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
#define CONFIG_SENSOR_ORIENTATION_01 90
#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_01 RK2928_PIN1_PD6
#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
#define CONFIG_SENSOR_IIC_ADDR_02 0x00
#define CONFIG_SENSOR_CIF_INDEX_02 0
#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
#define CONFIG_SENSOR_ORIENTATION_02 90
#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_02 RK2928_PIN1_PD6
#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */
#define CONFIG_SENSOR_IIC_ADDR_1 0x60
#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
#define CONFIG_SENSOR_CIF_INDEX_1 0
#define CONFIG_SENSOR_ORIENTATION_1 270
#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_1 RK2928_PIN1_PB7
#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
#define CONFIG_SENSOR_IIC_ADDR_11 0x00
#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
#define CONFIG_SENSOR_CIF_INDEX_11 0
#define CONFIG_SENSOR_ORIENTATION_11 270
#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO//RK30_PIN1_PB7
#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
#define CONFIG_SENSOR_IIC_ADDR_12 0x00
#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
#define CONFIG_SENSOR_CIF_INDEX_12 0
#define CONFIG_SENSOR_ORIENTATION_12 270
#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO//RK30_PIN1_PB7
#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
#endif //#ifdef CONFIG_VIDEO_RK29
/*---------------- Camera Sensor Configuration Macro End------------------------*/
#include "../../../drivers/media/video/rk2928_camera.c"
/*---------------- Camera Sensor Macro Define End ---------*/
#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
/*****************************************************************************************
* camera devices
* author: ddl@rock-chips.com
*****************************************************************************************/
#ifdef CONFIG_VIDEO_RK29
#define CONFIG_SENSOR_POWER_IOCTL_USR 0 //define this refer to your board layout
#define CONFIG_SENSOR_RESET_IOCTL_USR 0
#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
static void rk_cif_power(int on)
{
struct regulator *ldo_18,*ldo_28;
ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
printk("get cif ldo failed!\n");
return;
}
if(on == 0){
regulator_disable(ldo_28);
regulator_put(ldo_28);
regulator_disable(ldo_18);
regulator_put(ldo_18);
mdelay(500);
}
else{
regulator_set_voltage(ldo_28, 2800000, 2800000);
regulator_enable(ldo_28);
// printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
regulator_put(ldo_28);
regulator_set_voltage(ldo_18, 1800000, 1800000);
// regulator_set_suspend_voltage(ldo, 1800000);
regulator_enable(ldo_18);
// printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
regulator_put(ldo_18);
}
}
#if CONFIG_SENSOR_POWER_IOCTL_USR
static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
{
//#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
rk_cif_power(on);
}
#endif
#if CONFIG_SENSOR_RESET_IOCTL_USR
static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
{
#error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
}
#endif
#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
{
#error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
}
#endif
#if CONFIG_SENSOR_FLASH_IOCTL_USR
static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
{
#error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
}
#endif
static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
#if CONFIG_SENSOR_POWER_IOCTL_USR
.sensor_power_cb = sensor_power_usr_cb,
#else
.sensor_power_cb = NULL,
#endif
#if CONFIG_SENSOR_RESET_IOCTL_USR
.sensor_reset_cb = sensor_reset_usr_cb,
#else
.sensor_reset_cb = NULL,
#endif
#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
.sensor_powerdown_cb = sensor_powerdown_usr_cb,
#else
.sensor_powerdown_cb = NULL,
#endif
#if CONFIG_SENSOR_FLASH_IOCTL_USR
.sensor_flash_cb = sensor_flash_usr_cb,
#else
.sensor_flash_cb = NULL,
#endif
};
#if CONFIG_SENSOR_IIC_ADDR_0
static struct reginfo_t rk_init_data_sensor_reg_0[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_1
static struct reginfo_t rk_init_data_sensor_reg_1[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
{
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_01
static struct reginfo_t rk_init_data_sensor_reg_01[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
{
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_02
static struct reginfo_t rk_init_data_sensor_reg_02[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
{
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_11
static struct reginfo_t rk_init_data_sensor_reg_11[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
{
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_12
static struct reginfo_t rk_init_data_sensor_reg_12[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
{
{0x0000, 0x00,0,0}
};
#endif
static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
{
#if CONFIG_SENSOR_IIC_ADDR_0
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_0,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_1
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_1,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_01
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_01,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_02
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_02,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_11
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_11,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_12
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_12,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
};
#include "../../../drivers/media/video/rk2928_camera.c"
#endif /* CONFIG_VIDEO_RK29 */
#include "board-rk2928-fpga-key.c"
/**************************************************************************************************
* SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
**************************************************************************************************/
#ifdef CONFIG_SDMMC_RK29
#include "board-rk2928-sdk-sdmmc.c"
#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
#define SDMMC0_WRITE_PROTECT_PIN RK2928_PIN1_PA7 //According to your own project to set the value of write-protect-pin.
#endif
#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
#define SDMMC1_WRITE_PROTECT_PIN RK2928_PIN0_PD5 //According to your own project to set the value of write-protect-pin.
#endif
#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK2928_PIN0_PB2
#endif //endif ---#ifdef CONFIG_SDMMC_RK29
#ifdef CONFIG_SDMMC0_RK29
static int rk29_sdmmc0_cfg_gpio(void)
{
#ifdef CONFIG_SDMMC_RK29_OLD
rk30_mux_api_set(GPIO1B7_MMC0_CMD_NAME, GPIO1B_MMC0_CMD);
rk30_mux_api_set(GPIO1C0_MMC0_CLKOUT_NAME, GPIO1C_MMC0_CLKOUT);
rk30_mux_api_set(GPIO1C2_MMC0_D0_NAME, GPIO1C_MMC0_D0);
rk30_mux_api_set(GPIO1C3_MMC0_D1_NAME, GPIO1C_MMC0_D1);
rk30_mux_api_set(GPIO1C4_MMC0_D2_NAME, GPIO1C_MMC0_D2);
rk30_mux_api_set(GPIO1C5_MMC0_D3_NAME, GPIO1C_MMC0_D3);
rk30_mux_api_set(GPIO1C1_MMC0_DETN_NAME, GPIO1C_MMC0_DETN);
rk30_mux_api_set(GPIO1B6_MMC0_PWREN_NAME, GPIO1B_MMC0_PWREN);
gpio_request(RK30_PIN3_PA7, "sdmmc-power");
gpio_direction_output(RK2928_PIN1_PB6, GPIO_LOW);
#else
rk29_sdmmc_set_iomux(0, 0xFFFF);
rk30_mux_api_set(GPIO1C1_MMC0_DETN_NAME, GPIO1C_MMC0_DETN);
#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
#endif
#endif
return 0;
}
#define CONFIG_SDMMC0_USE_DMA
struct rk29_sdmmc_platform_data default_sdmmc0_data = {
.host_ocr_avail =
(MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
.host_caps =
(MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
.io_init = rk29_sdmmc0_cfg_gpio,
#if !defined(CONFIG_SDMMC_RK29_OLD)
.set_iomux = rk29_sdmmc_set_iomux,
#endif
.dma_name = "sd_mmc",
#ifdef CONFIG_SDMMC0_USE_DMA
.use_dma = 1,
#else
.use_dma = 0,
#endif
.detect_irq = RK2928_PIN1_PC1, // INVALID_GPIO
.enable_sd_wakeup = 0,
#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
.write_prt = SDMMC0_WRITE_PROTECT_PIN,
#else
.write_prt = INVALID_GPIO,
#endif
};
#endif // CONFIG_SDMMC0_RK29
#ifdef CONFIG_SDMMC1_RK29
#define CONFIG_SDMMC1_USE_DMA
static int rk29_sdmmc1_cfg_gpio(void)
{
#if defined(CONFIG_SDMMC_RK29_OLD)
rk30_mux_api_set(GPIO0B0_MMC1_CMD_NAME, GPIO0B_MMC1_CMD);
rk30_mux_api_set(GPIO0B1_MMC1_CLKOUT_NAME, GPIO0B_MMC1_CLKOUT);
rk30_mux_api_set(GPIO0B3_MMC1_D0_NAME, GPIO0B_MMC1_D0);
rk30_mux_api_set(GPIO0B4_MMC1_D1_NAME, GPIO0B_MMC1_D1);
rk30_mux_api_set(GPIO0B5_MMC1_D2_NAME, GPIO0B_MMC1_D2);
rk30_mux_api_set(GPIO0B6_MMC1_D3_NAME, GPIO0B_MMC1_D3);
//rk30_mux_api_set(GPIO0B2_MMC1_DETN_NAME, GPIO0B_MMC1_DETN);
#else
#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
#endif
#endif
return 0;
}
struct rk29_sdmmc_platform_data default_sdmmc1_data = {
.host_ocr_avail =
(MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
MMC_VDD_33_34),
#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
.host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
#else
.host_caps =
(MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
#endif
.io_init = rk29_sdmmc1_cfg_gpio,
#if !defined(CONFIG_SDMMC_RK29_OLD)
.set_iomux = rk29_sdmmc_set_iomux,
#endif
.dma_name = "sdio",
#ifdef CONFIG_SDMMC1_USE_DMA
.use_dma = 1,
#else
.use_dma = 0,
#endif
#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
#ifdef CONFIG_WIFI_CONTROL_FUNC
.status = rk29sdk_wifi_status,
.register_status_notify = rk29sdk_wifi_status_register,
#endif
#if 0
.detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
#endif
#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
.write_prt = SDMMC1_WRITE_PROTECT_PIN,
#else
.write_prt = INVALID_GPIO,
#endif
#else
.detect_irq = INVALID_GPIO,
.enable_sd_wakeup = 0,
#endif
};
#endif //endif--#ifdef CONFIG_SDMMC1_RK29
/**************************************************************************************************
* the end of setting for SDMMC devices
**************************************************************************************************/
#define RK2928_FB_MEM_SIZE 3*SZ_1M
#ifdef CONFIG_FB_ROCKCHIP
static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
{
return 0;
}
static int rk_fb_io_disable(void)
{
return 0;
}
static int rk_fb_io_enable(void)
{
return 0;
}
#if defined(CONFIG_LCDC_RK2928)
struct rk29fb_info lcdc_screen_info = {
.prop = PRMRY, //primary display device
.io_init = rk_fb_io_init,
.io_disable = rk_fb_io_disable,
.io_enable = rk_fb_io_enable,
.set_screen_info = set_lcd_info,
};
#endif
static struct resource resource_fb[] = {
[0] = {
.name = "fb0 buf",
.start = 0,
.end = 0,//RK30_FB0_MEM_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = "ipp buf", //for rotate
.start = 0,
.end = 0,//RK30_FB0_MEM_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device device_fb = {
.name = "rk-fb",
.id = -1,
.num_resources = ARRAY_SIZE(resource_fb),
.resource = resource_fb,
};
#endif
//i2c
#ifdef CONFIG_I2C0_RK30
static struct i2c_board_info __initdata i2c0_info[] = {
};
#endif
#ifdef CONFIG_I2C1_RK30
static struct i2c_board_info __initdata i2c1_info[] = {
};
#endif
#ifdef CONFIG_I2C2_RK30
static struct i2c_board_info __initdata i2c2_info[] = {
};
#endif
#ifdef CONFIG_I2C3_RK30
static struct i2c_board_info __initdata i2c3_info[] = {
};
#endif
#ifdef CONFIG_I2C_GPIO_RK30
static struct i2c_board_info __initdata i2c_gpio_info[] = {
};
#endif
static void __init rk30_i2c_register_board_info(void)
{
#ifdef CONFIG_I2C0_RK30
i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
#endif
#ifdef CONFIG_I2C1_RK30
i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
#endif
#ifdef CONFIG_I2C2_RK30
i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
#endif
#ifdef CONFIG_I2C3_RK30
i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
#endif
#ifdef CONFIG_I2C_GPIO_RK30
i2c_register_board_info(4, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
#endif
}
//end of i2c
static struct spi_board_info board_spi_devices[] = {
};
#ifdef CONFIG_ION
#define ION_RESERVE_SIZE (8 * SZ_1M)
static struct ion_platform_data rk30_ion_pdata = {
.nr = 1,
.heaps = {
{
.type = ION_HEAP_TYPE_CARVEOUT,
.id = ION_NOR_HEAP_ID,
.name = "norheap",
.size = ION_RESERVE_SIZE,
}
},
};
static struct platform_device device_ion = {
.name = "ion-rockchip",
.id = 0,
.dev = {
.platform_data = &rk30_ion_pdata,
},
};
#endif
static struct platform_device *devices[] __initdata = {
#ifdef CONFIG_ION
&device_ion,
#endif
#ifdef CONFIG_FB_ROCKCHIP
&device_fb,
#endif
};
static void __init rk2928_board_init(void)
{
rk30_i2c_register_board_info();
spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
platform_add_devices(devices, ARRAY_SIZE(devices));
}
static void __init rk2928_reserve(void)
{
#ifdef CONFIG_ION
rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
#endif
#ifdef CONFIG_FB_ROCKCHIP
resource_fb[0].start = board_mem_reserve_add("fb0", RK2928_FB_MEM_SIZE);
resource_fb[0].end = resource_fb[0].start + RK2928_FB_MEM_SIZE - 1;
#endif
board_mem_reserved();
}
#include <linux/clkdev.h>
struct clk {
const char *name;
unsigned long rate;
};
static struct clk xin24m = {
.name = "xin24m",
.rate = 24000000,
};
#define CLK(dev, con, ck) \
{ \
.dev_id = dev, \
.con_id = con, \
.clk = ck, \
}
static struct clk_lookup clks[] = {
CLK("rk30_i2c.0", "i2c", &xin24m),
CLK("rk30_i2c.1", "i2c", &xin24m),
CLK("rk30_i2c.2", "i2c", &xin24m),
CLK("rk30_i2c.3", "i2c", &xin24m),
CLK("rk29xx_spim.0", "spi", &xin24m),
CLK("rk29xx_spim.1", "spi", &xin24m),
CLK("rk_serial.0", "uart_div", &xin24m),
CLK("rk_serial.0", "uart_frac_div", &xin24m),
CLK("rk_serial.0", "uart", &xin24m),
CLK("rk_serial.0", "pclk_uart", &xin24m),
CLK("rk_serial.1", "uart_div", &xin24m),
CLK("rk_serial.1", "uart_frac_div", &xin24m),
CLK("rk_serial.1", "uart", &xin24m),
CLK("rk_serial.1", "pclk_uart", &xin24m),
CLK("rk_serial.2", "uart_div", &xin24m),
CLK("rk_serial.2", "uart_frac_div", &xin24m),
CLK("rk_serial.2", "uart", &xin24m),
CLK("rk_serial.2", "pclk_uart", &xin24m),
CLK("rk29_i2s.0", "i2s_div", &xin24m),
CLK("rk29_i2s.0", "i2s_frac_div", &xin24m),
CLK("rk29_i2s.0", "i2s", &xin24m),
CLK("rk29_i2s.0", "hclk_i2s", &xin24m),
CLK(NULL, "pd_lcdc0", &xin24m),
CLK(NULL, "hclk_lcdc0", &xin24m),
CLK(NULL, "aclk_lcdc0", &xin24m),
CLK(NULL, "dclk_lcdc0", &xin24m),
CLK(NULL, "pd_cif0", &xin24m),
CLK(NULL, "aclk_cif0", &xin24m),
CLK(NULL, "hclk_cif0", &xin24m),
CLK(NULL, "cif0_in", &xin24m),
CLK(NULL, "cif0_out", &xin24m),
};
void __init rk30_clock_init(void)
{
struct clk_lookup *lk;
for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
clkdev_add(lk);
}
}
void __init board_clock_init(void)
{
rk30_clock_init();
}
int clk_enable(struct clk *clk)
{
return 0;
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
return 24000000;
}
EXPORT_SYMBOL(clk_get_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
return 0;
}
EXPORT_SYMBOL(clk_set_rate);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
return 0;
}
EXPORT_SYMBOL(clk_set_parent);
MACHINE_START(RK2928, "RK2928board")
.boot_params = PLAT_PHYS_OFFSET + 0x800,
.fixup = rk2928_fixup,
.reserve = &rk2928_reserve,
.map_io = rk2928_map_io,
.init_irq = rk2928_init_irq,
.timer = &rk2928_timer,
.init_machine = rk2928_board_init,
MACHINE_END

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arch/arm/mach-rk2928/board-rk2928-sdk-camera.c Normal file
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#ifdef CONFIG_VIDEO_RK29
/*---------------- Camera Sensor Macro Define Begin ------------------------*/
/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */
#define CONFIG_SENSOR_IIC_ADDR_0 0x78// 0
#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 0
#define CONFIG_SENSOR_CIF_INDEX_0 0
#define CONFIG_SENSOR_ORIENTATION_0 90
#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_0 RK2928_PIN3_PB3
#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
#define CONFIG_SENSOR_IIC_ADDR_01 0x00
#define CONFIG_SENSOR_CIF_INDEX_01 0
#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
#define CONFIG_SENSOR_ORIENTATION_01 90
#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_01 RK2928_PIN3_PB3
#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
#define CONFIG_SENSOR_IIC_ADDR_02 0x00
#define CONFIG_SENSOR_CIF_INDEX_02 0
#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
#define CONFIG_SENSOR_ORIENTATION_02 90
#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_02 RK2928_PIN3_PB3
#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */
#define CONFIG_SENSOR_IIC_ADDR_1 0// 0x60
#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 3
#define CONFIG_SENSOR_CIF_INDEX_1 0
#define CONFIG_SENSOR_ORIENTATION_1 270
#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_1 RK2928_PIN3_PB3
#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
#define CONFIG_SENSOR_IIC_ADDR_11 0x00
#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
#define CONFIG_SENSOR_CIF_INDEX_11 0
#define CONFIG_SENSOR_ORIENTATION_11 270
#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO
#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
#define CONFIG_SENSOR_IIC_ADDR_12 0x00
#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
#define CONFIG_SENSOR_CIF_INDEX_12 0
#define CONFIG_SENSOR_ORIENTATION_12 270
#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO
#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
#endif //#ifdef CONFIG_VIDEO_RK29
/*---------------- Camera Sensor Configuration Macro End------------------------*/
#include "../../../drivers/media/video/rk2928_camera.c"
/*---------------- Camera Sensor Macro Define End ---------*/
#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
/*****************************************************************************************
* camera devices
* author: ddl@rock-chips.com
*****************************************************************************************/
#ifdef CONFIG_VIDEO_RK29
#define CONFIG_SENSOR_POWER_IOCTL_USR 0 //define this refer to your board layout
#define CONFIG_SENSOR_RESET_IOCTL_USR 0
#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
static void rk_cif_power(int on)
{
struct regulator *ldo_18,*ldo_28;
ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
printk("get cif ldo failed!\n");
return;
}
if(on == 0){
regulator_disable(ldo_28);
regulator_put(ldo_28);
regulator_disable(ldo_18);
regulator_put(ldo_18);
mdelay(500);
}
else{
regulator_set_voltage(ldo_28, 2800000, 2800000);
regulator_enable(ldo_28);
// printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
regulator_put(ldo_28);
regulator_set_voltage(ldo_18, 1800000, 1800000);
// regulator_set_suspend_voltage(ldo, 1800000);
regulator_enable(ldo_18);
// printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
regulator_put(ldo_18);
}
}
#if CONFIG_SENSOR_POWER_IOCTL_USR
static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
{
//#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
rk_cif_power(on);
}
#endif
#if CONFIG_SENSOR_RESET_IOCTL_USR
static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
{
#error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
}
#endif
#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
{
#error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
}
#endif
#if CONFIG_SENSOR_FLASH_IOCTL_USR
static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
{
#error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
}
#endif
static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
#if CONFIG_SENSOR_POWER_IOCTL_USR
.sensor_power_cb = sensor_power_usr_cb,
#else
.sensor_power_cb = NULL,
#endif
#if CONFIG_SENSOR_RESET_IOCTL_USR
.sensor_reset_cb = sensor_reset_usr_cb,
#else
.sensor_reset_cb = NULL,
#endif
#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
.sensor_powerdown_cb = sensor_powerdown_usr_cb,
#else
.sensor_powerdown_cb = NULL,
#endif
#if CONFIG_SENSOR_FLASH_IOCTL_USR
.sensor_flash_cb = sensor_flash_usr_cb,
#else
.sensor_flash_cb = NULL,
#endif
};
#if CONFIG_SENSOR_IIC_ADDR_0
static struct reginfo_t rk_init_data_sensor_reg_0[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_1
static struct reginfo_t rk_init_data_sensor_reg_1[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
{
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_01
static struct reginfo_t rk_init_data_sensor_reg_01[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
{
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_02
static struct reginfo_t rk_init_data_sensor_reg_02[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
{
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_11
static struct reginfo_t rk_init_data_sensor_reg_11[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
{
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_12
static struct reginfo_t rk_init_data_sensor_reg_12[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
{
{0x0000, 0x00,0,0}
};
#endif
static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
{
#if CONFIG_SENSOR_IIC_ADDR_0
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_0,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_1
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_1,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_01
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_01,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_02
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_02,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_11
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_11,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_12
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_12,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
};
#include "../../../drivers/media/video/rk2928_camera.c"
#endif /* CONFIG_VIDEO_RK29 */

65
arch/arm/mach-rk2928/board-rk2928-sdk-key.c Executable file
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#include <mach/gpio.h>
#include <plat/key.h>
#define EV_ENCALL KEY_F4
#define EV_MENU KEY_F1
#define PRESS_LEV_LOW 1
#define PRESS_LEV_HIGH 0
static struct rk29_keys_button key_button[] = {
{
.desc = "vol-",
.code = KEY_VOLUMEDOWN,
.gpio = RK2928_PIN0_PD1,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "play",
.code = KEY_POWER,
.gpio = RK2928_PIN3_PC5,
.active_low = PRESS_LEV_LOW,
//.code_long_press = EV_ENCALL,
.wakeup = 1,
},
{
.desc = "vol+",
.code = KEY_VOLUMEUP,
.gpio = RK2928_PIN0_PD0,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "menu",
.code = EV_MENU,
.adc_value = 135,
.gpio = INVALID_GPIO,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "home",
.code = KEY_HOME,
.adc_value = 550,
.gpio = INVALID_GPIO,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "esc",
.code = KEY_BACK,
.adc_value = 334,
.gpio = INVALID_GPIO,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "camera",
.code = KEY_CAMERA,
.adc_value = 743,
.gpio = INVALID_GPIO,
.active_low = PRESS_LEV_LOW,
},
};
struct rk29_keys_platform_data rk29_keys_pdata = {
.buttons = key_button,
.nbuttons = ARRAY_SIZE(key_button),
.chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
};

438
arch/arm/mach-rk2928/board-rk2928-sdk-sdmmc.c Normal file
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/* arch/arm/mach-rk30/board-rk30-sdk-sdmmc.c
*
* Copyright (C) 2012 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifdef CONFIG_SDMMC_RK29
#if !defined(CONFIG_SDMMC_RK29_OLD)
static void rk29_sdmmc_gpio_open(int device_id, int on)
{
switch(device_id)
{
case 0://mmc0
{
#ifdef CONFIG_SDMMC0_RK29
if(on)
{
gpio_direction_output(RK2928_PIN1_PC0,GPIO_HIGH);//set mmc0-clk to high
gpio_direction_output(RK2928_PIN1_PB7,GPIO_HIGH);// set mmc0-cmd to high.
gpio_direction_output(RK2928_PIN1_PC2,GPIO_HIGH);//set mmc0-data0 to high.
gpio_direction_output(RK2928_PIN1_PC3,GPIO_HIGH);//set mmc0-data1 to high.
gpio_direction_output(RK2928_PIN1_PC4,GPIO_HIGH);//set mmc0-data2 to high.
gpio_direction_output(RK2928_PIN1_PC5,GPIO_HIGH);//set mmc0-data3 to high.
mdelay(30);
}
else
{
rk30_mux_api_set(GPIO1C0_MMC0_CLKOUT_NAME, GPIO1C_GPIO1C0);
gpio_request(RK2928_PIN1_PC0, "mmc0-clk");
gpio_direction_output(RK2928_PIN1_PC0,GPIO_LOW);//set mmc0-clk to low.
rk30_mux_api_set(GPIO1B7_MMC0_CMD_NAME, GPIO1B_GPIO1B7);
gpio_request(RK2928_PIN1_PB7, "mmc0-cmd");
gpio_direction_output(RK2928_PIN1_PB7,GPIO_LOW);//set mmc0-cmd to low.
rk30_mux_api_set(GPIO1C2_MMC0_D0_NAME, GPIO1C_GPIO1C2);
gpio_request(RK2928_PIN1_PC2, "mmc0-data0");
gpio_direction_output(RK2928_PIN1_PC2,GPIO_LOW);//set mmc0-data0 to low.
rk30_mux_api_set(GPIO1C3_MMC0_D1_NAME, GPIO1C_GPIO1C3);
gpio_request(RK2928_PIN1_PC3, "mmc0-data1");
gpio_direction_output(RK2928_PIN1_PC3,GPIO_LOW);//set mmc0-data1 to low.
rk30_mux_api_set(GPIO1C4_MMC0_D2_NAME, GPIO1C_GPIO1C4);
gpio_request(RK2928_PIN1_PC4, "mmc0-data2");
gpio_direction_output(RK2928_PIN1_PC4,GPIO_LOW);//set mmc0-data2 to low.
rk30_mux_api_set(GPIO1C5_MMC0_D3_NAME, GPIO1C_GPIO1C5);
gpio_request(RK2928_PIN1_PC5, "mmc0-data3");
gpio_direction_output(RK2928_PIN1_PC5,GPIO_LOW);//set mmc0-data3 to low.
mdelay(30);
}
#endif
}
break;
case 1://mmc1
{
#ifdef CONFIG_SDMMC1_RK29
if(on)
{
gpio_direction_output(RK2928_PIN0_PB1,GPIO_HIGH);//set mmc1-clk to high
gpio_direction_output(RK2928_PIN0_PB0,GPIO_HIGH);//set mmc1-cmd to high.
gpio_direction_output(RK2928_PIN0_PB3,GPIO_HIGH);//set mmc1-data0 to high.
gpio_direction_output(RK2928_PIN0_PB4,GPIO_HIGH);//set mmc1-data1 to high.
gpio_direction_output(RK2928_PIN0_PB5,GPIO_HIGH);//set mmc1-data2 to high.
gpio_direction_output(RK2928_PIN0_PB6,GPIO_HIGH);//set mmc1-data3 to high.
mdelay(100);
}
else
{
rk30_mux_api_set(GPIO0B1_MMC1_CLKOUT_NAME, GPIO0B_GPIO0B1);
gpio_request(RK2928_PIN0_PB1, "mmc1-clk");
gpio_direction_output(RK2928_PIN0_PB1,GPIO_LOW);//set mmc1-clk to low.
rk30_mux_api_set(GPIO0B0_MMC1_CMD_NAME, GPIO0B_GPIO0B0);
gpio_request(RK2928_PIN0_PB0, "mmc1-cmd");
gpio_direction_output(RK2928_PIN0_PB0,GPIO_LOW);//set mmc1-cmd to low.
rk30_mux_api_set(GPIO0B3_MMC1_D0_NAME, GPIO0B_GPIO0B3);
gpio_request(RK2928_PIN0_PB3, "mmc1-data0");
gpio_direction_output(RK2928_PIN0_PB3,GPIO_LOW);//set mmc1-data0 to low.
mdelay(100);
}
#endif
}
break;
case 2: //mmc2
break;
default:
break;
}
}
static void rk29_sdmmc_set_iomux_mmc0(unsigned int bus_width)
{
switch (bus_width)
{
case 1://SDMMC_CTYPE_4BIT:
{
rk30_mux_api_set(GPIO1C3_MMC0_D1_NAME, GPIO1C_MMC0_D1);
rk30_mux_api_set(GPIO1C4_MMC0_D2_NAME, GPIO1C_MMC0_D2);
rk30_mux_api_set(GPIO1C5_MMC0_D3_NAME, GPIO1C_MMC0_D3);
}
break;
case 0x10000://SDMMC_CTYPE_8BIT:
break;
case 0xFFFF: //gpio_reset
{
rk30_mux_api_set(GPIO1B6_MMC0_PWREN_NAME, GPIO1B_GPIO1B6);
gpio_request(RK2928_PIN1_PB6,"sdmmc-power");
gpio_direction_output(RK2928_PIN1_PB6,GPIO_HIGH); //power-off
rk29_sdmmc_gpio_open(0, 0);
gpio_direction_output(RK2928_PIN1_PB6,GPIO_LOW); //power-on
rk29_sdmmc_gpio_open(0, 1);
}
break;
default: //case 0://SDMMC_CTYPE_1BIT:
{
rk30_mux_api_set(GPIO1B7_MMC0_CMD_NAME, GPIO1B_MMC0_CMD);
rk30_mux_api_set(GPIO1C0_MMC0_CLKOUT_NAME, GPIO1C_MMC0_CLKOUT);
rk30_mux_api_set(GPIO1C2_MMC0_D0_NAME, GPIO1C_MMC0_D0);
rk30_mux_api_set(GPIO1C3_MMC0_D1_NAME, GPIO1C_GPIO1C3);
gpio_request(RK2928_PIN1_PC3, "mmc0-data1");
gpio_direction_output(RK2928_PIN1_PC3,GPIO_HIGH);//set mmc0-data1 to high.
rk30_mux_api_set(GPIO1C4_MMC0_D2_NAME, GPIO1C_GPIO1C4);
gpio_request(RK2928_PIN1_PC4, "mmc0-data2");
gpio_direction_output(RK2928_PIN1_PC4,GPIO_HIGH);//set mmc0-data2 to high.
rk30_mux_api_set(GPIO1C5_MMC0_D3_NAME, GPIO1C_GPIO1C5);
gpio_request(RK2928_PIN1_PC5, "mmc0-data3");
gpio_direction_output(RK2928_PIN1_PC5,GPIO_HIGH);//set mmc0-data3 to high.
}
break;
}
}
static void rk29_sdmmc_set_iomux_mmc1(unsigned int bus_width)
{
rk30_mux_api_set(GPIO0B0_MMC1_CMD_NAME, GPIO0B_MMC1_CMD);
rk30_mux_api_set(GPIO0B1_MMC1_CLKOUT_NAME, GPIO0B_MMC1_CLKOUT);
rk30_mux_api_set(GPIO0B3_MMC1_D0_NAME, GPIO0B_MMC1_D0);
rk30_mux_api_set(GPIO0B4_MMC1_D1_NAME, GPIO0B_MMC1_D1);
rk30_mux_api_set(GPIO0B5_MMC1_D2_NAME, GPIO0B_MMC1_D2);
rk30_mux_api_set(GPIO0B6_MMC1_D3_NAME, GPIO0B_MMC1_D3);
}
static void rk29_sdmmc_set_iomux_mmc2(unsigned int bus_width)
{
;//
}
static void rk29_sdmmc_set_iomux(int device_id, unsigned int bus_width)
{
switch(device_id)
{
case 0:
#ifdef CONFIG_SDMMC0_RK29
rk29_sdmmc_set_iomux_mmc0(bus_width);
#endif
break;
case 1:
#ifdef CONFIG_SDMMC1_RK29
rk29_sdmmc_set_iomux_mmc1(bus_width);
#endif
break;
case 2:
rk29_sdmmc_set_iomux_mmc2(bus_width);
break;
default:
break;
}
}
#endif
//int rk29sdk_wifi_power_state = 0;
//int rk29sdk_bt_power_state = 0;
#ifdef CONFIG_WIFI_CONTROL_FUNC
#define RK30SDK_WIFI_GPIO_POWER_N RK2928_PIN0_PD6
#define RK29SDK_WIFI_GPIO_RESET_N RK2928_PIN3_PC2
#define PREALLOC_WLAN_SEC_NUM 4
#define PREALLOC_WLAN_BUF_NUM 160
#define PREALLOC_WLAN_SECTION_HEADER 24
#define WLAN_SECTION_SIZE_0 (PREALLOC_WLAN_BUF_NUM * 128)
#define WLAN_SECTION_SIZE_1 (PREALLOC_WLAN_BUF_NUM * 128)
#define WLAN_SECTION_SIZE_2 (PREALLOC_WLAN_BUF_NUM * 512)
#define WLAN_SECTION_SIZE_3 (PREALLOC_WLAN_BUF_NUM * 1024)
#define WLAN_SKB_BUF_NUM 16
static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM];
struct wifi_mem_prealloc {
void *mem_ptr;
unsigned long size;
};
static struct wifi_mem_prealloc wifi_mem_array[PREALLOC_WLAN_SEC_NUM] = {
{NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)},
{NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)},
{NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)},
{NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)}
};
static void *rk29sdk_mem_prealloc(int section, unsigned long size)
{
if (section == PREALLOC_WLAN_SEC_NUM)
return wlan_static_skb;
if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM))
return NULL;
if (wifi_mem_array[section].size < size)
return NULL;
return wifi_mem_array[section].mem_ptr;
}
static int __init rk29sdk_init_wifi_mem(void)
{
int i;
int j;
for (i = 0 ; i < WLAN_SKB_BUF_NUM ; i++) {
wlan_static_skb[i] = dev_alloc_skb(
((i < (WLAN_SKB_BUF_NUM / 2)) ? 4096 : 8192));
if (!wlan_static_skb[i])
goto err_skb_alloc;
}
for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) {
wifi_mem_array[i].mem_ptr =
kmalloc(wifi_mem_array[i].size, GFP_KERNEL);
if (!wifi_mem_array[i].mem_ptr)
goto err_mem_alloc;
}
return 0;
err_mem_alloc:
pr_err("Failed to mem_alloc for WLAN\n");
for (j = 0 ; j < i ; j++)
kfree(wifi_mem_array[j].mem_ptr);
i = WLAN_SKB_BUF_NUM;
err_skb_alloc:
pr_err("Failed to skb_alloc for WLAN\n");
for (j = 0 ; j < i ; j++)
dev_kfree_skb(wlan_static_skb[j]);
return -ENOMEM;
}
static int rk29sdk_wifi_cd = 0; /* wifi virtual 'card detect' status */
static void (*wifi_status_cb)(int card_present, void *dev_id);
static void *wifi_status_cb_devid;
static int rk29sdk_wifi_status(struct device *dev)
{
return rk29sdk_wifi_cd;
}
static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
{
if(wifi_status_cb)
return -EAGAIN;
wifi_status_cb = callback;
wifi_status_cb_devid = dev_id;
return 0;
}
static int __init rk29sdk_wifi_bt_gpio_control_init(void)
{
rk29sdk_init_wifi_mem();
rk29_mux_api_set(GPIO0D6_MMC1_PWREN_NAME, GPIO0D_GPIO0D6);
if (gpio_request(RK30SDK_WIFI_GPIO_POWER_N, "wifi_power")) {
pr_info("%s: request wifi power gpio failed\n", __func__);
return -1;
}
if (gpio_request(RK29SDK_WIFI_GPIO_RESET_N, "wifi reset")) {
pr_info("%s: request wifi reset gpio failed\n", __func__);
gpio_free(RK30SDK_WIFI_GPIO_POWER_N);
return -1;
}
/*
if (gpio_request(RK29SDK_BT_GPIO_RESET_N, "bt reset")) {
pr_info("%s: request bt reset gpio failed\n", __func__);
gpio_free(RK29SDK_WIFI_GPIO_RESET_N);
return -1;
}*/
gpio_direction_output(RK30SDK_WIFI_GPIO_POWER_N, GPIO_LOW);
gpio_direction_output(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
//gpio_direction_output(RK29SDK_BT_GPIO_RESET_N, GPIO_LOW);
#if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
rk29_mux_api_set(GPIO0B4_MMC1_D1_NAME, GPIO0B_GPIO0B4);
gpio_request(RK2928_PIN0_PB4, "mmc1-data1");
gpio_direction_output(RK2928_PIN0_PB4,GPIO_LOW);//set mmc1-data1 to low.
rk29_mux_api_set(GPIO0B5_MMC1_D2_NAME, GPIO0B_GPIO0B5);
gpio_request(RK2928_PIN0_PB5, "mmc1-data2");
gpio_direction_output(RK2928_PIN0_PB5,GPIO_LOW);//set mmc1-data2 to low.
rk29_mux_api_set(GPIO0B6_MMC1_D3_NAME, GPIO0B_GPIO0B6);
gpio_request(RK2928_PIN0_PB6, "mmc1-data3");
gpio_direction_output(RK2928_PIN0_PB6,GPIO_LOW);//set mmc1-data3 to low.
rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
#endif
pr_info("%s: init finished\n",__func__);
return 0;
}
static int rk29sdk_wifi_power(int on)
{
pr_info("%s: %d\n", __func__, on);
if (on){
gpio_set_value(RK30SDK_WIFI_GPIO_POWER_N, GPIO_HIGH);
mdelay(50);
#if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
rk29_sdmmc_gpio_open(1, 1); //added by xbw at 2011-10-13
#endif
gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_HIGH);
mdelay(100);
pr_info("wifi turn on power\n");
}else{
// if (!rk29sdk_bt_power_state){
gpio_set_value(RK30SDK_WIFI_GPIO_POWER_N, GPIO_LOW);
#if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
#endif
mdelay(100);
pr_info("wifi shut off power\n");
// }else
// {
// pr_info("wifi shouldn't shut off power, bt is using it!\n");
// }
gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
}
// rk29sdk_wifi_power_state = on;
return 0;
}
static int rk29sdk_wifi_reset_state;
static int rk29sdk_wifi_reset(int on)
{
pr_info("%s: %d\n", __func__, on);
gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, on);
mdelay(100);
rk29sdk_wifi_reset_state = on;
return 0;
}
int rk29sdk_wifi_set_carddetect(int val)
{
pr_info("%s:%d\n", __func__, val);
rk29sdk_wifi_cd = val;
if (wifi_status_cb){
wifi_status_cb(val, wifi_status_cb_devid);
}else {
pr_warning("%s, nobody to notify\n", __func__);
}
return 0;
}
EXPORT_SYMBOL(rk29sdk_wifi_set_carddetect);
#define WIFI_HOST_WAKE RK2928_PIN3_PC0
static struct resource resources[] = {
{
.start = WIFI_HOST_WAKE,
.flags = IORESOURCE_IRQ,
.name = "bcmdhd_wlan_irq",
},
};
static struct wifi_platform_data rk29sdk_wifi_control = {
.set_power = rk29sdk_wifi_power,
.set_reset = rk29sdk_wifi_reset,
.set_carddetect = rk29sdk_wifi_set_carddetect,
.mem_prealloc = rk29sdk_mem_prealloc,
};
static struct platform_device rk29sdk_wifi_device = {
.name = "bcmdhd_wlan",
.id = 1,
.num_resources = ARRAY_SIZE(resources),
.resource = resources,
.dev = {
.platform_data = &rk29sdk_wifi_control,
},
};
#endif
#endif // endif --#ifdef CONFIG_SDMMC_RK29

620
arch/arm/mach-rk2928/board-rk2928-sdk-tps65910.c Executable file
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#include <linux/regulator/machine.h>
#include <linux/i2c/twl.h>
#include <linux/mfd/tps65910.h>
#include <mach/sram.h>
#include <linux/platform_device.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#define gpio_readl(offset) readl_relaxed(RK2928_GPIO3_BASE + offset)
#define gpio_writel(v, offset) do { writel_relaxed(v, RK2928_GPIO3_BASE + offset); dsb(); } while (0)
#define GPIO_SWPORTA_DR 0x0000
#define GPIO_SWPORTA_DDR 0x0004
#define GPIO3_D2_OUTPUT (1<<26)
#define GPIO3_D2_OUTPUT_HIGH (1<<26)
#define GPIO3_D2_OUTPUT_LOW (~(1<<26))
#ifdef CONFIG_MFD_TPS65910
#define PMU_POWER_SLEEP RK2928_PIN3_PD2
extern int platform_device_register(struct platform_device *pdev);
int tps65910_pre_init(struct tps65910 *tps65910){
int val = 0;
int i = 0;
int err = -1;
printk("%s,line=%d\n", __func__,__LINE__);
gpio_request(PMU_POWER_SLEEP, "NULL");
gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW);
val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL2);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DEVCTRL2 reg\n");
return val;
}
/* Set sleep state active high and allow device turn-off after PWRON long press */
val |= (DEVCTRL2_SLEEPSIG_POL_MASK | DEVCTRL2_PWON_LP_OFF_MASK);
err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL2, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_DEVCTRL2 reg\n");
return err;
}
#if 1
/* set PSKIP=0 */
val = tps65910_reg_read(tps65910, TPS65910_DCDCCTRL);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val &= ~DEVCTRL_DEV_OFF_MASK;
val &= ~DEVCTRL_DEV_SLP_MASK;
err = tps65910_reg_write(tps65910, TPS65910_DCDCCTRL, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_DCDCCTRL reg\n");
return err;
}
#endif
/* Set the maxinum load current */
/* VDD1 */
val = tps65910_reg_read(tps65910, TPS65910_VDD1);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_VDD1 reg\n");
return val;
}
val |= (1<<5); //when 1: 1.5 A
val |= (0x07<<2); //TSTEP[2:0] = 111 : 2.5 mV/|¨¬s(sampling 3 Mhz/5)
err = tps65910_reg_write(tps65910, TPS65910_VDD1, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_VDD1 reg\n");
return err;
}
/* VDD2 */
val = tps65910_reg_read(tps65910, TPS65910_VDD2);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_VDD2 reg\n");
return val;
}
val |= (1<<5); //when 1: 1.5 A
err = tps65910_reg_write(tps65910, TPS65910_VDD2, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_VDD2 reg\n");
return err;
}
/* VIO */
val = tps65910_reg_read(tps65910, TPS65910_VIO);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_VIO reg\n");
return -EIO;
}
val |= (1<<6); //when 01: 1.0 A
err = tps65910_reg_write(tps65910, TPS65910_VIO, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_VIO reg\n");
return err;
}
#if 1
/* Mask ALL interrupts */
err = tps65910_reg_write(tps65910,TPS65910_INT_MSK, 0xFF);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_INT_MSK reg\n");
return err;
}
err = tps65910_reg_write(tps65910, TPS65910_INT_MSK2, 0x03);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_INT_MSK2 reg\n");
return err;
}
/* Set RTC Power, disable Smart Reflex in DEVCTRL_REG */
#if 1
val = 0;
val |= (DEVCTRL_SR_CTL_I2C_SEL_MASK);
err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_DEVCTRL reg\n");
return err;
}
printk(KERN_INFO "TPS65910 Set default voltage.\n");
#endif
#if 0
//read sleep control register for debug
for(i=0; i<6; i++)
{
err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
if (err) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return -EIO;
}
else
printk("%s.......is 0x%04x\n",__FUNCTION__,val);
}
#endif
#if 1
//sleep control register
/*set func when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val |= (1 << 1);
err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
/* open ldo when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_LDO_ON);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val &= 0;
err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_LDO_ON, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
/*set dc mode when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_RES_ON);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val |= 0xff;
err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_RES_ON, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
/*close ldo when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_SLEEP_SET_LDO_OFF);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val |= 0x9B;
err = tps65910_reg_write(tps65910, TPS65910_SLEEP_SET_LDO_OFF, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
#endif
#if 0
//read sleep control register for debug
for(i=0; i<6; i++)
{
err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
if (err) {
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return -EIO;
}
else
printk("%s.......is 0x%4x\n",__FUNCTION__,val);
}
#endif
#endif
printk("%s,line=%d\n", __func__,__LINE__);
return 0;
}
int tps65910_post_init(struct tps65910 *tps65910)
{
struct regulator *dcdc;
struct regulator *ldo;
printk("%s,line=%d\n", __func__,__LINE__);
#ifdef CONFIG_RK30_PWM_REGULATOR
platform_device_register(&pwm_regulator_device[0]);
#endif
dcdc = regulator_get(NULL, "vio"); //vcc_io
regulator_set_voltage(dcdc, 3300000, 3300000);
regulator_enable(dcdc);
printk("%s set vio vcc_io=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
ldo = regulator_get(NULL, "vpll"); // vcc25
regulator_set_voltage(ldo, 2500000, 2500000);
regulator_enable(ldo);
printk("%s set vpll vcc25=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "vdig2"); // vdd12
regulator_set_voltage(ldo, 1200000, 1200000);
regulator_enable(ldo);
printk("%s set vdig2 vdd12=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "vaux33"); //vcc_tp
regulator_set_voltage(ldo, 3300000, 3300000);
regulator_enable(ldo);
printk("%s set vaux33 vcc_tp=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
dcdc = regulator_get(NULL, "vdd_cpu"); //vdd_cpu
regulator_set_voltage(dcdc, 1200000, 1200000);
regulator_enable(dcdc);
printk("%s set vdd1 vdd_cpu=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
dcdc = regulator_get(NULL, "vdd2"); //vcc_ddr
regulator_set_voltage(dcdc, 1200000, 1200000); // 1.5*4/5 = 1.2 and Vout=1.5v
regulator_enable(dcdc);
printk("%s set vdd2 vcc_ddr=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
ldo = regulator_get(NULL, "vdig1"); //vcc18_cif
regulator_set_voltage(ldo, 1800000, 1800000);
regulator_enable(ldo);
printk("%s set vdig1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
dcdc = regulator_get(NULL, "vaux1"); //vcc28_cif
regulator_set_voltage(dcdc,2800000,2800000);
regulator_enable(dcdc);
printk("%s set vaux1 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
ldo = regulator_get(NULL, "vaux2"); //vcca33
regulator_set_voltage(ldo, 3300000, 3300000);
regulator_enable(ldo);
printk("%s set vaux2 vcca33=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "vdac"); //
regulator_set_voltage(ldo,1800000,1800000);
regulator_enable(ldo);
printk("%s set vdac =%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "vmmc"); //vccio_wl
regulator_set_voltage(ldo,3300000,3300000);
regulator_enable(ldo);
printk("%s set vmmc vccio_wl=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
printk("%s,line=%d END\n", __func__,__LINE__);
return 0;
}
static struct regulator_consumer_supply tps65910_smps1_supply[] = {
{
.supply = "vdd1",
},
{
.supply = "vdd_cpu",
},
};
static struct regulator_consumer_supply tps65910_smps2_supply[] = {
{
.supply = "vdd2",
},
};
static struct regulator_consumer_supply tps65910_smps3_supply[] = {
{
.supply = "vdd3",
},
};
static struct regulator_consumer_supply tps65910_smps4_supply[] = {
{
.supply = "vio",
},
};
static struct regulator_consumer_supply tps65910_ldo1_supply[] = {
{
.supply = "vdig1",
},
};
static struct regulator_consumer_supply tps65910_ldo2_supply[] = {
{
.supply = "vdig2",
},
};
static struct regulator_consumer_supply tps65910_ldo3_supply[] = {
{
.supply = "vaux1",
},
};
static struct regulator_consumer_supply tps65910_ldo4_supply[] = {
{
.supply = "vaux2",
},
};
static struct regulator_consumer_supply tps65910_ldo5_supply[] = {
{
.supply = "vaux33",
},
};
static struct regulator_consumer_supply tps65910_ldo6_supply[] = {
{
.supply = "vmmc",
},
};
static struct regulator_consumer_supply tps65910_ldo7_supply[] = {
{
.supply = "vdac",
},
};
static struct regulator_consumer_supply tps65910_ldo8_supply[] = {
{
.supply = "vpll",
},
};
static struct regulator_init_data tps65910_smps1 = {
.constraints = {
.name = "VDD1",
.min_uV = 600000,
.max_uV = 1500000,
.apply_uV = 1,
.always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_smps1_supply),
.consumer_supplies = tps65910_smps1_supply,
};
/* */
static struct regulator_init_data tps65910_smps2 = {
.constraints = {
.name = "VDD2",
.min_uV = 600000,
.max_uV = 1500000,
.apply_uV = 1,
.always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_smps2_supply),
.consumer_supplies = tps65910_smps2_supply,
};
/* */
static struct regulator_init_data tps65910_smps3 = {
.constraints = {
.name = "VDD3",
.min_uV = 1000000,
.max_uV = 1400000,
.apply_uV = 1,
.always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_smps3_supply),
.consumer_supplies = tps65910_smps3_supply,
};
static struct regulator_init_data tps65910_smps4 = {
.constraints = {
.name = "VIO",
.min_uV = 1800000,
.max_uV = 3300000,
.apply_uV = 1,
.always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_smps4_supply),
.consumer_supplies = tps65910_smps4_supply,
};
static struct regulator_init_data tps65910_ldo1 = {
.constraints = {
.name = "VDIG1",
.min_uV = 1200000,
.max_uV = 2700000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo1_supply),
.consumer_supplies = tps65910_ldo1_supply,
};
/* */
static struct regulator_init_data tps65910_ldo2 = {
.constraints = {
.name = "VDIG2",
.min_uV = 1000000,
.max_uV = 1800000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo2_supply),
.consumer_supplies = tps65910_ldo2_supply,
};
/* */
static struct regulator_init_data tps65910_ldo3 = {
.constraints = {
.name = "VAUX1",
.min_uV = 1800000,
.max_uV = 3300000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo3_supply),
.consumer_supplies = tps65910_ldo3_supply,
};
/* */
static struct regulator_init_data tps65910_ldo4 = {
.constraints = {
.name = "VAUX2",
.min_uV = 1800000,
.max_uV = 3300000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo4_supply),
.consumer_supplies = tps65910_ldo4_supply,
};
/* */
static struct regulator_init_data tps65910_ldo5 = {
.constraints = {
.name = "VAUX33",
.min_uV = 1800000,
.max_uV = 3300000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo5_supply),
.consumer_supplies = tps65910_ldo5_supply,
};
/* */
static struct regulator_init_data tps65910_ldo6 = {
.constraints = {
.name = "VMMC",
.min_uV = 1800000,
.max_uV = 3300000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo6_supply),
.consumer_supplies = tps65910_ldo6_supply,
};
/* */
static struct regulator_init_data tps65910_ldo7 = {
.constraints = {
.name = "VDAC",
.min_uV = 1800000,
.max_uV = 2850000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo7_supply),
.consumer_supplies = tps65910_ldo7_supply,
};
/* */
static struct regulator_init_data tps65910_ldo8 = {
.constraints = {
.name = "VPLL",
.min_uV = 1000000,
.max_uV = 2500000,
.apply_uV = 1,
.always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(tps65910_ldo8_supply),
.consumer_supplies = tps65910_ldo8_supply,
};
void __sramfunc board_pmu_suspend(void)
{
int ret;
ret = gpio_readl(GPIO_SWPORTA_DDR);
gpio_writel(ret | GPIO3_D2_OUTPUT, GPIO_SWPORTA_DDR);
ret = gpio_readl(GPIO_SWPORTA_DR);
gpio_writel(ret | GPIO3_D2_OUTPUT_HIGH, GPIO_SWPORTA_DR); //set pmu_sleep output high
}
void __sramfunc board_pmu_resume(void)
{
int ret;
ret = gpio_readl(GPIO_SWPORTA_DDR);
gpio_writel(ret | GPIO3_D2_OUTPUT, GPIO_SWPORTA_DDR);
ret = gpio_readl(GPIO_SWPORTA_DR);
gpio_writel(ret & GPIO3_D2_OUTPUT_LOW, GPIO_SWPORTA_DR); //set pmu_sleep output low
sram_udelay(2000);
}
static struct tps65910_board tps65910_data = {
.irq = (unsigned)TPS65910_HOST_IRQ,
.irq_base = NR_GIC_IRQS + NR_GPIO_IRQS,
.gpio_base = TPS65910_GPIO_EXPANDER_BASE,
.pre_init = tps65910_pre_init,
.post_init = tps65910_post_init,
//TPS65910_NUM_REGS = 13
// Regulators
.tps65910_pmic_init_data[TPS65910_REG_VRTC] = NULL,
.tps65910_pmic_init_data[TPS65910_REG_VIO] = &tps65910_smps4,
.tps65910_pmic_init_data[TPS65910_REG_VDD1] = &tps65910_smps1,
.tps65910_pmic_init_data[TPS65910_REG_VDD2] = &tps65910_smps2,
.tps65910_pmic_init_data[TPS65910_REG_VDD3] = &tps65910_smps3,
.tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &tps65910_ldo1,
.tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &tps65910_ldo2,
.tps65910_pmic_init_data[TPS65910_REG_VPLL] = &tps65910_ldo8,
.tps65910_pmic_init_data[TPS65910_REG_VDAC] = &tps65910_ldo7,
.tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &tps65910_ldo3,
.tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &tps65910_ldo4,
.tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &tps65910_ldo5,
.tps65910_pmic_init_data[TPS65910_REG_VMMC] = &tps65910_ldo6,
};
#endif

909
arch/arm/mach-rk2928/board-rk2928-sdk.c Executable file
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@ -0,0 +1,909 @@
/* arch/arm/mach-rk2928/board-rk2928-fpga.c
*
* Copyright (C) 2012 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/skbuff.h>
#include <linux/spi/spi.h>
#include <linux/mmc/host.h>
#include <linux/ion.h>
#include <linux/cpufreq.h>
#include <linux/clk.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
#include <asm/hardware/gic.h>
#include <mach/dvfs.h>
#include <mach/board.h>
#include <mach/hardware.h>
#include <mach/io.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <linux/fb.h>
#include <linux/regulator/machine.h>
#include <linux/rfkill-rk.h>
#include <linux/sensor-dev.h>
#include <linux/mfd/tps65910.h>
#include <linux/regulator/rk29-pwm-regulator.h>
#if defined(CONFIG_HDMI_RK30)
#include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
#endif
#if defined(CONFIG_SPIM_RK29)
#include "../../../drivers/spi/rk29_spim.h"
#endif
#ifdef CONFIG_THREE_FB_BUFFER
#define RK30_FB0_MEM_SIZE 12*SZ_1M
#else
#define RK30_FB0_MEM_SIZE 8*SZ_1M
#endif
#include "board-rk2928-sdk-camera.c"
#include "board-rk2928-sdk-key.c"
#if defined (CONFIG_EETI_EGALAX)
#define TOUCH_RESET_PIN RK2928_PIN3_PC3
#define TOUCH_INT_PIN RK2928_PIN3_PC7
static int EETI_EGALAX_init_platform_hw(void)
{
if(gpio_request(TOUCH_RESET_PIN,NULL) != 0){
gpio_free(TOUCH_RESET_PIN);
printk("p1003_init_platform_hw gpio_request error\n");
return -EIO;
}
if(gpio_request(TOUCH_INT_PIN,NULL) != 0){
gpio_free(TOUCH_INT_PIN);
printk("p1003_init_platform_hw gpio_request error\n");
return -EIO;
}
gpio_pull_updown(TOUCH_INT_PIN, 1);
gpio_direction_output(TOUCH_RESET_PIN, 0);
msleep(500);
gpio_set_value(TOUCH_RESET_PIN,GPIO_LOW);
msleep(500);
gpio_set_value(TOUCH_RESET_PIN,GPIO_HIGH);
return 0;
}
static struct eeti_egalax_platform_data eeti_egalax_info = {
.model= 1003,
.init_platform_hw= EETI_EGALAX_init_platform_hw,
.standby_pin = INVALID_GPIO,
//.standby_value = GPIO_HIGH,
.disp_on_pin = INVALID_GPIO,
//.disp_on_value = GPIO_HIGH,
};
#endif
static struct spi_board_info board_spi_devices[] = {
};
/***********************************************************
* rk30 backlight
************************************************************/
#ifdef CONFIG_BACKLIGHT_RK29_BL
#define PWM_ID 0
#define PWM_MUX_NAME GPIO0D2_PWM_0_NAME
#define PWM_MUX_MODE GPIO0D_PWM_0
#define PWM_MUX_MODE_GPIO GPIO0D_GPIO0D2
#define PWM_GPIO RK2928_PIN0_PD2
#define PWM_EFFECT_VALUE 1
#define LCD_DISP_ON_PIN
#ifdef LCD_DISP_ON_PIN
#define BL_EN_PIN RK2928_PIN3_PC4
#define BL_EN_VALUE GPIO_HIGH
#endif
static int rk29_backlight_io_init(void)
{
int ret = 0;
rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
#ifdef LCD_DISP_ON_PIN
// rk30_mux_api_set(BL_EN_MUX_NAME, BL_EN_MUX_MODE);
ret = gpio_request(BL_EN_PIN, NULL);
if (ret != 0) {
gpio_free(BL_EN_PIN);
}
gpio_direction_output(BL_EN_PIN, 0);
gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
#endif
return ret;
}
static int rk29_backlight_io_deinit(void)
{
int ret = 0;
#ifdef LCD_DISP_ON_PIN
gpio_free(BL_EN_PIN);
#endif
rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
return ret;
}
static int rk29_backlight_pwm_suspend(void)
{
int ret = 0;
rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE_GPIO);
if (gpio_request(PWM_GPIO, NULL)) {
printk("func %s, line %d: request gpio fail\n", __FUNCTION__, __LINE__);
return -1;
}
gpio_direction_output(PWM_GPIO, GPIO_LOW);
#ifdef LCD_DISP_ON_PIN
gpio_direction_output(BL_EN_PIN, 0);
gpio_set_value(BL_EN_PIN, !BL_EN_VALUE);
#endif
return ret;
}
static int rk29_backlight_pwm_resume(void)
{
gpio_free(PWM_GPIO);
rk30_mux_api_set(PWM_MUX_NAME, PWM_MUX_MODE);
#ifdef LCD_DISP_ON_PIN
msleep(30);
gpio_direction_output(BL_EN_PIN, 1);
gpio_set_value(BL_EN_PIN, BL_EN_VALUE);
#endif
return 0;
}
static struct rk29_bl_info rk29_bl_info = {
.pwm_id = PWM_ID,
.bl_ref = PWM_EFFECT_VALUE,
.io_init = rk29_backlight_io_init,
.io_deinit = rk29_backlight_io_deinit,
.pwm_suspend = rk29_backlight_pwm_suspend,
.pwm_resume = rk29_backlight_pwm_resume,
};
static struct platform_device rk29_device_backlight = {
.name = "rk29_backlight",
.id = -1,
.dev = {
.platform_data = &rk29_bl_info,
}
};
#endif
/*MMA8452 gsensor*/
#if defined (CONFIG_GS_MMA8452)
static int mma8452_init_platform_hw(void)
{
return 0;
}
static struct sensor_platform_data mma8452_info = {
.type = SENSOR_TYPE_ACCEL,
.irq_enable = 1,
.poll_delay_ms = 30,
.init_platform_hw = mma8452_init_platform_hw,
.orientation = {-1, 0, 0, 0, 0, 1, 0, -1, 0},
};
#endif
#if defined (CONFIG_COMPASS_AK8975)
static struct sensor_platform_data akm8975_info =
{
.type = SENSOR_TYPE_COMPASS,
.irq_enable = 1,
.poll_delay_ms = 30,
.m_layout =
{
{
{1, 0, 0},
{0, 1, 0},
{0, 0, 1},
},
{
{1, 0, 0},
{0, 1, 0},
{0, 0, 1},
},
{
{1, 0, 0},
{0, 1, 0},
{0, 0, 1},
},
{
{1, 0, 0},
{0, 1, 0},
{0, 0, 1},
},
}
};
#endif
#if defined(CONFIG_GYRO_L3G4200D)
#include <linux/l3g4200d.h>
static int l3g4200d_init_platform_hw(void)
{
return 0;
}
static struct sensor_platform_data l3g4200d_info = {
.type = SENSOR_TYPE_GYROSCOPE,
.irq_enable = 1,
.poll_delay_ms = 30,
.orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
.init_platform_hw = l3g4200d_init_platform_hw,
.x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
.y_min = 40,
.z_min = 20,
};
#endif
#ifdef CONFIG_LS_CM3217
static struct sensor_platform_data cm3217_info = {
.type = SENSOR_TYPE_LIGHT,
.irq_enable = 0,
.poll_delay_ms = 500,
};
#endif
#ifdef CONFIG_FB_ROCKCHIP
#define LCD_CABC_MUX_NAME GPIO2D1_LCDC0_D23_LCDC1_D23_NAME
#define LCD_CABC_GPIO_MODE GPIO2D_GPIO2D1
#define LCD_CABC_EN RK2928_PIN2_PD1
#define LCD_CABC_EN_VALUE GPIO_HIGH
static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
{
int ret = 0;
rk30_mux_api_set(LCD_CABC_MUX_NAME, LCD_CABC_GPIO_MODE);
ret = gpio_request(LCD_CABC_EN, NULL);
if (ret != 0)
{
gpio_free(LCD_CABC_EN);
printk(KERN_ERR "request lcd cabc en pin fail!\n");
return -1;
}
else
{
gpio_direction_output(LCD_CABC_EN, !LCD_CABC_EN_VALUE); //disable
}
return 0;
}
static int rk_fb_io_disable(void)
{
return 0;
}
static int rk_fb_io_enable(void)
{
return 0;
}
#if defined(CONFIG_LCDC_RK2928)
struct rk29fb_info lcdc_screen_info = {
.prop = PRMRY, //primary display device
.io_init = rk_fb_io_init,
.io_disable = rk_fb_io_disable,
.io_enable = rk_fb_io_enable,
.set_screen_info = set_lcd_info,
};
#endif
static struct resource resource_fb[] = {
[0] = {
.name = "fb0 buf",
.start = 0,
.end = 0,//RK30_FB0_MEM_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = "ipp buf", //for rotate
.start = 0,
.end = 0,//RK30_FB0_MEM_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[2] = {
.name = "fb2 buf",
.start = 0,
.end = 0,//RK30_FB0_MEM_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device device_fb = {
.name = "rk-fb",
.id = -1,
.num_resources = ARRAY_SIZE(resource_fb),
.resource = resource_fb,
};
#endif
#ifdef CONFIG_ION
#define ION_RESERVE_SIZE (80 * SZ_1M)
static struct ion_platform_data rk30_ion_pdata = {
.nr = 1,
.heaps = {
{
.type = ION_HEAP_TYPE_CARVEOUT,
.id = ION_NOR_HEAP_ID,
.name = "norheap",
.size = ION_RESERVE_SIZE,
}
},
};
static struct platform_device device_ion = {
.name = "ion-rockchip",
.id = 0,
.dev = {
.platform_data = &rk30_ion_pdata,
},
};
#endif
#ifdef CONFIG_RK30_PWM_REGULATOR
const static int pwm_voltage_map[] = {
1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
};
static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
{
.supply = "vdd_core",
}
};
struct regulator_init_data pwm_regulator_init_dcdc[1] =
{
{
.constraints = {
.name = "PWM_DCDC1",
.min_uV = 600000,
.max_uV = 1800000, //0.6-1.8V
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
.consumer_supplies = pwm_dcdc1_consumers,
},
};
static struct pwm_platform_data pwm_regulator_info[1] = {
{
.pwm_id = 2,
.pwm_gpio = RK2928_PIN0_PD4,
.pwm_iomux_name = GPIO0D4_PWM_2_NAME,
.pwm_iomux_pwm = GPIO0D_PWM_2,
.pwm_iomux_gpio = GPIO0D_GPIO0D4,
.pwm_voltage = 1200000,
.suspend_voltage = 1050000,
.min_uV = 1000000,
.max_uV = 1400000,
.coefficient = 455, //45.5%
.pwm_voltage_map = pwm_voltage_map,
.init_data = &pwm_regulator_init_dcdc[0],
},
};
struct platform_device pwm_regulator_device[1] = {
{
.name = "pwm-voltage-regulator",
.id = 0,
.dev = {
.platform_data = &pwm_regulator_info[0],
}
},
};
#endif
/**************************************************************************************************
* SDMMC devices, include the module of SD,MMC,and sdio.noted by xbw at 2012-03-05
**************************************************************************************************/
#ifdef CONFIG_SDMMC_RK29
#include "board-rk2928-sdk-sdmmc.c"
#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
#define SDMMC0_WRITE_PROTECT_PIN RK2928_PIN1_PA7 //According to your own project to set the value of write-protect-pin.
#endif
#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
#define SDMMC1_WRITE_PROTECT_PIN RK2928_PIN0_PD5 //According to your own project to set the value of write-protect-pin.
#endif
#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK2928_PIN0_PB2
#endif //endif ---#ifdef CONFIG_SDMMC_RK29
#ifdef CONFIG_SDMMC0_RK29
static int rk29_sdmmc0_cfg_gpio(void)
{
rk29_sdmmc_set_iomux(0, 0xFFFF);
rk30_mux_api_set(GPIO1C1_MMC0_DETN_NAME, GPIO1C_MMC0_DETN);
#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
gpio_direction_input(SDMMC0_WRITE_PROTECT_PIN);
#endif
return 0;
}
#define CONFIG_SDMMC0_USE_DMA
struct rk29_sdmmc_platform_data default_sdmmc0_data = {
.host_ocr_avail =
(MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36),
.host_caps =
(MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
.io_init = rk29_sdmmc0_cfg_gpio,
#if !defined(CONFIG_SDMMC_RK29_OLD)
.set_iomux = rk29_sdmmc_set_iomux,
#endif
.dma_name = "sd_mmc",
#ifdef CONFIG_SDMMC0_USE_DMA
.use_dma = 1,
#else
.use_dma = 0,
#endif
.detect_irq = RK2928_PIN1_PC1, // INVALID_GPIO
.enable_sd_wakeup = 0,
#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
.write_prt = SDMMC0_WRITE_PROTECT_PIN,
#else
.write_prt = INVALID_GPIO,
#endif
};
#endif // CONFIG_SDMMC0_RK29
#ifdef CONFIG_SDMMC1_RK29
#define CONFIG_SDMMC1_USE_DMA
static int rk29_sdmmc1_cfg_gpio(void)
{
#if defined(CONFIG_SDMMC_RK29_OLD)
rk30_mux_api_set(GPIO0B0_MMC1_CMD_NAME, GPIO0B_MMC1_CMD);
rk30_mux_api_set(GPIO0B1_MMC1_CLKOUT_NAME, GPIO0B_MMC1_CLKOUT);
rk30_mux_api_set(GPIO0B3_MMC1_D0_NAME, GPIO0B_MMC1_D0);
rk30_mux_api_set(GPIO0B4_MMC1_D1_NAME, GPIO0B_MMC1_D1);
rk30_mux_api_set(GPIO0B5_MMC1_D2_NAME, GPIO0B_MMC1_D2);
rk30_mux_api_set(GPIO0B6_MMC1_D3_NAME, GPIO0B_MMC1_D3);
//rk30_mux_api_set(GPIO0B2_MMC1_DETN_NAME, GPIO0B_MMC1_DETN);
#else
#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
gpio_request(SDMMC1_WRITE_PROTECT_PIN, "sdio-wp");
gpio_direction_input(SDMMC1_WRITE_PROTECT_PIN);
#endif
#endif
return 0;
}
struct rk29_sdmmc_platform_data default_sdmmc1_data = {
.host_ocr_avail =
(MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 |
MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
MMC_VDD_33_34),
#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
.host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
#else
.host_caps =
(MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
#endif
.io_init = rk29_sdmmc1_cfg_gpio,
#if !defined(CONFIG_SDMMC_RK29_OLD)
.set_iomux = rk29_sdmmc_set_iomux,
#endif
.dma_name = "sdio",
#ifdef CONFIG_SDMMC1_USE_DMA
.use_dma = 1,
#else
.use_dma = 0,
#endif
#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
#ifdef CONFIG_WIFI_CONTROL_FUNC
.status = rk29sdk_wifi_status,
.register_status_notify = rk29sdk_wifi_status_register,
#endif
#if 0
.detect_irq = RK29SDK_WIFI_SDIO_CARD_DETECT_N,
#endif
#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
.write_prt = SDMMC1_WRITE_PROTECT_PIN,
#else
.write_prt = INVALID_GPIO,
#endif
#else
.detect_irq = INVALID_GPIO,
.enable_sd_wakeup = 0,
#endif
};
#endif //endif--#ifdef CONFIG_SDMMC1_RK29
/**************************************************************************************************
* the end of setting for SDMMC devices
**************************************************************************************************/
#ifdef CONFIG_RFKILL_RK
// bluetooth rfkill device, its driver in net/rfkill/rfkill-rk.c
static struct rfkill_rk_platform_data rfkill_rk_platdata = {
.type = RFKILL_TYPE_BLUETOOTH,
.poweron_gpio = { // BT_REG_ON
.io = INVALID_GPIO,
.enable = GPIO_HIGH,
.iomux = {
.name = NULL,
},
},
.reset_gpio = { // BT_RST
.io = RK2928_PIN3_PD5, // set io to INVALID_GPIO for disable it
.enable = GPIO_LOW,
.iomux = {
.name = NULL,
},
},
.wake_gpio = { // BT_WAKE, use to control bt's sleep and wakeup
.io = RK2928_PIN0_PC6, // set io to INVALID_GPIO for disable it
.enable = GPIO_HIGH,
.iomux = {
.name = NULL,
},
},
.wake_host_irq = { // BT_HOST_WAKE, for bt wakeup host when it is in deep sleep
.gpio = {
.io = RK2928_PIN0_PC5, // set io to INVALID_GPIO for disable it
.enable = GPIO_LOW, // set GPIO_LOW for falling, set 0 for rising
.iomux = {
.name = NULL,
},
},
},
.rts_gpio = { // UART_RTS, enable or disable BT's data coming
.io = RK2928_PIN0_PC3, // set io to INVALID_GPIO for disable it
.enable = GPIO_LOW,
.iomux = {
.name = GPIO0C3_UART0_CTSN_NAME,
.fgpio = GPIO0C_GPIO0C3,
.fmux = GPIO0C_UART0_CTSN,
},
},
};
static struct platform_device device_rfkill_rk = {
.name = "rfkill_rk",
.id = -1,
.dev = {
.platform_data = &rfkill_rk_platdata,
},
};
#endif
#ifdef CONFIG_SND_SOC_RK2928
static struct resource resources_acodec[] = {
{
.start = RK2928_ACODEC_PHYS,
.end = RK2928_ACODEC_PHYS + RK2928_ACODEC_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = RK2928_PIN3_PD4,
.end = RK2928_PIN3_PD4,
.flags = IORESOURCE_IO,
},
};
static struct platform_device device_acodec = {
.name = "rk2928-codec",
.id = -1,
.num_resources = ARRAY_SIZE(resources_acodec),
.resource = resources_acodec,
};
#endif
static struct platform_device *devices[] __initdata = {
#ifdef CONFIG_BACKLIGHT_RK29_BL
&rk29_device_backlight,
#endif
#ifdef CONFIG_FB_ROCKCHIP
&device_fb,
#endif
#ifdef CONFIG_ION
&device_ion,
#endif
#ifdef CONFIG_WIFI_CONTROL_FUNC
&rk29sdk_wifi_device,
#endif
#ifdef CONFIG_RFKILL_RK
&device_rfkill_rk,
#endif
#ifdef CONFIG_SND_SOC_RK2928
&device_acodec,
#endif
};
//i2c
#ifdef CONFIG_I2C0_RK30
static struct i2c_board_info __initdata i2c0_info[] = {
#if defined (CONFIG_GS_MMA8452)
{
.type = "gs_mma8452",
.addr = 0x1d,
.flags = 0,
.irq = RK2928_PIN3_PD1,
.platform_data = &mma8452_info,
},
#endif
#if defined (CONFIG_COMPASS_AK8975)
{
.type = "ak8975",
.addr = 0x0d,
.flags = 0,
.irq = RK2928_PIN3_PD2,
.platform_data = &akm8975_info,
},
#endif
#if defined (CONFIG_GYRO_L3G4200D)
{
.type = "l3g4200d_gryo",
.addr = 0x69,
.flags = 0,
.irq = RK2928_PIN3_PD3,
.platform_data = &l3g4200d_info,
},
#endif
};
#endif
#ifdef CONFIG_I2C1_RK30
#ifdef CONFIG_MFD_TPS65910
#define TPS65910_HOST_IRQ RK2928_PIN3_PC6
#include "board-rk2928-sdk-tps65910.c"
#endif
static struct i2c_board_info __initdata i2c1_info[] = {
#if defined (CONFIG_MFD_TPS65910)
{
.type = "tps65910",
.addr = TPS65910_I2C_ID0,
.flags = 0,
.irq = TPS65910_HOST_IRQ,
.platform_data = &tps65910_data,
},
#endif
};
#endif
#ifdef CONFIG_I2C2_RK30
static struct i2c_board_info __initdata i2c2_info[] = {
#if defined (CONFIG_EETI_EGALAX)
{
.type = "egalax_i2c",
.addr = 0x04,
.flags = 0,
.irq = RK2928_PIN3_PC7,
.platform_data = &eeti_egalax_info,
},
#endif
#if defined (CONFIG_LS_CM3217)
{
.type = "lightsensor",
.addr = 0x10,
.flags = 0,
.platform_data = &cm3217_info,
},
#endif
};
#endif
#ifdef CONFIG_I2C3_RK30
static struct i2c_board_info __initdata i2c3_info[] = {
};
#endif
#ifdef CONFIG_I2C_GPIO_RK30
#define I2C_SDA_PIN INVALID_GPIO //set sda_pin here
#define I2C_SCL_PIN INVALID_GPIO //set scl_pin here
static int rk30_i2c_io_init(void)
{
//set iomux (gpio) here
return 0;
}
struct i2c_gpio_platform_data default_i2c_gpio_data = {
.sda_pin = I2C_SDA_PIN,
.scl_pin = I2C_SCL_PIN,
.udelay = 5, // clk = 500/udelay = 100Khz
.timeout = 100,//msecs_to_jiffies(100),
.bus_num = 5,
.io_init = rk30_i2c_io_init,
};
static struct i2c_board_info __initdata i2c_gpio_info[] = {
};
#endif
static void __init rk30_i2c_register_board_info(void)
{
#ifdef CONFIG_I2C0_RK30
i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info));
#endif
#ifdef CONFIG_I2C1_RK30
i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info));
#endif
#ifdef CONFIG_I2C2_RK30
i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info));
#endif
#ifdef CONFIG_I2C3_RK30
i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info));
#endif
#ifdef CONFIG_I2C_GPIO_RK30
i2c_register_board_info(4, i2c_gpio_info, ARRAY_SIZE(i2c_gpio_info));
#endif
}
//end of i2c
#define POWER_ON_PIN RK2928_PIN3_PC5 //power_hold
static void rk2928_pm_power_off(void)
{
printk(KERN_ERR "rk2928_pm_power_off start...\n");
#if defined(CONFIG_MFD_TPS65910)
tps65910_device_shutdown();//tps65910 shutdown
#endif
gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
};
static void __init rk2928_board_init(void)
{
gpio_request(POWER_ON_PIN, "poweronpin");
gpio_direction_output(POWER_ON_PIN, GPIO_HIGH);
gpio_free(POWER_ON_PIN);
pm_power_off = rk2928_pm_power_off;
rk30_i2c_register_board_info();
spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices));
platform_add_devices(devices, ARRAY_SIZE(devices));
//RK2928 USB DETECT IRQ: IRQ_OTG_BVALID
//board_usb_detect_init(RK30_PIN6_PA3);
#ifdef CONFIG_WIFI_CONTROL_FUNC
rk29sdk_wifi_bt_gpio_control_init();
#endif
}
static void __init rk2928_reserve(void)
{
#ifdef CONFIG_ION
rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE);
#endif
#ifdef CONFIG_FB_ROCKCHIP
resource_fb[0].start = board_mem_reserve_add("fb0", RK30_FB0_MEM_SIZE);
resource_fb[0].end = resource_fb[0].start + RK30_FB0_MEM_SIZE - 1;
#if 0
resource_fb[1].start = board_mem_reserve_add("ipp buf", RK30_FB0_MEM_SIZE);
resource_fb[1].end = resource_fb[1].start + RK30_FB0_MEM_SIZE - 1;
resource_fb[2].start = board_mem_reserve_add("fb2", RK30_FB0_MEM_SIZE);
resource_fb[2].end = resource_fb[2].start + RK30_FB0_MEM_SIZE - 1;
#endif
#endif
#ifdef CONFIG_VIDEO_RK29
rk30_camera_request_reserve_mem();
#endif
board_mem_reserved();
}
/**
* dvfs_cpu_logic_table: table for arm and logic dvfs
* @frequency : arm frequency
* @cpu_volt : arm voltage depend on frequency
* @logic_volt : logic voltage arm requests depend on frequency
* comments : min arm/logic voltage
*/
static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
{.frequency = 216 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},//0.975V/1.000V
{.frequency = 312 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},//0.975V/1.000V
{.frequency = 408 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},//1.000V/1.025V
{.frequency = 504 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},//1.000V/1.025V
{.frequency = 600 * 1000, .cpu_volt = 1200 * 1000, .logic_volt = 1200 * 1000},//1.025V/1.050V
{.frequency = 696 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.000V/1.025V
{.frequency = 816 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
{.frequency = 912 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
#if 0
{.frequency = 1008 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
{.frequency = 1104 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
{.frequency = 1200 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
{.frequency = 1104 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
{.frequency = 1248 * 1000, .cpu_volt = 1400 * 1000, .logic_volt = 1200 * 1000},//1.100V/1.050V
#endif
//{.frequency = 1000 * 1000, .cpu_volt = 1225 * 1000, .logic_volt = 1200 * 1000},//1.150V/1.100V
{.frequency = CPUFREQ_TABLE_END},
};
static struct cpufreq_frequency_table dvfs_gpu_table[] = {
{.frequency = 266 * 1000, .index = 1050 * 1000},
{.frequency = 400 * 1000, .index = 1275 * 1000},
{.frequency = CPUFREQ_TABLE_END},
};
static struct cpufreq_frequency_table dvfs_ddr_table[] = {
{.frequency = 300 * 1000, .index = 1050 * 1000},
{.frequency = 400 * 1000, .index = 1125 * 1000},
{.frequency = CPUFREQ_TABLE_END},
};
#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
void __init board_clock_init(void)
{
rk2928_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
//dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
printk("%s end\n", __func__);
}
MACHINE_START(RK2928, "RK2928board")
.boot_params = PLAT_PHYS_OFFSET + 0x800,
.fixup = rk2928_fixup,
.reserve = &rk2928_reserve,
.map_io = rk2928_map_io,
.init_irq = rk2928_init_irq,
.timer = &rk2928_timer,
.init_machine = rk2928_board_init,
MACHINE_END

751
arch/arm/mach-rk2928/clock.c Normal file
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/* linux/arch/arm/mach-rk30/clock.c
*
* Copyright (C) 2012 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/hardirq.h>
#include <linux/delay.h>
#include <mach/clock.h>
#include "clock.h"
#include <mach/dvfs.h>
#include <linux/delay.h>
#define CLOCK_PRINTK_DBG(fmt, args...) pr_debug(fmt, ## args);
#define CLOCK_PRINTK_ERR(fmt, args...) pr_err(fmt, ## args);
#define CLOCK_PRINTK_LOG(fmt, args...) pr_debug(fmt, ## args);
/* Clock flags */
/* bit 0 is free */
#define RATE_FIXED (1 << 1) /* Fixed clock rate */
#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
#define MHZ (1000*1000)
#define KHZ (1000)
static void __clk_recalc(struct clk *clk);
static void __propagate_rate(struct clk *tclk);
static void __clk_reparent(struct clk *child, struct clk *parent);
static LIST_HEAD(clocks);
static DEFINE_MUTEX(clocks_mutex);
static DEFINE_SPINLOCK(clockfw_lock);
static LIST_HEAD(root_clks);
static void clk_notify(struct clk *clk, unsigned long msg,
unsigned long old_rate, unsigned long new_rate);
#define LOCK() do { WARN_ON(in_irq()); if (!irqs_disabled()) spin_lock_bh(&clockfw_lock); } while (0)
#define UNLOCK() do { if (!irqs_disabled()) spin_unlock_bh(&clockfw_lock); } while (0)
/**********************************************for clock data****************************************************/
static struct clk *def_ops_clk=NULL;
void clk_register_default_ops_clk(struct clk *clk)
{
def_ops_clk=clk;
}
static struct clk *clk_default_get_parent(struct clk *clk)
{
if(def_ops_clk&&def_ops_clk->get_parent)
return def_ops_clk->get_parent(clk);
else return NULL;
}
static int clk_default_set_parent(struct clk *clk, struct clk *parent)
{
if(def_ops_clk&&def_ops_clk->set_parent)
return def_ops_clk->set_parent(clk,parent);
else
return -EINVAL;
}
int __init clk_disable_unused(void)
{
struct clk *ck;
list_for_each_entry(ck, &clocks, node) {
if (ck->usecount > 0 || ck->mode == NULL || (ck->flags & IS_PD))
continue;
LOCK();
clk_enable_nolock(ck);
clk_disable_nolock(ck);
UNLOCK();
}
return 0;
}
/**
* recalculate_root_clocks - recalculate and propagate all root clocks
*
* Recalculates all root clocks (clocks with no parent), which if the
* clock's .recalc is set correctly, should also propagate their rates.
* Called at init.
*/
void clk_recalculate_root_clocks_nolock(void)
{
struct clk *clkp;
list_for_each_entry(clkp, &root_clks, sibling) {
__clk_recalc(clkp);
__propagate_rate(clkp);
}
}
/*
void clk_recalculate_root_clocks(void)
{
LOCK();
clk_recalculate_root_clocks_nolock();
UNLOCK();
}*/
/**
* clk_preinit - initialize any fields in the struct clk before clk init
* @clk: struct clk * to initialize
*
* Initialize any struct clk fields needed before normal clk initialization
* can run. No return value.
*/
int clk_register(struct clk *clk)
{
if (clk == NULL || IS_ERR(clk))
return -EINVAL;
//INIT_LIST_HEAD(&clk->sibling);
INIT_LIST_HEAD(&clk->children);
/*
* trap out already registered clocks
*/
if (clk->node.next || clk->node.prev)
return 0;
mutex_lock(&clocks_mutex);
if (clk->get_parent)
clk->parent = clk->get_parent(clk);
else if (clk->parents)
clk->parent =clk_default_get_parent(clk);
if (clk->parent)
list_add(&clk->sibling, &clk->parent->children);
else
list_add(&clk->sibling, &root_clks);
list_add(&clk->node, &clocks);
mutex_unlock(&clocks_mutex);
return 0;
}
/************************************************************/
static void __clk_recalc(struct clk *clk)
{
if (unlikely(clk->flags & RATE_FIXED))
return;
if (clk->recalc)
clk->rate = clk->recalc(clk);
else if (clk->parent)
clk->rate = clk->parent->rate;
}
static void __clk_reparent(struct clk *child, struct clk *parent)
{
if (child->parent == parent)
return;
//CLOCK_PRINTK_DBG("%s reparent to %s (was %s)\n", child->name, parent->name, ((child->parent) ? child->parent->name : "NULL"));
list_del_init(&child->sibling);
if (parent)
list_add(&child->sibling, &parent->children);
child->parent = parent;
}
/* Propagate rate to children */
static void __propagate_rate(struct clk *tclk)
{
struct clk *clkp;
//CLOCK_PRINTK_DBG("propagate_rate clk %s\n",clkp->name);
list_for_each_entry(clkp, &tclk->children, sibling) {
__clk_recalc(clkp);
__propagate_rate(clkp);
}
//CLOCK_PRINTK_DBG("propagate_rate clk %s end\n",clkp->name);
}
int clk_enable_nolock(struct clk *clk)
{
int ret = 0;
if (clk->usecount == 0) {
if (clk->parent) {
ret = clk_enable_nolock(clk->parent);
if (ret)
return ret;
}
if (clk->notifier_count)
clk_notify(clk, CLK_PRE_ENABLE, clk->rate, clk->rate);
if (clk->mode)
ret = clk->mode(clk, 1);
if (clk->notifier_count)
clk_notify(clk, ret ? CLK_ABORT_ENABLE : CLK_POST_ENABLE, clk->rate, clk->rate);
if (ret) {
if (clk->parent)
clk_disable_nolock(clk->parent);
return ret;
}
pr_debug("%s enabled\n", clk->name);
}
clk->usecount++;
return ret;
}
void clk_disable_nolock(struct clk *clk)
{
if (clk->usecount == 0) {
CLOCK_PRINTK_ERR(KERN_ERR "Trying disable clock %s with 0 usecount\n", clk->name);
WARN_ON(1);
return;
}
if (--clk->usecount == 0) {
int ret = 0;
if (clk->notifier_count)
clk_notify(clk, CLK_PRE_DISABLE, clk->rate, clk->rate);
if (clk->mode)
ret = clk->mode(clk, 0);
if (clk->notifier_count)
clk_notify(clk, ret ? CLK_ABORT_DISABLE : CLK_POST_DISABLE, clk->rate, clk->rate);
pr_debug("%s disabled\n", clk->name);
if (ret == 0 && clk->parent)
clk_disable_nolock(clk->parent);
}
}
/* Given a clock and a rate apply a clock specific rounding function */
long clk_round_rate_nolock(struct clk *clk, unsigned long rate)
{
if (clk->round_rate)
return clk->round_rate(clk, rate);
if (clk->flags & RATE_FIXED)
CLOCK_PRINTK_ERR("clock: clk_round_rate called on fixed-rate clock %s\n", clk->name);
return clk->rate;
}
int is_suport_round_rate(struct clk *clk)
{
return (clk->round_rate) ? 0:(-1);
}
int clk_set_rate_nolock(struct clk *clk, unsigned long rate)
{
int ret;
unsigned long old_rate;
if (rate == clk->rate)
return 0;
if (clk->flags & CONFIG_PARTICIPANT)
return -EINVAL;
if (!clk->set_rate)
return -EINVAL;
pr_debug("**will set %s rate %lu\n", clk->name, rate);
old_rate = clk->rate;
if (clk->notifier_count)
clk_notify(clk, CLK_PRE_RATE_CHANGE, old_rate, rate);
ret = clk->set_rate(clk, rate);
if (ret == 0) {
__clk_recalc(clk);
pr_debug("**set %s rate recalc=%lu\n",clk->name,clk->rate);
__propagate_rate(clk);
}
if (clk->notifier_count)
clk_notify(clk, ret ? CLK_ABORT_RATE_CHANGE : CLK_POST_RATE_CHANGE, old_rate, clk->rate);
return ret;
}
int clk_set_parent_nolock(struct clk *clk, struct clk *parent)
{
int ret;
int enabled = clk->usecount > 0;
struct clk *old_parent = clk->parent;
if (clk->parent == parent)
return 0;
/* if clk is already enabled, enable new parent first and disable old parent later. */
if (enabled)
clk_enable_nolock(parent);
if (clk->set_parent)
ret = clk->set_parent(clk, parent);
else
ret = clk_default_set_parent(clk,parent);
if (ret == 0) {
/* OK */
//CLOCK_PRINTK_DBG("set_parent %s reparent\n",clk->name,parent->name);
__clk_reparent(clk, parent);
__clk_recalc(clk);
__propagate_rate(clk);
if (enabled)
clk_disable_nolock(old_parent);
} else {
//CLOCK_PRINTK_DBG("set_parent err\n",clk->name,parent->name);
if (enabled)
clk_disable_nolock(parent);
}
return ret;
}
/**********************************dvfs****************************************************/
struct clk_node *clk_get_dvfs_info(struct clk *clk)
{
return clk->dvfs_info;
}
int clk_set_rate_locked(struct clk * clk,unsigned long rate)
{
int ret;
//CLOCK_PRINTK_DBG("%s dvfs clk_set_locked\n",clk->name);
LOCK();
ret=clk_set_rate_nolock(clk, rate);;
UNLOCK();
return ret;
}
void clk_register_dvfs(struct clk_node *dvfs_clk, struct clk *clk)
{
clk->dvfs_info = dvfs_clk;
}
/*-------------------------------------------------------------------------
* Optional clock functions defined in include/linux/clk.h
*-------------------------------------------------------------------------*/
#ifdef RK30_CLK_OFFBOARD_TEST
long rk30_clk_round_rate(struct clk *clk, unsigned long rate)
#else
long clk_round_rate(struct clk *clk, unsigned long rate)
#endif
{
long ret = 0;
if (clk == NULL || IS_ERR(clk))
return ret;
LOCK();
ret = clk_round_rate_nolock(clk, rate);
UNLOCK();
return ret;
}
#ifdef RK30_CLK_OFFBOARD_TEST
EXPORT_SYMBOL(rk30_clk_round_rate);
#else
EXPORT_SYMBOL(clk_round_rate);
#endif
#ifdef RK30_CLK_OFFBOARD_TEST
unsigned long rk30_clk_get_rate(struct clk *clk)
#else
unsigned long clk_get_rate(struct clk *clk)
#endif
{
if (clk == NULL || IS_ERR(clk))
return 0;
return clk->rate;
}
#ifdef RK30_CLK_OFFBOARD_TEST
EXPORT_SYMBOL(rk30_clk_get_rate);
#else
EXPORT_SYMBOL(clk_get_rate);
#endif
/* Set the clock rate for a clock source */
#ifdef RK30_CLK_OFFBOARD_TEST
int rk30_clk_set_rate(struct clk *clk, unsigned long rate)
#else
int clk_set_rate(struct clk *clk, unsigned long rate)
#endif
{
int ret = -EINVAL;
if (clk == NULL || IS_ERR(clk)){
return ret;
}
if (rate == clk->rate)
return 0;
if (clk->dvfs_info!=NULL&&is_support_dvfs(clk->dvfs_info))
return dvfs_set_rate(clk, rate);
LOCK();
ret = clk_set_rate_nolock(clk, rate);
UNLOCK();
return ret;
}
#ifdef RK30_CLK_OFFBOARD_TEST
EXPORT_SYMBOL(rk30_clk_set_rate);
#else
EXPORT_SYMBOL(clk_set_rate);
#endif
#ifdef RK30_CLK_OFFBOARD_TEST
int rk30_clk_set_parent(struct clk *clk, struct clk *parent)
#else
int clk_set_parent(struct clk *clk, struct clk *parent)
#endif
{
int ret = -EINVAL;
if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
return ret;
if (clk->set_parent==NULL||clk->parents == NULL)
return ret;
LOCK();
if (clk->usecount == 0)
ret = clk_set_parent_nolock(clk, parent);
else
ret = -EBUSY;
UNLOCK();
return ret;
}
int clk_set_parent_force(struct clk *clk, struct clk *parent)
{
int ret = -EINVAL;
if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
return ret;
if (clk->set_parent==NULL||clk->parents == NULL)
return ret;
LOCK();
ret = clk_set_parent_nolock(clk, parent);
UNLOCK();
return ret;
}
#ifdef RK30_CLK_OFFBOARD_TEST
EXPORT_SYMBOL(rk30_clk_set_parent);
#else
EXPORT_SYMBOL(clk_set_parent);
#endif
#ifdef RK30_CLK_OFFBOARD_TEST
struct clk *rk30_clk_get_parent(struct clk *clk)
#else
struct clk *clk_get_parent(struct clk *clk)
#endif
{
if (clk == NULL || IS_ERR(clk)) {
return ERR_PTR(-EINVAL);
}
return clk->parent;
}
#ifdef RK30_CLK_OFFBOARD_TEST
EXPORT_SYMBOL(rk30_clk_get_parent);
#else
EXPORT_SYMBOL(clk_get_parent);
#endif
#ifdef RK30_CLK_OFFBOARD_TEST
void rk30_clk_disable(struct clk *clk)
#else
void clk_disable(struct clk *clk)
#endif
{
if (clk == NULL || IS_ERR(clk))
return;
LOCK();
clk_disable_nolock(clk);
UNLOCK();
}
#ifdef RK30_CLK_OFFBOARD_TEST
EXPORT_SYMBOL(rk30_clk_disable);
#else
EXPORT_SYMBOL(clk_disable);
#endif
#ifdef RK30_CLK_OFFBOARD_TEST
int rk30_clk_enable(struct clk *clk)
#else
int clk_enable(struct clk *clk)
#endif
{
int ret = 0;
if (clk == NULL || IS_ERR(clk))
return -EINVAL;
LOCK();
ret = clk_enable_nolock(clk);
UNLOCK();
return ret;
}
#ifdef RK30_CLK_OFFBOARD_TEST
EXPORT_SYMBOL(rk30_clk_enable);
#else
EXPORT_SYMBOL(clk_enable);
#endif
/* Clk notifier implementation */
/**
* struct clk_notifier - associate a clk with a notifier
* @clk: struct clk * to associate the notifier with
* @notifier_head: a raw_notifier_head for this clk
* @node: linked list pointers
*
* A list of struct clk_notifier is maintained by the notifier code.
* An entry is created whenever code registers the first notifier on a
* particular @clk. Future notifiers on that @clk are added to the
* @notifier_head.
*/
struct clk_notifier {
struct clk *clk;
struct raw_notifier_head notifier_head;
struct list_head node;
};
static LIST_HEAD(clk_notifier_list);
/**
* _clk_free_notifier_chain - safely remove struct clk_notifier
* @cn: struct clk_notifier *
*
* Removes the struct clk_notifier @cn from the clk_notifier_list and
* frees it.
*/
static void _clk_free_notifier_chain(struct clk_notifier *cn)
{
list_del(&cn->node);
kfree(cn);
}
/**
* clk_notify - call clk notifier chain
* @clk: struct clk * that is changing rate
* @msg: clk notifier type (i.e., CLK_POST_RATE_CHANGE; see mach/clock.h)
* @old_rate: old rate
* @new_rate: new rate
*
* Triggers a notifier call chain on the post-clk-rate-change notifier
* for clock 'clk'. Passes a pointer to the struct clk and the
* previous and current rates to the notifier callback. Intended to be
* called by internal clock code only. No return value.
*/
static void clk_notify(struct clk *clk, unsigned long msg,
unsigned long old_rate, unsigned long new_rate)
{
struct clk_notifier *cn;
struct clk_notifier_data cnd;
cnd.clk = clk;
cnd.old_rate = old_rate;
cnd.new_rate = new_rate;
UNLOCK();
list_for_each_entry(cn, &clk_notifier_list, node) {
if (cn->clk == clk) {
pr_debug("%s msg %lu rate %lu -> %lu\n", clk->name, msg, old_rate, new_rate);
raw_notifier_call_chain(&cn->notifier_head, msg, &cnd);
break;
}
}
LOCK();
}
/**
* clk_notifier_register - add a clock parameter change notifier
* @clk: struct clk * to watch
* @nb: struct notifier_block * with callback info
*
* Request notification for changes to the clock 'clk'. This uses a
* blocking notifier. Callback code must not call into the clock
* framework, as clocks_mutex is held. Pre-notifier callbacks will be
* passed the previous and new rate of the clock.
*
* clk_notifier_register() must be called from process
* context. Returns -EINVAL if called with null arguments, -ENOMEM
* upon allocation failure; otherwise, passes along the return value
* of blocking_notifier_chain_register().
*/
int rk30_clk_notifier_register(struct clk *clk, struct notifier_block *nb)
{
struct clk_notifier *cn = NULL, *cn_new = NULL;
int r;
struct clk *clkp;
if (!clk || IS_ERR(clk) || !nb)
return -EINVAL;
mutex_lock(&clocks_mutex);
list_for_each_entry(cn, &clk_notifier_list, node)
if (cn->clk == clk)
break;
if (cn->clk != clk) {
cn_new = kzalloc(sizeof(struct clk_notifier), GFP_KERNEL);
if (!cn_new) {
r = -ENOMEM;
goto cnr_out;
};
cn_new->clk = clk;
RAW_INIT_NOTIFIER_HEAD(&cn_new->notifier_head);
list_add(&cn_new->node, &clk_notifier_list);
cn = cn_new;
}
r = raw_notifier_chain_register(&cn->notifier_head, nb);
if (!IS_ERR_VALUE(r)) {
clkp = clk;
do {
clkp->notifier_count++;
} while ((clkp = clkp->parent));
} else {
if (cn_new)
_clk_free_notifier_chain(cn);
}
cnr_out:
mutex_unlock(&clocks_mutex);
return r;
}
EXPORT_SYMBOL(rk30_clk_notifier_register);
/**
* clk_notifier_unregister - remove a clock change notifier
* @clk: struct clk *
* @nb: struct notifier_block * with callback info
*
* Request no further notification for changes to clock 'clk'.
* Returns -EINVAL if called with null arguments; otherwise, passes
* along the return value of blocking_notifier_chain_unregister().
*/
int rk30_clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
{
struct clk_notifier *cn = NULL;
struct clk *clkp;
int r = -EINVAL;
if (!clk || IS_ERR(clk) || !nb)
return -EINVAL;
mutex_lock(&clocks_mutex);
list_for_each_entry(cn, &clk_notifier_list, node)
if (cn->clk == clk)
break;
if (cn->clk != clk) {
r = -ENOENT;
goto cnu_out;
};
r = raw_notifier_chain_unregister(&cn->notifier_head, nb);
if (!IS_ERR_VALUE(r)) {
clkp = clk;
do {
clkp->notifier_count--;
} while ((clkp = clkp->parent));
}
/*
* XXX ugh, layering violation. There should be some
* support in the notifier code for this.
*/
if (!cn->notifier_head.head)
_clk_free_notifier_chain(cn);
cnu_out:
mutex_unlock(&clocks_mutex);
return r;
}
EXPORT_SYMBOL(rk30_clk_notifier_unregister);
static struct clk_dump_ops *dump_def_ops;
void clk_register_dump_ops(struct clk_dump_ops *ops)
{
dump_def_ops=ops;
}
#ifdef CONFIG_RK_CLOCK_PROC
static int proc_clk_show(struct seq_file *s, void *v)
{
struct clk* clk;
if(!dump_def_ops)
return 0;
if(dump_def_ops->dump_clk)
{
mutex_lock(&clocks_mutex);
list_for_each_entry(clk, &clocks, node) {
if (!clk->parent)
{
dump_def_ops->dump_clk(s, clk, 0,&clocks);
}
}
mutex_unlock(&clocks_mutex);
}
if(dump_def_ops->dump_regs)
dump_def_ops->dump_regs(s);
return 0;
}
static int proc_clk_open(struct inode *inode, struct file *file)
{
return single_open(file, proc_clk_show, NULL);
}
static const struct file_operations proc_clk_fops = {
.open = proc_clk_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static int __init clk_proc_init(void)
{
proc_create("clocks", 0, NULL, &proc_clk_fops);
return 0;
}
late_initcall(clk_proc_init);
#endif /* CONFIG_RK_CLOCK_PROC */

99
arch/arm/mach-rk2928/clock.h Normal file
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#ifndef __MACH_CLOCK_H__
#define __MACH_CLOCK_H__
#ifndef CONFIG_ARCH_RK2928
#define RK30_CLK_OFFBOARD_TEST
#endif
/* Clock flags */
/* bit 0 is free */
#define RATE_FIXED (1 << 1) /* Fixed clock rate */
#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
#define IS_PD (1 << 2) /* Power Domain */
enum _clk_i2s_rate_support {
i2s_8192khz = 8192000,
i2s_11289_6khz = 11289600,
i2s_12288khz = 12288000,
i2s_22579_2khz = 22579200,
i2s_24576khz = 24576000,//HDMI
i2s_49152khz = 24576000,//HDMI
};
struct _pll_data{
u8 id;
void *table;
};
//struct clk_node;
struct clk {
struct list_head node;
const char *name;
struct clk *parent;
struct list_head children;
struct list_head sibling; /* node for children */
int (*mode)(struct clk *clk, int on);
unsigned long (*recalc)(struct clk *); /* if null, follow parent */
int (*set_rate)(struct clk *, unsigned long);
long (*round_rate)(struct clk *, unsigned long);
struct clk* (*get_parent)(struct clk *); /* get clk's parent from the hardware. default is clksel_get_parent if parents present */
int (*set_parent)(struct clk *, struct clk *); /* default is clksel_set_parent if parents present */
unsigned long rate;
u32 flags;
s16 usecount;
u16 notifier_count;
u8 gate_idx;
struct _pll_data *pll;
u32 clksel_con;
u32 div_mask;
u32 div_shift;
u32 div_max;
u32 src_mask;
u32 src_shift;
struct clk **parents;
u8 parents_num;
struct clk_node *dvfs_info;
};
int __init clk_disable_unused(void);
void clk_recalculate_root_clocks_nolock(void);
void clk_recalculate_root_clocks(void);
int clk_register(struct clk *clk);
void clk_register_default_ops_clk(struct clk *clk);
int clk_enable_nolock(struct clk *clk);
void clk_disable_nolock(struct clk *clk);
long clk_round_rate_nolock(struct clk *clk, unsigned long rate);
int clk_set_rate_nolock(struct clk *clk, unsigned long rate);
int clk_set_parent_nolock(struct clk *clk, struct clk *parent);
int clk_set_rate_locked(struct clk * clk,unsigned long rate);
void clk_register_dvfs(struct clk_node *dvfs_clk, struct clk *clk);
struct clk_node *clk_get_dvfs_info(struct clk *clk);
int is_suport_round_rate(struct clk *clk);
#ifdef RK30_CLK_OFFBOARD_TEST
#include <linux/device.h>
struct clk *rk30_clk_get(struct device *dev, const char *con_id);
#endif
#ifdef CONFIG_PROC_FS
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
struct clk_dump_ops {
void (*dump_clk)(struct seq_file *s, struct clk *clk, int deep,const struct list_head *root_clocks);
void (*dump_regs)(struct seq_file *s);
};
void clk_register_dump_ops(struct clk_dump_ops *ops);
#else
static void clk_register_dump_ops(struct clk_dump_ops *ops){
}
#endif
#endif

2619
arch/arm/mach-rk2928/clock_data.c Normal file
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148
arch/arm/mach-rk2928/common.c Normal file
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#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/pgtable-hwdef.h>
#include <asm/hardware/gic.h>
#include <asm/mach/arch.h>
#include <asm/hardware/cache-l2x0.h>
#include <plat/sram.h>
#include <mach/board.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/fiq.h>
#include <mach/loader.h>
//#include <mach/ddr.h>
static void __init rk2928_cpu_axi_init(void)
{
writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x0088); // cpu0
writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x0188); // cpu1r
writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x0388); // cpu1w
writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x4008); // peri
writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x5008); // gpu
writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x6008); // vpu
writel_relaxed(0xa, RK2928_CPU_AXI_BUS_BASE + 0x7188); // lcdc
writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x7208); // cif
writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x7288); // rga
writel_relaxed(0x3f, RK2928_CPU_AXI_BUS_BASE + 0x0014); // memory scheduler read latency
dsb();
}
#define L2_LY_SP_OFF (0)
#define L2_LY_SP_MSK (0x7)
#define L2_LY_RD_OFF (4)
#define L2_LY_RD_MSK (0x7)
#define L2_LY_WR_OFF (8)
#define L2_LY_WR_MSK (0x7)
#define L2_LY_SET(ly,off) (((ly)-1)<<(off))
static void __init rk2928_l2_cache_init(void)
{
#ifdef CONFIG_CACHE_L2X0
u32 aux_ctrl, aux_ctrl_mask;
writel_relaxed(L2_LY_SET(1,L2_LY_SP_OFF)
|L2_LY_SET(1,L2_LY_RD_OFF)
|L2_LY_SET(1,L2_LY_WR_OFF), RK2928_L2C_BASE + L2X0_TAG_LATENCY_CTRL);
writel_relaxed(L2_LY_SET(2,L2_LY_SP_OFF)
|L2_LY_SET(3,L2_LY_RD_OFF)
|L2_LY_SET(1,L2_LY_WR_OFF), RK2928_L2C_BASE + L2X0_DATA_LATENCY_CTRL);
/* L2X0 Prefetch Control */
writel_relaxed(0x70000003, RK2928_L2C_BASE + L2X0_PREFETCH_CTRL);
/* L2X0 Power Control */
writel_relaxed(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, RK2928_L2C_BASE + L2X0_POWER_CTRL);
aux_ctrl = (
// (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | // 16-way
(0x1 << 25) | // Round-robin cache replacement policy
(0x1 << 0) | // Full Line of Zero Enable
(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
// (0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | // 32KB way-size
(0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
(0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
(0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT) );
aux_ctrl_mask = ~(
// (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | // 16-way
(0x1 << 25) | // Cache replacement policy
(0x1 << 0) | // Full Line of Zero Enable
(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
// (0x7 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | // 32KB way-size
(0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
(0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
(0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT) );
l2x0_init(RK2928_L2C_BASE, aux_ctrl, aux_ctrl_mask);
#endif
}
static int boot_mode;
static void __init rk2928_boot_mode_init(void)
{
u32 boot_flag = (readl_relaxed(RK2928_GRF_BASE + GRF_OS_REG4) | (readl_relaxed(RK2928_GRF_BASE + GRF_OS_REG5) << 16)) - SYS_KERNRL_REBOOT_FLAG;
boot_mode = readl_relaxed(RK2928_GRF_BASE + GRF_OS_REG6);
if (boot_flag == BOOT_RECOVER) {
boot_mode = BOOT_MODE_RECOVERY;
}
if (boot_mode || boot_flag)
printk("Boot mode: %d flag: %d\n", boot_mode, boot_flag);
}
int board_boot_mode(void)
{
return boot_mode;
}
EXPORT_SYMBOL(board_boot_mode);
void __init rk2928_init_irq(void)
{
gic_init(0, IRQ_LOCALTIMER, GIC_DIST_BASE, GIC_CPU_BASE);
#ifdef CONFIG_FIQ
rk_fiq_init();
#endif
rk30_gpio_init();
}
extern void __init rk2928_map_common_io(void);
extern int __init clk_disable_unused(void);
void __init rk2928_map_io(void)
{
rk2928_map_common_io();
rk29_setup_early_printk();
rk2928_cpu_axi_init();
rk29_sram_init();
board_clock_init();
rk2928_l2_cache_init();
// ddr_init(DDR_TYPE, DDR_FREQ);
// clk_disable_unused();
rk2928_iomux_init();
rk2928_boot_mode_init();
}
extern u32 ddr_get_cap(void);
static __init u32 rk2928_get_ddr_size(void)
{
#ifdef CONFIG_MACH_RK2928_FPGA
return SZ_64M;
#else
return SZ_512M;
#endif
}
void __init rk2928_fixup(struct machine_desc *desc, struct tag *tags,
char **cmdline, struct meminfo *mi)
{
mi->nr_banks = 1;
mi->bank[0].start = PLAT_PHYS_OFFSET;
mi->bank[0].size = rk2928_get_ddr_size();
}

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arch/arm/mach-rk2928/cpufreq.c Normal file
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/*
* Copyright (C) 2012 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
//#define DEBUG 1
#define pr_fmt(fmt) "cpufreq: " fmt
#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/reboot.h>
#include <linux/suspend.h>
#include <linux/tick.h>
#include <linux/workqueue.h>
#include <asm/smp_plat.h>
#include <asm/cpu.h>
#include <mach/dvfs.h>
#include <linux/delay.h>
#include <linux/regulator/consumer.h>
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/earlysuspend.h>
#include <asm/unistd.h>
#include <asm/uaccess.h>
#ifdef DEBUG
#define FREQ_PRINTK_DBG(fmt, args...) pr_debug(fmt, ## args)
#define FREQ_PRINTK_LOG(fmt, args...) pr_debug(fmt, ## args)
#else
#define FREQ_PRINTK_DBG(fmt, args...) do {} while(0)
#define FREQ_PRINTK_LOG(fmt, args...) do {} while(0)
#endif
#define FREQ_PRINTK_ERR(fmt, args...) pr_err(fmt, ## args)
/* Frequency table index must be sequential starting at 0 */
static struct cpufreq_frequency_table default_freq_table[] = {
{.frequency = 816 * 1000, .index = 1100 * 1000},
{.frequency = CPUFREQ_TABLE_END},
};
static struct cpufreq_frequency_table *freq_table = default_freq_table;
static unsigned int max_freq = -1;
/*********************************************************/
/* additional symantics for "relation" in cpufreq with pm */
#define DISABLE_FURTHER_CPUFREQ 0x10
#define ENABLE_FURTHER_CPUFREQ 0x20
#define MASK_FURTHER_CPUFREQ 0x30
/* With 0x00(NOCHANGE), it depends on the previous "further" status */
static int no_cpufreq_access;
static unsigned int suspend_freq = 816 * 1000;
static struct workqueue_struct *freq_wq;
static struct clk *cpu_clk;
static struct clk *cpu_pll;
static struct clk *cpu_gpll;
static DEFINE_MUTEX(cpufreq_mutex);
static struct clk *gpu_clk;
#define GPU_MAX_RATE 350*1000*1000
static int cpufreq_scale_rate_for_dvfs(struct clk *clk, unsigned long rate, dvfs_set_rate_callback set_rate);
/*******************************************************/
static unsigned int rk30_getspeed(unsigned int cpu)
{
unsigned long rate;
if (cpu >= NR_CPUS)
return 0;
rate = clk_get_rate(cpu_clk) / 1000;
return rate;
}
static bool rk30_cpufreq_is_ondemand_policy(struct cpufreq_policy *policy)
{
char c = 0;
if (policy && policy->governor)
c = policy->governor->name[0];
return (c == 'o' || c == 'i' || c == 'c' || c == 'h');
}
/**********************thermal limit**************************/
#define CONFIG_RK30_CPU_FREQ_LIMIT_BY_TEMP
#ifdef CONFIG_RK30_CPU_FREQ_LIMIT_BY_TEMP
static void rk30_cpufreq_temp_limit_work_func(struct work_struct *work);
static DECLARE_DELAYED_WORK(rk30_cpufreq_temp_limit_work, rk30_cpufreq_temp_limit_work_func);
static unsigned int temp_limt_freq = -1;
module_param(temp_limt_freq, uint, 0444);
#define TEMP_LIMIT_FREQ 816000
static const struct cpufreq_frequency_table temp_limits[] = {
{.frequency = 1416 * 1000, .index = 50},
{.frequency = 1200 * 1000, .index = 55},
{.frequency = 1008 * 1000, .index = 60},
{.frequency = 816 * 1000, .index = 75},
};
//extern int rk30_tsadc_get_temp(unsigned int chn);
//#define get_cpu_thermal() rk30_tsadc_get_temp(0)
static void rk30_cpufreq_temp_limit_work_func(struct work_struct *work)
{
struct cpufreq_policy *policy;
int temp = 25, i;
unsigned int new = -1;
if (clk_get_rate(gpu_clk) > GPU_MAX_RATE)
goto out;
//temp = max(rk30_tsadc_get_temp(0), rk30_tsadc_get_temp(1));
FREQ_PRINTK_LOG("cpu_thermal(%d)\n", temp);
for (i = 0; i < ARRAY_SIZE(temp_limits); i++) {
if (temp > temp_limits[i].index) {
new = temp_limits[i].frequency;
}
}
if (temp_limt_freq != new) {
temp_limt_freq = new;
if (new != -1) {
FREQ_PRINTK_DBG("temp_limit set rate %d kHz\n", temp_limt_freq);
policy = cpufreq_cpu_get(0);
cpufreq_driver_target(policy, policy->cur, CPUFREQ_RELATION_L);
cpufreq_cpu_put(policy);
}
}
out:
queue_delayed_work(freq_wq, &rk30_cpufreq_temp_limit_work, HZ);
}
static int rk30_cpufreq_notifier_policy(struct notifier_block *nb,
unsigned long val, void *data)
{
struct cpufreq_policy *policy = data;
if (val != CPUFREQ_NOTIFY)
return 0;
if (rk30_cpufreq_is_ondemand_policy(policy)) {
FREQ_PRINTK_DBG("queue work\n");
queue_delayed_work(freq_wq, &rk30_cpufreq_temp_limit_work, 0);
} else {
FREQ_PRINTK_DBG("cancel work\n");
cancel_delayed_work_sync(&rk30_cpufreq_temp_limit_work);
}
return 0;
}
static struct notifier_block notifier_policy_block = {
.notifier_call = rk30_cpufreq_notifier_policy
};
#endif
/************************************dvfs tst************************************/
//#define CPU_FREQ_DVFS_TST
#ifdef CPU_FREQ_DVFS_TST
static unsigned int freq_dvfs_tst_rate;
static void rk30_cpufreq_dvsf_tst_work_func(struct work_struct *work);
static DECLARE_DELAYED_WORK(rk30_cpufreq_dvsf_tst_work, rk30_cpufreq_dvsf_tst_work_func);
static int test_count;
#define TEST_FRE_NUM 11
static int test_tlb_rate[TEST_FRE_NUM] = { 504, 1008, 504, 1200, 252, 816, 1416, 252, 1512, 252, 816 };
//static int test_tlb_rate[TEST_FRE_NUM]={504,1008,504,1200,252,816,1416,126,1512,126,816};
#define TEST_GPU_NUM 3
static int test_tlb_gpu[TEST_GPU_NUM] = { 360, 400, 180 };
static int test_tlb_ddr[TEST_GPU_NUM] = { 401, 200, 500 };
static int gpu_ddr = 0;
static void rk30_cpufreq_dvsf_tst_work_func(struct work_struct *work)
{
struct cpufreq_policy *policy = cpufreq_cpu_get(0);
gpu_ddr++;
#if 0
FREQ_PRINTK_LOG("cpufreq_dvsf_tst,ddr%u,gpu%u\n",
test_tlb_ddr[gpu_ddr % TEST_GPU_NUM],
test_tlb_gpu[gpu_ddr % TEST_GPU_NUM]);
clk_set_rate(ddr_clk, test_tlb_ddr[gpu_ddr % TEST_GPU_NUM] * 1000 * 1000);
clk_set_rate(gpu_clk, test_tlb_gpu[gpu_ddr % TEST_GPU_NUM] * 1000 * 1000);
#endif
test_count++;
freq_dvfs_tst_rate = test_tlb_rate[test_count % TEST_FRE_NUM] * 1000;
FREQ_PRINTK_LOG("cpufreq_dvsf_tst,cpu set rate %d\n", freq_dvfs_tst_rate);
cpufreq_driver_target(policy, policy->cur, CPUFREQ_RELATION_L);
cpufreq_cpu_put(policy);
queue_delayed_work(freq_wq, &rk30_cpufreq_dvsf_tst_work, msecs_to_jiffies(1000));
}
#endif /* CPU_FREQ_DVFS_TST */
/***********************************************************************/
static int rk30_verify_speed(struct cpufreq_policy *policy)
{
if (!freq_table)
return -EINVAL;
return cpufreq_frequency_table_verify(policy, freq_table);
}
static int rk30_cpu_init(struct cpufreq_policy *policy)
{
if (policy->cpu == 0) {
int i;
struct clk *ddr_clk;
gpu_clk = clk_get(NULL, "gpu");
if (!IS_ERR(gpu_clk))
clk_enable_dvfs(gpu_clk);
#if 0
ddr_clk = clk_get(NULL, "ddr");
if (!IS_ERR(ddr_clk))
{
clk_enable_dvfs(ddr_clk);
clk_set_rate(ddr_clk,clk_get_rate(ddr_clk)-1);
}
#endif
cpu_clk = clk_get(NULL, "cpu");
cpu_pll = clk_get(NULL, "arm_pll");
cpu_gpll = clk_get(NULL, "arm_gpll");
if (IS_ERR(cpu_clk))
return PTR_ERR(cpu_clk);
dvfs_clk_register_set_rate_callback(cpu_clk, cpufreq_scale_rate_for_dvfs);
freq_table = dvfs_get_freq_volt_table(cpu_clk);
if (freq_table == NULL) {
freq_table = default_freq_table;
}
max_freq = freq_table[0].frequency;
for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
max_freq = max(max_freq, freq_table[i].frequency);
}
clk_enable_dvfs(cpu_clk);
/* Limit gpu frequency between 133M to 400M */
#if 0
dvfs_clk_enable_limit(gpu_clk, 133000000, 400000000);
#endif
freq_wq = create_singlethread_workqueue("rk30_cpufreqd");
#ifdef CONFIG_RK30_CPU_FREQ_LIMIT_BY_TEMP
if (rk30_cpufreq_is_ondemand_policy(policy)) {
queue_delayed_work(freq_wq, &rk30_cpufreq_temp_limit_work, 0*HZ);
}
cpufreq_register_notifier(&notifier_policy_block, CPUFREQ_POLICY_NOTIFIER);
#endif
#ifdef CPU_FREQ_DVFS_TST
queue_delayed_work(freq_wq, &rk30_cpufreq_dvsf_tst_work, msecs_to_jiffies(20 * 1000));
#endif
}
//set freq min max
cpufreq_frequency_table_cpuinfo(policy, freq_table);
//sys nod
cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
policy->cur = rk30_getspeed(0);
policy->cpuinfo.transition_latency = 40 * NSEC_PER_USEC; // make ondemand default sampling_rate to 40000
/*
* On rk30 SMP configuartion, both processors share the voltage
* and clock. So both CPUs needs to be scaled together and hence
* needs software co-ordination. Use cpufreq affected_cpus
* interface to handle this scenario. Additional is_smp() check
* is to keep SMP_ON_UP build working.
*/
if (is_smp())
cpumask_setall(policy->cpus);
return 0;
}
static int rk30_cpu_exit(struct cpufreq_policy *policy)
{
if (policy->cpu != 0)
return 0;
cpufreq_frequency_table_cpuinfo(policy, freq_table);
clk_put(cpu_clk);
#ifdef CONFIG_RK30_CPU_FREQ_LIMIT_BY_TEMP
cpufreq_unregister_notifier(&notifier_policy_block, CPUFREQ_POLICY_NOTIFIER);
if (freq_wq)
cancel_delayed_work(&rk30_cpufreq_temp_limit_work);
#endif
if (freq_wq) {
flush_workqueue(freq_wq);
destroy_workqueue(freq_wq);
freq_wq = NULL;
}
return 0;
}
static struct freq_attr *rk30_cpufreq_attr[] = {
&cpufreq_freq_attr_scaling_available_freqs,
NULL,
};
/**************************earlysuspend freeze cpu frequency******************************/
static struct early_suspend ff_early_suspend;
#define FILE_GOV_MODE "/sys/devices/system/cpu/cpu0/cpufreq/scaling_governor"
#define FILE_SETSPEED "/sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed"
#define FILE_CUR_FREQ "/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq"
#define FF_DEBUG(fmt, args...) printk(KERN_DEBUG "FREEZE FREQ DEBUG:\t"fmt, ##args)
#define FF_ERROR(fmt, args...) printk(KERN_ERR "FREEZE FREQ ERROR:\t"fmt, ##args)
static int ff_read(char *file_path, char *buf)
{
struct file *file = NULL;
mm_segment_t old_fs;
loff_t offset = 0;
FF_DEBUG("read %s\n", file_path);
file = filp_open(file_path, O_RDONLY, 0);
if (IS_ERR(file)) {
FF_ERROR("%s error open file %s\n", __func__, file_path);
return -1;
}
old_fs = get_fs();
set_fs(KERNEL_DS);
file->f_op->read(file, (char *)buf, 32, &offset);
sscanf(buf, "%s", buf);
set_fs(old_fs);
filp_close(file, NULL);
file = NULL;
return 0;
}
static int ff_write(char *file_path, char *buf)
{
struct file *file = NULL;
mm_segment_t old_fs;
loff_t offset = 0;
FF_DEBUG("write %s %s size = %d\n", file_path, buf, strlen(buf));
file = filp_open(file_path, O_RDWR, 0);
if (IS_ERR(file)) {
FF_ERROR("%s error open file %s\n", __func__, file_path);
return -1;
}
old_fs = get_fs();
set_fs(KERNEL_DS);
file->f_op->write(file, (char *)buf, strlen(buf), &offset);
set_fs(old_fs);
filp_close(file, NULL);
file = NULL;
return 0;
}
static void ff_scale_votlage(char *name, int volt)
{
struct regulator* regulator;
int ret = 0;
FF_DEBUG("enter %s\n", __func__);
regulator = dvfs_get_regulator(name);
if (!regulator) {
FF_ERROR("get regulator %s ERROR\n", name);
return ;
}
ret = regulator_set_voltage(regulator, volt, volt);
if (ret != 0) {
FF_ERROR("set voltage error %s %d, ret = %d\n", name, volt, ret);
}
}
int clk_set_parent_force(struct clk *clk, struct clk *parent);
static void ff_early_suspend_func(struct early_suspend *h)
{
char buf[32];
FF_DEBUG("enter %s\n", __func__);
if (ff_read(FILE_GOV_MODE, buf) != 0) {
FF_ERROR("read current governor error\n");
return ;
} else {
FF_DEBUG("current governor = %s\n", buf);
}
strcpy(buf, "userspace");
if (ff_write(FILE_GOV_MODE, buf) != 0) {
FF_ERROR("set current governor error\n");
return ;
}
strcpy(buf, "252000");
if (ff_write(FILE_SETSPEED, buf) != 0) {
FF_ERROR("set speed to 252MHz error\n");
return ;
}
if (!IS_ERR(cpu_pll)&&!IS_ERR(cpu_gpll)&&!IS_ERR(cpu_clk))
{
clk_set_parent_force(cpu_clk,cpu_gpll);
clk_set_rate(cpu_clk,300*1000*1000);
clk_disable_dvfs(cpu_clk);
}
if (!IS_ERR(gpu_clk))
dvfs_clk_enable_limit(gpu_clk,75*1000*1000,133*1000*1000);
//ff_scale_votlage("vdd_cpu", 1000000);
//ff_scale_votlage("vdd_core", 1000000);
#ifdef CONFIG_HOTPLUG_CPU
cpu_down(1);
#endif
}
static void ff_early_resume_func(struct early_suspend *h)
{
char buf[32];
FF_DEBUG("enter %s\n", __func__);
if (!IS_ERR(cpu_pll)&&!IS_ERR(cpu_gpll)&&!IS_ERR(cpu_clk))
{
clk_set_parent_force(cpu_clk,cpu_pll);
clk_set_rate(cpu_clk,300*1000*1000);
clk_enable_dvfs(cpu_clk);
}
if (!IS_ERR(gpu_clk))
dvfs_clk_disable_limit(gpu_clk);
#ifdef CONFIG_HOTPLUG_CPU
cpu_up(1);
#endif
if (ff_read(FILE_GOV_MODE, buf) != 0) {
FF_ERROR("read current governor error\n");
return ;
} else {
FF_DEBUG("current governor = %s\n", buf);
}
if (ff_read(FILE_CUR_FREQ, buf) != 0) {
FF_ERROR("read current frequency error\n");
return ;
} else {
FF_DEBUG("current frequency = %s\n", buf);
}
strcpy(buf, "interactive");
if (ff_write(FILE_GOV_MODE, buf) != 0) {
FF_ERROR("set current governor error\n");
return ;
}
strcpy(buf, "interactive");
if (ff_write(FILE_GOV_MODE, buf) != 0) {
FF_ERROR("set current governor error\n");
return ;
}
}
static int __init ff_init(void)
{
FF_DEBUG("enter %s\n", __func__);
ff_early_suspend.suspend = ff_early_suspend_func;
ff_early_suspend.resume = ff_early_resume_func;
ff_early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB + 100;
register_early_suspend(&ff_early_suspend);
return 0;
}
static void __exit ff_exit(void)
{
FF_DEBUG("enter %s\n", __func__);
unregister_early_suspend(&ff_early_suspend);
}
/**************************target freq******************************/
static unsigned int cpufreq_scale_limt(unsigned int target_freq, struct cpufreq_policy *policy)
{
bool is_ondemand = rk30_cpufreq_is_ondemand_policy(policy);
static bool is_booting = true;
if (is_ondemand && clk_get_rate(gpu_clk) > GPU_MAX_RATE) // high performance?
return max_freq;
if (is_ondemand && is_booting && target_freq >= 1600 * 1000) {
s64 boottime_ms = ktime_to_ms(ktime_get_boottime());
if (boottime_ms > 30 * MSEC_PER_SEC) {
is_booting = false;
} else {
target_freq = 1416 * 1000;
}
}
#ifdef CONFIG_RK30_CPU_FREQ_LIMIT_BY_TEMP
if (is_ondemand && target_freq > policy->cur && policy->cur >= TEMP_LIMIT_FREQ) {
unsigned int i;
if (cpufreq_frequency_table_target(policy, freq_table, policy->cur + 1, CPUFREQ_RELATION_L, &i) == 0) {
unsigned int f = freq_table[i].frequency;
if (f < target_freq) {
target_freq = f;
}
}
}
/*
* If the new frequency is more than the thermal max allowed
* frequency, go ahead and scale the mpu device to proper frequency.
*/
if (is_ondemand) {
target_freq = min(target_freq, temp_limt_freq);
}
#endif
#ifdef CPU_FREQ_DVFS_TST
if (freq_dvfs_tst_rate) {
target_freq = freq_dvfs_tst_rate;
freq_dvfs_tst_rate = 0;
}
#endif
return target_freq;
}
int cpufreq_scale_rate_for_dvfs(struct clk *clk, unsigned long rate, dvfs_set_rate_callback set_rate)
{
unsigned int i;
int ret = -EINVAL;
struct cpufreq_freqs freqs;
freqs.new = rate / 1000;
freqs.old = rk30_getspeed(0);
for_each_online_cpu(freqs.cpu) {
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
}
FREQ_PRINTK_DBG("cpufreq_scale_rate_for_dvfs(%lu)\n", rate);
ret = set_rate(clk, rate);
#ifdef CONFIG_SMP
/*
* Note that loops_per_jiffy is not updated on SMP systems in
* cpufreq driver. So, update the per-CPU loops_per_jiffy value
* on frequency transition. We need to update all dependent CPUs.
*/
for_each_possible_cpu(i) {
per_cpu(cpu_data, i).loops_per_jiffy = loops_per_jiffy;
}
#endif
freqs.new = rk30_getspeed(0);
/* notifiers */
for_each_online_cpu(freqs.cpu) {
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
}
return ret;
}
static int rk30_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation)
{
unsigned int i, new_rate = 0;
int ret = 0;
if (!freq_table) {
FREQ_PRINTK_ERR("no freq table!\n");
return -EINVAL;
}
mutex_lock(&cpufreq_mutex);
if (relation & ENABLE_FURTHER_CPUFREQ)
no_cpufreq_access--;
if (no_cpufreq_access) {
#ifdef CONFIG_PM_VERBOSE
pr_err("denied access to %s as it is disabled temporarily\n", __func__);
#endif
ret = -EINVAL;
goto out;
}
if (relation & DISABLE_FURTHER_CPUFREQ)
no_cpufreq_access++;
relation &= ~MASK_FURTHER_CPUFREQ;
ret = cpufreq_frequency_table_target(policy, freq_table, target_freq, relation, &i);
if (ret) {
FREQ_PRINTK_ERR("no freq match for %d(ret=%d)\n", target_freq, ret);
goto out;
}
new_rate = freq_table[i].frequency;
if (!no_cpufreq_access)
new_rate = cpufreq_scale_limt(new_rate, policy);
FREQ_PRINTK_LOG("cpufreq req=%u,new=%u(was=%u)\n", target_freq, new_rate, rk30_getspeed(0));
if (new_rate == rk30_getspeed(0))
goto out;
ret = clk_set_rate(cpu_clk, new_rate * 1000);
out:
mutex_unlock(&cpufreq_mutex);
FREQ_PRINTK_DBG("cpureq set rate (%u) end\n", new_rate);
return ret;
}
static int rk30_cpufreq_pm_notifier_event(struct notifier_block *this,
unsigned long event, void *ptr)
{
int ret = NOTIFY_DONE;
struct cpufreq_policy *policy = cpufreq_cpu_get(0);
if (!policy)
return ret;
if (!rk30_cpufreq_is_ondemand_policy(policy))
goto out;
switch (event) {
case PM_SUSPEND_PREPARE:
ret = cpufreq_driver_target(policy, suspend_freq, DISABLE_FURTHER_CPUFREQ | CPUFREQ_RELATION_H);
if (ret < 0) {
ret = NOTIFY_BAD;
goto out;
}
ret = NOTIFY_OK;
break;
case PM_POST_RESTORE:
case PM_POST_SUSPEND:
cpufreq_driver_target(policy, suspend_freq, ENABLE_FURTHER_CPUFREQ | CPUFREQ_RELATION_H);
ret = NOTIFY_OK;
break;
}
out:
cpufreq_cpu_put(policy);
return ret;
}
static struct notifier_block rk30_cpufreq_pm_notifier = {
.notifier_call = rk30_cpufreq_pm_notifier_event,
};
static int rk30_cpufreq_reboot_notifier_event(struct notifier_block *this,
unsigned long event, void *ptr)
{
struct cpufreq_policy *policy = cpufreq_cpu_get(0);
if (policy) {
cpufreq_driver_target(policy, suspend_freq, DISABLE_FURTHER_CPUFREQ | CPUFREQ_RELATION_H);
cpufreq_cpu_put(policy);
}
return NOTIFY_OK;
}
static struct notifier_block rk30_cpufreq_reboot_notifier = {
.notifier_call = rk30_cpufreq_reboot_notifier_event,
};
static struct cpufreq_driver rk30_cpufreq_driver = {
.flags = CPUFREQ_CONST_LOOPS,
.verify = rk30_verify_speed,
.target = rk30_target,
.get = rk30_getspeed,
.init = rk30_cpu_init,
.exit = rk30_cpu_exit,
.name = "rk30",
.attr = rk30_cpufreq_attr,
};
static int __init rk30_cpufreq_init(void)
{
register_pm_notifier(&rk30_cpufreq_pm_notifier);
register_reboot_notifier(&rk30_cpufreq_reboot_notifier);
return cpufreq_register_driver(&rk30_cpufreq_driver);
}
static void __exit rk30_cpufreq_exit(void)
{
cpufreq_unregister_driver(&rk30_cpufreq_driver);
}
MODULE_DESCRIPTION("cpufreq driver for rock chip rk30");
MODULE_LICENSE("GPL");
device_initcall(rk30_cpufreq_init);
module_exit(rk30_cpufreq_exit);

840
arch/arm/mach-rk2928/devices.c Executable file
View File

@ -0,0 +1,840 @@
/* arch/arm/mach-rk2928/devices.c
*
* Copyright (C) 2012 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/fs.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#ifdef CONFIG_USB_ANDROID
#include <linux/usb/android_composite.h>
#endif
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <asm/pmu.h>
#include <mach/irqs.h>
#include <mach/board.h>
#include <mach/dma-pl330.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <plat/rk_fiq_debugger.h>
#ifdef CONFIG_ADC_RK30
static struct resource rk30_adc_resource[] = {
{
.start = IRQ_SARADC,
.end = IRQ_SARADC,
.flags = IORESOURCE_IRQ,
},
{
.start = RK2928_SARADC_PHYS,
.end = RK2928_SARADC_PHYS + RK2928_SARADC_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device device_adc = {
.name = "rk30-adc",
.id = -1,
.num_resources = ARRAY_SIZE(rk30_adc_resource),
.resource = rk30_adc_resource,
};
#endif
static u64 dma_dmamask = DMA_BIT_MASK(32);
static struct resource resource_dmac[] = {
[0] = {
.start = RK2928_DMAC_PHYS,
.end = RK2928_DMAC_PHYS + RK2928_DMAC_SIZE -1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_DMAC_0,
.end = IRQ_DMAC_1,
.flags = IORESOURCE_IRQ,
},
};
static struct rk29_pl330_platdata dmac_pdata = {
.peri = {
[0] = DMACH_I2S0_8CH_TX,
[1] = DMACH_I2S0_8CH_RX,
[2] = DMACH_UART0_TX,
[3] = DMACH_UART0_RX,
[4] = DMACH_UART1_TX,
[5] = DMACH_UART1_RX,
[6] = DMACH_UART2_TX,
[7] = DMACH_UART2_RX,
[8] = DMACH_SPI0_TX,
[9] = DMACH_SPI0_RX,
[10] = DMACH_SDMMC,
[11] = DMACH_SDIO,
[12] = DMACH_EMMC,
[13] = DMACH_DMAC1_MEMTOMEM,
[14] = DMACH_MAX,
[15] = DMACH_MAX,
[16] = DMACH_MAX,
[17] = DMACH_MAX,
[18] = DMACH_MAX,
[19] = DMACH_MAX,
[20] = DMACH_MAX,
[21] = DMACH_MAX,
[22] = DMACH_MAX,
[23] = DMACH_MAX,
[24] = DMACH_MAX,
[25] = DMACH_MAX,
[26] = DMACH_MAX,
[27] = DMACH_MAX,
[28] = DMACH_MAX,
[29] = DMACH_MAX,
[30] = DMACH_MAX,
[31] = DMACH_MAX,
},
};
static struct platform_device device_dmac = {
.name = "rk29-pl330",
.id = -1,
.num_resources = ARRAY_SIZE(resource_dmac),
.resource = resource_dmac,
.dev = {
.dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &dmac_pdata,
},
};
static struct platform_device *rk2928_dmacs[] __initdata = {
&device_dmac,
};
static void __init rk2928_init_dma(void)
{
platform_add_devices(rk2928_dmacs, ARRAY_SIZE(rk2928_dmacs));
}
#ifdef CONFIG_UART0_RK29
static struct resource resources_uart0[] = {
{
.start = IRQ_UART0,
.end = IRQ_UART0,
.flags = IORESOURCE_IRQ,
},
{
.start = RK2928_UART0_PHYS,
.end = RK2928_UART0_PHYS + RK2928_UART0_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device device_uart0 = {
.name = "rk_serial",
.id = 0,
.num_resources = ARRAY_SIZE(resources_uart0),
.resource = resources_uart0,
};
#endif
#ifdef CONFIG_UART1_RK29
static struct resource resources_uart1[] = {
{
.start = IRQ_UART1,
.end = IRQ_UART1,
.flags = IORESOURCE_IRQ,
},
{
.start = RK2928_UART1_PHYS,
.end = RK2928_UART1_PHYS + RK2928_UART1_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device device_uart1 = {
.name = "rk_serial",
.id = 1,
.num_resources = ARRAY_SIZE(resources_uart1),
.resource = resources_uart1,
};
#endif
#ifdef CONFIG_UART2_RK29
static struct resource resources_uart2[] = {
{
.start = IRQ_UART2,
.end = IRQ_UART2,
.flags = IORESOURCE_IRQ,
},
{
.start = RK2928_UART2_PHYS,
.end = RK2928_UART2_PHYS + RK2928_UART2_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device device_uart2 = {
.name = "rk_serial",
.id = 2,
.num_resources = ARRAY_SIZE(resources_uart2),
.resource = resources_uart2,
};
#endif
static void __init rk2928_init_uart(void)
{
#ifdef CONFIG_UART0_RK29
platform_device_register(&device_uart0);
#endif
#ifdef CONFIG_UART1_RK29
platform_device_register(&device_uart1);
#endif
#ifdef CONFIG_UART2_RK29
platform_device_register(&device_uart2);
#endif
}
//LCDC
#ifdef CONFIG_LCDC_RK2928
extern struct rk29fb_info lcdc_screen_info;
static struct resource resource_lcdc[] = {
[0] = {
.name = "lcdc reg",
.start = RK2928_LCDC_PHYS,
.end = RK2928_LCDC_PHYS + RK2928_LCDC_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = "lcdc irq",
.start = IRQ_LCDC,
.end = IRQ_LCDC,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device device_lcdc = {
.name = "rk2928-lcdc",
.id = 0,
.num_resources = ARRAY_SIZE(resource_lcdc),
.resource = resource_lcdc,
.dev = {
.platform_data = &lcdc_screen_info,
},
};
#endif
// i2c
#ifdef CONFIG_I2C0_CONTROLLER_RK29
#define I2C0_ADAP_TYPE I2C_RK29_ADAP
#define I2C0_START RK2928_I2C0_PHYS
#define I2C0_END RK2928_I2C0_PHYS + RK2928_I2C0_SIZE - 1
#endif
#ifdef CONFIG_I2C0_CONTROLLER_RK30
#define I2C0_ADAP_TYPE I2C_RK30_ADAP
#define I2C0_START RK2928_RKI2C0_PHYS
#define I2C0_END RK2928_RKI2C0_PHYS + RK2928_RKI2C0_SIZE - 1
#endif
#ifdef CONFIG_I2C1_CONTROLLER_RK29
#define I2C1_ADAP_TYPE I2C_RK29_ADAP
#define I2C1_START RK2928_I2C1_PHYS
#define I2C1_END RK2928_I2C1_PHYS + RK2928_I2C1_SIZE - 1
#endif
#ifdef CONFIG_I2C1_CONTROLLER_RK30
#define I2C1_ADAP_TYPE I2C_RK30_ADAP
#define I2C1_START RK2928_RKI2C1_PHYS
#define I2C1_END RK2928_RKI2C1_PHYS + RK2928_RKI2C1_SIZE - 1
#endif
#ifdef CONFIG_I2C2_CONTROLLER_RK29
#define I2C2_ADAP_TYPE I2C_RK29_ADAP
#define I2C2_START RK2928_I2C2_PHYS
#define I2C2_END RK2928_I2C2_PHYS + RK2928_I2C2_SIZE - 1
#endif
#ifdef CONFIG_I2C2_CONTROLLER_RK30
#define I2C2_ADAP_TYPE I2C_RK30_ADAP
#define I2C2_START RK2928_RKI2C2_PHYS
#define I2C2_END RK2928_RKI2C2_PHYS + RK2928_RKI2C2_SIZE - 1
#endif
#ifdef CONFIG_I2C3_CONTROLLER_RK29
#define I2C3_ADAP_TYPE I2C_RK29_ADAP
#define I2C3_START RK2928_I2C3_PHYS
#define I2C3_END RK2928_I2C3_PHYS + RK2928_I2C3_SIZE - 1
#endif
#ifdef CONFIG_I2C3_CONTROLLER_RK30
#define I2C3_ADAP_TYPE I2C_RK30_ADAP
#define I2C3_START RK2928_RKI2C3_PHYS
#define I2C3_END RK2928_RKI2C3_PHYS + RK2928_RKI2C3_SIZE - 1
#endif
#ifdef CONFIG_I2C0_RK30
static int i2c0_check_idle(void)
{
return I2C_IDLE;
}
static struct rk30_i2c_platform_data default_i2c0_data = {
.bus_num = 0,
.is_div_from_arm = 1,
.adap_type = I2C0_ADAP_TYPE,
.check_idle = &i2c0_check_idle,
};
static struct resource resources_i2c0[] = {
{
.start = IRQ_I2C0,
.end = IRQ_I2C0,
.flags = IORESOURCE_IRQ,
},
{
.start = I2C0_START,
.end = I2C0_END,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device device_i2c0 = {
.name = "rk30_i2c",
.id = 0,
.num_resources = ARRAY_SIZE(resources_i2c0),
.resource = resources_i2c0,
.dev = {
.platform_data = &default_i2c0_data,
},
};
#endif
#ifdef CONFIG_I2C1_RK30
static int i2c1_check_idle(void)
{
return I2C_IDLE;
}
static struct rk30_i2c_platform_data default_i2c1_data = {
.bus_num = 1,
.is_div_from_arm = 1,
.adap_type = I2C1_ADAP_TYPE,
.check_idle = &i2c1_check_idle,
};
static struct resource resources_i2c1[] = {
{
.start = IRQ_I2C1,
.end = IRQ_I2C1,
.flags = IORESOURCE_IRQ,
},
{
.start = I2C1_START,
.end = I2C1_END,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device device_i2c1 = {
.name = "rk30_i2c",
.id = 1,
.num_resources = ARRAY_SIZE(resources_i2c1),
.resource = resources_i2c1,
.dev = {
.platform_data = &default_i2c1_data,
},
};
#endif
#ifdef CONFIG_I2C2_RK30
static int i2c2_check_idle(void)
{
return I2C_IDLE;
}
static struct rk30_i2c_platform_data default_i2c2_data = {
.bus_num = 2,
.is_div_from_arm = 0,
.adap_type = I2C2_ADAP_TYPE,
.check_idle = &i2c2_check_idle,
};
static struct resource resources_i2c2[] = {
{
.start = IRQ_I2C2,
.end = IRQ_I2C2,
.flags = IORESOURCE_IRQ,
},
{
.start = I2C2_START,
.end = I2C2_END,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device device_i2c2 = {
.name = "rk30_i2c",
.id = 2,
.num_resources = ARRAY_SIZE(resources_i2c2),
.resource = resources_i2c2,
.dev = {
.platform_data = &default_i2c2_data,
},
};
#endif
#ifdef CONFIG_I2C3_RK30
static int i2c3_check_idle(void)
{
return I2C_IDLE;
}
static struct rk30_i2c_platform_data default_i2c3_data = {
.bus_num = 3,
.is_div_from_arm = 0,
.adap_type = I2C3_ADAP_TYPE,
.check_idle = &i2c3_check_idle,
};
static struct resource resources_i2c3[] = {
{
.start = IRQ_I2C3,
.end = IRQ_I2C3,
.flags = IORESOURCE_IRQ,
},
{
.start = I2C3_START,
.end = I2C3_END,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device device_i2c3 = {
.name = "rk30_i2c",
.id = 3,
.num_resources = ARRAY_SIZE(resources_i2c3),
.resource = resources_i2c3,
.dev = {
.platform_data = &default_i2c3_data,
},
};
#endif
#ifdef CONFIG_I2C_GPIO_RK30
static struct platform_device device_i2c_gpio = {
.name = "i2c-gpio",
.id = 4,
.dev = {
.platform_data = &default_i2c_gpio_data,
},
};
#endif
static void __init rk2928_init_i2c(void)
{
#ifdef CONFIG_I2C0_RK30
platform_device_register(&device_i2c0);
#endif
#ifdef CONFIG_I2C1_RK30
platform_device_register(&device_i2c1);
#endif
#ifdef CONFIG_I2C2_RK30
platform_device_register(&device_i2c2);
#endif
#ifdef CONFIG_I2C3_RK30
platform_device_register(&device_i2c3);
#endif
#ifdef CONFIG_I2C_GPIO_RK30
platform_device_register(&device_i2c_gpio);
#endif
}
//end of i2c
#if defined(CONFIG_SPIM0_RK29) || defined(CONFIG_SPIM1_RK29)
/*****************************************************************************************
* spi devices
* author: cmc@rock-chips.com
*****************************************************************************************/
#define SPI_CHIPSELECT_NUM 2
static int spi_io_init(struct spi_cs_gpio *cs_gpios, int cs_num)
{
int i;
if (cs_gpios) {
for (i = 0; i < cs_num; i++) {
rk30_mux_api_set(cs_gpios[i].cs_iomux_name, cs_gpios[i].cs_iomux_mode);
}
}
return 0;
}
static int spi_io_deinit(struct spi_cs_gpio *cs_gpios, int cs_num)
{
return 0;
}
static int spi_io_fix_leakage_bug(void)
{
#if 0
gpio_direction_output(RK29_PIN2_PC1, GPIO_LOW);
#endif
return 0;
}
static int spi_io_resume_leakage_bug(void)
{
#if 0
gpio_direction_output(RK29_PIN2_PC1, GPIO_HIGH);
#endif
return 0;
}
#endif
/*
* rk29xx spi master device
*/
#ifdef CONFIG_SPIM0_RK29
static struct spi_cs_gpio rk29xx_spi0_cs_gpios[SPI_CHIPSELECT_NUM] = {
{
.name = "spi0 cs0",
.cs_gpio = RK2928_PIN1_PB3,
.cs_iomux_name = GPIO1B3_SPI_CSN0_UART1_RTSN_NAME,
.cs_iomux_mode = GPIO1B_SPI_CSN0,
},
{
.name = "spi0 cs1",
.cs_gpio = RK2928_PIN1_PB4,
.cs_iomux_name = GPIO1B4_SPI_CSN1_UART1_CTSN_NAME,//if no iomux,set it NULL
.cs_iomux_mode = GPIO1B_SPI_CSN1,
},
};
static struct rk29xx_spi_platform_data rk29xx_spi0_platdata = {
.num_chipselect = SPI_CHIPSELECT_NUM,
.chipselect_gpios = rk29xx_spi0_cs_gpios,
.io_init = spi_io_init,
.io_deinit = spi_io_deinit,
.io_fix_leakage_bug = spi_io_fix_leakage_bug,
.io_resume_leakage_bug = spi_io_resume_leakage_bug,
};
static struct resource rk29_spi0_resources[] = {
{
.start = IRQ_SPI,
.end = IRQ_SPI,
.flags = IORESOURCE_IRQ,
},
{
.start = RK2928_SPI_PHYS,
.end = RK2928_SPI_PHYS + RK2928_SPI_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = DMACH_SPI0_TX,
.end = DMACH_SPI0_TX,
.flags = IORESOURCE_DMA,
},
{
.start = DMACH_SPI0_RX,
.end = DMACH_SPI0_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device rk29xx_device_spi0m = {
.name = "rk29xx_spim",
.id = 0,
.num_resources = ARRAY_SIZE(rk29_spi0_resources),
.resource = rk29_spi0_resources,
.dev = {
.dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &rk29xx_spi0_platdata,
},
};
#endif
static void __init rk2928_init_spim(void)
{
#ifdef CONFIG_SPIM0_RK29
platform_device_register(&rk29xx_device_spi0m);
#endif
}
#ifdef CONFIG_MTD_NAND_RK29XX
static struct resource resources_nand[] = {
{
.start = RK2928_NANDC_PHYS,
.end = RK2928_NANDC_PHYS + RK2928_NANDC_SIZE - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device device_nand = {
.name = "rk29xxnand",
.id = -1,
.resource = resources_nand,
.num_resources = ARRAY_SIZE(resources_nand),
};
#endif
#ifdef CONFIG_HDMI_RK2928
static struct resource resource_hdmi[] = {
[0] = {
.start = RK2928_HDMI_PHYS,
.end = RK2928_HDMI_PHYS + RK2928_HDMI_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_HDMI,
.end = IRQ_HDMI,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device device_hdmi = {
.name = "rk2928-hdmi",
.id = -1,
.num_resources = ARRAY_SIZE(resource_hdmi),
.resource = resource_hdmi,
};
#endif
#ifdef CONFIG_RGA_RK30
static struct resource resource_rga[] = {
[0] = {
.start = RK2928_RGA_PHYS,
.end = RK2928_RGA_PHYS + RK2928_RGA_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_RGA,
.end = IRQ_RGA,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device device_rga = {
.name = "rga",
.id = -1,
.num_resources = ARRAY_SIZE(resource_rga),
.resource = resource_rga,
};
#endif
#ifdef CONFIG_SND_RK29_SOC_I2S
#ifdef CONFIG_SND_RK29_SOC_I2S_8CH
static struct resource resource_iis0_8ch[] = {
[0] = {
.start = RK2928_I2S_PHYS,
.end = RK2928_I2S_PHYS + RK2928_I2S_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_I2S0_8CH_TX,
.end = DMACH_I2S0_8CH_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_I2S0_8CH_RX,
.end = DMACH_I2S0_8CH_RX,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = IRQ_I2S,
.end = IRQ_I2S,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device device_iis0_8ch = {
.name = "rk29_i2s",
.id = 0,
.num_resources = ARRAY_SIZE(resource_iis0_8ch),
.resource = resource_iis0_8ch,
};
#endif
#endif
static struct platform_device device_pcm = {
.name = "rockchip-audio",
.id = -1,
};
static void __init rk2928_init_i2s(void)
{
#ifdef CONFIG_SND_RK29_SOC_I2S_8CH
platform_device_register(&device_iis0_8ch);
#endif
platform_device_register(&device_pcm);
}
#ifdef CONFIG_KEYS_RK29
extern struct rk29_keys_platform_data rk29_keys_pdata;
static struct platform_device device_keys = {
.name = "rk29-keypad",
.id = -1,
.dev = {
.platform_data = &rk29_keys_pdata,
},
};
#endif
#ifdef CONFIG_USB20_OTG
/*DWC_OTG*/
static struct resource usb20_otg_resource[] = {
{
.start = IRQ_USB_OTG,
.end = IRQ_USB_OTG,
.flags = IORESOURCE_IRQ,
},
{
.start = RK2928_USBOTG20_PHYS,
.end = RK2928_USBOTG20_PHYS + RK2928_USBOTG20_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device device_usb20_otg = {
.name = "usb20_otg",
.id = -1,
.num_resources = ARRAY_SIZE(usb20_otg_resource),
.resource = usb20_otg_resource,
};
#endif
#ifdef CONFIG_USB20_HOST
static struct resource usb20_host_resource[] = {
{
.start = IRQ_USB_HOST,
.end = IRQ_USB_HOST,
.flags = IORESOURCE_IRQ,
},
{
.start = RK2928_USBHOST20_PHYS,
.end = RK2928_USBHOST20_PHYS + RK2928_USBHOST20_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device device_usb20_host = {
.name = "usb20_host",
.id = -1,
.num_resources = ARRAY_SIZE(usb20_host_resource),
.resource = usb20_host_resource,
};
#endif
#ifdef CONFIG_SDMMC0_RK29
static struct resource resources_sdmmc0[] = {
{
.start = IRQ_SDMMC,
.end = IRQ_SDMMC,
.flags = IORESOURCE_IRQ,
},
{
.start = RK2928_SDMMC_PHYS,
.end = RK2928_SDMMC_PHYS + RK2928_SDMMC_SIZE -1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device device_sdmmc0 = {
.name = "rk29_sdmmc",
.id = 0,
.num_resources = ARRAY_SIZE(resources_sdmmc0),
.resource = resources_sdmmc0,
.dev = {
.platform_data = &default_sdmmc0_data,
},
};
#endif
#ifdef CONFIG_SDMMC1_RK29
static struct resource resources_sdmmc1[] = {
{
.start = IRQ_SDIO,
.end = IRQ_SDIO,
.flags = IORESOURCE_IRQ,
},
{
.start = RK2928_SDIO_PHYS,
.end = RK2928_SDIO_PHYS + RK2928_SDIO_SIZE - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device device_sdmmc1 = {
.name = "rk29_sdmmc",
.id = 1,
.num_resources = ARRAY_SIZE(resources_sdmmc1),
.resource = resources_sdmmc1,
.dev = {
.platform_data = &default_sdmmc1_data,
},
};
#endif
static void __init rk2928_init_sdmmc(void)
{
#ifdef CONFIG_SDMMC0_RK29
platform_device_register(&device_sdmmc0);
#endif
#ifdef CONFIG_SDMMC1_RK29
platform_device_register(&device_sdmmc1);
#endif
}
static struct resource resource_arm_pmu = {
.start = IRQ_ARM_PMU,
.end = IRQ_ARM_PMU,
.flags = IORESOURCE_IRQ,
};
struct platform_device device_arm_pmu = {
.name = "arm-pmu",
.id = ARM_PMU_DEVICE_CPU,
.num_resources = 1,
.resource = &resource_arm_pmu,
};
static int __init rk2928_init_devices(void)
{
rk2928_init_dma();
rk2928_init_uart();
rk2928_init_i2c();
rk2928_init_spim();
#ifdef CONFIG_MTD_NAND_RK29XX
platform_device_register(&device_nand);
#endif
#ifdef CONFIG_ADC_RK30
platform_device_register(&device_adc);
#endif
#ifdef CONFIG_KEYS_RK29
platform_device_register(&device_keys);
#endif
#ifdef CONFIG_RGA_RK30
platform_device_register(&device_rga);
#endif
#ifdef CONFIG_LCDC_RK2928
platform_device_register(&device_lcdc);
#endif
#ifdef CONFIG_USB20_OTG
platform_device_register(&device_usb20_otg);
#endif
#ifdef CONFIG_USB20_HOST
platform_device_register(&device_usb20_host);
#endif
rk2928_init_sdmmc();
#if defined(CONFIG_FIQ_DEBUGGER) && defined(DEBUG_UART_PHYS)
rk_serial_debug_init(DEBUG_UART_BASE, IRQ_DEBUG_UART, IRQ_UART_SIGNAL, -1);
#endif
rk2928_init_i2s();
#ifdef CONFIG_HDMI_RK2928
platform_device_register(&device_hdmi);
#endif
platform_device_register(&device_arm_pmu);
return 0;
}
arch_initcall(rk2928_init_devices);

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#ifndef __MACH_BOARD_H
#define __MACH_BOARD_H
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/types.h>
#include <linux/timer.h>
#include <linux/notifier.h>
#include <asm/setup.h>
#include <plat/board.h>
#include <mach/sram.h>
#include <linux/i2c-gpio.h>
extern struct rk29_sdmmc_platform_data default_sdmmc0_data;
extern struct rk29_sdmmc_platform_data default_sdmmc1_data;
extern struct i2c_gpio_platform_data default_i2c_gpio_data;
void __init rk2928_map_common_io(void);
void __init rk2928_init_irq(void);
void __init rk2928_map_io(void);
struct machine_desc;
void __init rk2928_fixup(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi);
void __init rk2928_clock_data_init(unsigned long gpll,unsigned long cpll,u32 flags);
void __init board_clock_init(void);
void __init rk2928_iomux_init(void);
void board_gpio_suspend(void);
void board_gpio_resume(void);
void __sramfunc board_pmu_suspend(void);
void __sramfunc board_pmu_resume(void);
extern struct sys_timer rk2928_timer;
#ifndef _LINUX_WLAN_PLAT_H_
struct wifi_platform_data {
int (*set_power)(int val);
int (*set_reset)(int val);
int (*set_carddetect)(int val);
void *(*mem_prealloc)(int section, unsigned long size);
int (*get_mac_addr)(unsigned char *buf);
};
#endif
#if defined (CONFIG_EETI_EGALAX)
struct eeti_egalax_platform_data{
u16 model;
int (*get_pendown_state)(void);
int (*init_platform_hw)(void);
int (*eeti_egalax_platform_sleep)(void);
int (*eeti_egalax_platform_wakeup)(void);
void (*exit_platform_hw)(void);
int standby_pin;
int standby_value;
int disp_on_pin;
int disp_on_value;
};
#endif
#if defined (CONFIG_TOUCHSCREEN_SITRONIX_A720)
struct ft5x0x_platform_data{
u16 model;
int (*get_pendown_state)(void);
int (*init_platform_hw)(void);
int (*ft5x0x_platform_sleep)(void);
int (*ft5x0x_platform_wakeup)(void);
void (*exit_platform_hw)(void);
};
#endif
enum _periph_pll {
periph_pll_1485mhz = 148500000,
periph_pll_297mhz = 297000000,
periph_pll_300mhz = 300000000,
periph_pll_1188mhz = 1188000000, /* for box*/
};
enum _codec_pll {
codec_pll_360mhz = 360000000, /* for HDMI */
codec_pll_408mhz = 408000000,
codec_pll_456mhz = 456000000,
codec_pll_504mhz = 504000000,
codec_pll_552mhz = 552000000, /* for HDMI */
codec_pll_600mhz = 600000000,
codec_pll_742_5khz = 742500000,
codec_pll_798mhz = 798000000,
codec_pll_1064mhz = 1064000000,
codec_pll_1188mhz = 1188000000,
};
//max i2s rate
#define CLK_FLG_MAX_I2S_12288KHZ (1<<1)
#define CLK_FLG_MAX_I2S_22579_2KHZ (1<<2)
#define CLK_FLG_MAX_I2S_24576KHZ (1<<3)
#define CLK_FLG_MAX_I2S_49152KHZ (1<<4)
#define RK30_CLOCKS_DEFAULT_FLAGS (CLK_FLG_MAX_I2S_12288KHZ/*|CLK_FLG_EXT_27MHZ*/)
#define periph_pll_default periph_pll_297mhz
#define codec_pll_default codec_pll_798mhz
//#define codec_pll_default codec_pll_1064mhz
#endif

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#include <plat/clkdev.h>

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/* arch/arm/mach-rk29/include/mach/clock.h
*
* Copyright (C) 2011 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_RK30_CLOCK_H
#define __ASM_ARCH_RK30_CLOCK_H
/**
* struct clk_notifier_data - rate data to pass to the notifier callback
* @clk: struct clk * being changed
* @old_rate: previous rate of this clock
* @new_rate: new rate of this clock
*
* For a pre-notifier, old_rate is the clock's rate before this rate
* change, and new_rate is what the rate will be in the future. For a
* post-notifier, old_rate and new_rate are both set to the clock's
* current rate (this was done to optimize the implementation).
*/
struct clk_notifier_data {
struct clk *clk;
unsigned long old_rate;
unsigned long new_rate;
};
/*
* Clk notifier callback types
*
* Since the notifier is called with interrupts disabled, any actions
* taken by callbacks must be extremely fast and lightweight.
*
* CLK_PRE_RATE_CHANGE - called after all callbacks have approved the
* rate change, immediately before the clock rate is changed, to
* indicate that the rate change will proceed. Drivers must
* immediately terminate any operations that will be affected by
* the rate change. Callbacks must always return NOTIFY_DONE.
*
* CLK_ABORT_RATE_CHANGE: called if the rate change failed for some
* reason after CLK_PRE_RATE_CHANGE. In this case, all registered
* notifiers on the clock will be called with
* CLK_ABORT_RATE_CHANGE. Callbacks must always return
* NOTIFY_DONE.
*
* CLK_POST_RATE_CHANGE - called after the clock rate change has
* successfully completed. Callbacks must always return
* NOTIFY_DONE.
*
*/
#define CLK_PRE_RATE_CHANGE 1
#define CLK_POST_RATE_CHANGE 2
#define CLK_ABORT_RATE_CHANGE 3
#define CLK_PRE_ENABLE 4
#define CLK_POST_ENABLE 5
#define CLK_ABORT_ENABLE 6
#define CLK_PRE_DISABLE 7
#define CLK_POST_DISABLE 8
#define CLK_ABORT_DISABLE 9
struct notifier_block;
extern int clk_notifier_register(struct clk *clk, struct notifier_block *nb);
extern int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
#endif

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#ifndef __MACH_CRU_H
#define __MACH_CRU_H
enum rk_plls_id {
APLL_ID = 0,
DPLL_ID,
CPLL_ID,
GPLL_ID,
END_PLL_ID,
};
/*****cru reg offset*****/
#define CRU_MODE_CON 0x40
#define CRU_CLKSEL_CON 0x44
#define CRU_CLKGATE_CON 0xd0
#define CRU_GLB_SRST_FST 0x100
#define CRU_GLB_SRST_SND 0x104
#define CRU_SOFTRST_CON 0x110
#define PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4))
#define CRU_CLKSELS_CON_CNT (35)
#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + ((i) * 4))
#define CRU_CLKGATES_CON_CNT (10)
#define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + ((i) * 4))
#define CRU_SOFTRSTS_CON_CNT (9)
#define CRU_SOFTRSTS_CON(i) (CRU_SOFTRST_CON + ((i) * 4))
#define CRU_MISC_CON (0x134)
#define CRU_GLB_CNT_TH (0x140)
/*PLL_CON 0,1,2*/
#define PLL_PWR_ON (1)
#define PLL_PWR_DN (0)
#define PLL_BYPASS (1 << 15)
#define PLL_NO_BYPASS (0 << 15)
//con0
#define PLL_BYPASS_SHIFT (15)
#define PLL_POSTDIV1_MASK (0x7)
#define PLL_POSTDIV1_SHIFT (12)
#define PLL_FBDIV_MASK (0xfff)
#define PLL_FBDIV_SHIFT (0)
//con1
#define PLL_RSTMODE_SHIFT (15)
#define PLL_RST_SHIFT (14)
#define PLL_PWR_DN_SHIFT (13)
#define PLL_DSMPD_SHIFT (12)
#define PLL_LOCK_SHIFT (10)
#define PLL_POSTDIV2_MASK (0x7)
#define PLL_POSTDIV2_SHIFT (6)
#define PLL_REFDIV_MASK (0x3f)
#define PLL_REFDIV_SHIFT (0)
//con2
#define PLL_FOUT4PHASE_PWR_DN_SHIFT (27)
#define PLL_FOUTVCO_PWR_DN_SHIFT (26)
#define PLL_FOUTPOSTDIV_PWR_DN_SHIFT (25)
#define PLL_DAC_PWR_DN_SHIFT (24)
#define PLL_FRAC_MASK (0xffffff)
#define PLL_FRAC_SHIFT (0)
/********************************************************************/
#define CRU_GET_REG_BIT_VAL(reg, bits_shift) (((reg) >> (bits_shift)) & (0x1))
#define CRU_GET_REG_BITS_VAL(reg, bits_shift, msk) (((reg) >> (bits_shift)) & (msk))
#define CRU_SET_BIT(val, bits_shift) (((val) & (0x1)) << (bits_shift))
#define CRU_SET_BITS(val, bits_shift, msk) (((val) & (msk)) << (bits_shift))
#define CRU_W_MSK(bits_shift, msk) ((msk) << ((bits_shift) + 16))
#define CRU_W_MSK_SETBITS(val, bits_shift, msk) (CRU_W_MSK(bits_shift, msk) \
| CRU_SET_BITS(val, bits_shift, msk))
#define CRU_W_MSK_SETBIT(val, bits_shift) (CRU_W_MSK(bits_shift, 0x1) \
| CRU_SET_BIT(val, bits_shift))
#define PLL_SET_REFDIV(val) CRU_W_MSK_SETBITS(val, PLL_REFDIV_SHIFT, PLL_REFDIV_MASK)
#define PLL_SET_FBDIV(val) CRU_W_MSK_SETBITS(val, PLL_FBDIV_SHIFT, PLL_FBDIV_MASK)
#define PLL_SET_POSTDIV1(val) CRU_W_MSK_SETBITS(val, PLL_POSTDIV1_SHIFT, PLL_POSTDIV1_MASK)
#define PLL_SET_POSTDIV2(val) CRU_W_MSK_SETBITS(val, PLL_POSTDIV2_SHIFT, PLL_POSTDIV2_MASK)
#define PLL_SET_FRAC(val) CRU_SET_BITS(val, PLL_FRAC_SHIFT, PLL_FRAC_MASK)
#define PLL_GET_REFDIV(reg) CRU_GET_REG_BITS_VAL(reg, PLL_REFDIV_SHIFT, PLL_REFDIV_MASK)
#define PLL_GET_FBDIV(reg) CRU_GET_REG_BITS_VAL(reg, PLL_FBDIV_SHIFT, PLL_FBDIV_MASK)
#define PLL_GET_POSTDIV1(reg) CRU_GET_REG_BITS_VAL(reg, PLL_POSTDIV1_SHIFT, PLL_POSTDIV1_MASK)
#define PLL_GET_POSTDIV2(reg) CRU_GET_REG_BITS_VAL(reg, PLL_POSTDIV2_SHIFT, PLL_POSTDIV2_MASK)
#define PLL_GET_FRAC(reg) CRU_GET_REG_BITS_VAL(reg, PLL_FRAC_SHIFT, PLL_FRAC_MASK)
//#define APLL_SET_BYPASS(val) CRU_SET_BIT(val, PLL_BYPASS_SHIFT)
#define PLL_SET_DSMPD(val) CRU_W_MSK_SETBIT(val, PLL_DSMPD_SHIFT)
#define PLL_GET_DSMPD(reg) CRU_GET_REG_BIT_VAL(reg, PLL_DSMPD_SHIFT)
/*******************MODE BITS***************************/
#define PLL_MODE_MSK(id) (0x1 << ((id) * 4))
#define PLL_MODE_SHIFT(id) ((id) * 4)
#define PLL_MODE_SLOW(id) (CRU_W_MSK_SETBIT(0x0, PLL_MODE_SHIFT(id)))
#define PLL_MODE_NORM(id) (CRU_W_MSK_SETBIT(0x1, PLL_MODE_SHIFT(id)))
/*******************CLKSEL0 BITS***************************/
#define CLK_SET_DIV_CON_SUB1(val, bits_shift, msk) CRU_W_MSK_SETBITS((val - 1), bits_shift, msk)
#define CPU_CLK_PLL_SEL_SHIFT (13)
#define CORE_CLK_PLL_SEL_SHIFT (7)
#define SEL_APLL (0)
#define SEL_GPLL (1)
#define CPU_SEL_PLL(plls) CRU_W_MSK_SETBIT(plls, CPU_CLK_PLL_SEL_SHIFT)
#define CORE_SEL_PLL(plls) CRU_W_MSK_SETBIT(plls, CORE_CLK_PLL_SEL_SHIFT)
#define ACLK_CPU_DIV_MASK (0x1f)
#define ACLK_CPU_DIV_SHIFT (8)
#define A9_CORE_DIV_MASK (0x1f)
#define A9_CORE_DIV_SHIFT (0)
#define ACLK_CPU_DIV(val) CLK_SET_DIV_CON_SUB1(val, ACLK_CPU_DIV_SHIFT, ACLK_CPU_DIV_MASK)
#define CLK_CORE_DIV(val) CLK_SET_DIV_CON_SUB1(val, A9_CORE_DIV_SHIFT, A9_CORE_DIV_MASK)
/*******************CLKSEL1 BITS***************************/
#define PCLK_CPU_DIV_MASK (0x7)
#define PCLK_CPU_DIV_SHIFT (12)
#define HCLK_CPU_DIV_MASK (0x3)
#define HCLK_CPU_DIV_SHIFT (8)
#define ACLK_CORE_DIV_MASK (0x1)
#define ACLK_CORE_DIV_SHIFT (4)
#define CORE_PERIPH_DIV_MASK (0xf)
#define CORE_PERIPH_DIV_SHIFT (0)
#define PCLK_CPU_DIV(val) CLK_SET_DIV_CON_SUB1(val, PCLK_CPU_DIV_SHIFT, PCLK_CPU_DIV_MASK)
#define HCLK_CPU_DIV(val) CLK_SET_DIV_CON_SUB1(val, HCLK_CPU_DIV_SHIFT, HCLK_CPU_DIV_MASK)
#define ACLK_CORE_DIV(val) CLK_SET_DIV_CON_SUB1(val, ACLK_CORE_DIV_SHIFT, ACLK_CORE_DIV_MASK)
#define CLK_CORE_PERI_DIV(val) CLK_SET_DIV_CON_SUB1(val, CORE_PERIPH_DIV_SHIFT, CORE_PERIPH_DIV_MASK)
/*******************clksel10***************************/
#define PERI_PLL_SEL_SHIFT 15
#define PERI_PCLK_DIV_MASK (0x3)
#define PERI_PCLK_DIV_SHIFT (12)
#define PERI_HCLK_DIV_MASK (0x3)
#define PERI_HCLK_DIV_SHIFT (8)
#define PERI_ACLK_DIV_MASK (0x1f)
#define PERI_ACLK_DIV_SHIFT (0)
#define SEL_2PLL_GPLL (0)
#define SEL_2PLL_CPLL (1)
#define RATIO_11 (1)
#define RATIO_21 (2)
#define RATIO_41 (4)
#define RATIO_81 (8)
#define PERI_CLK_SEL_PLL(plls) CRU_W_MSK_SETBIT(plls, PERI_PLL_SEL_SHIFT)
#define PERI_SET_A2P_RATIO(ratio) CRU_W_MSK_SETBITS(ratio, PERI_PCLK_DIV_SHIFT, PERI_PCLK_DIV_MASK)
#define PERI_SET_A2H_RATIO(ratio) CRU_W_MSK_SETBITS(ratio, PERI_HCLK_DIV_SHIFT, PERI_PCLK_DIV_MASK)
#define PERI_SET_ACLK_DIV(val) CRU_W_MSK_SETBITS(val, PERI_ACLK_DIV_SHIFT, PERI_ACLK_DIV_MASK)
/*******************gate BITS***************************/
#define CLK_GATE_CLKID_CONS(i) CRU_CLKGATES_CON((i) / 16)
#define CLK_GATE(i) (1 << ((i)%16))
#define CLK_UN_GATE(i) (0)
#define CLK_GATE_W_MSK(i) (1 << (((i) % 16) + 16))
#define CLK_GATE_CLKID(i) (16 * (i))
enum cru_clk_gate {
/* SCU CLK GATE 0 CON */
CLK_GATE_CORE_PERIPH = CLK_GATE_CLKID(0),
CLK_GATE_CPU_GPLL,
CLK_GATE_DDRPHY_SRC,
CLK_GATE_ACLK_CPU,
CLK_GATE_HCLK_CPU,
CLK_GATE_PCLK_CPU,
CLK_GATE_0RES6,
CLK_GATE_ACLK_CORE,
CLK_GATE_0RES8,
CLK_GATE_I2S_SRC,
CLK_GATE_I2S_FRAC_SRC,
CLK_GATE_HCLK_VIO_PRE,
CLK_GATE_0RES12,
CLK_GATE_0RES13,
CLK_GATE_0RES14,
CLK_GATE_TESTCLK,
CLK_GATE_TIMER0 = CLK_GATE_CLKID(1),
CLK_GATE_TIMER1,
CLK_GATE_1RES2,
CLK_GATE_JTAG,
CLK_GATE_1RES4,
CLK_GATE_OTGPHY0,
CLK_GATE_OTGPHY1,
CLK_GATE_1RES7,
CLK_GATE_UART0_SRC,
CLK_GATE_UART0_FRAC_SRC,
CLK_GATE_UART1_SRC,
CLK_GATE_UART1_FRAC_SRC,
CLK_GATE_UART2_SRC,
CLK_GATE_UART2_FRAC_SRC,
CLK_GATE_1RES14,
CLK_GATE_1RES15,
CLK_GATE_PERIPH_SRC = CLK_GATE_CLKID(2),
CLK_GATE_ACLK_PERIPH,
CLK_GATE_HCLK_PERIPH,
CLK_GATE_PCLK_PERIPH,
CLK_GATE_2RES4,
CLK_GATE_2RES5,
CLK_GATE_2RES6,
CLK_GATE_2RES7,
CLK_GATE_SARADC_SRC,
CLK_GATE_SPI0_SRC,
CLK_GATE_2RES10,
CLK_GATE_MMC0_SRC,
CLK_GATE_2RES12,
CLK_GATE_SDIO_SRC,
CLK_GATE_EMMC_SRC,
CLK_GATE_2RES15,
CLK_GATE_ACLK_VIO_SRC = CLK_GATE_CLKID(3),
CLK_GATE_DCLK_LCDC0_SRC,
CLK_GATE_SCLK_LCDC_SRC,
CLK_GATE_PCLKIN_CIF,
CLK_GATE_ACLK_GPS,
CLK_GATE_3RES5,
CLK_GATE_3RES6,
CLK_GATE_CIF_OUT_SRC,
CLK_GATE_PCLK_HDMI,
CLK_GATE_ACLK_VEPU_SRC,
CLK_GATE_HCLK_VEPU,
CLK_GATE_ACLK_VDPU_SRC,
CLK_GATE_HCLK_VDPU,
CLK_GATE_GPU_PRE,
CLK_GATE_3RES14,
CLK_GATE_3RES15,
CLK_GATE_HCLK_PERI_AXI_MATRIX = CLK_GATE_CLKID(4),
CLK_GATE_PCLK_PERI_AXI_MATRIX,
CLK_GATE_ACLK_CPU_PERI,
CLK_GATE_ACLK_PERI_AXI_MATRIX,
CLK_GATE_4RES4,
CLK_GATE_4RES5,
CLK_GATE_4RES6,
CLK_GATE_4RES7,
CLK_GATE_4RES8,
CLK_GATE_4RES9,
CLK_GATE_ACLK_STRC_SYS,
CLK_GATE_4RES11,
CLK_GATE_ACLK_INTMEM,
CLK_GATE_4RES13,
CLK_GATE_4RES14,
CLK_GATE_4RES15,
CLK_GATE_5RES0 = CLK_GATE_CLKID(5),
CLK_GATE_ACLK_DMAC2,
CLK_GATE_PCLK_EFUSE,
CLK_GATE_5RES3,
CLK_GATE_PCLK_GRF,
CLK_GATE_5RES5,
CLK_GATE_HCLK_ROM,
CLK_GATE_PCLK_DDRUPCTL,
CLK_GATE_5RES8,
CLK_GATE_HCLK_NANDC,
CLK_GATE_HCLK_SDMMC0,
CLK_GATE_HCLK_SDIO,
CLK_GATE_5RES12,
CLK_GATE_HCLK_OTG0,
CLK_GATE_PCLK_ACODEC,
CLK_GATE_5RES15,
CLK_GATE_ACLK_LCDC0 = CLK_GATE_CLKID(6),
CLK_GATE_HCLK_LCDC0,
CLK_GATE_6RES2,
CLK_GATE_6RES3,
CLK_GATE_HCLK_CIF,
CLK_GATE_ACLK_CIF,
CLK_GATE_6RES6,
CLK_GATE_6RES7,
CLK_GATE_6RES8,
CLK_GATE_6RES9,
CLK_GATE_HCLK_RGA,
CLK_GATE_ACLK_RGA,
CLK_GATE_HCLK_VIO_BUS,
CLK_GATE_ACLK_VIO0,
CLK_GATE_6RES14,
CLK_GATE_6RES15,
CLK_GATE_HCLK_EMMC = CLK_GATE_CLKID(7),
CLK_GATE_7RES1,
CLK_GATE_HCLK_I2S,
CLK_GATE_HCLK_OTG1,
CLK_GATE_7RES4,
CLK_GATE_7RES5,
CLK_GATE_7RES6,
CLK_GATE_PCLK_TIMER0,
CLK_GATE_PCLK_TIMER1,
CLK_GATE_7RES9,
CLK_GATE_PCLK_PWM01,
CLK_GATE_7RES11,
CLK_GATE_PCLK_SPI0,
CLK_GATE_7RES13,
CLK_GATE_PCLK_SARADC,
CLK_GATE_PCLK_WDT,
CLK_GATE_PCLK_UART0 = CLK_GATE_CLKID(8),
CLK_GATE_PCLK_UART1,
CLK_GATE_PCLK_UART2,
CLK_GATE_8RES3,
CLK_GATE_PCLK_I2C0,
CLK_GATE_PCLK_I2C1,
CLK_GATE_PCLK_I2C2,
CLK_GATE_PCLK_I2C3,
CLK_GATE_8RES8,
CLK_GATE_PCLK_GPIO0,
CLK_GATE_PCLK_GPIO1,
CLK_GATE_PCLK_GPIO2,
CLK_GATE_PCLK_GPIO3,
CLK_GATE_8RES13,
CLK_GATE_8RES14,
CLK_GATE_8RES15,
CLK_GATE_CLK_CORE_DBG = CLK_GATE_CLKID(9),
CLK_GATE_PCLK_DBG,
CLK_GATE_9RES2,
CLK_GATE_9RES3,
CLK_GATE_CLK_L2C,
CLK_GATE_9RES5,
CLK_GATE_9RES6,
CLK_GATE_9RES7,
CLK_GATE_9RES8,
CLK_GATE_9RES9,
CLK_GATE_HCLK_USB_PERI,
CLK_GATE_HCLK_PERI_ARBI,
CLK_GATE_ACLK_PERI_NIU,
CLK_GATE_9RES13,
CLK_GATE_9RES14,
CLK_GATE_9RES15,
CLK_GATE_MAX,
};
#define SOFT_RST_ID(i) (16 * (i))
enum cru_soft_reset {
SOFT_RST_CORE_SRST_WDT_SEL = SOFT_RST_ID(0),
SOFT_RST_ACLK_CORE,
SOFT_RST_MCORE,
SOFT_RST_0RES3,
SOFT_RST_0RES4,
SOFT_RST_0RES5,
SOFT_RST_0RES6,
SOFT_RST_MCORE_DBG,
SOFT_RST_0RES8,
SOFT_RST_0RES9,
SOFT_RST_0RES10,
SOFT_RST_0RES11,
SOFT_RST_CORE0_WDT,
SOFT_RST_0RES13,
SOFT_RST_STRC_SYS_AXI,
SOFT_RST_0RES15,
SOFT_RST_CPU_STRC_SYS_AXI = SOFT_RST_ID(1),
SOFT_RST_CPUSYS_AHB,
SOFT_RST_L2MEM_CON_AXI,
SOFT_RST_AHB2APB,
SOFT_RST_1RES4,
SOFT_RST_INTMEM,
SOFT_RST_ROM,
SOFT_RST_PERI_NIU,
SOFT_RST_I2S,
SOFT_RST_1RES9,
SOFT_RST_1RES10,
SOFT_RST_TIMER0,
SOFT_RST_TIMER1,
SOFT_RST_1RES13,
SOFT_RST_EFUSE_APB,
SOFT_RST_ACODEC,
SOFT_RST_GPIO0 = SOFT_RST_ID(2),
SOFT_RST_GPIO1,
SOFT_RST_GPIO2,
SOFT_RST_GPIO3,
SOFT_RST_2RES4,
SOFT_RST_2RES5,
SOFT_RST_2RES6,
SOFT_RST_UART0,
SOFT_RST_UART1,
SOFT_RST_UART2,
SOFT_RST_2RES10,
SOFT_RST_I2C0,
SOFT_RST_I2C1,
SOFT_RST_I2C2,
SOFT_RST_I2C3,
SOFT_RST_2RES15,
SOFT_RST_PWM0 = SOFT_RST_ID(3),
SOFT_RST_PWM1,
SOFT_RST_DAP_PO,
SOFT_RST_DAP,
SOFT_RST_DAP_SYS,
SOFT_RST_3RES5,
SOFT_RST_3RES6,
SOFT_RST_GRF,
SOFT_RST_I2C,
SOFT_RST_PERIPHSYS_AXI,
SOFT_RST_PERIPHSYS_AHB,
SOFT_RST_PERIPHSYS_APB,
SOFT_RST_PWM2,
SOFT_RST_CPU_PERI,
SOFT_RST_EMEM_PERI,
SOFT_RST_USB_PERI,
SOFT_RST_DMA2 = SOFT_RST_ID(4),
SOFT_RST_4RES1,
SOFT_RST_4RES2,
SOFT_RST_GPS,
SOFT_RST_NANDC,
SOFT_RST_USBOTG0,
SOFT_RST_USBPHY0,
SOFT_RST_OTGC0,
SOFT_RST_USBOTG1,
SOFT_RST_USBPHY1,
SOFT_RST_OTGC1,
SOFT_RST_4RES11,
SOFT_RST_4RES12,
SOFT_RST_4RES13,
SOFT_RST_4RES14,
SOFT_RST_DDRMSCH,
SOFT_RST_5RES0 = SOFT_RST_ID(5),
SOFT_RST_MMC0,
SOFT_RST_SDIO,
SOFT_RST_EMMC,
SOFT_RST_SPI0,
SOFT_RST_5RES5,
SOFT_RST_WDT,
SOFT_RST_SARADC,
SOFT_RST_DDRPHY,
SOFT_RST_DDRPHY_APB,
SOFT_RST_DDRCTRL,
SOFT_RST_DDRCTRL_APB,
SOFT_RST_5RES12,
SOFT_RST_5RES13,
SOFT_RST_5RES14,
SOFT_RST_5RES15,
SOFT_RST_HDMI_PCLK = SOFT_RST_ID(6),
SOFT_RST_HDMI_DCLK,
SOFT_RST_VIO0_AXI,
SOFT_RST_VIO_BUS_AHB,
SOFT_RST_LCDC0_AXI,
SOFT_RST_LCDC0_AHB,
SOFT_RST_LCDC0_DCLK,
SOFT_RST_UTMI0,
SOFT_RST_UTMI1,
SOFT_RST_USBPOR,
SOFT_RST_6RES10,
SOFT_RST_6RES11,
SOFT_RST_RGA_AXI,
SOFT_RST_RGA_AHB,
SOFT_RST_CIF0,
SOFT_RST_LCDC_SCL,
SOFT_RST_VCODEC_AXI = SOFT_RST_ID(7),
SOFT_RST_VCODEC_AHB,
SOFT_RST_VIO1_AXI,
SOFT_RST_CPU_VCODEC,
SOFT_RST_VCODEC_NIU_AXI,
SOFT_RST_7RES5,
SOFT_RST_7RES6,
SOFT_RST_7RES7,
SOFT_RST_GPU,
SOFT_RST_7RES9,
SOFT_RST_GPU_NIU_AXI,
SOFT_RST_7RES11,
SOFT_RST_7RES12,
SOFT_RST_7RES13,
SOFT_RST_7RES14,
SOFT_RST_7RES15,
SOFT_RST_8RES0 = SOFT_RST_ID(8),
SOFT_RST_8RES1,
SOFT_RST_CORE_DBG,
SOFT_RST_DBG_APB,
SOFT_RST_8RES4,
SOFT_RST_8RES5,
SOFT_RST_8RES6,
SOFT_RST_8RES7,
SOFT_RST_8RES8,
SOFT_RST_8RES9,
SOFT_RST_8RES10,
SOFT_RST_8RES11,
SOFT_RST_8RES12,
SOFT_RST_8RES13,
SOFT_RST_8RES14,
SOFT_RST_8RES15,
SOFT_RST_MAX,
};
/*****cru reg end*****/
static inline void cru_set_soft_reset(enum cru_soft_reset idx, bool on)
{
const void __iomem *reg = RK2928_CRU_BASE + CRU_SOFTRSTS_CON(idx >> 4);
u32 val = on ? 0x10001U << (idx & 0xf) : 0x10000U << (idx & 0xf);
writel_relaxed(val, reg);
dsb();
}
#endif

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#include <plat/debug-macro.S>

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#include <plat/dma-pl330.h>

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/* arch/arm/mach-rk30/rk30_dvfs.h
*
* Copyright (C) 2012 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _RK30_DVFS_H_
#define _RK30_DVFS_H_
#include <mach/clock.h>
typedef int (*vd_dvfs_target_callback)(struct clk *clk, unsigned long rate);
typedef int (*dvfs_set_rate_callback)(struct clk *clk, unsigned long rate);
typedef int (*clk_dvfs_target_callback)(struct clk *clk, unsigned long rate,
dvfs_set_rate_callback set_rate);
/**
* struct vd_node: To Store All Voltage Domains' info
* @name: Voltage Domain's Name
* @regulator_name: Voltage domain's regulator name
* @cur_volt: Voltage Domain's Current Voltage
* @regulator: Voltage Domain's regulator point
* @node: Point of he Voltage Domain List Node
* @pd_list: Head of Power Domain List Belongs to This Voltage Domain
* @req_volt_list: The list of clocks requests
* @dvfs_mutex: Lock
* @vd_dvfs_target: Callback function
*/
struct vd_node {
char *name;
char *regulator_name;
int cur_volt;
int volt_set_flag;
struct regulator *regulator;
struct list_head node;
struct list_head pd_list;
struct list_head req_volt_list;
//struct mutex dvfs_mutex;
vd_dvfs_target_callback vd_dvfs_target;
};
/**
* struct pd_node: To Store All Power Domains' info
* @name: Power Domain's Name
* @cur_volt: Power Domain's Current Voltage
* @pd_status: Power Domain's status
* @vd: Voltage Domain the power domain belongs to
* @pd_clk: Look power domain as a clock
* @node: List node to Voltage Domain
* @clk_list: Head of Power Domain's Clocks List
*/
struct pd_node {
char *name;
int cur_volt;
unsigned char pd_status;
struct vd_node *vd;
//struct clk *pd_clk;
struct list_head node;
struct list_head clk_list;
};
struct pd_node_lookup {
struct pd_node *pd;
};
struct clk_list{
struct clk_node *dvfs_clk;
struct list_head node;
};
struct pds_list {
struct clk_list clk_list;
struct pd_node *pd;
};
struct depend_list {
int req_volt;
struct clk_node *dvfs_clk;
struct vd_node *dep_vd;
struct list_head node2clk;
struct list_head node2vd;
struct cpufreq_frequency_table *dep_table;
};
struct depend_lookup {
char *clk_name;
struct clk_node *dvfs_clk;
struct vd_node *dep_vd;
struct depend_list dep_list;
struct cpufreq_frequency_table *dep_table;
};
/**
* struct clk_node: To Store All dvfs clocks' info
* @name: Dvfs clock's Name
* @set_freq: Dvfs clock's Current Frequency
* @set_volt: Dvfs clock's Current Voltage
* @enable_dvfs: Sign if DVFS clock enable
* @clk: System clk's point
* @pds: Power Domains dvfs clock belongs to
* @vd: Voltage Domains dvfs clock belongs to
* @depend_list: Dvfs Clock depend list
* @dvfs_nb: Notify list
* @dvfs_table: Frequency and voltage table for dvfs
* @clk_dvfs_target: Callback function
*/
struct clk_node {
char *name;
int set_freq; //KHZ
int set_volt; //MV
int enable_dvfs;
int freq_limit_en; //sign if use limit frequency
unsigned int min_rate; //limit min frequency
unsigned int max_rate; //limit max frequency
struct clk *clk;
struct pds_list *pds;
struct vd_node *vd;
struct list_head depend_list;
struct notifier_block *dvfs_nb;
struct cpufreq_frequency_table *dvfs_table;
clk_dvfs_target_callback clk_dvfs_target;
};
struct dvfs_arm_table {
unsigned int frequency; /* kHz - doesn't need to be in ascending
* order */
unsigned int cpu_volt; /* any */
unsigned int logic_volt;
};
#ifdef CONFIG_DVFS
int rk30_dvfs_init(void);
int is_support_dvfs(struct clk_node *dvfs_info);
int dvfs_set_rate(struct clk *clk, unsigned long rate);
int clk_enable_dvfs(struct clk *clk);
int clk_disable_dvfs(struct clk *clk);
void dvfs_clk_register_set_rate_callback(struct clk *clk, clk_dvfs_target_callback clk_dvfs_target);
struct cpufreq_frequency_table *dvfs_get_freq_volt_table(struct clk *clk);
int dvfs_set_freq_volt_table(struct clk *clk, struct cpufreq_frequency_table *table);
int dvfs_set_depend_table(struct clk *clk, char *vd_name, struct cpufreq_frequency_table *table);
int dvfs_set_arm_logic_volt(struct dvfs_arm_table *dvfs_cpu_logic_table, struct cpufreq_frequency_table *cpu_dvfs_table, struct cpufreq_frequency_table *dep_cpu2core_table);
struct regulator* dvfs_get_regulator(char *regulator_name);
int dvfs_clk_enable_limit(struct clk *clk, unsigned int min_rate, unsigned max_rate);
int dvfs_clk_disable_limit(struct clk *clk);
void avs_init(void);
void avs_init_val_get(int index,int vol,char *s);
int avs_set_scal_val(u8 avs_base);
int dvfs_avs_scale_table(struct clk* clk, char* depend_vd_name);
#else
static inline int rk30_dvfs_init(void) { return 0; }
static inline int is_support_dvfs(struct clk_node *dvfs_info) { return 0; }
static inline int dvfs_set_rate(struct clk *clk, unsigned long rate) { return 0; }
static inline int clk_enable_dvfs(struct clk *clk) { return 0; }
static inline int clk_disable_dvfs(struct clk *clk) { return 0; }
static inline void dvfs_clk_register_set_rate_callback(struct clk *clk, clk_dvfs_target_callback clk_dvfs_target) {}
static inline struct cpufreq_frequency_table *dvfs_get_freq_volt_table(struct clk *clk) { return NULL; }
static inline int dvfs_set_freq_volt_table(struct clk *clk, struct cpufreq_frequency_table *table) { return 0; }
static inline int dvfs_set_depend_table(struct clk *clk, char *vd_name, struct cpufreq_frequency_table *table) {return 0;}
static inline int dvfs_set_arm_logic_volt(struct dvfs_arm_table *dvfs_cpu_logic_table, struct cpufreq_frequency_table *cpu_dvfs_table, struct cpufreq_frequency_table *dep_cpu2core_table){ return 0; }
static inline struct regulator* dvfs_get_regulator(char *regulator_name){ return NULL; }
static inline int dvfs_clk_enable_limit(struct clk *clk, unsigned int min_rate, unsigned max_rate){ return 0; }
static inline int dvfs_clk_disable_limit(struct clk *clk){ return 0; };
static inline void avs_init(void){};
static inline void avs_init_val_get(int index, int vol, char *s){};
static inline int avs_set_scal_val(u8 avs_base){ return 0; };
static inline int dvfs_avs_scale_table(struct clk* clk, char* depend_vd_name){ return 0; };
#endif
#endif

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#include <plat/entry-macro.S>

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#include <plat/fiq.h>

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#ifndef __MACH_GPIO_H
#define __MACH_GPIO_H
#include <mach/irqs.h>
#include <linux/init.h>
//定义GPIO相关寄存器偏移地址
#define GPIO_SWPORT_DR 0x00
#define GPIO_SWPORT_DDR 0x04
#define GPIO_INTEN 0x30
#define GPIO_INTMASK 0x34
#define GPIO_INTTYPE_LEVEL 0x38
#define GPIO_INT_POLARITY 0x3c
#define GPIO_INT_STATUS 0x40
#define GPIO_INT_RAWSTATUS 0x44
#define GPIO_DEBOUNCE 0x48
#define GPIO_PORTS_EOI 0x4c
#define GPIO_EXT_PORT 0x50
#define GPIO_LS_SYNC 0x60
#define NUM_GROUP 32
#define MAX_BANK 4
#define PIN_BASE NR_GIC_IRQS
#define RK2928_TOTOL_GPIO_NUM (NUM_GROUP*MAX_BANK)
#define SPI_FPGA_EXPANDER_BASE (PIN_BASE+RK2928_TOTOL_GPIO_NUM)
#if defined (CONFIG_SPI_FPGA_GPIO)
#define GPIO_EXPANDER_BASE (PIN_BASE+RK2928_TOTOL_GPIO_NUM+CONFIG_SPI_FPGA_GPIO_NUM)
#else
#define GPIO_EXPANDER_BASE (PIN_BASE+RK2928_TOTOL_GPIO_NUM)
#endif
#if defined(CONFIG_IOEXTEND_TCA6424)
#define TCA6424_TOTOL_GPIO_NUM 24
#define TCA6424_TOTOL_GPIO_IRQ_NUM 24
#define TCA6424_GPIO_EXPANDER_BASE GPIO_EXPANDER_BASE
#else
#define TCA6424_TOTOL_GPIO_NUM 0
#define TCA6424_TOTOL_GPIO_IRQ_NUM 0
#endif
#if defined(CONFIG_GPIO_WM831X)
#define WM831X_TOTOL_GPIO_NUM 12
#define WM831X_GPIO_EXPANDER_BASE (GPIO_EXPANDER_BASE+TCA6424_TOTOL_GPIO_NUM)
#else
#define WM831X_TOTOL_GPIO_NUM 0
#define WM831X_GPIO_EXPANDER_BASE (GPIO_EXPANDER_BASE+TCA6424_TOTOL_GPIO_NUM)
#endif
#if defined (CONFIG_GPIO_WM8994)
#define CONFIG_GPIO_WM8994_NUM 11
#define WM8994_GPIO_EXPANDER_BASE (GPIO_EXPANDER_BASE+WM831X_TOTOL_GPIO_NUM)
#else
#define CONFIG_GPIO_WM8994_NUM 0
#define WM8994_GPIO_EXPANDER_BASE (GPIO_EXPANDER_BASE+WM831X_TOTOL_GPIO_NUM)
#endif
#if defined (CONFIG_GPIO_TPS65910)
#define CONFIG_GPIO_TPS65910_NUM 9
#define TPS65910_GPIO_EXPANDER_BASE (WM8994_GPIO_EXPANDER_BASE+CONFIG_GPIO_WM8994_NUM)
#else
#define CONFIG_GPIO_TPS65910_NUM 0
#define TPS65910_GPIO_EXPANDER_BASE (WM8994_GPIO_EXPANDER_BASE+CONFIG_GPIO_WM8994_NUM)
#endif
//定义GPIO的PIN口最大数目。CONFIG_SPI_FPGA_GPIO_NUM表示FPGA的PIN脚数。
#define ARCH_NR_GPIOS (PIN_BASE + RK2928_TOTOL_GPIO_NUM + TCA6424_TOTOL_GPIO_NUM + WM831X_TOTOL_GPIO_NUM + CONFIG_SPI_FPGA_GPIO_NUM + CONFIG_GPIO_WM8994_NUM + CONFIG_GPIO_TPS65910_NUM)
#define INVALID_GPIO -1
#define RK2928_PIN0_PA0 (0*NUM_GROUP + PIN_BASE + 0)
#define RK2928_PIN0_PA1 (0*NUM_GROUP + PIN_BASE + 1)
#define RK2928_PIN0_PA2 (0*NUM_GROUP + PIN_BASE + 2)
#define RK2928_PIN0_PA3 (0*NUM_GROUP + PIN_BASE + 3)
#define RK2928_PIN0_PA4 (0*NUM_GROUP + PIN_BASE + 4)
#define RK2928_PIN0_PA5 (0*NUM_GROUP + PIN_BASE + 5)
#define RK2928_PIN0_PA6 (0*NUM_GROUP + PIN_BASE + 6)
#define RK2928_PIN0_PA7 (0*NUM_GROUP + PIN_BASE + 7)
#define RK2928_PIN0_PB0 (0*NUM_GROUP + PIN_BASE + 8)
#define RK2928_PIN0_PB1 (0*NUM_GROUP + PIN_BASE + 9)
#define RK2928_PIN0_PB2 (0*NUM_GROUP + PIN_BASE + 10)
#define RK2928_PIN0_PB3 (0*NUM_GROUP + PIN_BASE + 11)
#define RK2928_PIN0_PB4 (0*NUM_GROUP + PIN_BASE + 12)
#define RK2928_PIN0_PB5 (0*NUM_GROUP + PIN_BASE + 13)
#define RK2928_PIN0_PB6 (0*NUM_GROUP + PIN_BASE + 14)
#define RK2928_PIN0_PB7 (0*NUM_GROUP + PIN_BASE + 15)
#define RK2928_PIN0_PC0 (0*NUM_GROUP + PIN_BASE + 16)
#define RK2928_PIN0_PC1 (0*NUM_GROUP + PIN_BASE + 17)
#define RK2928_PIN0_PC2 (0*NUM_GROUP + PIN_BASE + 18)
#define RK2928_PIN0_PC3 (0*NUM_GROUP + PIN_BASE + 19)
#define RK2928_PIN0_PC4 (0*NUM_GROUP + PIN_BASE + 20)
#define RK2928_PIN0_PC5 (0*NUM_GROUP + PIN_BASE + 21)
#define RK2928_PIN0_PC6 (0*NUM_GROUP + PIN_BASE + 22)
#define RK2928_PIN0_PC7 (0*NUM_GROUP + PIN_BASE + 23)
#define RK2928_PIN0_PD0 (0*NUM_GROUP + PIN_BASE + 24)
#define RK2928_PIN0_PD1 (0*NUM_GROUP + PIN_BASE + 25)
#define RK2928_PIN0_PD2 (0*NUM_GROUP + PIN_BASE + 26)
#define RK2928_PIN0_PD3 (0*NUM_GROUP + PIN_BASE + 27)
#define RK2928_PIN0_PD4 (0*NUM_GROUP + PIN_BASE + 28)
#define RK2928_PIN0_PD5 (0*NUM_GROUP + PIN_BASE + 29)
#define RK2928_PIN0_PD6 (0*NUM_GROUP + PIN_BASE + 30)
#define RK2928_PIN0_PD7 (0*NUM_GROUP + PIN_BASE + 31)
#define RK2928_PIN1_PA0 (1*NUM_GROUP + PIN_BASE + 0)
#define RK2928_PIN1_PA1 (1*NUM_GROUP + PIN_BASE + 1)
#define RK2928_PIN1_PA2 (1*NUM_GROUP + PIN_BASE + 2)
#define RK2928_PIN1_PA3 (1*NUM_GROUP + PIN_BASE + 3)
#define RK2928_PIN1_PA4 (1*NUM_GROUP + PIN_BASE + 4)
#define RK2928_PIN1_PA5 (1*NUM_GROUP + PIN_BASE + 5)
#define RK2928_PIN1_PA6 (1*NUM_GROUP + PIN_BASE + 6)
#define RK2928_PIN1_PA7 (1*NUM_GROUP + PIN_BASE + 7)
#define RK2928_PIN1_PB0 (1*NUM_GROUP + PIN_BASE + 8)
#define RK2928_PIN1_PB1 (1*NUM_GROUP + PIN_BASE + 9)
#define RK2928_PIN1_PB2 (1*NUM_GROUP + PIN_BASE + 10)
#define RK2928_PIN1_PB3 (1*NUM_GROUP + PIN_BASE + 11)
#define RK2928_PIN1_PB4 (1*NUM_GROUP + PIN_BASE + 12)
#define RK2928_PIN1_PB5 (1*NUM_GROUP + PIN_BASE + 13)
#define RK2928_PIN1_PB6 (1*NUM_GROUP + PIN_BASE + 14)
#define RK2928_PIN1_PB7 (1*NUM_GROUP + PIN_BASE + 15)
#define RK2928_PIN1_PC0 (1*NUM_GROUP + PIN_BASE + 16)
#define RK2928_PIN1_PC1 (1*NUM_GROUP + PIN_BASE + 17)
#define RK2928_PIN1_PC2 (1*NUM_GROUP + PIN_BASE + 18)
#define RK2928_PIN1_PC3 (1*NUM_GROUP + PIN_BASE + 19)
#define RK2928_PIN1_PC4 (1*NUM_GROUP + PIN_BASE + 20)
#define RK2928_PIN1_PC5 (1*NUM_GROUP + PIN_BASE + 21)
#define RK2928_PIN1_PC6 (1*NUM_GROUP + PIN_BASE + 22)
#define RK2928_PIN1_PC7 (1*NUM_GROUP + PIN_BASE + 23)
#define RK2928_PIN1_PD0 (1*NUM_GROUP + PIN_BASE + 24)
#define RK2928_PIN1_PD1 (1*NUM_GROUP + PIN_BASE + 25)
#define RK2928_PIN1_PD2 (1*NUM_GROUP + PIN_BASE + 26)
#define RK2928_PIN1_PD3 (1*NUM_GROUP + PIN_BASE + 27)
#define RK2928_PIN1_PD4 (1*NUM_GROUP + PIN_BASE + 28)
#define RK2928_PIN1_PD5 (1*NUM_GROUP + PIN_BASE + 29)
#define RK2928_PIN1_PD6 (1*NUM_GROUP + PIN_BASE + 30)
#define RK2928_PIN1_PD7 (1*NUM_GROUP + PIN_BASE + 31)
#define RK2928_PIN2_PA0 (2*NUM_GROUP + PIN_BASE + 0)
#define RK2928_PIN2_PA1 (2*NUM_GROUP + PIN_BASE + 1)
#define RK2928_PIN2_PA2 (2*NUM_GROUP + PIN_BASE + 2)
#define RK2928_PIN2_PA3 (2*NUM_GROUP + PIN_BASE + 3)
#define RK2928_PIN2_PA4 (2*NUM_GROUP + PIN_BASE + 4)
#define RK2928_PIN2_PA5 (2*NUM_GROUP + PIN_BASE + 5)
#define RK2928_PIN2_PA6 (2*NUM_GROUP + PIN_BASE + 6)
#define RK2928_PIN2_PA7 (2*NUM_GROUP + PIN_BASE + 7)
#define RK2928_PIN2_PB0 (2*NUM_GROUP + PIN_BASE + 8)
#define RK2928_PIN2_PB1 (2*NUM_GROUP + PIN_BASE + 9)
#define RK2928_PIN2_PB2 (2*NUM_GROUP + PIN_BASE + 10)
#define RK2928_PIN2_PB3 (2*NUM_GROUP + PIN_BASE + 11)
#define RK2928_PIN2_PB4 (2*NUM_GROUP + PIN_BASE + 12)
#define RK2928_PIN2_PB5 (2*NUM_GROUP + PIN_BASE + 13)
#define RK2928_PIN2_PB6 (2*NUM_GROUP + PIN_BASE + 14)
#define RK2928_PIN2_PB7 (2*NUM_GROUP + PIN_BASE + 15)
#define RK2928_PIN2_PC0 (2*NUM_GROUP + PIN_BASE + 16)
#define RK2928_PIN2_PC1 (2*NUM_GROUP + PIN_BASE + 17)
#define RK2928_PIN2_PC2 (2*NUM_GROUP + PIN_BASE + 18)
#define RK2928_PIN2_PC3 (2*NUM_GROUP + PIN_BASE + 19)
#define RK2928_PIN2_PC4 (2*NUM_GROUP + PIN_BASE + 20)
#define RK2928_PIN2_PC5 (2*NUM_GROUP + PIN_BASE + 21)
#define RK2928_PIN2_PC6 (2*NUM_GROUP + PIN_BASE + 22)
#define RK2928_PIN2_PC7 (2*NUM_GROUP + PIN_BASE + 23)
#define RK2928_PIN2_PD0 (2*NUM_GROUP + PIN_BASE + 24)
#define RK2928_PIN2_PD1 (2*NUM_GROUP + PIN_BASE + 25)
#define RK2928_PIN2_PD2 (2*NUM_GROUP + PIN_BASE + 26)
#define RK2928_PIN2_PD3 (2*NUM_GROUP + PIN_BASE + 27)
#define RK2928_PIN2_PD4 (2*NUM_GROUP + PIN_BASE + 28)
#define RK2928_PIN2_PD5 (2*NUM_GROUP + PIN_BASE + 29)
#define RK2928_PIN2_PD6 (2*NUM_GROUP + PIN_BASE + 30)
#define RK2928_PIN2_PD7 (2*NUM_GROUP + PIN_BASE + 31)
#define RK2928_PIN3_PA0 (3*NUM_GROUP + PIN_BASE + 0)
#define RK2928_PIN3_PA1 (3*NUM_GROUP + PIN_BASE + 1)
#define RK2928_PIN3_PA2 (3*NUM_GROUP + PIN_BASE + 2)
#define RK2928_PIN3_PA3 (3*NUM_GROUP + PIN_BASE + 3)
#define RK2928_PIN3_PA4 (3*NUM_GROUP + PIN_BASE + 4)
#define RK2928_PIN3_PA5 (3*NUM_GROUP + PIN_BASE + 5)
#define RK2928_PIN3_PA6 (3*NUM_GROUP + PIN_BASE + 6)
#define RK2928_PIN3_PA7 (3*NUM_GROUP + PIN_BASE + 7)
#define RK2928_PIN3_PB0 (3*NUM_GROUP + PIN_BASE + 8)
#define RK2928_PIN3_PB1 (3*NUM_GROUP + PIN_BASE + 9)
#define RK2928_PIN3_PB2 (3*NUM_GROUP + PIN_BASE + 10)
#define RK2928_PIN3_PB3 (3*NUM_GROUP + PIN_BASE + 11)
#define RK2928_PIN3_PB4 (3*NUM_GROUP + PIN_BASE + 12)
#define RK2928_PIN3_PB5 (3*NUM_GROUP + PIN_BASE + 13)
#define RK2928_PIN3_PB6 (3*NUM_GROUP + PIN_BASE + 14)
#define RK2928_PIN3_PB7 (3*NUM_GROUP + PIN_BASE + 15)
#define RK2928_PIN3_PC0 (3*NUM_GROUP + PIN_BASE + 16)
#define RK2928_PIN3_PC1 (3*NUM_GROUP + PIN_BASE + 17)
#define RK2928_PIN3_PC2 (3*NUM_GROUP + PIN_BASE + 18)
#define RK2928_PIN3_PC3 (3*NUM_GROUP + PIN_BASE + 19)
#define RK2928_PIN3_PC4 (3*NUM_GROUP + PIN_BASE + 20)
#define RK2928_PIN3_PC5 (3*NUM_GROUP + PIN_BASE + 21)
#define RK2928_PIN3_PC6 (3*NUM_GROUP + PIN_BASE + 22)
#define RK2928_PIN3_PC7 (3*NUM_GROUP + PIN_BASE + 23)
#define RK2928_PIN3_PD0 (3*NUM_GROUP + PIN_BASE + 24)
#define RK2928_PIN3_PD1 (3*NUM_GROUP + PIN_BASE + 25)
#define RK2928_PIN3_PD2 (3*NUM_GROUP + PIN_BASE + 26)
#define RK2928_PIN3_PD3 (3*NUM_GROUP + PIN_BASE + 27)
#define RK2928_PIN3_PD4 (3*NUM_GROUP + PIN_BASE + 28)
#define RK2928_PIN3_PD5 (3*NUM_GROUP + PIN_BASE + 29)
#define RK2928_PIN3_PD6 (3*NUM_GROUP + PIN_BASE + 30)
#define RK2928_PIN3_PD7 (3*NUM_GROUP + PIN_BASE + 31)
#if defined(CONFIG_SPI_FPGA_GPIO)
#define FPGA_PIO0_00 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 0)
#define FPGA_PIO0_01 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 1)
#define FPGA_PIO0_02 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 2)
#define FPGA_PIO0_03 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 3)
#define FPGA_PIO0_04 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 4)
#define FPGA_PIO0_05 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 5)
#define FPGA_PIO0_06 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 6)
#define FPGA_PIO0_07 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 7)
#define FPGA_PIO0_08 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 0)
#define FPGA_PIO0_09 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 1)
#define FPGA_PIO0_10 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 2)
#define FPGA_PIO0_11 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 3)
#define FPGA_PIO0_12 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 4)
#define FPGA_PIO0_13 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 5)
#define FPGA_PIO0_14 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 6)
#define FPGA_PIO0_15 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 7)
#define FPGA_PIO1_00 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 0)
#define FPGA_PIO1_01 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 1)
#define FPGA_PIO1_02 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 2)
#define FPGA_PIO1_03 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 3)
#define FPGA_PIO1_04 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 4)
#define FPGA_PIO1_05 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 5)
#define FPGA_PIO1_06 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 6)
#define FPGA_PIO1_07 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 7)
#define FPGA_PIO1_08 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 0)
#define FPGA_PIO1_09 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 1)
#define FPGA_PIO1_10 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 2)
#define FPGA_PIO1_11 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 3)
#define FPGA_PIO1_12 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 4)
#define FPGA_PIO1_13 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 5)
#define FPGA_PIO1_14 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 6)
#define FPGA_PIO1_15 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 7)
#define FPGA_PIO2_00 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 0)
#define FPGA_PIO2_01 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 1)
#define FPGA_PIO2_02 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 2)
#define FPGA_PIO2_03 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 3)
#define FPGA_PIO2_04 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 4)
#define FPGA_PIO2_05 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 5)
#define FPGA_PIO2_06 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 6)
#define FPGA_PIO2_07 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 7)
#define FPGA_PIO2_08 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 0)
#define FPGA_PIO2_09 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 1)
#define FPGA_PIO2_10 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 2)
#define FPGA_PIO2_11 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 3)
#define FPGA_PIO2_12 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 4)
#define FPGA_PIO2_13 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 5)
#define FPGA_PIO2_14 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 6)
#define FPGA_PIO2_15 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 7)
#define FPGA_PIO3_00 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 0)
#define FPGA_PIO3_01 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 1)
#define FPGA_PIO3_02 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 2)
#define FPGA_PIO3_03 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 3)
#define FPGA_PIO3_04 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 4)
#define FPGA_PIO3_05 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 5)
#define FPGA_PIO3_06 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 6)
#define FPGA_PIO3_07 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 7)
#define FPGA_PIO3_08 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 0)
#define FPGA_PIO3_09 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 1)
#define FPGA_PIO3_10 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 2)
#define FPGA_PIO3_11 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 3)
#define FPGA_PIO3_12 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 4)
#define FPGA_PIO3_13 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 5)
#define FPGA_PIO3_14 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 6)
#define FPGA_PIO3_15 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 7)
#define FPGA_PIO4_00 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 0)
#define FPGA_PIO4_01 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 1)
#define FPGA_PIO4_02 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 2)
#define FPGA_PIO4_03 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 3)
#define FPGA_PIO4_04 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 4)
#define FPGA_PIO4_05 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 5)
#define FPGA_PIO4_06 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 6)
#define FPGA_PIO4_07 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 7)
#define FPGA_PIO4_08 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 0)
#define FPGA_PIO4_09 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 1)
#define FPGA_PIO4_10 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 2)
#define FPGA_PIO4_11 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 3)
#define FPGA_PIO4_12 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 4)
#define FPGA_PIO4_13 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 5)
#define FPGA_PIO4_14 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 6)
#define FPGA_PIO4_15 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 7)
#define FPGA_PIO5_00 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 0)
#define FPGA_PIO5_01 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 1)
#define FPGA_PIO5_02 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 2)
#define FPGA_PIO5_03 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 3)
#define FPGA_PIO5_04 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 4)
#define FPGA_PIO5_05 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 5)
#define FPGA_PIO5_06 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 6)
#define FPGA_PIO5_07 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 7)
#define FPGA_PIO5_08 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 0)
#define FPGA_PIO5_09 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 1)
#define FPGA_PIO5_10 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 2)
#define FPGA_PIO5_11 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 3)
#define FPGA_PIO5_12 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 4)
#define FPGA_PIO5_13 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 5)
#define FPGA_PIO5_14 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 6)
#define FPGA_PIO5_15 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 7)
#endif
#if defined(CONFIG_IOEXTEND_TCA6424)
#define TCA6424_P00 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 0)
#define TCA6424_P01 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 1)
#define TCA6424_P02 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 2)
#define TCA6424_P03 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 3)
#define TCA6424_P04 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 4)
#define TCA6424_P05 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 5)
#define TCA6424_P06 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 6)
#define TCA6424_P07 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 7)
#define TCA6424_P10 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 0)
#define TCA6424_P11 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 1)
#define TCA6424_P12 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 2)
#define TCA6424_P13 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 3)
#define TCA6424_P14 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 4)
#define TCA6424_P15 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 5)
#define TCA6424_P16 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 6)
#define TCA6424_P17 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 7)
#define TCA6424_P20 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 0)
#define TCA6424_P21 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 1)
#define TCA6424_P22 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 2)
#define TCA6424_P23 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 3)
#define TCA6424_P24 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 4)
#define TCA6424_P25 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 5)
#define TCA6424_P26 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 6)
#define TCA6424_P27 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 7)
#endif
#if defined(CONFIG_GPIO_WM831X)
#define WM831X_P01 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 0)
#define WM831X_P02 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 1)
#define WM831X_P03 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 2)
#define WM831X_P04 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 3)
#define WM831X_P05 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 4)
#define WM831X_P06 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 5)
#define WM831X_P07 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 6)
#define WM831X_P08 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 7)
#define WM831X_P09 (WM831X_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 0)
#define WM831X_P10 (WM831X_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 1)
#define WM831X_P11 (WM831X_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 2)
#define WM831X_P12 (WM831X_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 3)
#endif
#include <plat/gpio.h>
#ifndef __ASSEMBLY__
extern void __init rk30_gpio_init(void);
static inline int gpio_to_irq(unsigned gpio)
{
return gpio - PIN_BASE + NR_GIC_IRQS;
}
static inline int irq_to_gpio(unsigned irq)
{
return irq - NR_GIC_IRQS + PIN_BASE;
}
#endif /* __ASSEMBLY__ */
#endif

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arch/arm/mach-rk2928/include/mach/hardware.h Normal file
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#ifndef __MACH_HARDWARE_H
#define __MACH_HARDWARE_H
#endif

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arch/arm/mach-rk2928/include/mach/io.h Normal file
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#ifndef __MACH_IO_H
#define __MACH_IO_H
#include <plat/io.h>
/*
* RK2928 IO memory map:
*
* Virt Phys Size What
* ---------------------------------------------------------------------------
* FEA00000 10000000 3M
* FED00000 20000000 1M
* FEF00000 0 8K SRAM
*/
#define RK2928_IO_TO_VIRT0(pa) IOMEM(pa + (0xFEA00000 - 0x10000000))
#define RK2928_IO_TO_VIRT1(pa) IOMEM(pa + (0xFED00000 - 0x20000000))
#define RK2928_IMEM_PHYS 0x10080000
#define RK2928_IMEM_BASE IOMEM(0xFEF00000)
#define RK2928_IMEM_NONCACHED RK2928_IO_TO_VIRT0(RK2928_IMEM_PHYS)
#define RK2928_IMEM_SIZE SZ_8K
#define RK2928_GPU_PHYS 0x10090000
#define RK2928_GPU_SIZE SZ_64K
#define RK2928_ROM_PHYS 0x10100000
#define RK2928_ROM_SIZE SZ_16K
#define RK2928_VCODEC_PHYS 0x10104000
#define RK2928_VCODEC_SIZE SZ_16K
#define RK2928_CIF_PHYS 0x1010a000
#define RK2928_CIF_SIZE SZ_8K
#define RK2928_RGA_PHYS 0x1010c000
#define RK2928_RGA_SIZE SZ_8K
#define RK2928_LCDC_PHYS 0x1010e000
#define RK2928_LCDC_SIZE SZ_8K
#define RK2928_CPU_AXI_BUS_PHYS 0x10128000
#define RK2928_CPU_AXI_BUS_BASE RK2928_IO_TO_VIRT0(RK2928_CPU_AXI_BUS_PHYS)
#define RK2928_CPU_AXI_BUS_SIZE SZ_32K
#define RK2928_L2C_PHYS 0x10138000
#define RK2928_L2C_BASE RK2928_IO_TO_VIRT0(RK2928_L2C_PHYS)
#define RK2928_L2C_SIZE SZ_16K
#define RK2928_SCU_PHYS 0x1013c000
#define RK2928_SCU_BASE RK2928_IO_TO_VIRT0(RK2928_SCU_PHYS)
#define RK2928_SCU_SIZE SZ_256
#define RK2928_GICC_PHYS 0x1013c100
#define RK2928_GICC_BASE RK2928_IO_TO_VIRT0(RK2928_GICC_PHYS)
#define RK2928_GICC_SIZE SZ_256
#define RK2928_GTIMER_PHYS 0x1013c200
#define RK2928_GTIMER_BASE RK2928_IO_TO_VIRT0(RK2928_GTIMER_PHYS)
#define RK2928_GTIMER_SIZE SZ_1K
#define RK2928_PTIMER_PHYS 0x1013c600
#define RK2928_PTIMER_BASE RK2928_IO_TO_VIRT0(RK2928_PTIMER_PHYS)
#define RK2928_PTIMER_SIZE (SZ_2K + SZ_512)
#define RK2928_GICD_PHYS 0x1013d000
#define RK2928_GICD_BASE RK2928_IO_TO_VIRT0(RK2928_GICD_PHYS)
#define RK2928_GICD_SIZE SZ_4K
#define RK2928_CORE_PHYS RK2928_L2C_PHYS
#define RK2928_CORE_BASE RK2928_IO_TO_VIRT0(RK2928_CORE_PHYS)
#define RK2928_CORE_SIZE (RK2928_L2C_SIZE + SZ_8K)
#define RK2928_USBOTG20_PHYS 0x10180000
#define RK2928_USBOTG20_SIZE SZ_256K
#define RK2928_USBHOST20_PHYS 0x101c0000
#define RK2928_USBHOST20_SIZE SZ_256K
#define RK2928_SDMMC_PHYS 0x10214000
#define RK2928_SDMMC_SIZE SZ_16K
#define RK2928_SDIO_PHYS 0x10218000
#define RK2928_SDIO_SIZE SZ_16K
#define RK2928_EMMC_PHYS 0x1021c000
#define RK2928_EMMC_SIZE SZ_16K
#define RK2928_I2S_PHYS 0x10220000
#define RK2928_I2S_SIZE SZ_8K
#define RK2928_AHB_ARB0_PHYS 0x10234000
#define RK2928_AHB_ARB0_SIZE SZ_32K
#define RK2928_AHB_ARB1_PHYS 0x1023C000
#define RK2928_AHB_ARB1_SIZE (784 * SZ_1K)
#define RK2928_PERI_AXI_BUS_PHYS 0x10300000
#define RK2928_PERI_AXI_BUS_SIZE SZ_1M
#define RK2928_GPS_PHYS 0x10400000
#define RK2928_GPS_SIZE SZ_1M
#define RK2928_NANDC_PHYS 0x10500000
#define RK2928_NANDC_SIZE SZ_16K
#define RK2928_CRU_PHYS 0x20000000
#define RK2928_CRU_BASE RK2928_IO_TO_VIRT1(RK2928_CRU_PHYS)
#define RK2928_CRU_SIZE SZ_4K
#define RK2928_DDR_PCTL_PHYS 0x20004000
#define RK2928_DDR_PCTL_BASE RK2928_IO_TO_VIRT1(RK2928_DDR_PCTL_PHYS)
#define RK2928_DDR_PCTL_SIZE SZ_16K
#define RK2928_GRF_PHYS 0x20008000
#define RK2928_GRF_BASE RK2928_IO_TO_VIRT1(RK2928_GRF_PHYS)
#define RK2928_GRF_SIZE SZ_4K
#define RK2928_DDR_PHY_PHYS 0x2000a000
#define RK2928_DDR_PHY_BASE RK2928_IO_TO_VIRT1(RK2928_DDR_PHY_PHYS)
#define RK2928_DDR_PHY_SIZE (SZ_16K + SZ_8K)
#define RK2928_DBG_PHYS 0x20020000
#define RK2928_DBG_SIZE SZ_64K
#define RK2928_ACODEC_PHYS 0x20030000
#define RK2928_ACODEC_SIZE SZ_16K
#define RK2928_HDMI_PHYS 0x20034000
#define RK2928_HDMI_SIZE SZ_16K
#define RK2928_TIMER0_PHYS 0x20044000
#define RK2928_TIMER0_BASE RK2928_IO_TO_VIRT1(RK2928_TIMER0_PHYS)
#define RK2928_TIMER0_SIZE SZ_4K
#define RK2928_TIMER1_PHYS 0x20046000
#define RK2928_TIMER1_BASE RK2928_IO_TO_VIRT1(RK2928_TIMER1_PHYS)
#define RK2928_TIMER1_SIZE SZ_4K
#define RK2928_WDT_PHYS 0x2004c000
#define RK2928_WDT_SIZE SZ_4K
#define RK2928_PWM_PHYS 0x20050000
#define RK2928_PWM_BASE RK2928_IO_TO_VIRT1(RK2928_PWM_PHYS)
#define RK2928_PWM_SIZE SZ_4K
#define RK2928_I2C1_PHYS 0x20054000
#define RK2928_I2C1_SIZE SZ_4K
#define RK2928_RKI2C1_PHYS 0x20056000
#define RK2928_RKI2C1_SIZE SZ_4K
#define RK2928_I2C2_PHYS 0x20058000
#define RK2928_I2C2_SIZE SZ_4K
#define RK2928_RKI2C2_PHYS 0x2005a000
#define RK2928_RKI2C2_SIZE SZ_4K
#define RK2928_I2C3_PHYS 0x2005c000
#define RK2928_I2C3_SIZE SZ_4K
#define RK2928_RKI2C3_PHYS 0x2005e000
#define RK2928_RKI2C3_SIZE SZ_4K
#define RK2928_UART0_PHYS 0x20060000
#define RK2928_UART0_BASE RK2928_IO_TO_VIRT1(RK2928_UART0_PHYS)
#define RK2928_UART0_SIZE SZ_4K
#define RK2928_UART1_PHYS 0x20064000
#define RK2928_UART1_BASE RK2928_IO_TO_VIRT1(RK2928_UART1_PHYS)
#define RK2928_UART1_SIZE SZ_4K
#define RK2928_UART2_PHYS 0x20068000
#define RK2928_UART2_BASE RK2928_IO_TO_VIRT1(RK2928_UART2_PHYS)
#define RK2928_UART2_SIZE SZ_4K
#define RK2928_SARADC_PHYS 0x2006c000
#define RK2928_SARADC_SIZE SZ_4K
#define RK2928_I2C0_PHYS 0x20070000
#define RK2928_I2C0_SIZE SZ_4K
#define RK2928_RKI2C0_PHYS 0x20072000
#define RK2928_RKI2C0_SIZE SZ_4K
#define RK2928_SPI_PHYS 0x20074000
#define RK2928_SPI_SIZE SZ_16K
#define RK2928_DMAC_PHYS 0x20078000
#define RK2928_DMAC_SIZE SZ_16K
#define RK2928_GPIO0_PHYS 0x2007c000
#define RK2928_GPIO0_BASE RK2928_IO_TO_VIRT1(RK2928_GPIO0_PHYS)
#define RK2928_GPIO0_SIZE SZ_4K
#define RK2928_GPIO1_PHYS 0x20080000
#define RK2928_GPIO1_BASE RK2928_IO_TO_VIRT1(RK2928_GPIO1_PHYS)
#define RK2928_GPIO1_SIZE SZ_4K
#define RK2928_GPIO2_PHYS 0x20084000
#define RK2928_GPIO2_BASE RK2928_IO_TO_VIRT1(RK2928_GPIO2_PHYS)
#define RK2928_GPIO2_SIZE SZ_4K
#define RK2928_GPIO3_PHYS 0x20088000
#define RK2928_GPIO3_BASE RK2928_IO_TO_VIRT1(RK2928_GPIO3_PHYS)
#define RK2928_GPIO3_SIZE SZ_4K
#define RK2928_EFUSE_PHYS 0x20090000
#define RK2928_EFUSE_SIZE SZ_4K
#if CONFIG_RK_DEBUG_UART == 0
#define DEBUG_UART_PHYS RK2928_UART0_PHYS
#define DEBUG_UART_BASE RK2928_UART0_BASE
#elif CONFIG_RK_DEBUG_UART == 1
#define DEBUG_UART_PHYS RK2928_UART1_PHYS
#define DEBUG_UART_BASE RK2928_UART1_BASE
#elif CONFIG_RK_DEBUG_UART == 2
#define DEBUG_UART_PHYS RK2928_UART2_PHYS
#define DEBUG_UART_BASE RK2928_UART2_BASE
#endif
#define GIC_DIST_BASE RK2928_GICD_BASE
#define GIC_CPU_BASE RK2928_GICC_BASE
#endif

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arch/arm/mach-rk2928/include/mach/iomux.h Executable file
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/*
* arch/arm/mach-rk2928/include/mach/iomux.h
*
*Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __RK2928_IOMUX_H__
#define __RK2928_IOMUX_H__
#include <linux/init.h>
//gpio0a
#define GPIO0A_GPIO0A0 0
#define GPIO0A_I2C0_SCL 1
#define GPIO0A_GPIO0A1 0
#define GPIO0A_I2C0_SDA 1
#define GPIO0A_GPIO0A2 0
#define GPIO0A_I2C1_SCL 1
#define GPIO0A_GPIO0A3 0
#define GPIO0A_I2C1_SDA 1
#define GPIO0A_GPIO0A6 0
#define GPIO0A_I2C3_SCL 1
#define GPIO0A_HDMI_DDCSCL 2
#define GPIO0A_GPIO0A7 0
#define GPIO0A_I2C3_SDA 1
#define GPIO0A_HDMI_DDCSDA 2
//gpio0b
#define GPIO0B_GPIO0B0 0
#define GPIO0B_MMC1_CMD 1
#define GPIO0B_GPIO0B1 0
#define GPIO0B_MMC1_CLKOUT 1
#define GPIO0B_GPIO0B2 0
#define GPIO0B_MMC1_DETN 1
#define GPIO0B_GPIO0B3 0
#define GPIO0B_MMC1_D0 1
#define GPIO0B_GPIO0B4 0
#define GPIO0B_MMC1_D1 1
#define GPIO0B_GPIO0B5 0
#define GPIO0B_MMC1_D2 1
#define GPIO0B_GPIO0B6 0
#define GPIO0B_MMC1_D3 1
#define GPIO0B_GPIO0B7 0
#define GPIO0B_HDMI_HOTPLUGIN 1
//gpio0c
#define GPIO0C_GPIO0C0 0
#define GPIO0C_UART0_SOUT 1
#define GPIO0C_GPIO0C1 0
#define GPIO0C_UART0_SIN 1
#define GPIO0C_GPIO0C2 0
#define GPIO0C_UART0_RTSN 1
#define GPIO0C_GPIO0C3 0
#define GPIO0C_UART0_CTSN 1
#define GPIO0C_GPIO0C4 0
#define GPIO0C_HDMI_CECSDA 1
#define GPIO0C_GPIO0C7 0
#define GPIO0C_NAND_CS1 1
//gpio0d
#define GPIO0D_GPIO0D0 0
#define GPIO0D_UART2_RTSN 1
#define GPIO0D_GPIO0D1 0
#define GPIO0D_UART2_CTSN 1
#define GPIO0D_GPIO0D2 0
#define GPIO0D_PWM_0 1
#define GPIO0D_GPIO0D3 0
#define GPIO0D_PWM_1 1
#define GPIO0D_GPIO0D4 0
#define GPIO0D_PWM_2 1
#define GPIO0D_GPIO0D5 0
#define GPIO0D_MMC1_WRPRT 1
#define GPIO0D_GPIO0D6 0
#define GPIO0D_MMC1_PWREN 1
#define GPIO0D_GPIO0D7 0
#define GPIO0D_MMC1_BKEPWR 1
//gpio1a
#define GPIO1A_GPIO1A0 0
#define GPIO1A_I2S_MCLK 1
#define GPIO1A_GPIO1A1 0
#define GPIO1A_I2S_SCLK 1
#define GPIO1A_GPIO1A2 0
#define GPIO1A_I2S_LRCKRX 1
#define GPIO1A_GPS_CLK 2
#define GPIO1A_GPIO1A3 0
#define GPIO1A_I2S_LRCKTX 1
#define GPIO1A_GPIO1A4 0
#define GPIO1A_I2S_SDO 1
#define GPIO1A_GPS_MAG 2
#define GPIO1A_GPIO1A5 0
#define GPIO1A_I2S_SDI 1
#define GPIO1A_GPS_SIGN 2
#define GPIO1A_GPIO1A6 0
#define GPIO1A_MMC1_INTN 1
#define GPIO1A_GPIO1A7 0
#define GPIO1A_MMC0_WRPRT 1
//gpio1b
#define GPIO1B_GPIO1B0 0
#define GPIO1B_SPI_CLK 1
#define GPIO1B_UART1_CTSN 2
#define GPIO1B_GPIO1B1 0
#define GPIO1B_SPI_TXD 1
#define GPIO1B_UART1_SOUT 2
#define GPIO1B_GPIO1B2 0
#define GPIO1B_SPI_RXD 1
#define GPIO1B_UART1_SIN 2
#define GPIO1B_GPIO1B3 0
#define GPIO1B_SPI_CSN0 1
#define GPIO1B_UART1_RTSN 2
#define GPIO1B_GPIO1B4 0
#define GPIO1B_SPI_CSN1 1
#define GPIO1B_GPIO1B5 0
#define GPIO1B_MMC0_RSTNOUT 1
#define GPIO1B_GPIO1B6 0
#define GPIO1B_MMC0_PWREN 1
#define GPIO1B_GPIO1B7 0
#define GPIO1B_MMC0_CMD 1
//gpio1c
#define GPIO1C_GPIO1C0 0
#define GPIO1C_MMC0_CLKOUT 1
#define GPIO1C_GPIO1C1 0
#define GPIO1C_MMC0_DETN 1
#define GPIO1C_GPIO1C2 0
#define GPIO1C_MMC0_D0 1
#define GPIO1C_GPIO1C3 0
#define GPIO1C_MMC0_D1 1
#define GPIO1C_GPIO1C4 0
#define GPIO1C_MMC0_D2 1
#define GPIO1C_GPIO1C5 0
#define GPIO1C_MMC0_D3 1
#define GPIO1C_GPIO1C6 0
#define GPIO1C_NAND_CS2 1
#define GPIO1C_EMMC_CMD 2
#define GPIO1C_GPIO1C7 0
#define GPIO1C_NAND_CS3 1
#define GPIO1C_EMMC_RSTNOUT 2
//gpio1d
#define GPIO1D_GPIO1D0 0
#define GPIO1D_NAND_D0 1
#define GPIO1D_EMMC_D0 2
#define GPIO1D_GPIO1D1 0
#define GPIO1D_NAND_D1 1
#define GPIO1D_EMMC_D1 2
#define GPIO1D_GPIO1D2 0
#define GPIO1D_NAND_D2 1
#define GPIO1D_EMMC_D2 2
#define GPIO1D_GPIO1D3 0
#define GPIO1D_NAND_D3 1
#define GPIO1D_EMMC_D3 2
#define GPIO1D_GPIO1D4 0
#define GPIO1D_NAND_D4 1
#define GPIO1D_EMMC_D4 2
#define GPIO1D_GPIO1D5 0
#define GPIO1D_NAND_D5 1
#define GPIO1D_EMMC_D5 2
#define GPIO1D_GPIO1D6 0
#define GPIO1D_NAND_D6 1
#define GPIO1D_EMMC_D6 2
#define GPIO1D_GPIO1D7 0
#define GPIO1D_NAND_D7 1
#define GPIO1D_EMMC_D7 2
//gpio2a
#define GPIO2A_GPIO2A0 0
#define GPIO2A_NAND_ALE 1
#define GPIO2A_GPIO2A1 0
#define GPIO2A_NAND_CLE 1
#define GPIO2A_GPIO2A2 0
#define GPIO2A_NAND_WRN 1
#define GPIO2A_GPIO2A3 0
#define GPIO2A_NAND_RDN 1
#define GPIO2A_GPIO2A4 0
#define GPIO2A_NAND_RDY 1
#define GPIO2A_GPIO2A5 0
#define GPIO2A_NAND_WP 1
#define GPIO2A_EMMC_PWREN 2
#define GPIO2A_GPIO2A6 0
#define GPIO2A_NAND_CS0 1
#define GPIO2A_GPIO2A7 0
#define GPIO2A_NAND_DPS 1
#define GPIO2A_EMMC_CLKOUT 2
//gpio2b
#define GPIO2B_GPIO2B0 0
#define GPIO2B_LCDC0_DCLK 1
#define GPIO2B_LCDC1_DCLK 2
#define GPIO2B_GPIO2B1 0
#define GPIO2B_LCDC0_HSYNC 1
#define GPIO2B_LCDC1_HSYNC 2
#define GPIO2B_GPIO2B2 0
#define GPIO2B_LCDC0_VSYNC 1
#define GPIO2B_LCDC1_VSYNC 2
#define GPIO2B_GPIO2B3 0
#define GPIO2B_LCDC0_DEN 1
#define GPIO2B_LCDC1_DEN 2
#define GPIO2B_GPIO2B4 0
#define GPIO2B_LCDC0_D10 1
#define GPIO2B_LCDC1_D10 2
#define GPIO2B_GPIO2B5 0
#define GPIO2B_LCDC0_D11 1
#define GPIO2B_LCDC1_D11 2
#define GPIO2B_GPIO2B6 0
#define GPIO2B_LCDC0_D12 1
#define GPIO2B_LCDC1_D12 2
#define GPIO2B_GPIO2B7 0
#define GPIO2B_LCDC0_D13 1
#define GPIO2B_LCDC1_D13 2
//gpio2c
#define GPIO2C_GPIO2C0 0
#define GPIO2C_LCDC0_D14 1
#define GPIO2C_LCDC1_D14 2
#define GPIO2C_GPIO2C1 0
#define GPIO2C_LCDC0_D15 1
#define GPIO2C_LCDC1_D15 2
#define GPIO2C_GPIO2C2 0
#define GPIO2C_LCDC0_D16 1
#define GPIO2C_LCDC1_D16 2
#define GPIO2C_GPIO2C3 0
#define GPIO2C_LCDC0_D17 1
#define GPIO2C_LCDC1_D17 2
#define GPIO2C_GPIO2C4 0
#define GPIO2C_LCDC0_D18 1
#define GPIO2C_LCDC1_D18 2
#define GPIO2C_I2C2_SDA 3
#define GPIO2C_GPIO2C5 0
#define GPIO2C_LCDC0_D19 1
#define GPIO2C_LCDC1_D19 2
#define GPIO2C_I2C2_SCL 3
#define GPIO2C_GPIO2C6 0
#define GPIO2C_LCDC0_D20 1
#define GPIO2C_LCDC1_D20 2
#define GPIO2C_UART2_SIN 3
#define GPIO2C_GPIO2C7 0
#define GPIO2C_LCDC0_D21 1
#define GPIO2C_LCDC1_D21 2
#define GPIO2C_UART2_SOUT 3
//gpio2d
#define GPIO2D_GPIO2D0 0
#define GPIO2D_LCDC0_D22 1
#define GPIO2D_LCDC1_D22 2
#define GPIO2D_GPIO2D1 0
#define GPIO2D_LCDC0_D23 1
#define GPIO2D_LCDC1_D23 2
//gpio3c
#define GPIO3C_GPIO3C1 0
#define GPIO3C_OTG_DRVVBUS 1
//gpio3d
#define GPIO3D_GPIO3D7 0
#define GPIO3D_TESTCLK_OUT 1
//gpio0a
#define GPIO0A0_I2C0_SCL_NAME "gpio0a0_i2c0_scl_name"
#define GPIO0A1_I2C0_SDA_NAME "gpio0a1_i2c0_sda_name"
#define GPIO0A2_I2C1_SCL_NAME "gpio0a2_i2c1_scl_name"
#define GPIO0A3_I2C1_SDA_NAME "gpio0a3_i2c1_sda_name"
#define GPIO0A6_I2C3_SCL_HDMI_DDCSCL_NAME "gpio0a6_i2c3_scl_hdmi_ddcscl_name"
#define GPIO0A7_I2C3_SDA_HDMI_DDCSDA_NAME "gpio0a7_i2c3_sda_hdmi_ddcsda_name"
//gpio0b
#define GPIO0B0_MMC1_CMD_NAME "gpio0b0_mmc1_cmd_name"
#define GPIO0B1_MMC1_CLKOUT_NAME "gpio0b1_mmc1_clkout_name"
#define GPIO0B2_MMC1_DETN_NAME "gpio0b2_mmc1_detn_name"
#define GPIO0B3_MMC1_D0_NAME "gpio0b3_mmc1_d0_name"
#define GPIO0B4_MMC1_D1_NAME "gpio0b4_mmc1_d1_name"
#define GPIO0B5_MMC1_D2_NAME "gpio0b5_mmc1_d2_name"
#define GPIO0B6_MMC1_D3_NAME "gpio0b6_mmc1_d3_name"
#define GPIO0B7_HDMI_HOTPLUGIN_NAME "gpio0b7_hdmi_hotplugin_name"
//gpio0c
#define GPIO0C0_UART0_SOUT_NAME "gpio0c0_uart0_sout_name"
#define GPIO0C1_UART0_SIN_NAME "gpio0c1_uart0_sin_name"
#define GPIO0C2_UART0_RTSN_NAME "gpio0c2_uart0_rtsn_name"
#define GPIO0C3_UART0_CTSN_NAME "gpio0c3_uart0_ctsn_name"
#define GPIO0C4_HDMI_CECSDA_NAME "gpio0c4_hdmi_cecsda_name"
#define GPIO0C7_NAND_CS1_NAME "gpio0c7_nand_cs1_name"
//gpio0d
#define GPIO0D0_UART2_RTSN_NAME "gpio0d0_uart2_rtsn_name"
#define GPIO0D1_UART2_CTSN_NAME "gpio0d1_uart2_ctsn_name"
#define GPIO0D2_PWM_0_NAME "gpio0d2_pwm_0_name"
#define GPIO0D3_PWM_1_NAME "gpio0d3_pwm_1_name"
#define GPIO0D4_PWM_2_NAME "gpio0d4_pwm_2_name"
#define GPIO0D5_MMC1_WRPRT_NAME "gpio0d5_mmc1_wrprt_name"
#define GPIO0D6_MMC1_PWREN_NAME "gpio0d6_mmc1_pwren_name"
#define GPIO0D7_MMC1_BKEPWR_NAME "gpio0d7_mmc1_bkepwr_name"
//gpio1a
#define GPIO1A0_I2S_MCLK_NAME "gpio1a0_i2s_mclk_name"
#define GPIO1A1_I2S_SCLK_NAME "gpio1a1_i2s_sclk_name"
#define GPIO1A2_I2S_LRCKRX_GPS_CLK_NAME "gpio1a2_i2s_lrckrx_gps_clk_name"
#define GPIO1A3_I2S_LRCKTX_NAME "gpio1a3_i2s_lrcktx_name"
#define GPIO1A4_I2S_SDO_GPS_MAG_NAME "gpio1a4_i2s_sdo_gps_mag_name"
#define GPIO1A5_I2S_SDI_GPS_SIGN_NAME "gpio1a5_i2s_sdi_gps_sign_name"
#define GPIO1A6_MMC1_INTN_NAME "gpio1a6_mmc1_intn_name"
#define GPIO1A7_MMC0_WRPRT_NAME "gpio1a7_mmc0_wrprt_name"
//gpio1b
#define GPIO1B0_SPI_CLK_UART1_CTSN_NAME "gpio1b0_spi_clk_uart1_ctsn_name"
#define GPIO1B1_SPI_TXD_UART1_SOUT_NAME "gpio1b1_spi_txd_uart1_sout_name"
#define GPIO1B2_SPI_RXD_UART1_SIN_NAME "gpio1b2_spi_rxd_uart1_sin_name"
#define GPIO1B3_SPI_CSN0_UART1_RTSN_NAME "gpio1b3_spi_csn0_uart1_rtsn_name"
#define GPIO1B4_SPI_CSN1_NAME "gpio1b4_spi_csn1_name"
#define GPIO1B5_MMC0_RSTNOUT_NAME "gpio1b5_mmc0_rstnout_name"
#define GPIO1B6_MMC0_PWREN_NAME "gpio1b6_mmc0_pwren_name"
#define GPIO1B7_MMC0_CMD_NAME "gpio1b7_mmc0_cmd_name"
//gpio1c
#define GPIO1C0_MMC0_CLKOUT_NAME "gpio1c0_mmc0_clkout_name"
#define GPIO1C1_MMC0_DETN_NAME "gpio1c1_mmc0_detn_name"
#define GPIO1C2_MMC0_D0_NAME "gpio1c2_mmc0_d0_name"
#define GPIO1C3_MMC0_D1_NAME "gpio1c3_mmc0_d1_name"
#define GPIO1C4_MMC0_D2_NAME "gpio1c4_mmc0_d2_name"
#define GPIO1C5_MMC0_D3_NAME "gpio1c5_mmc0_d3_name"
#define GPIO1C6_NAND_CS2_EMMC_CMD_NAME "gpio1c6_nand_cs2_emmc_cmd_name"
#define GPIO1C7_NAND_CS3_EMMC_RSTNOUT_NAME "gpio1c7_nand_cs3_emmc_rstnout_name"
//gpio1d
#define GPIO1D0_NAND_D0_EMMC_D0_NAME "gpio1d0_nand_d0_emmc_d0_name"
#define GPIO1D1_NAND_D1_EMMC_D1_NAME "gpio1d1_nand_d1_emmc_d1_name"
#define GPIO1D2_NAND_D2_EMMC_D2_NAME "gpio1d2_nand_d2_emmc_d2_name"
#define GPIO1D3_NAND_D3_EMMC_D3_NAME "gpio1d3_nand_d3_emmc_d3_name"
#define GPIO1D4_NAND_D4_EMMC_D4_NAME "gpio1d4_nand_d4_emmc_d4_name"
#define GPIO1D5_NAND_D5_EMMC_D5_NAME "gpio1d5_nand_d5_emmc_d5_name"
#define GPIO1D6_NAND_D6_EMMC_D6_NAME "gpio1d6_nand_d6_emmc_d6_name"
#define GPIO1D7_NAND_D7_EMMC_D7_NAME "gpio1d7_nand_d7_emmc_d7_name"
//gpio2a
#define GPIO2A0_NAND_ALE_NAME "gpio2a0_nand_ale_name"
#define GPIO2A1_NAND_CLE_NAME "gpio2a1_nand_cle_name"
#define GPIO2A2_NAND_WRN_NAME "gpio2a2_nand_wrn_name"
#define GPIO2A3_NAND_RDN_NAME "gpio2a3_nand_rdn_name"
#define GPIO2A4_NAND_RDY_NAME "gpio2a4_nand_rdy_name"
#define GPIO2A5_NAND_WP_EMMC_PWREN_NAME "gpio2a5_nand_wp_emmc_pwren_name"
#define GPIO2A6_NAND_CS0_NAME "gpio2a6_nand_cs0_name"
#define GPIO2A7_NAND_DPS_EMMC_CLKOUT_NAME "gpio2a7_nand_dps_emmc_clkout_name"
//gpio2b
#define GPIO2B0_LCDC0_DCLK_LCDC1_DCLK_NAME "gpio2b0_lcdc0_dclk_lcdc1_dclk_name"
#define GPIO2B1_LCDC0_HSYNC_LCDC1_HSYNC_NAME "gpio2b1_lcdc0_hsync_lcdc1_hsync_name"
#define GPIO2B2_LCDC0_VSYNC_LCDC1_VSYNC_NAME "gpio2b2_lcdc0_vsync_lcdc1_vsync_name"
#define GPIO2B3_LCDC0_DEN_LCDC1_DEN_NAME "gpio2b3_lcdc0_den_lcdc1_den_name"
#define GPIO2B4_LCDC0_D10_LCDC1_D10_NAME "gpio2b4_lcdc0_d10_lcdc1_d10_name"
#define GPIO2B5_LCDC0_D11_LCDC1_D11_NAME "gpio2b5_lcdc0_d11_lcdc1_d11_name"
#define GPIO2B6_LCDC0_D12_LCDC1_D12_NAME "gpio2b6_lcdc0_d12_lcdc1_d12_name"
#define GPIO2B7_LCDC0_D13_LCDC1_D13_NAME "gpio2b7_lcdc0_d13_lcdc1_d13_name"
//gpio2c
#define GPIO2C0_LCDC0_D14_LCDC1_D14_NAME "gpio2c0_lcdc0_d14_lcdc1_d14_name"
#define GPIO2C1_LCDC0_D15_LCDC1_D15_NAME "gpio2c1_lcdc0_d15_lcdc1_d15_name"
#define GPIO2C2_LCDC0_D16_LCDC1_D16_NAME "gpio2c2_lcdc0_d16_lcdc1_d16_name"
#define GPIO2C3_LCDC0_D17_LCDC1_D17_NAME "gpio2c3_lcdc0_d17_lcdc1_d17_name"
#define GPIO2C4_LCDC0_D18_LCDC1_D18_I2C2_SDA_NAME "gpio2c4_lcdc0_d18_lcdc1_d18_i2c2_sda_name"
#define GPIO2C5_LCDC0_D19_LCDC1_D19_I2C2_SCL_NAME "gpio2c5_lcdc0_d19_lcdc1_d19_i2c2_scl_name"
#define GPIO2C6_LCDC0_D20_LCDC1_D20_UART2_SIN_NAME "gpio2c6_lcdc0_d20_lcdc1_d20_uart2_sin_name"
#define GPIO2C7_LCDC0_D21_LCDC1_D21_UART2_SOUT_NAME "gpio2c7_lcdc0_d21_lcdc1_d21_uart2_sout_name"
//gpio2d
#define GPIO2D0_LCDC0_D22_LCDC1_D22_NAME "gpio2d0_lcdc0_d22_lcdc1_d22_name"
#define GPIO2D1_LCDC0_D23_LCDC1_D23_NAME "gpio2d1_lcdc0_d23_lcdc1_d23_name"
//gpio3c
#define GPIO3C1_OTG_DRVVBUS_NAME "gpio3c1_otg_drvvbus_name"
//gpio3d
#define GPIO3D7_TESTCLK_OUT_NAME "gpio3d7_testclk_out_name"
#define DEFAULT 0
#define INITIAL 1
#define GRF_GPIO0A_IOMUX RK2928_GRF_BASE+0x00a8
#define GRF_GPIO0B_IOMUX RK2928_GRF_BASE+0x00ac
#define GRF_GPIO0C_IOMUX RK2928_GRF_BASE+0x00b0
#define GRF_GPIO0D_IOMUX RK2928_GRF_BASE+0x00b4
#define GRF_GPIO1A_IOMUX RK2928_GRF_BASE+0x00b8
#define GRF_GPIO1B_IOMUX RK2928_GRF_BASE+0x00bc
#define GRF_GPIO1C_IOMUX RK2928_GRF_BASE+0x00c0
#define GRF_GPIO1D_IOMUX RK2928_GRF_BASE+0x00c4
#define GRF_GPIO2A_IOMUX RK2928_GRF_BASE+0x00c8
#define GRF_GPIO2B_IOMUX RK2928_GRF_BASE+0x00cc
#define GRF_GPIO2C_IOMUX RK2928_GRF_BASE+0x00d0
#define GRF_GPIO2D_IOMUX RK2928_GRF_BASE+0x00d4
#define GRF_GPIO3C_IOMUX RK2928_GRF_BASE+0x00e0
#define GRF_GPIO3D_IOMUX RK2928_GRF_BASE+0x00e4
#define GRF_GPIO0L_PULL 0x0118
#define GRF_GPIO0H_PULL 0x011c
#define GRF_GPIO1L_PULL 0x0120
#define GRF_GPIO1H_PULL 0x0124
#define GRF_GPIO2L_PULL 0x0128
#define GRF_GPIO2H_PULL 0x012c
#define GRF_GPIO3L_PULL 0x0130
#define GRF_GPIO3H_PULL 0x0134
#define GRF_SOC_CON0 0x0140
#define GRF_SOC_CON1 0x0144
#define GRF_SOC_CON2 0x0148
#define GRF_SOC_STATUS0 0x014c
#define GRF_LVDS_CON0 0x0150
#define GRF_DMAC1_CON0 0x015c
#define GRF_DMAC1_CON1 0x0160
#define GRF_DMAC1_CON2 0x0164
#define GRF_UOC0_CON0 0x016c
#define GRF_UOC0_CON1 0x0170
#define GRF_UOC0_CON2 0x0174
#define GRF_UOC0_CON3 0x0178
#define GRF_UOC0_CON5 0x017c
#define GRF_UOC1_CON0 0x0180
#define GRF_UOC1_CON1 0x0184
#define GRF_UOC1_CON2 0x0188
#define GRF_UOC1_CON3 0x018c
#define GRF_UOC1_CON4 0x0190
#define GRF_UOC1_CON5 0x0194
#define GRF_DDRC_STAT 0x019c
#define GRF_OS_REG0 0x01c8
#define GRF_OS_REG1 0x01cc
#define GRF_OS_REG2 0x01d0
#define GRF_OS_REG3 0x01d4
#define GRF_OS_REG4 0x01d8
#define GRF_OS_REG5 0x01dc
#define GRF_OS_REG6 0x01e0
#define GRF_OS_REG7 0x01e4
#define MUX_CFG(desc,reg,off,interl,mux_mode,bflags) \
{ \
.name = desc, \
.offset = off, \
.interleave = interl, \
.mux_reg = GRF_##reg##_IOMUX, \
.mode = mux_mode, \
.premode = mux_mode, \
.flags = bflags, \
},
struct mux_config {
char *name;
const unsigned int offset;
unsigned int mode;
unsigned int premode;
const void* __iomem mux_reg;
const unsigned int interleave;
unsigned int flags;
};
#define rk29_mux_api_set rk30_mux_api_set
extern int __init rk30_iomux_init(void);
extern void rk30_mux_api_set(char *name, unsigned int mode);
extern int rk30_mux_api_get(char *name);
#endif

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arch/arm/mach-rk2928/include/mach/irqs.h Normal file
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#ifndef __MACH_IRQS_H
#define __MACH_IRQS_H
#define FIQ_START 0
#define IRQ_LOCALTIMER 29
#define IRQ_DMAC_0 32
#define IRQ_DMAC_1 33
#define IRQ_DDR_PCTL 34
#define IRQ_GPU_GP 35
#define IRQ_GPU_MMU 36
#define IRQ_GPU_PP 37
#define IRQ_VEPU 38
#define IRQ_VDPU 39
#define IRQ_CIF 40
#define IRQ_LCDC 41
#define IRQ_USB_OTG 42
#define IRQ_USB_HOST 43
#define IRQ_GPS 44
#define IRQ_GPS_TIMER 45
#define IRQ_SDMMC 46
#define IRQ_SDIO 47
#define IRQ_EMMC 48
#define IRQ_SARADC 49
#define IRQ_NANDC 50
#define IRQ_I2S 51
#define IRQ_UART0 52
#define IRQ_UART1 53
#define IRQ_UART2 54
#define IRQ_SPI 55
#define IRQ_I2C0 56
#define IRQ_I2C1 57
#define IRQ_I2C2 58
#define IRQ_I2C3 59
#define IRQ_TIMER0 60
#define IRQ_TIMER1 61
#define IRQ_PWM0 62
#define IRQ_PWM1 63
#define IRQ_PWM2 64
#define IRQ_WDT 66
#define IRQ_OTG_BVALID 67
#define IRQ_GPIO0 68
#define IRQ_GPIO1 69
#define IRQ_GPIO2 70
#define IRQ_GPIO3 71
#define IRQ_PERI_AHB_USB_ARBITER 74
#define IRQ_PERI_AHB_EMEM_ARBITER 75
#define IRQ_RGA 76
#define IRQ_HDMI 77
#define IRQ_SDMMC_DETECT 78
#define IRQ_SDIO_DETECT 79
#define IRQ_ARM_PMU 118
//hhb@rock-chips.com this spi is used for fiq_debugger signal irq
#define IRQ_UART_SIGNAL 127
#if CONFIG_RK_DEBUG_UART >= 0 && CONFIG_RK_DEBUG_UART < 3
#define IRQ_DEBUG_UART (IRQ_UART0 + CONFIG_RK_DEBUG_UART)
#endif
#define NR_GIC_IRQS (4 * 32)
#define NR_GPIO_IRQS (4 * 32)
#define NR_BOARD_IRQS 64
#define NR_IRQS (NR_GIC_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
#endif

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#include <plat/loader.h>

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arch/arm/mach-rk2928/include/mach/memory.h Normal file
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#ifndef __MACH_MEMORY_H
#define __MACH_MEMORY_H
#include <plat/memory.h>
#include <mach/io.h>
/*
* SRAM memory whereabouts
*/
#define SRAM_CODE_OFFSET (RK2928_IMEM_BASE + 0x0000)
#define SRAM_CODE_END (RK2928_IMEM_BASE + 0x0FFF)
#define SRAM_DATA_OFFSET (RK2928_IMEM_BASE + 0x1000)
#define SRAM_DATA_END (RK2928_IMEM_BASE + 0x1FFF)
#endif

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#ifndef __MACH_PMU_H
#define __MACH_PMU_H
enum pmu_power_domain {
PD_A9_0 = 0,
PD_A9_1,
PD_ALIVE,
PD_RTC,
PD_SCU,
PD_CPU,
PD_PERI = 6,
PD_VIO,
PD_VIDEO,
PD_VCODEC = PD_VIDEO,
PD_GPU,
PD_DBG,
};
static inline bool pmu_power_domain_is_on(enum pmu_power_domain pd)
{
return true;
}
static inline void pmu_set_power_domain(enum pmu_power_domain pd, bool on)
{
}
enum pmu_idle_req {
IDLE_REQ_CPU = 0,
IDLE_REQ_PERI,
IDLE_REQ_GPU,
IDLE_REQ_VIDEO,
IDLE_REQ_VIO,
};
static inline void pmu_set_idle_request(enum pmu_idle_req req, bool idle)
{
}
#endif

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arch/arm/mach-rk2928/include/mach/rk2928_camera.h Normal file
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/* camera driver header file
Copyright (C) 2003, Intel Corporation
Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_ARCH_CAMERA_RK2928_H_
#define __ASM_ARCH_CAMERA_RK2928_H_
#define RK29_CAM_DRV_NAME "rk-camera-rk2928"
#define RK_SUPPORT_CIF0 1
#define RK_SUPPORT_CIF1 0
#include <plat/rk_camera.h>
#define CONFIG_CAMERA_SCALE_CROP_MACHINE RK_CAM_SCALE_CROP_ARM
#if (CONFIG_CAMERA_SCALE_CROP_MACHINE==RK_CAM_SCALE_CROP_ARM)
#define CAMERA_SCALE_CROP_MACHINE "arm"
#elif (CONFIG_CAMERA_SCALE_CROP_MACHINE==RK_CAM_SCALE_CROP_IPP)
#define CAMERA_SCALE_CROP_MACHINE "ipp"
#elif (CONFIG_CAMERA_SCALE_CROP_MACHINE==RK_CAM_SCALE_CROP_RGA)
#define CAMERA_SCALE_CROP_MACHINE "rga"
#elif (CONFIG_CAMERA_SCALE_CROP_MACHINE==RK_CAM_SCALE_CROP_PP)
#define CAMERA_SCALE_CROP_MACHINE "pp"
#endif
#if (CONFIG_CAMERA_SCALE_CROP_MACHINE == RK_CAM_SCALE_CROP_ARM)
#define CAMERA_VIDEOBUF_ARM_ACCESS 1
#else
#define CAMERA_VIDEOBUF_ARM_ACCESS 0
#endif
#endif

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#ifndef __MACH_SRAM_H
#define __MACH_SRAM_H
#include <plat/sram.h>
#define SRAM_LOOPS_PER_USEC 24
#define SRAM_LOOP(loops) do { unsigned int i = (loops); if (i < 7) i = 7; barrier(); asm volatile(".align 4; 1: subs %0, %0, #1; bne 1b;" : "+r" (i)); } while (0)
/* delay on slow mode */
#define sram_udelay(usecs) SRAM_LOOP((usecs)*SRAM_LOOPS_PER_USEC)
/* delay on deep slow mode */
#define sram_32k_udelay(usecs) SRAM_LOOP(((usecs)*SRAM_LOOPS_PER_USEC)/(24000000/32768))
#endif

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arch/arm/mach-rk2928/include/mach/system.h Normal file
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#include <plat/system.h>

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arch/arm/mach-rk2928/include/mach/timex.h Normal file
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#include <plat/timex.h>

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arch/arm/mach-rk2928/include/mach/uncompress.h Normal file
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#include <plat/uncompress.h>

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#ifndef __MACH_VMALLOC_H
#define __MACH_VMALLOC_H
#define VMALLOC_END 0xFE800000
#endif

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/* arch/arm/mach-rk2928/io.c
*
* Copyright (C) 2012 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/page.h>
#include <asm/mach/map.h>
#define RK2928_DEVICE(name) { \
.virtual = (unsigned long) RK2928_##name##_BASE, \
.pfn = __phys_to_pfn(RK2928_##name##_PHYS), \
.length = RK2928_##name##_SIZE, \
.type = MT_DEVICE, \
}
static struct map_desc rk2928_io_desc[] __initdata = {
RK2928_DEVICE(CORE),
RK2928_DEVICE(CPU_AXI_BUS),
#if CONFIG_RK_DEBUG_UART == 0
RK2928_DEVICE(UART0),
#elif CONFIG_RK_DEBUG_UART == 1
RK2928_DEVICE(UART1),
#elif CONFIG_RK_DEBUG_UART == 2
RK2928_DEVICE(UART2),
#endif
RK2928_DEVICE(GRF),
RK2928_DEVICE(CRU),
RK2928_DEVICE(GPIO0),
RK2928_DEVICE(GPIO1),
RK2928_DEVICE(GPIO2),
RK2928_DEVICE(GPIO3),
RK2928_DEVICE(TIMER0),
RK2928_DEVICE(TIMER1),
RK2928_DEVICE(PWM),
RK2928_DEVICE(DDR_PCTL),
RK2928_DEVICE(DDR_PHY),
{
.virtual = (unsigned long) RK2928_IMEM_NONCACHED,
.pfn = __phys_to_pfn(RK2928_IMEM_PHYS),
.length = RK2928_IMEM_SIZE,
.type = MT_MEMORY_NONCACHED,
},
};
void __init rk2928_map_common_io(void)
{
iotable_init(rk2928_io_desc, ARRAY_SIZE(rk2928_io_desc));
}

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/*
* arch/arm/mach-rk2928/iomux.c
*
*Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <asm/system.h>
#include <asm/io.h>
#include <linux/spinlock.h>
#include <mach/io.h>
#include <mach/iomux.h>
//#define IOMUX_DBG
static struct mux_config rk30_muxs[] = {
/*
* description mux mode mux mux
* reg offset inter mode
*/
//gpio0a
MUX_CFG(GPIO0A0_I2C0_SCL_NAME, GPIO0A, 0, 1, 0, DEFAULT)
MUX_CFG(GPIO0A1_I2C0_SDA_NAME, GPIO0A, 2, 1, 0, DEFAULT)
MUX_CFG(GPIO0A2_I2C1_SCL_NAME, GPIO0A, 4, 1, 0, DEFAULT)
MUX_CFG(GPIO0A3_I2C1_SDA_NAME, GPIO0A, 6, 1, 0, DEFAULT)
MUX_CFG(GPIO0A6_I2C3_SCL_HDMI_DDCSCL_NAME, GPIO0A, 12, 2, 0, DEFAULT)
MUX_CFG(GPIO0A7_I2C3_SDA_HDMI_DDCSDA_NAME, GPIO0A, 14, 2, 0, DEFAULT)
//gpio0b
MUX_CFG(GPIO0B0_MMC1_CMD_NAME, GPIO0B, 0, 1, 0, DEFAULT)
MUX_CFG(GPIO0B1_MMC1_CLKOUT_NAME, GPIO0B, 2, 1, 0, DEFAULT)
MUX_CFG(GPIO0B2_MMC1_DETN_NAME, GPIO0B, 4, 1, 0, DEFAULT)
MUX_CFG(GPIO0B3_MMC1_D0_NAME, GPIO0B, 6, 1, 0, DEFAULT)
MUX_CFG(GPIO0B4_MMC1_D1_NAME, GPIO0B, 8, 1, 0, DEFAULT)
MUX_CFG(GPIO0B5_MMC1_D2_NAME, GPIO0B, 10, 1, 0, DEFAULT)
MUX_CFG(GPIO0B6_MMC1_D3_NAME, GPIO0B, 12, 1, 0, DEFAULT)
MUX_CFG(GPIO0B7_HDMI_HOTPLUGIN_NAME, GPIO0B, 14, 1, 0, DEFAULT)
//gpio0c
MUX_CFG(GPIO0C0_UART0_SOUT_NAME, GPIO0C, 0, 1, 0, DEFAULT)
MUX_CFG(GPIO0C1_UART0_SIN_NAME, GPIO0C, 2, 1, 0, DEFAULT)
MUX_CFG(GPIO0C2_UART0_RTSN_NAME, GPIO0C, 4, 1, 0, DEFAULT)
MUX_CFG(GPIO0C3_UART0_CTSN_NAME, GPIO0C, 6, 1, 0, DEFAULT)
MUX_CFG(GPIO0C4_HDMI_CECSDA_NAME, GPIO0C, 8, 1, 0, DEFAULT)
MUX_CFG(GPIO0C7_NAND_CS1_NAME, GPIO0C, 14, 1, 0, DEFAULT)
//gpio0d
MUX_CFG(GPIO0D0_UART2_RTSN_NAME, GPIO0D, 0, 1, 0, DEFAULT)
MUX_CFG(GPIO0D1_UART2_CTSN_NAME, GPIO0D, 2, 1, 0, DEFAULT)
MUX_CFG(GPIO0D2_PWM_0_NAME, GPIO0D, 4, 1, 0, DEFAULT)
MUX_CFG(GPIO0D3_PWM_1_NAME, GPIO0D, 6, 1, 0, DEFAULT)
MUX_CFG(GPIO0D4_PWM_2_NAME, GPIO0D, 8, 1, 0, DEFAULT)
MUX_CFG(GPIO0D5_MMC1_WRPRT_NAME, GPIO0D, 10, 1, 0, DEFAULT)
MUX_CFG(GPIO0D6_MMC1_PWREN_NAME, GPIO0D, 12, 1, 0, DEFAULT)
MUX_CFG(GPIO0D7_MMC1_BKEPWR_NAME, GPIO0D, 14, 1, 0, DEFAULT)
//gpio1a
MUX_CFG(GPIO1A0_I2S_MCLK_NAME, GPIO1A, 0, 1, 0, DEFAULT)
MUX_CFG(GPIO1A1_I2S_SCLK_NAME, GPIO1A, 2, 1, 0, DEFAULT)
MUX_CFG(GPIO1A2_I2S_LRCKRX_GPS_CLK_NAME, GPIO1A, 4, 2, 0, DEFAULT)
MUX_CFG(GPIO1A3_I2S_LRCKTX_NAME, GPIO1A, 6, 1, 0, DEFAULT)
MUX_CFG(GPIO1A4_I2S_SDO_GPS_MAG_NAME, GPIO1A, 8, 2, 0, DEFAULT)
MUX_CFG(GPIO1A5_I2S_SDI_GPS_SIGN_NAME, GPIO1A, 10, 2, 0, DEFAULT)
MUX_CFG(GPIO1A6_MMC1_INTN_NAME, GPIO1A, 12, 1, 0, DEFAULT)
MUX_CFG(GPIO1A7_MMC0_WRPRT_NAME, GPIO1A, 14, 1, 0, DEFAULT)
//gpio1b
MUX_CFG(GPIO1B0_SPI_CLK_UART1_CTSN_NAME, GPIO1B, 0, 2, 0, DEFAULT)
MUX_CFG(GPIO1B1_SPI_TXD_UART1_SOUT_NAME, GPIO1B, 2, 2, 0, DEFAULT)
MUX_CFG(GPIO1B2_SPI_RXD_UART1_SIN_NAME, GPIO1B, 4, 2, 0, DEFAULT)
MUX_CFG(GPIO1B3_SPI_CSN0_UART1_RTSN_NAME, GPIO1B, 6, 2, 0, DEFAULT)
MUX_CFG(GPIO1B4_SPI_CSN1_NAME, GPIO1B, 8, 1, 0, DEFAULT)
MUX_CFG(GPIO1B5_MMC0_RSTNOUT_NAME, GPIO1B, 10, 1, 0, DEFAULT)
MUX_CFG(GPIO1B6_MMC0_PWREN_NAME, GPIO1B, 12, 1, 0, DEFAULT)
MUX_CFG(GPIO1B7_MMC0_CMD_NAME, GPIO1B, 14, 1, 0, DEFAULT)
//gpio1c
MUX_CFG(GPIO1C0_MMC0_CLKOUT_NAME, GPIO1C, 0, 1, 0, DEFAULT)
MUX_CFG(GPIO1C1_MMC0_DETN_NAME, GPIO1C, 2, 1, 0, DEFAULT)
MUX_CFG(GPIO1C2_MMC0_D0_NAME, GPIO1C, 4, 1, 0, DEFAULT)
MUX_CFG(GPIO1C3_MMC0_D1_NAME, GPIO1C, 6, 1, 0, DEFAULT)
MUX_CFG(GPIO1C4_MMC0_D2_NAME, GPIO1C, 8, 1, 0, DEFAULT)
MUX_CFG(GPIO1C5_MMC0_D3_NAME, GPIO1C, 10, 1, 0, DEFAULT)
MUX_CFG(GPIO1C6_NAND_CS2_EMMC_CMD_NAME, GPIO1C, 12, 2, 0, DEFAULT)
MUX_CFG(GPIO1C7_NAND_CS3_EMMC_RSTNOUT_NAME, GPIO1C, 14, 2, 0, DEFAULT)
//gpio1d
MUX_CFG(GPIO1D0_NAND_D0_EMMC_D0_NAME, GPIO1D, 0, 2, 0, DEFAULT)
MUX_CFG(GPIO1D1_NAND_D1_EMMC_D1_NAME, GPIO1D, 2, 2, 0, DEFAULT)
MUX_CFG(GPIO1D2_NAND_D2_EMMC_D2_NAME, GPIO1D, 4, 2, 0, DEFAULT)
MUX_CFG(GPIO1D3_NAND_D3_EMMC_D3_NAME, GPIO1D, 6, 2, 0, DEFAULT)
MUX_CFG(GPIO1D4_NAND_D4_EMMC_D4_NAME, GPIO1D, 8, 2, 0, DEFAULT)
MUX_CFG(GPIO1D5_NAND_D5_EMMC_D5_NAME, GPIO1D, 10, 2, 0, DEFAULT)
MUX_CFG(GPIO1D6_NAND_D6_EMMC_D6_NAME, GPIO1D, 12, 2, 0, DEFAULT)
MUX_CFG(GPIO1D7_NAND_D7_EMMC_D7_NAME, GPIO1D, 14, 2, 0, DEFAULT)
//gpio2a
MUX_CFG(GPIO2A0_NAND_ALE_NAME, GPIO2A, 0, 1, 0, DEFAULT)
MUX_CFG(GPIO2A1_NAND_CLE_NAME, GPIO2A, 2, 1, 0, DEFAULT)
MUX_CFG(GPIO2A2_NAND_WRN_NAME, GPIO2A, 4, 1, 0, DEFAULT)
MUX_CFG(GPIO2A3_NAND_RDN_NAME, GPIO2A, 6, 1, 0, DEFAULT)
MUX_CFG(GPIO2A4_NAND_RDY_NAME, GPIO2A, 8, 1, 0, DEFAULT)
MUX_CFG(GPIO2A5_NAND_WP_EMMC_PWREN_NAME, GPIO2A, 10, 2, 0, DEFAULT)
MUX_CFG(GPIO2A6_NAND_CS0_NAME, GPIO2A, 12, 1, 0, DEFAULT)
MUX_CFG(GPIO2A7_NAND_DPS_EMMC_CLKOUT_NAME, GPIO2A, 14, 2, 0, DEFAULT)
//gpio2b
MUX_CFG(GPIO2B0_LCDC0_DCLK_LCDC1_DCLK_NAME, GPIO2B, 0, 2, 0, DEFAULT)
MUX_CFG(GPIO2B1_LCDC0_HSYNC_LCDC1_HSYNC_NAME, GPIO2B, 2, 2, 0, DEFAULT)
MUX_CFG(GPIO2B2_LCDC0_VSYNC_LCDC1_VSYNC_NAME, GPIO2B, 4, 2, 0, DEFAULT)
MUX_CFG(GPIO2B3_LCDC0_DEN_LCDC1_DEN_NAME, GPIO2B, 6, 2, 0, DEFAULT)
MUX_CFG(GPIO2B4_LCDC0_D10_LCDC1_D10_NAME, GPIO2B, 8, 2, 0, DEFAULT)
MUX_CFG(GPIO2B5_LCDC0_D11_LCDC1_D11_NAME, GPIO2B, 10, 2, 0, DEFAULT)
MUX_CFG(GPIO2B6_LCDC0_D12_LCDC1_D12_NAME, GPIO2B, 12, 2, 0, DEFAULT)
MUX_CFG(GPIO2B7_LCDC0_D13_LCDC1_D13_NAME, GPIO2B, 14, 2, 0, DEFAULT)
//gpio2c
MUX_CFG(GPIO2C0_LCDC0_D14_LCDC1_D14_NAME, GPIO2C, 0, 2, 0, DEFAULT)
MUX_CFG(GPIO2C1_LCDC0_D15_LCDC1_D15_NAME, GPIO2C, 2, 2, 0, DEFAULT)
MUX_CFG(GPIO2C2_LCDC0_D16_LCDC1_D16_NAME, GPIO2C, 4, 2, 0, DEFAULT)
MUX_CFG(GPIO2C3_LCDC0_D17_LCDC1_D17_NAME, GPIO2C, 6, 2, 0, DEFAULT)
MUX_CFG(GPIO2C4_LCDC0_D18_LCDC1_D18_I2C2_SDA_NAME,GPIO2C, 8, 2, 0, DEFAULT)
MUX_CFG(GPIO2C5_LCDC0_D19_LCDC1_D19_I2C2_SCL_NAME,GPIO2C, 10, 2, 0, DEFAULT)
MUX_CFG(GPIO2C6_LCDC0_D20_LCDC1_D20_UART2_SIN_NAME,GPIO2C, 12, 2, 0, DEFAULT)
MUX_CFG(GPIO2C7_LCDC0_D21_LCDC1_D21_UART2_SOUT_NAME,GPIO2C, 14, 2, 0, DEFAULT)
//gpio2d
MUX_CFG(GPIO2D0_LCDC0_D22_LCDC1_D22_NAME, GPIO2D, 0, 2, 0, DEFAULT)
MUX_CFG(GPIO2D1_LCDC0_D23_LCDC1_D23_NAME, GPIO2D, 2, 2, 0, DEFAULT)
//gpio3c
MUX_CFG(GPIO3C1_OTG_DRVVBUS_NAME, GPIO3C, 2, 1, 0, DEFAULT)
//gpio3d
MUX_CFG(GPIO3D7_TESTCLK_OUT_NAME, GPIO3D, 14, 1, 0, DEFAULT)
};
void rk30_mux_set(struct mux_config *cfg)
{
int regValue = 0;
int mask;
mask = (((1<<(cfg->interleave))-1)<<cfg->offset) << 16;
regValue |= mask;
regValue |=(cfg->mode<<cfg->offset);
#ifdef IOMUX_DBG
printk("%s::reg=0x%p,Value=0x%x,mask=0x%x\n",__FUNCTION__,cfg->mux_reg,regValue,mask);
#endif
writel_relaxed(regValue,cfg->mux_reg);
dsb();
return;
}
int __init rk2928_iomux_init(void)
{
int i;
printk("%s\n",__func__);
for(i=0;i<ARRAY_SIZE(rk30_muxs);i++)
{
if(rk30_muxs[i].flags != DEFAULT)
rk30_mux_set(&rk30_muxs[i]);
}
#if defined(CONFIG_UART0_RK29) || (CONFIG_RK_DEBUG_UART == 0)
rk30_mux_api_set(GPIO0C0_UART0_SOUT_NAME, GPIO0C_UART0_SOUT);
rk30_mux_api_set(GPIO0C1_UART0_SIN_NAME, GPIO0C_UART0_SIN);
#ifdef CONFIG_UART0_CTS_RTS_RK29
rk30_mux_api_set(GPIO0C2_UART0_RTSN_NAME, GPIO0C_UART0_RTSN);
rk30_mux_api_set(GPIO0C3_UART0_CTSN_NAME, GPIO0C_UART0_CTSN);
#endif
#endif
#if defined(CONFIG_UART1_RK29) || (CONFIG_RK_DEBUG_UART == 1)
//UART1 OR SPIM0
rk30_mux_api_set(GPIO1B2_SPI_RXD_UART1_SIN_NAME, GPIO1B_UART1_SIN);
rk30_mux_api_set(GPIO1B1_SPI_TXD_UART1_SOUT_NAME, GPIO1B_UART1_SOUT);
#ifdef CONFIG_UART1_CTS_RTS_RK29
rk30_mux_api_set(GPIO1B0_SPI_CLK_UART1_CTSN_NAME, GPIO1B_UART1_CTSN);
rk30_mux_api_set(GPIO1B3_SPI_CSN0_UART1_RTSN_NAME, GPIO1B_UART1_RTSN);
#endif
#endif
#if defined(CONFIG_UART2_RK29) || (CONFIG_RK_DEBUG_UART == 2)
rk30_mux_api_set(GPIO2C6_LCDC0_D20_LCDC1_D20_UART2_SIN_NAME, GPIO2C_UART2_SIN);
rk30_mux_api_set(GPIO2C7_LCDC0_D21_LCDC1_D21_UART2_SOUT_NAME, GPIO2C_UART2_SOUT);
#ifdef CONFIG_UART2_CTS_RTS_RK29
rk30_mux_api_set(GPIO0D0_UART2_RTSN_NAME, GPIO0D_UART2_RTSN);
rk30_mux_api_set(GPIO0D1_UART2_CTSN_NAME, GPIO0D_UART2_CTSN);
#endif
#endif
#ifdef CONFIG_SPIM0_RK29
//UART1 OR SPIM0
rk30_mux_api_set(GPIO1B0_SPI_CLK_UART1_CTSN_NAME, GPIO1B_SPI_CLK);
rk30_mux_api_set(GPIO1B1_SPI_TXD_UART1_SOUT_NAME, GPIO1B_SPI_TXD);
rk30_mux_api_set(GPIO1B2_SPI_RXD_UART1_SIN_NAME, GPIO1B_SPI_RXD);
rk30_mux_api_set(GPIO1B3_SPI_CSN0_UART1_RTSN_NAME, GPIO1B_SPI_CSN0);
#endif
#ifdef CONFIG_I2C0_RK30
rk30_mux_api_set(GPIO0A0_I2C0_SCL_NAME, GPIO0A_I2C0_SCL);
rk30_mux_api_set(GPIO0A1_I2C0_SDA_NAME, GPIO0A_I2C0_SDA);
#endif
#ifdef CONFIG_I2C1_RK30
rk30_mux_api_set(GPIO0A2_I2C1_SCL_NAME, GPIO0A_I2C1_SCL);
rk30_mux_api_set(GPIO0A3_I2C1_SDA_NAME, GPIO0A_I2C1_SDA);
#endif
#ifdef CONFIG_I2C2_RK30
rk30_mux_api_set(GPIO2C4_LCDC0_D18_LCDC1_D18_I2C2_SDA_NAME, GPIO2C_I2C2_SDA);
rk30_mux_api_set(GPIO2C5_LCDC0_D19_LCDC1_D19_I2C2_SCL_NAME, GPIO2C_I2C2_SCL);
#endif
#ifdef CONFIG_I2C3_RK30
rk30_mux_api_set(GPIO0A6_I2C3_SCL_HDMI_DDCSCL_NAME, GPIO0A_I2C3_SCL);
rk30_mux_api_set(GPIO0A7_I2C3_SDA_HDMI_DDCSDA_NAME, GPIO0A_I2C3_SDA);
#endif
return 0;
}
/*
*config iomux : input iomux name and iomux flags
*/
void rk30_mux_api_set(char *name, unsigned int mode)
{
int i;
if (!name) {
return;
}
for(i=0;i<ARRAY_SIZE(rk30_muxs);i++)
{
if (!strcmp(rk30_muxs[i].name, name))
{
rk30_muxs[i].premode = rk30_muxs[i].mode;
rk30_muxs[i].mode = mode;
rk30_mux_set(&rk30_muxs[i]);
break;
}
}
}
EXPORT_SYMBOL(rk30_mux_api_set);
int rk30_mux_api_get(char *name)
{
int i,ret=0;
if (!name) {
return -1;
}
for(i=0;i<ARRAY_SIZE(rk30_muxs);i++)
{
if (!strcmp(rk30_muxs[i].name, name))
{
ret = readl(rk30_muxs[i].mux_reg);
ret = (ret >> rk30_muxs[i].offset) &((1<<(rk30_muxs[i].interleave))-1);
return ret;
}
}
return -1;
}
EXPORT_SYMBOL(rk30_mux_api_get);

494
arch/arm/mach-rk2928/pm.c Executable file
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@ -0,0 +1,494 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/suspend.h>
#include <linux/random.h>
#include <linux/crc32.h>
#include <linux/io.h>
#include <linux/wakelock.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <mach/pmu.h>
#include <mach/board.h>
#include <mach/system.h>
#include <mach/sram.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/cru.h>
#define cru_readl(offset) readl_relaxed(RK2928_CRU_BASE + offset)
#define cru_writel(v, offset) do { writel_relaxed(v, RK2928_CRU_BASE + offset); dsb(); } while (0)
#define grf_readl(offset) readl_relaxed(RK2928_GRF_BASE + offset)
#define grf_writel(v, offset) do { writel_relaxed(v, RK2928_GRF_BASE + offset); dsb(); } while (0)
#define gate_save_soc_clk(val, _save, cons, w_msk) \
do { \
(_save) = cru_readl(cons); \
cru_writel(((~(val) | (_save)) & (w_msk)) | ((w_msk) << 16), cons); \
} while (0)
void __sramfunc sram_printch(char byte)
{
#ifdef DEBUG_UART_BASE
u32 clk_gate2, clk_gate4, clk_gate8;
gate_save_soc_clk(0
| (1 << CLK_GATE_ACLK_PERIPH % 16)
| (1 << CLK_GATE_HCLK_PERIPH % 16)
| (1 << CLK_GATE_PCLK_PERIPH % 16)
, clk_gate2, CRU_CLKGATES_CON(2), 0
| (1 << ((CLK_GATE_ACLK_PERIPH % 16) + 16))
| (1 << ((CLK_GATE_HCLK_PERIPH % 16) + 16))
| (1 << ((CLK_GATE_PCLK_PERIPH % 16) + 16)));
gate_save_soc_clk((1 << CLK_GATE_ACLK_CPU_PERI % 16)
, clk_gate4, CRU_CLKGATES_CON(4),
(1 << ((CLK_GATE_ACLK_CPU_PERI % 16) + 16)));
gate_save_soc_clk((1 << ((CLK_GATE_PCLK_UART0 + CONFIG_RK_DEBUG_UART) % 16)),
clk_gate8, CRU_CLKGATES_CON(8),
(1 << (((CLK_GATE_PCLK_UART0 + CONFIG_RK_DEBUG_UART) % 16) + 16)));
sram_udelay(1);
writel_relaxed(byte, DEBUG_UART_BASE);
dsb();
/* loop check LSR[6], Transmitter Empty bit */
while (!(readl_relaxed(DEBUG_UART_BASE + 0x14) & 0x40))
barrier();
cru_writel(0xffff0000 | clk_gate2, CRU_CLKGATES_CON(2));
cru_writel(0xffff0000 | clk_gate4, CRU_CLKGATES_CON(4));
cru_writel(0xffff0000 | clk_gate8, CRU_CLKGATES_CON(8));
if (byte == '\n')
sram_printch('\r');
#endif
}
__weak void __sramfunc ddr_suspend(void) {}
__weak void __sramfunc ddr_resume(void) {}
__weak uint32_t __sramfunc ddr_change_freq(uint32_t nMHz) { return nMHz; }
#ifdef CONFIG_DDR_TEST
static int ddr_debug=0;
module_param(ddr_debug, int, 0644);
static int inline calc_crc32(u32 addr, size_t len)
{
return crc32_le(~0, (const unsigned char *)addr, len);
}
static void ddr_testmode(void)
{
int32_t g_crc1, g_crc2;
uint32_t nMHz;
uint32_t n = 0;
uint32_t min,max;
extern char _stext[], _etext[];
if (ddr_debug == 1) {
max=500;
min=100;
for (;;) {
sram_printascii("\n change freq:");
g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
do
{
nMHz = min + random32();
nMHz %= max;
}while(nMHz < min);
sram_printhex(nMHz);
sram_printch(' ');
nMHz = ddr_change_freq(nMHz);
sram_printhex(n++);
sram_printch(' ');
g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
if (g_crc1!=g_crc2) {
sram_printascii("fail\n");
}
//ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
// sram_printascii("change freq success\n");
}
} else if(ddr_debug == 2) {
for (;;) {
sram_printch(' ');
sram_printch('9');
sram_printch('9');
sram_printch('9');
sram_printch(' ');
g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
nMHz = (random32()>>13);// 16.7s max
ddr_suspend();
sram_udelay(nMHz);
ddr_resume();
sram_printhex(nMHz);
sram_printch(' ');
sram_printhex(n++);
g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
if (g_crc1 != g_crc2) {
sram_printch(' ');
sram_printch('f');
sram_printch('a');
sram_printch('i');
sram_printch('l');
}
// ddr_print("check image crc32 fail!, count:%d\n", n++);
// sram_printascii("self refresh fail\n");
//else
//ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
// sram_printascii("self refresh success\n");
}
} else if (ddr_debug == 3) {
extern int memtester(void);
memtester();
}
else
{
ddr_change_freq(ddr_debug);
ddr_debug=0;
}
}
#else
static void ddr_testmode(void) {}
#endif
static noinline void rk2928_pm_dump_irq(void)
{
u32 irq_gpio = (readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + (IRQ_GPIO0 / 32) * 4) >> (IRQ_GPIO0 % 32)) & 0xF;
printk("wakeup irq: %08x %08x %08x\n",
readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + 4),
readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + 8),
readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + 12));
if (irq_gpio & 1)
printk("wakeup gpio0: %08x\n", readl_relaxed(RK2928_GPIO0_BASE + GPIO_INT_STATUS));
if (irq_gpio & 2)
printk("wakeup gpio1: %08x\n", readl_relaxed(RK2928_GPIO1_BASE + GPIO_INT_STATUS));
if (irq_gpio & 4)
printk("wakeup gpio2: %08x\n", readl_relaxed(RK2928_GPIO2_BASE + GPIO_INT_STATUS));
if (irq_gpio & 8)
printk("wakeup gpio3: %08x\n", readl_relaxed(RK2928_GPIO3_BASE + GPIO_INT_STATUS));
}
#define DUMP_GPIO_INTEN(ID) \
do { \
u32 en = readl_relaxed(RK2928_GPIO##ID##_BASE + GPIO_INTEN); \
if (en) { \
sram_printascii("GPIO" #ID "_INTEN: "); \
sram_printhex(en); \
sram_printch('\n'); \
} \
} while (0)
static noinline void rk2928_pm_dump_inten(void)
{
DUMP_GPIO_INTEN(0);
DUMP_GPIO_INTEN(1);
DUMP_GPIO_INTEN(2);
DUMP_GPIO_INTEN(3);
}
static void pm_pll_wait_lock(int pll_idx)
{
u32 pll_state[4] = { 1, 0, 2, 3 };
u32 bit = 0x10u << pll_state[pll_idx];
u32 delay = pll_idx == APLL_ID ? 24000000U : 2400000000U;
while (delay > 0) {
if (grf_readl(GRF_SOC_STATUS0) & bit)
break;
delay--;
}
if (delay == 0) {
//CRU_PRINTK_ERR("wait pll bit 0x%x time out!\n", bit);
sram_printch('p');
sram_printch('l');
sram_printch('l');
sram_printhex(pll_idx);
sram_printch('\n');
}
}
#define power_on_pll(id) \
cru_writel(PLL_PWR_DN_W_MSK|PLL_PWR_ON,PLL_CONS((id),3));\
pm_pll_wait_lock((id))
#define DDR_SAVE_SP(save_sp) do { save_sp = ddr_save_sp(((unsigned long)SRAM_DATA_END & (~7))); } while (0)
#define DDR_RESTORE_SP(save_sp) do { ddr_save_sp(save_sp); } while (0)
static unsigned long save_sp;
static noinline void interface_ctr_reg_pread(void)
{
u32 addr;
flush_cache_all();
outer_flush_all();
local_flush_tlb_all();
for (addr = (u32)SRAM_CODE_OFFSET; addr < (u32)SRAM_DATA_END; addr += PAGE_SIZE)
readl_relaxed(addr);
readl_relaxed(RK2928_GRF_BASE);
readl_relaxed(RK2928_DDR_PCTL_BASE);
readl_relaxed(RK2928_DDR_PHY_BASE);
// readl_relaxed(RK2928_I2C1_BASE);
}
__weak void board_gpio_suspend(void) {}
__weak void board_gpio_resume(void) {}
__weak void __sramfunc board_pmu_suspend(void) {}
__weak void __sramfunc board_pmu_resume(void) {}
__weak void __sramfunc rk30_suspend_voltage_set(unsigned int vol) {}
__weak void __sramfunc rk30_suspend_voltage_resume(unsigned int vol) {}
__weak void rk30_pwm_suspend_voltage_set(void) {}
__weak void rk30_pwm_resume_voltage_set(void) {}
__weak void __sramfunc rk30_pwm_logic_suspend_voltage(void) {}
__weak void __sramfunc rk30_pwm_logic_resume_voltage(void) {}
static void __sramfunc rk2928_sram_suspend(void)
{
u32 cru_clksel0_con;
u32 clkgt_regs[CRU_CLKGATES_CON_CNT];
int i;
sram_printch('5');
ddr_suspend();
sram_printch('6');
rk30_suspend_voltage_set(1000000);
rk30_pwm_logic_suspend_voltage();
sram_printch('7');
for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
clkgt_regs[i] = cru_readl(CRU_CLKGATES_CON(i));
}
gate_save_soc_clk(0
| (1 << CLK_GATE_CORE_PERIPH)
| (1 << CLK_GATE_DDRPHY_SRC)
| (1 << CLK_GATE_ACLK_CPU)
| (1 << CLK_GATE_HCLK_CPU)
| (1 << CLK_GATE_PCLK_CPU)
| (1 << CLK_GATE_ACLK_CORE)
, clkgt_regs[0], CRU_CLKGATES_CON(0), 0xffff);
if (((clkgt_regs[8] >> (CLK_GATE_PCLK_GPIO0 % 16)) & 0xf) != 0xf) {
gate_save_soc_clk(0
| (1 << CLK_GATE_PERIPH_SRC % 16)
| (1 << CLK_GATE_PCLK_PERIPH % 16)
, clkgt_regs[2], CRU_CLKGATES_CON(2), 0xffff);
} else {
gate_save_soc_clk(0, clkgt_regs[2], CRU_CLKGATES_CON(2), 0xffff);
}
gate_save_soc_clk(0
| (1 << CLK_GATE_ACLK_STRC_SYS % 16)
| (1 << CLK_GATE_ACLK_INTMEM % 16)
, clkgt_regs[4], CRU_CLKGATES_CON(4), 0xffff);
gate_save_soc_clk(0
| (1 << CLK_GATE_PCLK_GRF % 16)
| (1 << CLK_GATE_PCLK_DDRUPCTL % 16)
, clkgt_regs[5], CRU_CLKGATES_CON(5), 0xffff);
gate_save_soc_clk(0, clkgt_regs[7], CRU_CLKGATES_CON(7), 0xffff);
gate_save_soc_clk(0
| (1 << CLK_GATE_CLK_L2C % 16)
, clkgt_regs[9], CRU_CLKGATES_CON(9), 0xffff);
board_pmu_suspend();
cru_clksel0_con = cru_readl(CRU_CLKSELS_CON(0));
cru_writel((0x1f << 16) | 0x1f, CRU_CLKSELS_CON(0));
dsb();
wfi();
cru_writel((0x1f << 16) | cru_clksel0_con, CRU_CLKSELS_CON(0));
board_pmu_resume();
for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
cru_writel(clkgt_regs[i] | 0xffff0000, CRU_CLKGATES_CON(i));
}
sram_printch('7');
rk30_pwm_logic_resume_voltage();
rk30_suspend_voltage_resume(1100000);
sram_printch('6');
ddr_resume();
sram_printch('5');
}
static void noinline rk2928_suspend(void)
{
DDR_SAVE_SP(save_sp);
rk2928_sram_suspend();
DDR_RESTORE_SP(save_sp);
}
static int rk2928_pm_enter(suspend_state_t state)
{
u32 i;
u32 clkgt_regs[CRU_CLKGATES_CON_CNT];
u32 clk_sel0, clk_sel1, clk_sel10;
u32 cru_mode_con;
// dump GPIO INTEN for debug
rk2928_pm_dump_inten();
sram_printch('0');
#ifdef CONFIG_DDR_TEST
// memory tester
if (ddr_debug != 0)
ddr_testmode();
#endif
sram_printch('1');
local_fiq_disable();
for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
clkgt_regs[i] = cru_readl(CRU_CLKGATES_CON(i));
}
gate_save_soc_clk(0
| (1 << CLK_GATE_CORE_PERIPH)
| (1 << CLK_GATE_CPU_GPLL)
| (1 << CLK_GATE_DDRPHY_SRC)
| (1 << CLK_GATE_ACLK_CPU)
| (1 << CLK_GATE_HCLK_CPU)
| (1 << CLK_GATE_PCLK_CPU)
| (1 << CLK_GATE_ACLK_CORE)
, clkgt_regs[0], CRU_CLKGATES_CON(0), 0xffff);
gate_save_soc_clk(0, clkgt_regs[1], CRU_CLKGATES_CON(1), 0xffff);
gate_save_soc_clk(0
| (1 << CLK_GATE_PERIPH_SRC % 16)
| (1 << CLK_GATE_PCLK_PERIPH % 16)
| (1 << CLK_GATE_ACLK_PERIPH % 16)
, clkgt_regs[2], CRU_CLKGATES_CON(2), 0xffff);
gate_save_soc_clk(0, clkgt_regs[3], CRU_CLKGATES_CON(3), 0xffff);
gate_save_soc_clk(0
| (1 << CLK_GATE_HCLK_PERI_AXI_MATRIX % 16)
| (1 << CLK_GATE_PCLK_PERI_AXI_MATRIX % 16)
| (1 << CLK_GATE_ACLK_CPU_PERI % 16)
| (1 << CLK_GATE_ACLK_PERI_AXI_MATRIX % 16)
| (1 << CLK_GATE_ACLK_STRC_SYS % 16)
| (1 << CLK_GATE_ACLK_INTMEM % 16)
, clkgt_regs[4], CRU_CLKGATES_CON(4), 0xffff);
gate_save_soc_clk(0
| (1 << CLK_GATE_PCLK_GRF % 16)
| (1 << CLK_GATE_PCLK_DDRUPCTL % 16)
, clkgt_regs[5], CRU_CLKGATES_CON(5), 0xffff);
gate_save_soc_clk(0, clkgt_regs[6], CRU_CLKGATES_CON(6), 0xffff);
gate_save_soc_clk(0
| (1 << CLK_GATE_PCLK_PWM01 % 16)
, clkgt_regs[7], CRU_CLKGATES_CON(7), 0xffff);
gate_save_soc_clk(0
| (1 << CLK_GATE_PCLK_GPIO0 % 16)
| (1 << CLK_GATE_PCLK_GPIO1 % 16)
| (1 << CLK_GATE_PCLK_GPIO2 % 16)
| (1 << CLK_GATE_PCLK_GPIO3 % 16)
, clkgt_regs[8], CRU_CLKGATES_CON(8), 0xffff);
gate_save_soc_clk(0
| (1 << CLK_GATE_CLK_L2C % 16)
| (1 << CLK_GATE_HCLK_PERI_ARBI % 16)
| (1 << CLK_GATE_ACLK_PERI_NIU % 16)
, clkgt_regs[9], CRU_CLKGATES_CON(9), 0xffff);
sram_printch('2');
cru_mode_con = cru_readl(CRU_MODE_CON);
//apll
clk_sel0 = cru_readl(CRU_CLKSELS_CON(0));
clk_sel1 = cru_readl(CRU_CLKSELS_CON(1));
cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
cru_writel(CLK_CORE_DIV(1) | ACLK_CPU_DIV(1) | CPU_SEL_PLL(SEL_APLL), CRU_CLKSELS_CON(0));
cru_writel(CLK_CORE_PERI_DIV(1) | ACLK_CORE_DIV(1) | HCLK_CPU_DIV(1) | PCLK_CPU_DIV(1), CRU_CLKSELS_CON(1));
//cpll
cru_writel(PLL_MODE_SLOW(CPLL_ID), CRU_MODE_CON);
//gpll
clk_sel10 = cru_readl(CRU_CLKSELS_CON(10));
cru_writel(PLL_MODE_SLOW(GPLL_ID), CRU_MODE_CON);
cru_writel(PERI_SET_ACLK_DIV(1)
| PERI_SET_A2H_RATIO(RATIO_11)
| PERI_SET_A2P_RATIO(RATIO_11)
, CRU_CLKSELS_CON(10));
sram_printch('3');
rk30_pwm_suspend_voltage_set();
board_gpio_suspend();
interface_ctr_reg_pread();
sram_printch('4');
rk2928_suspend();
sram_printch('4');
board_gpio_resume();
rk30_pwm_resume_voltage_set();
sram_printch('3');
//gpll
cru_writel(0xffff0000 | clk_sel10, CRU_CLKSELS_CON(10));
cru_writel(clk_sel10, CRU_CLKSELS_CON(10));
cru_writel((PLL_MODE_MSK(GPLL_ID) << 16) | (PLL_MODE_MSK(GPLL_ID) & cru_mode_con), CRU_MODE_CON);
//cpll
cru_writel((PLL_MODE_MSK(CPLL_ID) << 16) | (PLL_MODE_MSK(CPLL_ID) & cru_mode_con), CRU_MODE_CON);
//apll
cru_writel(0xffff0000 | clk_sel1, CRU_CLKSELS_CON(1));
cru_writel(0xffff0000 | clk_sel0, CRU_CLKSELS_CON(0));
cru_writel((PLL_MODE_MSK(APLL_ID) << 16) | (PLL_MODE_MSK(APLL_ID) & cru_mode_con), CRU_MODE_CON);
sram_printch('2');
for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
cru_writel(clkgt_regs[i] | 0xffff0000, CRU_CLKGATES_CON(i));
}
local_fiq_enable();
sram_printch('1');
sram_printascii("0\n");
rk2928_pm_dump_irq();
return 0;
}
static int rk2928_pm_prepare(void)
{
/* disable entering idle by disable_hlt() */
disable_hlt();
return 0;
}
static void rk2928_pm_finish(void)
{
enable_hlt();
}
static struct platform_suspend_ops rk2928_pm_ops = {
.enter = rk2928_pm_enter,
.valid = suspend_valid_only_mem,
.prepare = rk2928_pm_prepare,
.finish = rk2928_pm_finish,
};
static int __init rk2928_pm_init(void)
{
suspend_set_ops(&rk2928_pm_ops);
#ifdef CONFIG_EARLYSUSPEND
pm_set_vt_switch(0); /* disable vt switch while suspend */
#endif
return 0;
}
__initcall(rk2928_pm_init);

39
arch/arm/mach-rk2928/reset.c Executable file
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@ -0,0 +1,39 @@
#include <linux/io.h>
#include <linux/kernel.h>
#include <mach/system.h>
#include <linux/string.h>
#include <mach/cru.h>
#include <mach/iomux.h>
#include <mach/loader.h>
#include <mach/board.h>
static void rk2928_arch_reset(char mode, const char *cmd)
{
u32 boot_flag = 0;
u32 boot_mode = BOOT_MODE_REBOOT;
if (cmd) {
if (!strcmp(cmd, "loader") || !strcmp(cmd, "bootloader"))
boot_flag = SYS_LOADER_REBOOT_FLAG + BOOT_LOADER;
else if(!strcmp(cmd, "recovery"))
boot_flag = SYS_LOADER_REBOOT_FLAG + BOOT_RECOVER;
else if (!strcmp(cmd, "charge"))
boot_mode = BOOT_MODE_CHARGE;
} else {
if (system_state != SYSTEM_RESTART)
boot_mode = BOOT_MODE_PANIC;
}
writel_relaxed(0xffff0000 | (boot_flag&0xFFFFuL), RK2928_GRF_BASE + GRF_OS_REG4); // for loader
writel_relaxed(0xffff0000 | ((boot_flag>>16)&0xFFFFuL), RK2928_GRF_BASE + GRF_OS_REG5); // for loader
writel_relaxed(0xffff0000 | boot_mode, RK2928_GRF_BASE + GRF_OS_REG6); // for linux
dsb();
/* disable remap */
writel_relaxed(1 << (12 + 16), RK2928_GRF_BASE + GRF_SOC_CON0);
/* pll enter slow mode */
writel_relaxed(PLL_MODE_SLOW(APLL_ID) | PLL_MODE_SLOW(CPLL_ID) | PLL_MODE_SLOW(GPLL_ID), RK2928_CRU_BASE + CRU_MODE_CON);
dsb();
writel_relaxed(0xeca8, RK2928_CRU_BASE + CRU_GLB_SRST_SND);
dsb();
}
void (*arch_reset)(char, const char *) = rk2928_arch_reset;

215
arch/arm/mach-rk2928/timer.c Normal file
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@ -0,0 +1,215 @@
/* linux/arch/arm/mach-rk2928/timer.c
*
* Copyright (C) 2012 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/init.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/io.h>
#include <asm/sched_clock.h>
#include <asm/mach/time.h>
#define TIMER_LOAD_COUNT 0x0000
#define TIMER_CUR_VALUE 0x0004
#define TIMER_CONTROL_REG 0x0008
#define TIMER_EOI 0x000C
#define TIMER_INT_STATUS 0x0010
#define TIMER_DISABLE 6
#define TIMER_ENABLE 3
#define TIMER_ENABLE_FREE_RUNNING 5
static inline void timer_write(u32 n, u32 v, u32 offset)
{
__raw_writel(v, RK2928_TIMER0_BASE + 0x2000 * n + offset);
dsb();
}
static inline u32 timer_read(u32 n, u32 offset)
{
return __raw_readl(RK2928_TIMER0_BASE + 0x2000 * n + offset);
}
#define RK_TIMER_ENABLE(n) timer_write(n, TIMER_ENABLE, TIMER_CONTROL_REG)
#define RK_TIMER_ENABLE_FREE_RUNNING(n) timer_write(n, TIMER_ENABLE_FREE_RUNNING, TIMER_CONTROL_REG)
#define RK_TIMER_DISABLE(n) timer_write(n, TIMER_DISABLE, TIMER_CONTROL_REG)
#define RK_TIMER_SETCOUNT(n, count) timer_write(n, count, TIMER_LOAD_COUNT)
#define RK_TIMER_GETCOUNT(n) timer_read(n, TIMER_LOAD_COUNT)
#define RK_TIMER_READVALUE(n) timer_read(n, TIMER_CUR_VALUE)
#define RK_TIMER_INT_CLEAR(n) timer_read(n, TIMER_EOI)
#define RK_TIMER_INT_STATUS(n) timer_read(n, TIMER_INT_STATUS)
#define TIMER_CLKEVT 0 /* timer0 */
#define IRQ_NR_TIMER_CLKEVT IRQ_TIMER0
#define TIMER_CLKEVT_NAME "timer0"
#define TIMER_CLKSRC 1 /* timer1 */
#define IRQ_NR_TIMER_CLKSRC IRQ_TIMER1
#define TIMER_CLKSRC_NAME "timer1"
static int rk2928_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt)
{
do {
RK_TIMER_DISABLE(TIMER_CLKEVT);
RK_TIMER_SETCOUNT(TIMER_CLKEVT, cycles);
RK_TIMER_ENABLE(TIMER_CLKEVT);
} while (RK_TIMER_READVALUE(TIMER_CLKEVT) > cycles);
return 0;
}
static void rk2928_timer_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
{
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
rk2928_timer_set_next_event(24000000 / HZ - 1, evt);
break;
case CLOCK_EVT_MODE_RESUME:
case CLOCK_EVT_MODE_ONESHOT:
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
RK_TIMER_DISABLE(TIMER_CLKEVT);
break;
}
}
static struct clock_event_device rk2928_timer_clockevent = {
.name = TIMER_CLKEVT_NAME,
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.rating = 200,
.set_next_event = rk2928_timer_set_next_event,
.set_mode = rk2928_timer_set_mode,
};
static irqreturn_t rk2928_timer_clockevent_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = dev_id;
RK_TIMER_INT_CLEAR(TIMER_CLKEVT);
if (evt->mode == CLOCK_EVT_MODE_ONESHOT)
RK_TIMER_DISABLE(TIMER_CLKEVT);
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct irqaction rk2928_timer_clockevent_irq = {
.name = TIMER_CLKEVT_NAME,
.flags = IRQF_DISABLED | IRQF_TIMER,
.handler = rk2928_timer_clockevent_interrupt,
.irq = IRQ_NR_TIMER_CLKEVT,
.dev_id = &rk2928_timer_clockevent,
};
static __init int rk2928_timer_init_clockevent(void)
{
struct clock_event_device *ce = &rk2928_timer_clockevent;
struct clk *clk = clk_get(NULL, TIMER_CLKEVT_NAME);
struct clk *pclk = clk_get(NULL, "pclk_" TIMER_CLKEVT_NAME);
struct clk *pclk_periph = clk_get(NULL, "pclk_periph");
clk_set_parent(clk, pclk_periph);
clk_enable(pclk);
clk_enable(clk);
RK_TIMER_DISABLE(TIMER_CLKEVT);
setup_irq(rk2928_timer_clockevent_irq.irq, &rk2928_timer_clockevent_irq);
ce->irq = rk2928_timer_clockevent_irq.irq;
ce->cpumask = cpu_all_mask;
clockevents_config_and_register(ce, clk_get_rate(clk), 0xF, 0xFFFFFFFF);
return 0;
}
static cycle_t rk2928_timer_read(struct clocksource *cs)
{
return ~RK_TIMER_READVALUE(TIMER_CLKSRC);
}
#define MASK (u32)~0
static struct clocksource rk2928_timer_clocksource = {
.name = TIMER_CLKSRC_NAME,
.rating = 200,
.read = rk2928_timer_read,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static void __init rk2928_timer_init_clocksource(void)
{
static char err[] __initdata = KERN_ERR "%s: can't register clocksource!\n";
struct clocksource *cs = &rk2928_timer_clocksource;
struct clk *clk = clk_get(NULL, TIMER_CLKSRC_NAME);
struct clk *pclk = clk_get(NULL, "pclk_" TIMER_CLKSRC_NAME);
struct clk *pclk_periph = clk_get(NULL, "pclk_periph");
clk_set_parent(clk, pclk_periph);
clk_enable(pclk);
clk_enable(clk);
RK_TIMER_DISABLE(TIMER_CLKSRC);
clk_disable(clk);
RK_TIMER_SETCOUNT(TIMER_CLKSRC, 0xFFFFFFFF);
RK_TIMER_ENABLE_FREE_RUNNING(TIMER_CLKSRC);
clk_enable(clk);
if (clocksource_register_hz(cs, clk_get_rate(clk)))
printk(err, cs->name);
}
#ifdef CONFIG_HAVE_SCHED_CLOCK
static DEFINE_CLOCK_DATA(cd);
unsigned long long notrace sched_clock(void)
{
u32 cyc = ~RK_TIMER_READVALUE(TIMER_CLKSRC);
return cyc_to_sched_clock(&cd, cyc, MASK);
}
static void notrace rk2928_update_sched_clock(void)
{
u32 cyc = ~RK_TIMER_READVALUE(TIMER_CLKSRC);
update_sched_clock(&cd, cyc, MASK);
}
static void __init rk2928_sched_clock_init(void)
{
init_sched_clock(&cd, rk2928_update_sched_clock, 32, clk_get_rate(clk_get(NULL, TIMER_CLKSRC_NAME)));
}
#endif
static void __init rk2928_timer_init(void)
{
rk2928_timer_init_clocksource();
rk2928_timer_init_clockevent();
#ifdef CONFIG_HAVE_SCHED_CLOCK
rk2928_sched_clock_init();
#endif
}
struct sys_timer rk2928_timer = {
.init = rk2928_timer_init
};

15
arch/arm/mach-rk30/Kconfig
View File

@ -28,3 +28,18 @@ config MACH_RK30_PHONE_A22
endchoice
endif
if ARCH_RK31
choice
prompt "RK31xx Board Type"
config MACH_RK31_FPGA
bool "RK31 FPGA board"
config MACH_RK3066B_SDK
bool "RK3066B(RK31) SDK board"
endchoice
endif

11
arch/arm/mach-rk30/Makefile Executable file → Normal file
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@ -1,5 +1,7 @@
ifneq ($(CONFIG_MACH_RK31_FPGA),y)
obj-y += clock.o
obj-y += clock_data.o
endif
obj-y += common.o
CFLAGS_common.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
obj-y += ddr.o
@ -16,15 +18,18 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_CPU_FREQ) += cpufreq.o
obj-$(CONFIG_CPU_FREQ) += cpufreq.o video_state.o
obj-$(CONFIG_DVFS) += dvfs.o
obj-$(CONFIG_DDR_FREQ) += ddr_freq.o
obj-$(CONFIG_RK30_I2C_INSRAM) += i2c_sram.o
obj-$(CONFIG_MACH_RK3066_SDK) += board-rk30-sdk.o board-rk30-sdk-key.o
obj-$(CONFIG_MACH_RK30_SDK) += board-rk30-sdk.o board-rk30-sdk-key.o
obj-$(CONFIG_MACH_RK3066_SDK) += board-rk30-sdk.o
obj-$(CONFIG_MACH_RK30_SDK) += board-rk30-sdk.o
obj-$(CONFIG_MACH_RK30_PHONE) += board-rk30-phone.o board-rk30-phone-key.o
obj-$(CONFIG_MACH_RK30_PHONE_PAD) += board-rk30-phonepad.o board-rk30-phonepad-key.o board-rk30-phonepad-rfkill.o
obj-$(CONFIG_MACH_RK30_PHONE_LOQUAT) += board-rk30-phone-loquat.o board-rk30-phone-loquat-key.o
obj-$(CONFIG_MACH_RK30_DS1001B) += board-rk30-ds1001b.o board-rk30-ds1001b-key.o board-rk30-ds1001b-rfkill.o
obj-$(CONFIG_MACH_RK30_PHONE_A22) += board-rk30-phone-a22.o board-rk30-phone-a22-key.o
obj-$(CONFIG_MACH_RK31_FPGA) += board-rk31-fpga.o
obj-$(CONFIG_MACH_RK3066B_SDK) += board-rk3066b-sdk.o board-rk3066b-sdk-key.o

842
arch/arm/mach-rk30/board-rk30-ds1001b-wm8326.c Executable file
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@ -0,0 +1,842 @@
#include <linux/regulator/machine.h>
#include <linux/mfd/wm831x/pdata.h>
#include <linux/mfd/wm831x/core.h>
#include <linux/mfd/wm831x/gpio.h>
#include <linux/mfd/wm831x/pmu.h>
#include <mach/sram.h>
#define cru_readl(offset) readl_relaxed(RK30_CRU_BASE + offset)
#define cru_writel(v, offset) do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
#define CRU_CLKGATE5_CON_ADDR 0x00e4
#define GRF_GPIO6L_DIR_ADDR 0x0030
#define GRF_GPIO6L_DO_ADDR 0x0068
#define GRF_GPIO6L_EN_ADDR 0x00a0
#define CRU_CLKGATE5_GRFCLK_ON 0x00100000
#define CRU_CLKGATE5_GRFCLK_OFF 0x00100010
#define GPIO6_PB1_DIR_OUT 0x02000200
#define GPIO6_PB1_DO_LOW 0x02000000
#define GPIO6_PB1_DO_HIGH 0x02000200
#define GPIO6_PB1_EN_MASK 0x02000200
#define GPIO6_PB1_UNEN_MASK 0x02000000
/* wm8326 pmu*/
#if defined(CONFIG_GPIO_WM831X)
static struct rk29_gpio_expander_info wm831x_gpio_settinginfo[] = {
{
.gpio_num = WM831X_P01, // tp3
.pin_type = GPIO_OUT,
.pin_value = GPIO_LOW,
},
{
.gpio_num = WM831X_P02, //tp4
.pin_type = GPIO_IN,
},
{
.gpio_num = WM831X_P03, //tp2
.pin_type = GPIO_OUT,
.pin_value = GPIO_HIGH,
},
{
.gpio_num = WM831X_P04, //tp1
.pin_type = GPIO_IN,
},
{
.gpio_num = WM831X_P05, //tp1
.pin_type = GPIO_IN,
},
{
.gpio_num = WM831X_P06, //tp1
.pin_type = GPIO_OUT,
.pin_value = GPIO_HIGH,
},
{
.gpio_num = WM831X_P07, //tp1
.pin_type = GPIO_IN,
},
{
.gpio_num = WM831X_P08, //tp1
.pin_type = GPIO_OUT,
.pin_value = GPIO_HIGH,
},
{
.gpio_num = WM831X_P09, //tp1
.pin_type = GPIO_OUT,
.pin_value = GPIO_HIGH,
},
{
.gpio_num = WM831X_P10, //tp1
.pin_type = GPIO_IN,
},
{
.gpio_num = WM831X_P11, //tp1
.pin_type = GPIO_OUT,
.pin_value = GPIO_HIGH,
},
{
.gpio_num = WM831X_P12,
.pin_type = GPIO_OUT,
.pin_value = GPIO_HIGH,
},
};
#endif
#if defined(CONFIG_MFD_WM831X)
#define UNLOCK_SECURITY_KEY ~(0x1<<5)
#define LOCK_SECURITY_KEY 0x00
#define PMU_POWER_SLEEP RK30_PIN6_PB1
static struct wm831x *Wm831x;
static int wm831x_pre_init(struct wm831x *parm)
{
int ret;
Wm831x = parm;
// printk("%s\n", __func__);
gpio_request(PMU_POWER_SLEEP, "NULL");
gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW);
#ifdef CONFIG_WM8326_VBAT_LOW_DETECTION
#ifdef CONFIG_BATTERY_RK30_VOL3V8
wm831x_set_bits(parm,WM831X_SYSVDD_CONTROL ,0xc077,0xc035); //pvdd power on dect vbat voltage
printk("+++The vbat is too low+++\n");
#endif
#endif
ret = wm831x_reg_read(parm, WM831X_POWER_STATE) & 0xffff;
wm831x_reg_write(parm, WM831X_POWER_STATE, (ret & 0xfff8) | 0x04);
wm831x_set_bits(parm, WM831X_RTC_CONTROL, WM831X_RTC_ALAM_ENA_MASK, 0x0400);//enable rtc alam
//BATT_FET_ENA = 1
wm831x_reg_write(parm, WM831X_SECURITY_KEY, 0x9716); // unlock security key
wm831x_set_bits(parm, WM831X_RESET_CONTROL, 0x1003, 0x1001);
ret = wm831x_reg_read(parm, WM831X_RESET_CONTROL) & 0xffff & UNLOCK_SECURITY_KEY; // enternal reset active in sleep
// printk("%s:WM831X_RESET_CONTROL=0x%x\n", __func__, ret);
wm831x_reg_write(parm, WM831X_RESET_CONTROL, ret);
wm831x_set_bits(parm,WM831X_DC1_ON_CONFIG ,0x0300,0x0000); //set dcdc mode is FCCM
wm831x_set_bits(parm,WM831X_DC2_ON_CONFIG ,0x0300,0x0000);
wm831x_set_bits(parm,WM831X_DC3_ON_CONFIG ,0x0300,0x0000);
wm831x_set_bits(parm,0x4066,0x0300,0x0000);
#ifndef CONFIG_MACH_RK3066_SDK
wm831x_set_bits(parm,WM831X_LDO10_CONTROL ,0x0040,0x0040);// set ldo10 in switch mode
#endif
wm831x_set_bits(parm,WM831X_STATUS_LED_1 ,0xc300,0xc100);// set led1 on(in manual mode)
wm831x_set_bits(parm,WM831X_STATUS_LED_2 ,0xc300,0xc000);//set led2 off(in manual mode)
wm831x_set_bits(parm,WM831X_LDO5_SLEEP_CONTROL ,0xe000,0x2000);// set ldo5 is disable in sleep mode
wm831x_set_bits(parm,WM831X_LDO1_SLEEP_CONTROL ,0xe000,0x2000);// set ldo1 is disable in sleep mode
wm831x_reg_write(parm, WM831X_SECURITY_KEY, LOCK_SECURITY_KEY); // lock security key
return 0;
}
static int wm831x_mask_interrupt(struct wm831x *Wm831x)
{
/**************************clear interrupt********************/
wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_1,0xffff);
wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_2,0xffff);
wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_3,0xffff);
wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_4,0xffff);
wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_5,0xffff);
wm831x_reg_write(Wm831x,WM831X_SYSTEM_INTERRUPTS_MASK,0xbedc); //mask interrupt which not used
return 0;
/*****************************************************************/
}
#ifdef CONFIG_WM8326_VBAT_LOW_DETECTION
static int wm831x_low_power_detection(struct wm831x *wm831x)
{
#ifdef CONFIG_BATTERY_RK30_VOL3V8
wm831x_reg_write(wm831x,WM831X_SYSTEM_INTERRUPTS_MASK,0xbe5c);
wm831x_set_bits(wm831x,WM831X_INTERRUPT_STATUS_1_MASK,0x8000,0x0000);
wm831x_set_bits(wm831x,WM831X_SYSVDD_CONTROL ,0xc077,0x0035); //set pvdd low voltage is 3.1v hi voltage is 3.3v
#else
wm831x_reg_write(wm831x,WM831X_AUXADC_CONTROL,0x803f); //open adc
wm831x_reg_write(wm831x,WM831X_AUXADC_CONTROL,0xd03f);
wm831x_reg_write(wm831x,WM831X_AUXADC_SOURCE,0x0001);
wm831x_reg_write(wm831x,WM831X_COMPARATOR_CONTROL,0x0001);
wm831x_reg_write(wm831x,WM831X_COMPARATOR_1,0x2844); //set the low power is 3.1v
wm831x_reg_write(wm831x,WM831X_INTERRUPT_STATUS_1_MASK,0x99ee);
wm831x_set_bits(wm831x,WM831X_SYSTEM_INTERRUPTS_MASK,0x0100,0x0000);
if (wm831x_reg_read(wm831x,WM831X_AUXADC_DATA)< 0x1844){
printk("The vbat is too low.\n");
wm831x_device_shutdown(wm831x);
}
#endif
return 0;
}
#endif
#define AVS_BASE 172
int wm831x_post_init(struct wm831x *Wm831x)
{
struct regulator *dcdc;
struct regulator *ldo;
ldo = regulator_get(NULL, "ldo6"); //vcc_33
regulator_set_voltage(ldo, 3300000, 3300000);
regulator_set_suspend_voltage(ldo, 3300000);
regulator_enable(ldo);
// printk("%s set ldo6 vcc_33=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "ldo4"); // vdd_11
regulator_set_voltage(ldo, 1100000, 1100000);
regulator_set_suspend_voltage(ldo, 1000000);
regulator_enable(ldo);
// printk("%s set ldo4 vdd_11=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "ldo5"); //vcc_25
regulator_set_voltage(ldo, 2500000, 2500000);
regulator_set_suspend_voltage(ldo, 2500000);
regulator_enable(ldo);
// printk("%s set ldo5 vcc_25=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
dcdc = regulator_get(NULL, "dcdc4"); // vcc_io
#ifdef CONFIG_MACH_RK3066_SDK
regulator_set_voltage(dcdc, 3300000, 3300000);
regulator_set_suspend_voltage(dcdc, 3100000);
#else
regulator_set_voltage(dcdc, 3000000, 3000000);
regulator_set_suspend_voltage(dcdc, 2800000);
#endif
regulator_enable(dcdc);
// printk("%s set dcdc4 vcc_io=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
dcdc = regulator_get(NULL, "vdd_cpu"); // vdd_arm
regulator_set_voltage(dcdc, 1100000, 1100000);
regulator_set_suspend_voltage(dcdc, 1000000);
regulator_enable(dcdc);
printk("%s set dcdc2 vdd_cpu(vdd_arm)=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
dcdc = regulator_get(NULL, "vdd_core"); // vdd_log
/* Read avs value under logic 1.1V*/
regulator_set_voltage(dcdc, 1100000, 1100000);
avs_init_val_get(1,1100000,"wm8326 init");
udelay(600);
avs_set_scal_val(AVS_BASE);
regulator_set_voltage(dcdc, 1150000, 1150000);
regulator_set_suspend_voltage(dcdc, 1000000);
regulator_enable(dcdc);
printk("%s set dcdc1 vdd_core(vdd_log)=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
dcdc = regulator_get(NULL, "dcdc3"); // vcc_ddr
regulator_set_voltage(dcdc, 1150000, 1150000);
regulator_set_suspend_voltage(dcdc, 1150000);
regulator_enable(dcdc);
// printk("%s set dcdc3 vcc_ddr=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
ldo = regulator_get(NULL, "ldo7"); // vcc28_cif
regulator_set_voltage(ldo, 2800000, 2800000);
regulator_set_suspend_voltage(ldo, 2800000);
regulator_enable(ldo);
// printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "ldo1"); // vcc18_cif
regulator_set_voltage(ldo, 1800000, 1800000);
regulator_set_suspend_voltage(ldo, 1800000);
regulator_enable(ldo);
// printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "ldo8"); // vcca_33
regulator_set_voltage(ldo, 3300000, 3300000);
regulator_set_suspend_voltage(ldo, 3300000);
regulator_enable(ldo);
// printk("%s set ldo8 vcca_33=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "ldo2"); //vccio_wl
regulator_set_voltage(ldo, 1800000, 1800000);
regulator_set_suspend_voltage(ldo, 1800000);
regulator_enable(ldo);
// printk("%s set ldo2 vccio_wl=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "ldo10"); //flash io
regulator_set_voltage(ldo, 1800000, 1800000);
regulator_set_suspend_voltage(ldo, 1800000);
regulator_enable(ldo);
// printk("%s set ldo10 vcca_wl=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
#ifdef CONFIG_MACH_RK3066_SDK
ldo = regulator_get(NULL, "ldo3"); //vdd11_hdmi
regulator_set_voltage(ldo, 1100000, 1100000);
regulator_set_suspend_voltage(ldo, 1100000);
#else
ldo = regulator_get(NULL, "ldo3"); //vdd_12
regulator_set_voltage(ldo, 1200000, 1200000);
regulator_set_suspend_voltage(ldo, 1200000);
#endif
regulator_enable(ldo);
// printk("%s set ldo3 vdd_12=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "ldo9"); //vcc_tp
regulator_set_voltage(ldo, 3300000, 3300000);
regulator_set_suspend_voltage(ldo, 3300000);
regulator_enable(ldo);
// printk("%s set ldo9 vcc_tp=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
wm831x_mask_interrupt(Wm831x);
#ifdef CONFIG_WM8326_VBAT_LOW_DETECTION
wm831x_low_power_detection(Wm831x);
#endif
printk("wm831x_post_init end");
return 0;
}
static int wm831x_last_deinit(struct wm831x *Wm831x)
{
struct regulator *ldo;
printk("%s\n", __func__);
ldo = regulator_get(NULL, "ldo1");
regulator_disable(ldo);
regulator_put(ldo);
ldo = regulator_get(NULL, "ldo2");
regulator_disable(ldo);
regulator_put(ldo);
ldo = regulator_get(NULL, "ldo3");
regulator_disable(ldo);
regulator_put(ldo);
ldo = regulator_get(NULL, "ldo4");
//regulator_disable(ldo);
regulator_put(ldo);
ldo = regulator_get(NULL, "ldo5");
// regulator_disable(ldo);
regulator_put(ldo);
ldo = regulator_get(NULL, "ldo6");
// regulator_disable(ldo);
regulator_put(ldo);
ldo = regulator_get(NULL, "ldo7");
regulator_disable(ldo);
regulator_put(ldo);
ldo = regulator_get(NULL, "ldo8");
regulator_disable(ldo);
regulator_put(ldo);
ldo = regulator_get(NULL, "ldo9");
regulator_disable(ldo);
regulator_put(ldo);
ldo = regulator_get(NULL, "ldo10");
regulator_disable(ldo);
regulator_put(ldo);
return 0;
}
struct wm831x_status_pdata wm831x_status_platdata[WM831X_MAX_STATUS] = {
{
.default_src = WM831X_STATUS_OTP,
.name = "wm831x_status0",
.default_trigger = "wm831x_otp",
},
{
.default_src = WM831X_STATUS_POWER,
.name = "wm831x_status1",
.default_trigger = "wm831x_power",
},
};
static struct regulator_consumer_supply dcdc1_consumers[] = {
{
.supply = "vdd_core",
}
};
static struct regulator_consumer_supply dcdc2_consumers[] = {
{
.supply = "vdd_cpu",
}
};
static struct regulator_consumer_supply dcdc3_consumers[] = {
{
.supply = "dcdc3",
}
};
static struct regulator_consumer_supply dcdc4_consumers[] = {
{
.supply = "dcdc4",
}
};
#if 0
static struct regulator_consumer_supply epe1_consumers[] = {
{
.supply = "epe1",
}
};
static struct regulator_consumer_supply epe2_consumers[] = {
{
.supply = "epe2",
}
};
#endif
static struct regulator_consumer_supply ldo1_consumers[] = {
{
.supply = "ldo1",
}
};
static struct regulator_consumer_supply ldo2_consumers[] = {
{
.supply = "ldo2",
}
};
static struct regulator_consumer_supply ldo3_consumers[] = {
{
.supply = "ldo3",
}
};
static struct regulator_consumer_supply ldo4_consumers[] = {
{
.supply = "ldo4",
}
};
static struct regulator_consumer_supply ldo5_consumers[] = {
{
.supply = "ldo5",
}
};
static struct regulator_consumer_supply ldo6_consumers[] = {
{
.supply = "ldo6",
}
};
static struct regulator_consumer_supply ldo7_consumers[] = {
{
.supply = "ldo7",
}
};
static struct regulator_consumer_supply ldo8_consumers[] = {
{
.supply = "ldo8",
}
};
static struct regulator_consumer_supply ldo9_consumers[] = {
{
.supply = "ldo9",
}
};
static struct regulator_consumer_supply ldo10_consumers[] = {
{
.supply = "ldo10",
}
};
static struct regulator_consumer_supply ldo11_consumers[] = {
{
.supply = "ldo11",
}
};
struct regulator_init_data wm831x_regulator_init_dcdc[WM831X_MAX_DCDC] = {
{
.constraints = {
.name = "DCDC1",
.min_uV = 600000,
.max_uV = 1800000, //0.6-1.8V
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(dcdc1_consumers),
.consumer_supplies = dcdc1_consumers,
},
{
.constraints = {
.name = "DCDC2",
.min_uV = 600000,
.max_uV = 1800000, //0.6-1.8V
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(dcdc2_consumers),
.consumer_supplies = dcdc2_consumers,
},
{
.constraints = {
.name = "DCDC3",
.min_uV = 850000,
.max_uV = 3400000, //0.85-3.4V
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(dcdc3_consumers),
.consumer_supplies = dcdc3_consumers,
},
{
.constraints = {
.name = "DCDC4",
.min_uV = 850000,
.max_uV = 3400000, //0.85-3.4V
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(dcdc4_consumers),
.consumer_supplies = dcdc4_consumers,
},
};
#if 0
struct regulator_init_data wm831x_regulator_init_epe[WM831X_MAX_EPE] = {
{
.constraints = {
.name = "EPE1",
.min_uV = 1200000,
.max_uV = 3000000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(epe1_consumers),
.consumer_supplies = epe1_consumers,
},
{
.constraints = {
.name = "EPE2",
.min_uV = 1200000,
.max_uV = 3000000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(epe2_consumers),
.consumer_supplies = epe2_consumers,
},
};
#endif
struct regulator_init_data wm831x_regulator_init_ldo[WM831X_MAX_LDO] = {
{
.constraints = {
.name = "LDO1",
.min_uV = 900000,
.max_uV = 3300000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo1_consumers),
.consumer_supplies = ldo1_consumers,
},
{
.constraints = {
.name = "LDO2",
.min_uV = 900000,
.max_uV = 3300000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
.consumer_supplies = ldo2_consumers,
},
{
.constraints = {
.name = "LDO3",
.min_uV = 900000,
.max_uV = 3300000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo3_consumers),
.consumer_supplies = ldo3_consumers,
},
{
.constraints = {
.name = "LDO4",
.min_uV = 900000,
.max_uV = 3300000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo4_consumers),
.consumer_supplies = ldo4_consumers,
},
{
.constraints = {
.name = "LDO5",
.min_uV = 900000,
.max_uV = 3300000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo5_consumers),
.consumer_supplies = ldo5_consumers,
},
{
.constraints = {
.name = "LDO6",
.min_uV = 900000,
.max_uV = 3300000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo6_consumers),
.consumer_supplies = ldo6_consumers,
},
{
.constraints = {
.name = "LDO7",
.min_uV = 1000000,
.max_uV = 3500000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo7_consumers),
.consumer_supplies = ldo7_consumers,
},
{
.constraints = {
.name = "LDO8",
.min_uV = 1000000,
.max_uV = 3500000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo8_consumers),
.consumer_supplies = ldo8_consumers,
},
{
.constraints = {
.name = "LDO9",
.min_uV = 1000000,
.max_uV = 3500000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo9_consumers),
.consumer_supplies = ldo9_consumers,
},
{
.constraints = {
.name = "LDO10",
.min_uV = 1000000,
.max_uV = 3500000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo10_consumers),
.consumer_supplies = ldo10_consumers,
},
{
.constraints = {
.name = "LDO11",
.min_uV = 800000,
.max_uV = 1550000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo11_consumers),
.consumer_supplies = ldo11_consumers,
},
};
static int wm831x_init_pin_type(struct wm831x *wm831x)
{
struct wm831x_pdata *pdata;
struct rk29_gpio_expander_info *wm831x_gpio_settinginfo;
uint16_t wm831x_settingpin_num;
int i;
if (!wm831x || !wm831x->dev)
goto out;
pdata = wm831x->dev->platform_data;
if (!pdata)
goto out;
wm831x_gpio_settinginfo = pdata->settinginfo;
if (!wm831x_gpio_settinginfo)
goto out;
wm831x_settingpin_num = pdata->settinginfolen;
for (i = 0; i < wm831x_settingpin_num; i++) {
if (wm831x_gpio_settinginfo[i].pin_type == GPIO_IN) {
wm831x_set_bits(wm831x,
WM831X_GPIO1_CONTROL + i,
WM831X_GPN_DIR_MASK | WM831X_GPN_TRI_MASK,
1 << WM831X_GPN_DIR_SHIFT | 1 << WM831X_GPN_TRI_SHIFT);
if (i == 1) {
wm831x_set_bits(wm831x,
WM831X_GPIO1_CONTROL + i,
WM831X_GPN_POL_MASK,
0x0400);
wm831x_set_bits(wm831x,
WM831X_GPIO1_CONTROL + i,
WM831X_GPN_FN_MASK,
0x0003);
} // set gpio2 sleep/wakeup
if (i == 9) {
wm831x_set_bits(wm831x,
WM831X_GPIO1_CONTROL + i,
WM831X_GPN_PULL_MASK,
0x0000); //disable pullup/down
wm831x_set_bits(wm831x,
WM831X_GPIO1_CONTROL + i,
WM831X_GPN_PWR_DOM_MASK,
0x0800);
wm831x_set_bits(wm831x,
WM831X_GPIO1_CONTROL + i,
WM831X_GPN_ENA_MASK,
0x0000);
} //set gpio10 as adc input
} else {
wm831x_set_bits(wm831x,
WM831X_GPIO1_CONTROL + i,
WM831X_GPN_DIR_MASK | WM831X_GPN_TRI_MASK,
1 << WM831X_GPN_TRI_SHIFT);
if (wm831x_gpio_settinginfo[i].pin_value == GPIO_HIGH) {
wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, 1 << i, 1 << i);
} else {
wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, 1 << i, 0 << i);
}
if (i == 2) {
wm831x_set_bits(wm831x,
WM831X_GPIO1_CONTROL + i,
WM831X_GPN_PWR_DOM_MASK | WM831X_GPN_POL_MASK |WM831X_GPN_FN_MASK,
1 << WM831X_GPN_POL_SHIFT | 1 << WM831X_GPN_PWR_DOM_SHIFT | 1 << 0);
} // set gpio3 as clkout output 32.768K
}
}
#if 0
for (i = 0; i < pdata->gpio_pin_num; i++) {
wm831x_set_bits(wm831x,
WM831X_GPIO1_CONTROL + i,
WM831X_GPN_PULL_MASK | WM831X_GPN_POL_MASK | WM831X_GPN_OD_MASK | WM831X_GPN_TRI_MASK,
1 << WM831X_GPN_POL_SHIFT | 1 << WM831X_GPN_TRI_SHIFT);
ret = wm831x_reg_read(wm831x, WM831X_GPIO1_CONTROL + i);
printk("Gpio%d Pin Configuration = %x\n", i, ret);
}
#endif
out:
return 0;
}
void __sramfunc board_pmu_suspend(void)
{
cru_writel(CRU_CLKGATE5_GRFCLK_ON,CRU_CLKGATE5_CON_ADDR); //open grf clk
grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
grf_writel(GPIO6_PB1_DO_HIGH, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output low
grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
}
void __sramfunc board_pmu_resume(void)
{
grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
grf_writel(GPIO6_PB1_DO_LOW, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output high
grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
#ifdef CONFIG_CLK_SWITCH_TO_32K
sram_32k_udelay(10000);
#else
sram_udelay(10000);
#endif
}
static struct wm831x_pdata wm831x_platdata = {
/** Called before subdevices are set up */
.pre_init = wm831x_pre_init,
/** Called after subdevices are set up */
.post_init = wm831x_post_init,
/** Called before subdevices are power down */
.last_deinit = wm831x_last_deinit,
#if defined(CONFIG_GPIO_WM831X)
.gpio_base = WM831X_GPIO_EXPANDER_BASE,
.gpio_pin_num = WM831X_TOTOL_GPIO_NUM,
.settinginfo = wm831x_gpio_settinginfo,
.settinginfolen = ARRAY_SIZE(wm831x_gpio_settinginfo),
.pin_type_init = wm831x_init_pin_type,
.irq_base = NR_GIC_IRQS + NR_GPIO_IRQS,
#endif
/** LED1 = 0 and so on */
.status = { &wm831x_status_platdata[0], &wm831x_status_platdata[1] },
/** DCDC1 = 0 and so on */
.dcdc = {
&wm831x_regulator_init_dcdc[0],
&wm831x_regulator_init_dcdc[1],
&wm831x_regulator_init_dcdc[2],
&wm831x_regulator_init_dcdc[3],
},
/** EPE1 = 0 and so on */
//.epe = { &wm831x_regulator_init_epe[0], &wm831x_regulator_init_epe[1] },
/** LDO1 = 0 and so on */
.ldo = {
&wm831x_regulator_init_ldo[0],
&wm831x_regulator_init_ldo[1],
&wm831x_regulator_init_ldo[2],
&wm831x_regulator_init_ldo[3],
&wm831x_regulator_init_ldo[4],
&wm831x_regulator_init_ldo[5],
&wm831x_regulator_init_ldo[6],
&wm831x_regulator_init_ldo[7],
&wm831x_regulator_init_ldo[8],
&wm831x_regulator_init_ldo[9],
&wm831x_regulator_init_ldo[10],
},
};
#endif

2
arch/arm/mach-rk30/board-rk30-ds1001b.c
View File

@ -1326,7 +1326,7 @@ static struct i2c_board_info __initdata i2c0_info[] = {
#endif
#ifdef CONFIG_I2C1_RK30
#include "board-rk30-sdk-wm8326.c"
#include "board-rk30-ds1001b-wm8326.c"
static struct i2c_board_info __initdata i2c1_info[] = {
#if defined (CONFIG_MFD_WM831X_I2C)

10
arch/arm/mach-rk30/board-rk30-phone-twl60xx.c
View File

@ -743,14 +743,16 @@ static struct twl4030_power_data tps80032_scripts_data __initdata = {
void twl60xx_pmu_early_suspend(struct regulator_dev *rdev)
{
printk("%s\n", __func__);
twl_reg_write(REG_INT_MSK_STS_A,TWL_MODULE_PIH, 0x00); //open vlow interrupt
int ret;
ret = twl_reg_read(REG_INT_MSK_STS_A,TWL_MODULE_PIH);
twl_reg_write(REG_INT_MSK_STS_A,TWL_MODULE_PIH, ret & (~(1 << 2))); //open vlow interrupt
}
void twl60xx_pmu_early_resume(struct regulator_dev *rdev)
{
printk("%s\n", __func__);
twl_reg_write(REG_INT_MSK_STS_A,TWL_MODULE_PIH, 0x04); //close vlow interrupt
int ret;
ret = twl_reg_read(REG_INT_MSK_STS_A,TWL_MODULE_PIH);
twl_reg_write(REG_INT_MSK_STS_A,TWL_MODULE_PIH, ret |(1 << 2)); //close vlow interrupt
}
#else
void twl60xx_pmu_early_suspend(struct regulator_dev *rdev)

139
arch/arm/mach-rk30/board-rk30-phone.c
View File

@ -876,15 +876,37 @@ static int lis3dh_init_platform_hw(void)
return 0;
}
static struct gsensor_platform_data lis3dh_info = {
.model = lis3dh,
.swap_xy = 0,
.swap_xyz = 1,
static struct sensor_platform_data lis3dh_info = {
.type = SENSOR_TYPE_ACCEL,
.irq_enable = 1,
.poll_delay_ms = 30,
.init_platform_hw = lis3dh_init_platform_hw,
.orientation = {-1, 0, 0, 0, 0, 1, 0, -1, 0},
.orientation = {0, 1, 0, 0, 0, -1, 1, 0, 0},
};
#endif
#if defined (CONFIG_GS_KXTIK)
#define KXTIK_INT_PIN RK30_PIN4_PC0
static int kxtik_init_platform_hw(void)
{
rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
return 0;
}
static struct sensor_platform_data kxtik_info = {
.type = SENSOR_TYPE_ACCEL,
.irq_enable = 1,
.poll_delay_ms = 30,
.init_platform_hw = kxtik_init_platform_hw,
.orientation = {0, 1, 0, 0, 0, -1, 1, 0, 0},
};
#endif
#if defined (CONFIG_RK_HEADSET_DET) || defined (CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET)
@ -980,63 +1002,51 @@ static struct sensor_platform_data l3g4200d_info = {
#endif
#ifdef CONFIG_LS_CM3217
#define CM3217_POWER_PIN INVALID_GPIO
#define CM3217_IRQ_PIN INVALID_GPIO
static int cm3217_init_hw(void)
{
#if 0
if (gpio_request(CM3217_POWER_PIN, NULL) != 0) {
gpio_free(CM3217_POWER_PIN);
printk("%s: request cm3217 power pin error\n", __func__);
return -EIO;
}
gpio_pull_updown(CM3217_POWER_PIN, PullDisable);
if (gpio_request(CM3217_IRQ_PIN, NULL) != 0) {
gpio_free(CM3217_IRQ_PIN);
printk("%s: request cm3217 int pin error\n", __func__);
return -EIO;
}
gpio_pull_updown(CM3217_IRQ_PIN, PullDisable);
#endif
return 0;
}
static void cm3217_exit_hw(void)
{
#if 0
gpio_free(CM3217_POWER_PIN);
gpio_free(CM3217_IRQ_PIN);
#endif
return;
}
static struct cm3217_platform_data cm3217_info = {
.irq_pin = CM3217_IRQ_PIN,
.power_pin = CM3217_POWER_PIN,
.init_platform_hw = cm3217_init_hw,
.exit_platform_hw = cm3217_exit_hw,
static struct sensor_platform_data cm3217_info = {
.type = SENSOR_TYPE_LIGHT,
.irq_enable = 0,
.poll_delay_ms = 500,
};
#endif
#if defined(CONFIG_PS_AL3006)
static struct sensor_platform_data proximity_info = {
static struct sensor_platform_data proximity_al3006_info = {
.type = SENSOR_TYPE_PROXIMITY,
.irq_enable = 1,
.poll_delay_ms = 200,
};
#endif
#if defined(CONFIG_PS_STK3171)
static struct sensor_platform_data proximity_stk3171_info = {
.type = SENSOR_TYPE_PROXIMITY,
.irq_enable = 1,
.poll_delay_ms = 200,
};
#endif
#if defined(CONFIG_LS_AL3006)
static struct sensor_platform_data light_info = {
static struct sensor_platform_data light_al3006_info = {
.type = SENSOR_TYPE_LIGHT,
.irq_enable = 1,
.poll_delay_ms = 200,
};
#endif
#if defined(CONFIG_LS_STK3171)
static struct sensor_platform_data light_stk3171_info = {
.type = SENSOR_TYPE_LIGHT,
.irq_enable = 1,
.poll_delay_ms = 200,
};
#endif
#ifdef CONFIG_FB_ROCKCHIP
@ -1685,7 +1695,7 @@ static struct i2c_board_info __initdata i2c0_info[] = {
#endif
#if defined (CONFIG_GS_LIS3DH)
{
.type = "lis3dh",
.type = "gs_lis3dh",
.addr = 0x19,
.flags = 0,
.irq = LIS3DH_INT_PIN,
@ -1693,6 +1703,17 @@ static struct i2c_board_info __initdata i2c0_info[] = {
},
#endif
#if defined (CONFIG_GS_KXTIK)
{
.type = "gs_kxtik",
.addr = 0x0F,
.flags = 0,
.irq = KXTIK_INT_PIN,
.platform_data = &kxtik_info,
},
#endif
#if defined (CONFIG_COMPASS_AK8975)
{
.type = "ak8975",
@ -1726,9 +1747,19 @@ static struct i2c_board_info __initdata i2c0_info[] = {
.addr = 0x1c, //sel = 0; if sel =1, then addr = 0x1D
.flags = 0,
.irq = RK30_PIN6_PA2,
.platform_data = &light_info,
.platform_data = &light_al3006_info,
},
#endif
#if defined (CONFIG_LS_STK3171)
{
.type = "ls_stk3171",
.addr = 0x48,
.flags = 0,
.irq = RK30_PIN6_PA2,
.platform_data = &light_stk3171_info,
},
#endif
#if defined (CONFIG_PS_AL3006)
{
@ -1736,10 +1767,21 @@ static struct i2c_board_info __initdata i2c0_info[] = {
.addr = 0x1c, //sel = 0; if sel =1, then addr = 0x1D
.flags = 0,
.irq = RK30_PIN6_PA2,
.platform_data = &proximity_info,
.platform_data = &proximity_al3006_info,
},
#endif
#if defined (CONFIG_PS_STK3171)
{
.type = "ps_stk3171",
.addr = 0x48,
.flags = 0,
.irq = RK30_PIN6_PA2,
.platform_data = &proximity_stk3171_info,
},
#endif
#if defined (CONFIG_SND_SOC_RK1000)
{
.type = "rk1000_i2c_codec",
@ -1848,10 +1890,9 @@ static struct i2c_board_info __initdata i2c2_info[] = {
#if defined (CONFIG_LS_CM3217)
{
.type = "lightsensor",
.type = "light_cm3217",
.addr = 0x10,
.flags = 0,
.irq = CM3217_IRQ_PIN,
.platform_data = &cm3217_info,
},
#endif

353
arch/arm/mach-rk30/board-rk30-phonepad.c
View File

@ -45,6 +45,7 @@
#include <linux/rfkill-rk.h>
#include <linux/sensor-dev.h>
#include <linux/mfd/tps65910.h>
#include <linux/regulator/rk29-pwm-regulator.h>
#include "../../../drivers/headset_observe/rk_headset.h"
#if defined(CONFIG_HDMI_RK30)
@ -71,10 +72,19 @@
#if defined(CONFIG_SEW868)
#include <linux/sew868.h>
#endif
#if defined(CONFIG_MI700)
#include <linux/mi700.h>
#endif
#if defined(CONFIG_ANDROID_TIMED_GPIO)
#include "../../../drivers/staging/android/timed_gpio.h"
#endif
#if defined(CONFIG_MT6620)
#include <linux/gps.h>
#endif
#ifdef CONFIG_THREE_FB_BUFFER
#define RK30_FB0_MEM_SIZE 12*SZ_1M
#else
@ -85,18 +95,18 @@
#ifdef CONFIG_VIDEO_RK29
/*---------------- Camera Sensor Macro Define Begin ------------------------*/
/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */
#define CONFIG_SENSOR_IIC_ADDR_0 0x78
#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 4
#define CONFIG_SENSOR_CIF_INDEX_0 1
#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_SID130B /* back camera sensor */
#define CONFIG_SENSOR_IIC_ADDR_0 0x6e
#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 3
#define CONFIG_SENSOR_CIF_INDEX_0 0 // 1
#define CONFIG_SENSOR_ORIENTATION_0 90
#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN1_PD6
#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN1_PB7
#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_L
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
@ -154,14 +164,14 @@
#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */
#define CONFIG_SENSOR_IIC_ADDR_1 0x60
#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_SIV121D /* front camera sensor 0 */
#define CONFIG_SENSOR_IIC_ADDR_1 0x66
#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 3
#define CONFIG_SENSOR_CIF_INDEX_1 0
#define CONFIG_SENSOR_CIF_INDEX_1 0
#define CONFIG_SENSOR_ORIENTATION_1 270
#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN1_PB7
#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN1_PB6
#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
@ -243,8 +253,8 @@
static void rk_cif_power(int on)
{
struct regulator *ldo_18,*ldo_28;
ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
ldo_28 = regulator_get(NULL, "vmmc"); // vcc28_cif ldo7
ldo_18 = regulator_get(NULL, "vdig1"); // vcc18_cif ldo1
if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
printk("get cif ldo failed!\n");
return;
@ -614,7 +624,7 @@ static int rk_headset_io_init(int gpio, char *iomux_name, int iomux_mode)
struct rk_headset_pdata rk_headset_info = {
.Headset_gpio = RK30_PIN0_PC7,
.headset_in_type = HEADSET_IN_HIGH,
.headset_in_type = HEADSET_IN_LOW,
.Hook_adc_chn = 2,
.hook_key_code = KEY_MEDIA,
.headset_gpio_info = {GPIO0C7_TRACECTL_SMCADDR3_NAME, GPIO0C_GPIO0C7},
@ -960,7 +970,51 @@ struct platform_device rk30_device_sew868 = {
}
};
#endif
#if defined(CONFIG_MI700)
#define BP_POWER RK29_PIN6_PB1
#define BP_RESET RK29_PIN6_PC7
static int mi700_io_init(void)
{
int result;
result = gpio_request(BP_RESET, NULL);
if (result)
{
gpio_free(BP_RESET);
printk("failed to request BP_RESET gpio\n");
}
result = gpio_request(BP_POWER, NULL);
if (result)
{
gpio_free(BP_POWER);
printk("failed to request BP_POWER gpio\n");
}
return 0;
}
static int mi700_io_deinit(void)
{
gpio_free(BP_RESET);
gpio_free(BP_POWER);
return 0;
}
struct rk29_mi700_data rk29_mi700_info = {
.io_init = mi700_io_init,
.io_deinit = mi700_io_deinit,
.bp_power = RK29_PIN6_PB1,//RK29_PIN0_PB4,
.bp_reset = RK29_PIN6_PC7,//RK29_PIN0_PB3,
.bp_wakeup_ap = RK29_PIN6_PC6,//RK29_PIN0_PC2,
.ap_wakeup_bp = NULL,//RK29_PIN0_PB0,
};
struct platform_device rk29_device_mi700 = {
.name = "MI700",
.id = -1,
.dev = {
.platform_data = &rk29_mi700_info,
}
};
#endif
/*MMA8452 gsensor*/
#if defined (CONFIG_GS_MMA8452)
#define MMA8452_INT_PIN RK30_PIN4_PC0
@ -995,8 +1049,27 @@ static struct sensor_platform_data lis3dh_info = {
.irq_enable = 1,
.poll_delay_ms = 30,
.init_platform_hw = lis3dh_init_platform_hw,
.orientation = {-1, 0, 0, 0, 0, 1, 0, -1, 0},
.orientation = {-1, 0, 0, 0, 0, -1, 0, 1, 0},
};
#endif
#if defined (CONFIG_GS_KXTIK)
#define KXTIK_INT_PIN RK30_PIN4_PC0
static int kxtik_init_platform_hw(void)
{
rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
return 0;
}
static struct sensor_platform_data kxtik_info = {
.type = SENSOR_TYPE_ACCEL,
.irq_enable = 1,
.poll_delay_ms = 30,
.init_platform_hw = kxtik_init_platform_hw,
.orientation = {0, 1, 0, 0, 0, -1, 1, 0, 0},
};
#endif
#if defined (CONFIG_COMPASS_AK8975)
static struct sensor_platform_data akm8975_info =
@ -1007,9 +1080,9 @@ static struct sensor_platform_data akm8975_info =
.m_layout =
{
{
{1, 0, 0},
{0, 1, 0},
{0, 0, 1},
{1, 0, 0},
{0, 0, -1},
},
{
@ -1050,7 +1123,7 @@ static struct sensor_platform_data l3g4200d_info = {
.type = SENSOR_TYPE_GYROSCOPE,
.irq_enable = 1,
.poll_delay_ms = 30,
.orientation = {0, 1, 0, -1, 0, 0, 0, 0, 1},
.orientation = {0, 1, 0, -1, 0, 0, 0, 0, -1},
.init_platform_hw = l3g4200d_init_platform_hw,
.x_min = 40,//x_min,y_min,z_min = (0-100) according to hardware
.y_min = 40,
@ -1068,6 +1141,42 @@ static struct sensor_platform_data cm3217_info = {
#endif
#if defined(CONFIG_PS_AL3006)
static struct sensor_platform_data proximity_al3006_info = {
.type = SENSOR_TYPE_PROXIMITY,
.irq_enable = 1,
.poll_delay_ms = 200,
};
#endif
#if defined(CONFIG_PS_STK3171)
static struct sensor_platform_data proximity_stk3171_info = {
.type = SENSOR_TYPE_PROXIMITY,
.irq_enable = 1,
.poll_delay_ms = 200,
};
#endif
#if defined(CONFIG_LS_AL3006)
static struct sensor_platform_data light_al3006_info = {
.type = SENSOR_TYPE_LIGHT,
.irq_enable = 1,
.poll_delay_ms = 200,
};
#endif
#if defined(CONFIG_LS_STK3171)
static struct sensor_platform_data light_stk3171_info = {
.type = SENSOR_TYPE_LIGHT,
.irq_enable = 1,
.poll_delay_ms = 200,
};
#endif
#ifdef CONFIG_FB_ROCKCHIP
#define LCD_CS_MUX_NAME GPIO4C7_SMCDATA7_TRACEDATA7_NAME
@ -1303,6 +1412,7 @@ static struct platform_device device_ion = {
#endif
#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK30_PIN6_PB2
#define RK29SDK_WIFI_SDIO_CARD_INT RK30_PIN3_PD2
#endif //endif ---#ifdef CONFIG_SDMMC_RK29
@ -1358,6 +1468,12 @@ struct rk29_sdmmc_platform_data default_sdmmc0_data = {
#else
.use_dma = 0,
#endif
#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
.status = rk29sdk_wifi_mmc0_status,
.register_status_notify = rk29sdk_wifi_mmc0_status_register,
#endif
.detect_irq = RK30_PIN3_PB6, // INVALID_GPIO
.enable_sd_wakeup = 0,
@ -1422,7 +1538,7 @@ struct rk29_sdmmc_platform_data default_sdmmc1_data = {
#endif
#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
#ifdef CONFIG_WIFI_CONTROL_FUNC
#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
.status = rk29sdk_wifi_status,
.register_status_notify = rk29sdk_wifi_status_register,
#endif
@ -1436,6 +1552,10 @@ struct rk29_sdmmc_platform_data default_sdmmc1_data = {
.write_prt = INVALID_GPIO,
#endif
#if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
.sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
#endif
#else
.detect_irq = INVALID_GPIO,
.enable_sd_wakeup = 0,
@ -1466,16 +1586,9 @@ static struct platform_device rk30_device_adc_battery = {
},
};
#endif
#if CONFIG_RK30_PWM_REGULATOR
struct pwm_platform_data {
int pwm_id;
int pwm_gpio;
//char pwm_iomux_name[50];
char* pwm_iomux_name;
unsigned int pwm_iomux_pwm;
int pwm_iomux_gpio;
int pwm_voltage;
struct regulator_init_data *init_data;
#ifdef CONFIG_RK30_PWM_REGULATOR
const static int pwm_voltage_map[] = {
1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
};
static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
@ -1507,6 +1620,11 @@ static struct pwm_platform_data pwm_regulator_info[1] = {
.pwm_iomux_pwm = GPIO0D_PWM3,
.pwm_iomux_gpio = GPIO0D_GPIO0D6,
.pwm_voltage = 1100000,
.suspend_voltage = 1050000,
.min_uV = 1000000,
.max_uV = 1400000,
.coefficient = 455, //45.5%
.pwm_voltage_map = pwm_voltage_map,
.init_data = &pwm_regulator_init_dcdc[0],
},
};
@ -1608,9 +1726,14 @@ static struct platform_device *devices[] __initdata = {
#ifdef CONFIG_RK_IRDA
&irda_device,
#endif
#ifdef CONFIG_WIFI_CONTROL_FUNC
#if defined(CONFIG_WIFI_CONTROL_FUNC)||defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
&rk29sdk_wifi_device,
#endif
#if defined(CONFIG_MT6620)
&mt3326_device_gps,
#endif
#ifdef CONFIG_RK29_SUPPORT_MODEM
&rk30_device_modem,
#endif
@ -1629,6 +1752,9 @@ static struct platform_device *devices[] __initdata = {
#if defined (CONFIG_RK_HEADSET_DET) || defined (CONFIG_RK_HEADSET_IRQ_HOOK_ADC_DET)
&rk_device_headset,
#endif
#if defined(CONFIG_MI700)
&rk29_device_mi700,
#endif
#ifdef CONFIG_BATTERY_RK30_ADC
&rk30_device_adc_battery,
#endif
@ -1658,6 +1784,18 @@ static struct i2c_board_info __initdata i2c0_info[] = {
.platform_data = &lis3dh_info,
},
#endif
#if defined (CONFIG_GS_KXTIK)
{
.type = "gs_kxtik",
.addr = 0x0F,
.flags = 0,
.irq = KXTIK_INT_PIN,
.platform_data = &kxtik_info,
},
#endif
#if defined (CONFIG_COMPASS_AK8975)
{
.type = "ak8975",
@ -1676,6 +1814,56 @@ static struct i2c_board_info __initdata i2c0_info[] = {
.platform_data = &l3g4200d_info,
},
#endif
#if defined (CONFIG_INPUT_LPSENSOR_AL3006)
{
.type = "al3006",
.addr = 0x1c, //sel = 0; if sel =1, then addr = 0x1D
.flags = 0,
.irq = RK30_PIN6_PA2,
},
#endif
#if defined (CONFIG_LS_AL3006)
{
.type = "light_al3006",
.addr = 0x1c, //sel = 0; if sel =1, then addr = 0x1D
.flags = 0,
.irq = RK30_PIN6_PA2,
.platform_data = &light_al3006_info,
},
#endif
#if defined (CONFIG_LS_STK3171)
{
.type = "ls_stk3171",
.addr = 0x48,
.flags = 0,
.irq = RK30_PIN6_PA2,
.platform_data = &light_stk3171_info,
},
#endif
#if defined (CONFIG_PS_AL3006)
{
.type = "proximity_al3006",
.addr = 0x1c, //sel = 0; if sel =1, then addr = 0x1D
.flags = 0,
.irq = RK30_PIN6_PA2,
.platform_data = &proximity_al3006_info,
},
#endif
#if defined (CONFIG_PS_STK3171)
{
.type = "ps_stk3171",
.addr = 0x48,
.flags = 0,
.irq = RK30_PIN6_PA2,
.platform_data = &proximity_stk3171_info,
},
#endif
#if defined (CONFIG_SND_SOC_RK1000)
{
.type = "rk1000_i2c_codec",
@ -1745,6 +1933,9 @@ static struct i2c_board_info __initdata i2c0_info[] = {
};
#endif
#define PMIC_TYPE_WM8326 1
#define PMIC_TYPE_TPS65910 2
int __sramdata g_pmic_type = 0;
#ifdef CONFIG_I2C1_RK30
#ifdef CONFIG_MFD_WM831X_I2C
#include "board-rk30-sdk-wm8326.c"
@ -1776,6 +1967,78 @@ static struct i2c_board_info __initdata i2c1_info[] = {
};
#endif
void __sramfunc board_pmu_suspend(void)
{
#if defined (CONFIG_MFD_WM831X_I2C)
if(g_pmic_type == PMIC_TYPE_WM8326)
board_pmu_wm8326_suspend();
#endif
#if defined (CONFIG_MFD_TPS65910)
if(g_pmic_type == PMIC_TYPE_TPS65910)
board_pmu_tps65910_suspend();
#endif
}
void __sramfunc board_pmu_resume(void)
{
#if defined (CONFIG_MFD_WM831X_I2C)
if(g_pmic_type == PMIC_TYPE_WM8326)
board_pmu_wm8326_resume();
#endif
#if defined (CONFIG_MFD_TPS65910)
if(g_pmic_type == PMIC_TYPE_TPS65910)
board_pmu_tps65910_resume();
#endif
}
int __sramdata gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
void __sramfunc rk30_pwm_logic_suspend_voltage(void)
{
#ifdef CONFIG_RK30_PWM_REGULATOR
// int gpio0d7_iomux,gpio0d7_do,gpio0d7_dir,gpio0d7_en;
sram_udelay(10000);
gpio0d7_iomux = readl_relaxed(GRF_GPIO0D_IOMUX);
gpio0d7_do = grf_readl(GRF_GPIO0H_DO);
gpio0d7_dir = grf_readl(GRF_GPIO0H_DIR);
gpio0d7_en = grf_readl(GRF_GPIO0H_EN);
writel_relaxed((1<<30), GRF_GPIO0D_IOMUX);
grf_writel((1<<31)|(1<<15), GRF_GPIO0H_DIR);
grf_writel((1<<31)|(1<<15), GRF_GPIO0H_DO);
grf_writel((1<<31)|(1<<15), GRF_GPIO0H_EN);
#endif
}
void __sramfunc rk30_pwm_logic_resume_voltage(void)
{
#ifdef CONFIG_RK30_PWM_REGULATOR
writel_relaxed((1<<30)|gpio0d7_iomux, GRF_GPIO0D_IOMUX);
grf_writel((1<<31)|gpio0d7_en, GRF_GPIO0H_EN);
grf_writel((1<<31)|gpio0d7_dir, GRF_GPIO0H_DIR);
grf_writel((1<<31)|gpio0d7_do, GRF_GPIO0H_DO);
sram_udelay(10000);
#endif
}
extern void pwm_suspend_voltage(void);
extern void pwm_resume_voltage(void);
void rk30_pwm_suspend_voltage_set(void)
{
#ifdef CONFIG_RK30_PWM_REGULATOR
pwm_suspend_voltage();
#endif
}
void rk30_pwm_resume_voltage_set(void)
{
#ifdef CONFIG_RK30_PWM_REGULATOR
pwm_resume_voltage();
#endif
}
#ifdef CONFIG_I2C2_RK30
static struct i2c_board_info __initdata i2c2_info[] = {
#if defined (CONFIG_TOUCHSCREEN_GT8XX)
@ -1798,7 +2061,7 @@ static struct i2c_board_info __initdata i2c2_info[] = {
#endif
#if defined (CONFIG_LS_CM3217)
{
.type = "lightsensor",
.type = "light_cm3217",
.addr = 0x10,
.flags = 0,
.platform_data = &cm3217_info,
@ -1902,16 +2165,19 @@ void rk30_pm_power_off(void)
arm_pm_restart(0, NULL);
}
#endif
#if PMIC_IS_WM831X
#if defined(CONFIG_MFD_WM831X)
wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
wm831x_device_shutdown(Wm831x);//wm8326 shutdown
#endif
#else
#if defined(CONFIG_MFD_TPS65910)
tps65910_device_shutdown();//tps65910 shutdown
#endif
#endif
#if defined(CONFIG_MFD_WM831X)
if(g_pmic_type == PMIC_TYPE_WM8326)
{
wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
wm831x_device_shutdown(Wm831x);//wm8326 shutdown
}
#endif
#if defined(CONFIG_MFD_TPS65910)
if(g_pmic_type == PMIC_TYPE_TPS65910)
{
tps65910_device_shutdown();//tps65910 shutdown
}
#endif
gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
while(1);
}
@ -1938,6 +2204,10 @@ static void __init machine_rk30_board_init(void)
rk29sdk_wifi_bt_gpio_control_init();
#endif
dcr_en_low();
#if defined(CONFIG_MT6620)
clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 48*1000000);
#endif
}
static void __init rk30_reserve(void)
@ -1997,7 +2267,8 @@ static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
void __init board_clock_init(void)
{
rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
//support uart 1-3Mbits/s
rk30_clock_data_init(periph_pll_default, codec_pll_768mhz, RK30_CLOCKS_DEFAULT_FLAGS | CLK_FLG_UART_1_3M);
dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);

448
arch/arm/mach-rk30/board-rk30-sdk-camera.c Normal file
View File

@ -0,0 +1,448 @@
#ifdef CONFIG_VIDEO_RK29
/*---------------- Camera Sensor Macro Define Begin ------------------------*/
/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */
#define CONFIG_SENSOR_IIC_ADDR_0 0x78
#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 4
#define CONFIG_SENSOR_CIF_INDEX_0 1
#define CONFIG_SENSOR_ORIENTATION_0 90
#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN1_PD6
#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
#define CONFIG_SENSOR_IIC_ADDR_01 0x00
#define CONFIG_SENSOR_CIF_INDEX_01 1
#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
#define CONFIG_SENSOR_ORIENTATION_01 90
#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_01 RK30_PIN1_PD6
#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
#define CONFIG_SENSOR_IIC_ADDR_02 0x00
#define CONFIG_SENSOR_CIF_INDEX_02 1
#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
#define CONFIG_SENSOR_ORIENTATION_02 90
#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_02 RK30_PIN1_PD6
#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */
#define CONFIG_SENSOR_IIC_ADDR_1 0x60
#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 3
#define CONFIG_SENSOR_CIF_INDEX_1 0
#define CONFIG_SENSOR_ORIENTATION_1 270
#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN1_PB7
#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
#define CONFIG_SENSOR_IIC_ADDR_11 0x00
#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
#define CONFIG_SENSOR_CIF_INDEX_11 0
#define CONFIG_SENSOR_ORIENTATION_11 270
#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO//RK30_PIN1_PB7
#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
#define CONFIG_SENSOR_IIC_ADDR_12 0x00
#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
#define CONFIG_SENSOR_CIF_INDEX_12 0
#define CONFIG_SENSOR_ORIENTATION_12 270
#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO//RK30_PIN1_PB7
#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
#endif //#ifdef CONFIG_VIDEO_RK29
/*---------------- Camera Sensor Configuration Macro End------------------------*/
#include "../../../drivers/media/video/rk30_camera.c"
/*---------------- Camera Sensor Macro Define End ---------*/
#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
/*****************************************************************************************
* camera devices
* author: ddl@rock-chips.com
*****************************************************************************************/
#ifdef CONFIG_VIDEO_RK29
#define CONFIG_SENSOR_POWER_IOCTL_USR 1 //define this refer to your board layout
#define CONFIG_SENSOR_RESET_IOCTL_USR 0
#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
static void rk_cif_power(int on)
{
struct regulator *ldo_18,*ldo_28;
ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
printk("get cif ldo failed!\n");
return;
}
if(on == 0){
regulator_disable(ldo_28);
regulator_put(ldo_28);
regulator_disable(ldo_18);
regulator_put(ldo_18);
mdelay(500);
}
else{
regulator_set_voltage(ldo_28, 2800000, 2800000);
regulator_enable(ldo_28);
// printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
regulator_put(ldo_28);
regulator_set_voltage(ldo_18, 1800000, 1800000);
// regulator_set_suspend_voltage(ldo, 1800000);
regulator_enable(ldo_18);
// printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
regulator_put(ldo_18);
}
}
#if CONFIG_SENSOR_POWER_IOCTL_USR
static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
{
//#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
rk_cif_power(on);
}
#endif
#if CONFIG_SENSOR_RESET_IOCTL_USR
static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
{
#error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
}
#endif
#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
{
#error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
}
#endif
#if CONFIG_SENSOR_FLASH_IOCTL_USR
static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
{
#error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
}
#endif
static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
#if CONFIG_SENSOR_POWER_IOCTL_USR
.sensor_power_cb = sensor_power_usr_cb,
#else
.sensor_power_cb = NULL,
#endif
#if CONFIG_SENSOR_RESET_IOCTL_USR
.sensor_reset_cb = sensor_reset_usr_cb,
#else
.sensor_reset_cb = NULL,
#endif
#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
.sensor_powerdown_cb = sensor_powerdown_usr_cb,
#else
.sensor_powerdown_cb = NULL,
#endif
#if CONFIG_SENSOR_FLASH_IOCTL_USR
.sensor_flash_cb = sensor_flash_usr_cb,
#else
.sensor_flash_cb = NULL,
#endif
};
#if CONFIG_SENSOR_IIC_ADDR_0
static struct reginfo_t rk_init_data_sensor_reg_0[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_1
static struct reginfo_t rk_init_data_sensor_reg_1[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
{
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_01
static struct reginfo_t rk_init_data_sensor_reg_01[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
{
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_02
static struct reginfo_t rk_init_data_sensor_reg_02[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
{
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_11
static struct reginfo_t rk_init_data_sensor_reg_11[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
{
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_12
static struct reginfo_t rk_init_data_sensor_reg_12[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
{
{0x0000, 0x00,0,0}
};
#endif
static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
{
#if CONFIG_SENSOR_IIC_ADDR_0
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_0,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_1
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_1,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_01
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_01,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_02
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_02,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_11
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_11,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_12
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_12,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
};
#include "../../../drivers/media/video/rk30_camera.c"
#endif /* CONFIG_VIDEO_RK29 */

302
arch/arm/mach-rk30/board-rk30-sdk-sdmmc.c Normal file → Executable file
View File

@ -92,7 +92,19 @@ static void rk29_sdmmc_gpio_open(int device_id, int on)
rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_GPIO3C1);
gpio_request(RK30_PIN3_PC1, "mmc1-data0");
gpio_direction_output(RK30_PIN3_PC1,GPIO_LOW);//set mmc1-data0 to low.
#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
rk29_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C_GPIO3C2);
gpio_request(RK30_PIN3_PC2, "mmc1-data1");
gpio_direction_output(RK30_PIN3_PC2,GPIO_LOW);//set mmc1-data1 to low.
rk29_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C_GPIO3C3);
gpio_request(RK30_PIN3_PC3, "mmc1-data2");
gpio_direction_output(RK30_PIN3_PC3,GPIO_LOW);//set mmc1-data2 to low.
rk29_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C_GPIO3C4);
gpio_request(RK30_PIN3_PC4, "mmc1-data3");
gpio_direction_output(RK30_PIN3_PC4,GPIO_LOW);//set mmc1-data3 to low.
#endif
mdelay(100);
}
#endif
@ -128,11 +140,13 @@ static void rk29_sdmmc_set_iomux_mmc0(unsigned int bus_width)
gpio_request(RK30_PIN3_PA7,"sdmmc-power");
gpio_direction_output(RK30_PIN3_PA7,GPIO_HIGH); //power-off
#if 0 //replace the power control into rk29_sdmmc_set_ios(); modifyed by xbw at 2012-08-12
rk29_sdmmc_gpio_open(0, 0);
gpio_direction_output(RK30_PIN3_PA7,GPIO_LOW); //power-on
rk29_sdmmc_gpio_open(0, 1);
#endif
}
break;
@ -197,9 +211,23 @@ static void rk29_sdmmc_set_iomux(int device_id, unsigned int bus_width)
#endif
static int rk29sdk_wifi_status(struct device *dev);
static int rk29sdk_wifi_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id);
//int rk29sdk_wifi_power_state = 0;
//int rk29sdk_bt_power_state = 0;
#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
static int rk29sdk_wifi_mmc0_status(struct device *dev);
static int rk29sdk_wifi_mmc0_status_register(void (*callback)(int card_presend, void *dev_id), void *dev_id);
static int rk29sdk_wifi_mmc0_cd = 0; /* wifi virtual 'card detect' status */
static void (*wifi_mmc0_status_cb)(int card_present, void *dev_id);
static void *wifi_mmc0_status_cb_devid;
int rk29sdk_wifi_power_state = 0;
int rk29sdk_bt_power_state = 0;
#endif
static int rk29sdk_wifi_cd = 0; /* wifi virtual 'card detect' status */
static void (*wifi_status_cb)(int card_present, void *dev_id);
static void *wifi_status_cb_devid;
#ifdef CONFIG_WIFI_CONTROL_FUNC
//#define RK29SDK_WIFI_BT_GPIO_POWER_N RK30_PIN3_PD0
@ -284,10 +312,6 @@ static int __init rk29sdk_init_wifi_mem(void)
return -ENOMEM;
}
static int rk29sdk_wifi_cd = 0; /* wifi virtual 'card detect' status */
static void (*wifi_status_cb)(int card_present, void *dev_id);
static void *wifi_status_cb_devid;
static int rk29sdk_wifi_status(struct device *dev)
{
return rk29sdk_wifi_cd;
@ -418,6 +442,240 @@ static struct resource resources[] = {
},
};
///////////////////////////////////////////////////////////////////////////////////
#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
#if defined(CONFIG_MACH_RK30_PHONE_PAD)
#if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
#define USE_SDMMC_CONTROLLER_FOR_WIFI 0
#define RK29SDK_WIFI_COMBO_GPIO_POWER_N RK30_PIN4_PD2
#define RK29SDK_WIFI_COMBO_GPIO_RESET_N RK30_PIN4_PD1
#define RK29SDK_WIFI_COMBO_GPIO_VDDIO RK30_PIN1_PA6
#define RK29SDK_WIFI_COMBO_GPIO_BGF_INT_B RK30_PIN1_PA7
#define RK29SDK_WIFI_COMBO_GPS_SYNC RK30_PIN3_PC7
#else
#define USE_SDMMC_CONTROLLER_FOR_WIFI 1
#define RK29SDK_WIFI_COMBO_GPIO_POWER_N RK30_PIN3_PC7
#define RK29SDK_WIFI_COMBO_GPIO_RESET_N RK30_PIN3_PD1
#define RK29SDK_WIFI_COMBO_GPIO_WIFI_INT_B RK30_PIN3_PD2
//#define RK29SDK_WIFI_COMBO_GPIO_VDDIO RK30_PIN6_PB4
#define RK29SDK_WIFI_COMBO_GPIO_BGF_INT_B RK30_PIN6_PA7
#define RK29SDK_WIFI_COMBO_GPS_SYNC RK30_PIN3_PD0
#endif
#else
#if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
#define USE_SDMMC_CONTROLLER_FOR_WIFI 0
#define RK29SDK_WIFI_COMBO_GPIO_POWER_N RK30_PIN4_PD2
#define RK29SDK_WIFI_COMBO_GPIO_RESET_N RK30_PIN4_PD1
#define RK29SDK_WIFI_COMBO_GPIO_VDDIO RK30_PIN1_PA6
#define RK29SDK_WIFI_COMBO_GPIO_BGF_INT_B RK30_PIN1_PA7
#define RK29SDK_WIFI_COMBO_GPS_SYNC RK30_PIN3_PC7
#else
#define USE_SDMMC_CONTROLLER_FOR_WIFI 1
#define RK29SDK_WIFI_COMBO_GPIO_POWER_N RK30_PIN3_PD0
#define RK29SDK_WIFI_COMBO_GPIO_RESET_N RK30_PIN3_PD1
#define RK29SDK_WIFI_COMBO_GPIO_WIFI_INT_B RK30_PIN3_PD2
#define RK29SDK_WIFI_COMBO_GPIO_VDDIO RK30_PIN6_PB4
#define RK29SDK_WIFI_COMBO_GPIO_BGF_INT_B RK30_PIN3_PC6
#define RK29SDK_WIFI_COMBO_GPS_SYNC RK30_PIN3_PC7
#endif
#endif
#define debug_combo_system 0
int rk29sdk_wifi_combo_get_BGFgpio(void)
{
return RK29SDK_WIFI_COMBO_GPIO_BGF_INT_B;
}
EXPORT_SYMBOL(rk29sdk_wifi_combo_get_BGFgpio);
int rk29sdk_wifi_combo_get_GPS_SYNC_gpio(void)
{
return RK29SDK_WIFI_COMBO_GPS_SYNC;
}
EXPORT_SYMBOL(rk29sdk_wifi_combo_get_GPS_SYNC_gpio);
static int rk29sdk_wifi_combo_module_gpio_init(void)
{
if (gpio_request(RK29SDK_WIFI_COMBO_GPIO_RESET_N, "combo-RST"))
{
pr_info("%s:request combo-RST failed\n", __func__);
return -1;
}
gpio_direction_output(RK29SDK_WIFI_COMBO_GPIO_RESET_N, GPIO_LOW);
if (gpio_request(RK29SDK_WIFI_COMBO_GPIO_POWER_N, "combo-PMUEN"))
{
pr_info("%s:request combo-PMUEN failed\n", __func__);
return -1;
}
//gpio_pull_updown(RK29SDK_WIFI_COMBO_GPIO_POWER_N,0);
//gpio_direction_input(RK29SDK_WIFI_COMBO_GPIO_POWER_N);
gpio_direction_output(RK29SDK_WIFI_COMBO_GPIO_POWER_N, GPIO_LOW);
return 0;
}
int rk29sdk_wifi_combo_module_power(int on)
{
if(on)
{
//gpio_set_value(RK29SDK_WIFI_COMBO_GPIO_VDDIO, GPIO_HIGH);
//mdelay(10);
gpio_set_value(RK29SDK_WIFI_COMBO_GPIO_POWER_N, GPIO_HIGH);
mdelay(10);
pr_info("combo-module turn on power\n");
}
else
{
gpio_set_value(RK29SDK_WIFI_COMBO_GPIO_POWER_N, GPIO_LOW);
mdelay(10);
//gpio_set_value(RK29SDK_WIFI_COMBO_GPIO_VDDIO, GPIO_LOW);
pr_info("combo-module turn off power\n");
}
return 0;
}
EXPORT_SYMBOL(rk29sdk_wifi_combo_module_power);
int rk29sdk_wifi_combo_module_reset(int on)
{
if(on)
{
gpio_set_value(RK29SDK_WIFI_COMBO_GPIO_RESET_N, GPIO_HIGH);
pr_info("combo-module reset out 1\n");
}
else
{
gpio_set_value(RK29SDK_WIFI_COMBO_GPIO_RESET_N, GPIO_LOW);
pr_info("combo-module reset out 0\n");
}
return 0;
}
EXPORT_SYMBOL(rk29sdk_wifi_combo_module_reset);
static int rk29sdk_wifi_mmc0_status(struct device *dev)
{
return rk29sdk_wifi_mmc0_cd;
}
static int rk29sdk_wifi_mmc0_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
{
if(wifi_mmc0_status_cb)
return -EAGAIN;
wifi_mmc0_status_cb = callback;
wifi_mmc0_status_cb_devid = dev_id;
return 0;
}
static int rk29sdk_wifi_status(struct device *dev)
{
return rk29sdk_wifi_cd;
}
static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
{
if(wifi_status_cb)
return -EAGAIN;
wifi_status_cb = callback;
wifi_status_cb_devid = dev_id;
return 0;
}
extern unsigned int sdio_irq_global;
int rk29sdk_wifi_power(int on)
{
pr_info("%s: %d\n", __func__, on);
if (on){
#if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
#if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
rk29_sdmmc_gpio_open(0, 1);
#else
rk29_sdmmc_gpio_open(1, 0);
mdelay(10);
rk29_sdmmc_gpio_open(1, 1);
#endif
#endif
mdelay(100);
pr_info("wifi turn on power\n");
}
else
{
#if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
#if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
rk29_sdmmc_gpio_open(0, 0);
#else
rk29_sdmmc_gpio_open(1, 0);
#endif
#endif
mdelay(100);
pr_info("wifi shut off power\n");
}
rk29sdk_wifi_power_state = on;
return 0;
}
EXPORT_SYMBOL(rk29sdk_wifi_power);
int rk29sdk_wifi_reset(int on)
{
return 0;
}
EXPORT_SYMBOL(rk29sdk_wifi_reset);
#if defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
int rk29sdk_wifi_set_carddetect(int val)
{
pr_info("%s:%d\n", __func__, val);
rk29sdk_wifi_mmc0_cd = val;
if (wifi_mmc0_status_cb){
wifi_mmc0_status_cb(val, wifi_mmc0_status_cb_devid);
}else {
pr_warning("%s,in mmc0 nobody to notify\n", __func__);
}
return 0;
}
#else
int rk29sdk_wifi_set_carddetect(int val)
{
pr_info("%s:%d\n", __func__, val);
rk29sdk_wifi_cd = val;
if (wifi_status_cb){
wifi_status_cb(val, wifi_status_cb_devid);
}else {
pr_warning("%s,in mmc1 nobody to notify\n", __func__);
}
return 0;
}
#endif
EXPORT_SYMBOL(rk29sdk_wifi_set_carddetect);
#endif /// #endif ---#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
#if defined(CONFIG_WIFI_CONTROL_FUNC)
static struct wifi_platform_data rk29sdk_wifi_control = {
.set_power = rk29sdk_wifi_power,
.set_reset = rk29sdk_wifi_reset,
@ -434,6 +692,38 @@ static struct platform_device rk29sdk_wifi_device = {
.platform_data = &rk29sdk_wifi_control,
},
};
#elif defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
#if debug_combo_system
static struct combo_module_platform_data rk29sdk_combo_module_control = {
.set_power = rk29sdk_wifi_combo_module_power,
.set_reset = rk29sdk_wifi_combo_module_reset,
};
static struct platform_device rk29sdk_combo_module_device = {
.name = "combo-system",
.id = 1,
.dev = {
.platform_data = &rk29sdk_combo_module_control,
},
};
#endif
static struct wifi_platform_data rk29sdk_wifi_control = {
.set_power = rk29sdk_wifi_power,
.set_reset = rk29sdk_wifi_reset,
.set_carddetect = rk29sdk_wifi_set_carddetect,
};
static struct platform_device rk29sdk_wifi_device = {
.name = "combo-wifi",
.id = 1,
.dev = {
.platform_data = &rk29sdk_wifi_control,
},
};
#endif

191
arch/arm/mach-rk30/board-rk30-sdk-tps65910.c
View File

@ -34,109 +34,105 @@ int tps65910_pre_init(struct tps65910 *tps65910){
int val = 0;
int i = 0;
int err = -1;
#ifdef CONFIG_RK30_PWM_REGULATOR
platform_device_register(&pwm_regulator_device[0]);
#endif
printk("%s,line=%d\n", __func__,__LINE__);
//gpio_request(PMU_POWER_SLEEP, "NULL");
//gpio_direction_output(PMU_POWER_SLEEP, GPIO_HIGH);
val = tps65910_reg_read(tps65910, TPS65910_REG_DEVCTRL2);
val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL2);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_REG_DEVCTRL2 reg\n");
printk(KERN_ERR "Unable to read TPS65910_DEVCTRL2 reg\n");
return val;
}
/* Set sleep state active high and allow device turn-off after PWRON long press */
val |= (TPS65910_DEV2_SLEEPSIG_POL | TPS65910_DEV2_PWON_LP_OFF);
val |= (DEVCTRL2_SLEEPSIG_POL_MASK | DEVCTRL2_PWON_LP_OFF_MASK);
err = tps65910_reg_write(tps65910, TPS65910_REG_DEVCTRL2, val);
err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL2, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_REG_DEVCTRL2 reg\n");
printk(KERN_ERR "Unable to write TPS65910_DEVCTRL2 reg\n");
return err;
}
#if 1
/* set PSKIP=0 */
val = tps65910_reg_read(tps65910, TPS65910_REG_DCDCCTRL);
val = tps65910_reg_read(tps65910, TPS65910_DCDCCTRL);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n");
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
//val &= ~(1 << 4);
val &= 0xFC;
// val |= 0x03;
err = tps65910_reg_write(tps65910, TPS65910_REG_DCDCCTRL, val);
val &= ~DEVCTRL_DEV_OFF_MASK;
val &= ~DEVCTRL_DEV_SLP_MASK;
err = tps65910_reg_write(tps65910, TPS65910_DCDCCTRL, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_REG_DCDCCTRL reg\n");
printk(KERN_ERR "Unable to write TPS65910_DCDCCTRL reg\n");
return err;
}
#endif
/* Set the maxinum load current */
/* VDD1 */
val = tps65910_reg_read(tps65910, TPS65910_REG_VDD1);
val = tps65910_reg_read(tps65910, TPS65910_VDD1);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_REG_VDD1 reg\n");
printk(KERN_ERR "Unable to read TPS65910_VDD1 reg\n");
return val;
}
val |= (1<<5);
val |= (0x07<<2);
err = tps65910_reg_write(tps65910, TPS65910_REG_VDD1, val);
val |= (1<<5); //when 1: 1.5 A
val |= (0x07<<2); //TSTEP[2:0] = 111 : 2.5 mV/¦Ìs(sampling 3 Mhz/5)
err = tps65910_reg_write(tps65910, TPS65910_VDD1, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_REG_VDD1 reg\n");
printk(KERN_ERR "Unable to write TPS65910_VDD1 reg\n");
return err;
}
/* VDD2 */
val = tps65910_reg_read(tps65910, TPS65910_REG_VDD2);
val = tps65910_reg_read(tps65910, TPS65910_VDD2);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_REG_VDD2 reg\n");
printk(KERN_ERR "Unable to read TPS65910_VDD2 reg\n");
return val;
}
val |= (1<<5);
err = tps65910_reg_write(tps65910, TPS65910_REG_VDD2, val);
val |= (1<<5); //when 1: 1.5 A
err = tps65910_reg_write(tps65910, TPS65910_VDD2, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_REG_VDD2 reg\n");
printk(KERN_ERR "Unable to write TPS65910_VDD2 reg\n");
return err;
}
/* VIO */
val = tps65910_reg_read(tps65910, TPS65910_REG_VIO);
val = tps65910_reg_read(tps65910, TPS65910_VIO);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_REG_VIO reg\n");
printk(KERN_ERR "Unable to read TPS65910_VIO reg\n");
return -EIO;
}
val |= (1<<6);
err = tps65910_reg_write(tps65910, TPS65910_REG_VIO, val);
val |= (1<<6); //when 01: 1.0 A
err = tps65910_reg_write(tps65910, TPS65910_VIO, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_REG_VIO reg\n");
printk(KERN_ERR "Unable to write TPS65910_VIO reg\n");
return err;
}
#if 1
/* Mask ALL interrupts */
err = tps65910_reg_write(tps65910,TPS65910_REG_INT_MSK, 0xFF);
err = tps65910_reg_write(tps65910,TPS65910_INT_MSK, 0xFF);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_REG_INT_MSK reg\n");
printk(KERN_ERR "Unable to write TPS65910_INT_MSK reg\n");
return err;
}
err = tps65910_reg_write(tps65910, TPS65910_REG_INT_MSK2, 0x03);
err = tps65910_reg_write(tps65910, TPS65910_INT_MSK2, 0x03);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_REG_INT_MSK2 reg\n");
printk(KERN_ERR "Unable to write TPS65910_INT_MSK2 reg\n");
return err;
}
/* Set RTC Power, disable Smart Reflex in DEVCTRL_REG */
#if 1
val = 0;
val |= (TPS65910_SR_CTL_I2C_SEL);
err = tps65910_reg_write(tps65910, TPS65910_REG_DEVCTRL, val);
val |= (DEVCTRL_SR_CTL_I2C_SEL_MASK);
err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
if (err) {
printk(KERN_ERR "Unable to write TPS65910_REG_DEVCTRL reg\n");
printk(KERN_ERR "Unable to write TPS65910_DEVCTRL reg\n");
return err;
}
printk(KERN_INFO "TPS65910 Set default voltage.\n");
@ -145,9 +141,9 @@ int tps65910_pre_init(struct tps65910 *tps65910){
//read sleep control register for debug
for(i=0; i<6; i++)
{
err = tps65910_reg_read(tps65910, &val, TPS65910_REG_DEVCTRL+i);
err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
if (err) {
printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n");
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return -EIO;
}
else
@ -158,65 +154,72 @@ int tps65910_pre_init(struct tps65910 *tps65910){
#if 1
//sleep control register
/*set func when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_REG_DEVCTRL);
val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n");
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val |= (1 << 1);
err = tps65910_reg_write(tps65910, TPS65910_REG_DEVCTRL, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_REG_VDIG1);
return err;
}
/* open ldo when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_REG_SLEEP_KEEP_LDO_ON);
val |= (1 << 1);
err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
/* open ldo when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_LDO_ON);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n");
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val &= 0;
err = tps65910_reg_write(tps65910, TPS65910_REG_SLEEP_KEEP_LDO_ON, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_REG_VDIG1);
return err;
}
/*set dc mode when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_REG_SLEEP_KEEP_RES_ON);
val &= 0;
err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_LDO_ON, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
/*set dc mode when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_RES_ON);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n");
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val |= 0xff;
err = tps65910_reg_write(tps65910, TPS65910_REG_SLEEP_KEEP_RES_ON, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_REG_VDIG1);
return err;
}
/*close ldo when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_REG_SLEEP_SET_LDO_OFF);
val |= 0xff;
err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_RES_ON, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
/*close ldo when in sleep mode */
val = tps65910_reg_read(tps65910, TPS65910_SLEEP_SET_LDO_OFF);
if (val<0) {
printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n");
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return val;
}
val |= 0x9B;
err = tps65910_reg_write(tps65910, TPS65910_REG_SLEEP_SET_LDO_OFF, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_REG_VDIG1);
return err;
}
val |= 0x0b;
err = tps65910_reg_write(tps65910, TPS65910_SLEEP_SET_LDO_OFF, val);
if (err) {
printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
\n", TPS65910_VDIG1);
return err;
}
#endif
#if 0
//read sleep control register for debug
for(i=0; i<6; i++)
{
err = tps65910_reg_read(tps65910, &val, TPS65910_REG_DEVCTRL+i);
err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
if (err) {
printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n");
printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
return -EIO;
}
else
@ -234,6 +237,13 @@ int tps65910_post_init(struct tps65910 *tps65910)
struct regulator *ldo;
printk("%s,line=%d\n", __func__,__LINE__);
g_pmic_type = PMIC_TYPE_TPS65910;
printk("%s:g_pmic_type=%d\n",__func__,g_pmic_type);
#ifdef CONFIG_RK30_PWM_REGULATOR
platform_device_register(&pwm_regulator_device[0]);
#endif
dcdc = regulator_get(NULL, "vio"); //vcc_io
regulator_set_voltage(dcdc, 3000000, 3000000);
regulator_enable(dcdc);
@ -310,15 +320,6 @@ int tps65910_post_init(struct tps65910 *tps65910)
printk("%s set vmmc vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
#ifdef CONFIG_RK30_PWM_REGULATOR
dcdc = regulator_get(NULL, "vdd_core"); // vdd_log
regulator_set_voltage(dcdc, 1150000, 1150000);
regulator_enable(dcdc);
printk("%s set vdd_core=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
#endif
printk("%s,line=%d END\n", __func__,__LINE__);
@ -580,13 +581,13 @@ static struct regulator_init_data tps65910_ldo8 = {
.consumer_supplies = tps65910_ldo8_supply,
};
void __sramfunc board_pmu_suspend(void)
void __sramfunc board_pmu_tps65910_suspend(void)
{
grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
grf_writel(GPIO6_PB1_DO_HIGH, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output low
grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
}
void __sramfunc board_pmu_resume(void)
void __sramfunc board_pmu_tps65910_resume(void)
{
grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
grf_writel(GPIO6_PB1_DO_LOW, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output low
@ -601,6 +602,7 @@ void __sramfunc board_pmu_resume(void)
static struct tps65910_board tps65910_data = {
.irq = (unsigned)TPS65910_HOST_IRQ,
.irq_base = NR_GIC_IRQS + NR_GPIO_IRQS,
.gpio_base = TPS65910_GPIO_EXPANDER_BASE,
.pre_init = tps65910_pre_init,
.post_init = tps65910_post_init,
@ -620,6 +622,7 @@ static struct tps65910_board tps65910_data = {
.tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &tps65910_ldo4,
.tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &tps65910_ldo5,
.tps65910_pmic_init_data[TPS65910_REG_VMMC] = &tps65910_ldo6,
};

143
arch/arm/mach-rk30/board-rk30-sdk-wm8326.c
View File

@ -5,6 +5,7 @@
#include <linux/mfd/wm831x/pmu.h>
#include <mach/sram.h>
#include <linux/earlysuspend.h>
#define cru_readl(offset) readl_relaxed(RK30_CRU_BASE + offset)
#define cru_writel(v, offset) do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
@ -182,7 +183,10 @@ int wm831x_post_init(struct wm831x *Wm831x)
struct regulator *dcdc;
struct regulator *ldo;
g_pmic_type = PMIC_TYPE_WM8326;
printk("%s:g_pmic_type=%d\n",__func__,g_pmic_type);
ldo = regulator_get(NULL, "ldo6"); //vcc_33
regulator_set_voltage(ldo, 3300000, 3300000);
regulator_set_suspend_voltage(ldo, 3300000);
@ -495,7 +499,8 @@ struct regulator_init_data wm831x_regulator_init_dcdc[WM831X_MAX_DCDC] = {
.min_uV = 600000,
.max_uV = 1800000, //0.6-1.8V
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST | REGULATOR_MODE_IDLE,
},
.num_consumer_supplies = ARRAY_SIZE(dcdc1_consumers),
.consumer_supplies = dcdc1_consumers,
@ -506,7 +511,8 @@ struct regulator_init_data wm831x_regulator_init_dcdc[WM831X_MAX_DCDC] = {
.min_uV = 600000,
.max_uV = 1800000, //0.6-1.8V
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST | REGULATOR_MODE_IDLE,
},
.num_consumer_supplies = ARRAY_SIZE(dcdc2_consumers),
.consumer_supplies = dcdc2_consumers,
@ -517,7 +523,8 @@ struct regulator_init_data wm831x_regulator_init_dcdc[WM831X_MAX_DCDC] = {
.min_uV = 850000,
.max_uV = 3400000, //0.85-3.4V
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST | REGULATOR_MODE_IDLE,
},
.num_consumer_supplies = ARRAY_SIZE(dcdc3_consumers),
.consumer_supplies = dcdc3_consumers,
@ -528,7 +535,8 @@ struct regulator_init_data wm831x_regulator_init_dcdc[WM831X_MAX_DCDC] = {
.min_uV = 850000,
.max_uV = 3400000, //0.85-3.4V
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_STANDBY | REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST | REGULATOR_MODE_IDLE,
},
.num_consumer_supplies = ARRAY_SIZE(dcdc4_consumers),
.consumer_supplies = dcdc4_consumers,
@ -569,7 +577,8 @@ struct regulator_init_data wm831x_regulator_init_ldo[WM831X_MAX_LDO] = {
.min_uV = 900000,
.max_uV = 3300000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(ldo1_consumers),
.consumer_supplies = ldo1_consumers,
@ -580,7 +589,8 @@ struct regulator_init_data wm831x_regulator_init_ldo[WM831X_MAX_LDO] = {
.min_uV = 900000,
.max_uV = 3300000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
.consumer_supplies = ldo2_consumers,
@ -591,7 +601,8 @@ struct regulator_init_data wm831x_regulator_init_ldo[WM831X_MAX_LDO] = {
.min_uV = 900000,
.max_uV = 3300000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(ldo3_consumers),
.consumer_supplies = ldo3_consumers,
@ -602,7 +613,8 @@ struct regulator_init_data wm831x_regulator_init_ldo[WM831X_MAX_LDO] = {
.min_uV = 900000,
.max_uV = 3300000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(ldo4_consumers),
.consumer_supplies = ldo4_consumers,
@ -613,7 +625,8 @@ struct regulator_init_data wm831x_regulator_init_ldo[WM831X_MAX_LDO] = {
.min_uV = 900000,
.max_uV = 3300000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(ldo5_consumers),
.consumer_supplies = ldo5_consumers,
@ -624,7 +637,8 @@ struct regulator_init_data wm831x_regulator_init_ldo[WM831X_MAX_LDO] = {
.min_uV = 900000,
.max_uV = 3300000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(ldo6_consumers),
.consumer_supplies = ldo6_consumers,
@ -635,7 +649,8 @@ struct regulator_init_data wm831x_regulator_init_ldo[WM831X_MAX_LDO] = {
.min_uV = 1000000,
.max_uV = 3500000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(ldo7_consumers),
.consumer_supplies = ldo7_consumers,
@ -646,7 +661,8 @@ struct regulator_init_data wm831x_regulator_init_ldo[WM831X_MAX_LDO] = {
.min_uV = 1000000,
.max_uV = 3500000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(ldo8_consumers),
.consumer_supplies = ldo8_consumers,
@ -657,7 +673,8 @@ struct regulator_init_data wm831x_regulator_init_ldo[WM831X_MAX_LDO] = {
.min_uV = 1000000,
.max_uV = 3500000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(ldo9_consumers),
.consumer_supplies = ldo9_consumers,
@ -668,7 +685,8 @@ struct regulator_init_data wm831x_regulator_init_ldo[WM831X_MAX_LDO] = {
.min_uV = 1000000,
.max_uV = 3500000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(ldo10_consumers),
.consumer_supplies = ldo10_consumers,
@ -679,7 +697,8 @@ struct regulator_init_data wm831x_regulator_init_ldo[WM831X_MAX_LDO] = {
.min_uV = 800000,
.max_uV = 1550000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
.valid_modes_mask = REGULATOR_MODE_IDLE | REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(ldo11_consumers),
.consumer_supplies = ldo11_consumers,
@ -774,14 +793,101 @@ static int wm831x_init_pin_type(struct wm831x *wm831x)
return 0;
}
void __sramfunc board_pmu_suspend(void)
#ifdef CONFIG_HAS_EARLYSUSPEND
void wm831x_pmu_early_suspend(struct regulator_dev *rdev)
{
struct regulator *dcdc;
struct regulator *ldo;
printk("%s\n", __func__);
dcdc = regulator_get(NULL, "dcdc4"); //vcc_io
regulator_set_voltage(dcdc, 2800000, 2800000);
regulator_set_mode(dcdc, REGULATOR_MODE_STANDBY);
regulator_enable(dcdc);
printk("%s set dcdc4 vcc_io=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
ldo = regulator_get(NULL, "ldo1"); //
regulator_set_mode(ldo, REGULATOR_MODE_IDLE);
regulator_enable(ldo);
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "ldo4");
regulator_set_mode(ldo, REGULATOR_MODE_IDLE);
regulator_enable(ldo);
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "ldo6");
regulator_set_mode(ldo, REGULATOR_MODE_IDLE);
regulator_enable(ldo);
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "ldo8");
regulator_set_mode(ldo, REGULATOR_MODE_IDLE);
regulator_enable(ldo);
regulator_put(ldo);
udelay(100);
}
void wm831x_pmu_early_resume(struct regulator_dev *rdev)
{
struct regulator *dcdc;
struct regulator *ldo;
printk("%s\n", __func__);
dcdc = regulator_get(NULL, "dcdc4"); //vcc_io
regulator_set_voltage(dcdc, 3000000, 3000000);
regulator_set_mode(dcdc, REGULATOR_MODE_FAST);
regulator_enable(dcdc);
printk("%s set dcdc4 vcc_io=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
ldo = regulator_get(NULL, "ldo1"); //
regulator_set_mode(ldo, REGULATOR_MODE_NORMAL);
regulator_enable(ldo);
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "ldo4");
regulator_set_mode(ldo, REGULATOR_MODE_NORMAL);
regulator_enable(ldo);
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "ldo6");
regulator_set_mode(ldo, REGULATOR_MODE_NORMAL);
regulator_enable(ldo);
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "ldo8");
regulator_set_mode(ldo, REGULATOR_MODE_NORMAL);
regulator_enable(ldo);
regulator_put(ldo);
udelay(100);
}
#else
void wm831x_pmu_early_suspend(struct regulator_dev *rdev)
{
}
void wm831x_pmu_early_resume(struct regulator_dev *rdev)
{
}
#endif
void __sramfunc board_pmu_wm8326_suspend(void)
{
cru_writel(CRU_CLKGATE5_GRFCLK_ON,CRU_CLKGATE5_CON_ADDR); //open grf clk
grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
grf_writel(GPIO6_PB1_DO_HIGH, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output low
grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
}
void __sramfunc board_pmu_resume(void)
void __sramfunc board_pmu_wm8326_resume(void)
{
grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
grf_writel(GPIO6_PB1_DO_LOW, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output high
@ -792,6 +898,7 @@ void __sramfunc board_pmu_resume(void)
sram_udelay(10000);
#endif
}
static struct wm831x_pdata wm831x_platdata = {
/** Called before subdevices are set up */

703
arch/arm/mach-rk30/board-rk30-sdk.c
View File

@ -44,6 +44,7 @@
#include <linux/regulator/machine.h>
#include <linux/rfkill-rk.h>
#include <linux/sensor-dev.h>
#include <linux/regulator/rk29-pwm-regulator.h>
#if defined(CONFIG_HDMI_RK30)
#include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
#endif
@ -67,460 +68,18 @@
#include "../../../drivers/staging/android/timed_gpio.h"
#endif
#if defined(CONFIG_MT6620)
#include <linux/gps.h>
#endif
#ifdef CONFIG_THREE_FB_BUFFER
#define RK30_FB0_MEM_SIZE 12*SZ_1M
#else
#define RK30_FB0_MEM_SIZE 8*SZ_1M
#endif
#ifdef CONFIG_VIDEO_RK29
/*---------------- Camera Sensor Macro Define Begin ------------------------*/
/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */
#define CONFIG_SENSOR_IIC_ADDR_0 0x78
#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 4
#define CONFIG_SENSOR_CIF_INDEX_0 1
#define CONFIG_SENSOR_ORIENTATION_0 90
#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN1_PD6
#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000
#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */
#define CONFIG_SENSOR_IIC_ADDR_01 0x00
#define CONFIG_SENSOR_CIF_INDEX_01 1
#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4
#define CONFIG_SENSOR_ORIENTATION_01 90
#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_01 RK30_PIN1_PD6
#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000
#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */
#define CONFIG_SENSOR_IIC_ADDR_02 0x00
#define CONFIG_SENSOR_CIF_INDEX_02 1
#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4
#define CONFIG_SENSOR_ORIENTATION_02 90
#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_02 RK30_PIN1_PD6
#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000
#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */
#define CONFIG_SENSOR_IIC_ADDR_1 0x60
#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 3
#define CONFIG_SENSOR_CIF_INDEX_1 0
#define CONFIG_SENSOR_ORIENTATION_1 270
#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN1_PB7
#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000
#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */
#define CONFIG_SENSOR_IIC_ADDR_11 0x00
#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3
#define CONFIG_SENSOR_CIF_INDEX_11 0
#define CONFIG_SENSOR_ORIENTATION_11 270
#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO//RK30_PIN1_PB7
#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000
#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */
#define CONFIG_SENSOR_IIC_ADDR_12 0x00
#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3
#define CONFIG_SENSOR_CIF_INDEX_12 0
#define CONFIG_SENSOR_ORIENTATION_12 270
#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO//RK30_PIN1_PB7
#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO
#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L
#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L
#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H
#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L
#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000
#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000
#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000
#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000
#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000
#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000
#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000
#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000
#endif //#ifdef CONFIG_VIDEO_RK29
/*---------------- Camera Sensor Configuration Macro End------------------------*/
#include "../../../drivers/media/video/rk30_camera.c"
/*---------------- Camera Sensor Macro Define End ---------*/
#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
/*****************************************************************************************
* camera devices
* author: ddl@rock-chips.com
*****************************************************************************************/
#ifdef CONFIG_VIDEO_RK29
#define CONFIG_SENSOR_POWER_IOCTL_USR 1 //define this refer to your board layout
#define CONFIG_SENSOR_RESET_IOCTL_USR 0
#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
static void rk_cif_power(int on)
{
struct regulator *ldo_18,*ldo_28;
ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
printk("get cif ldo failed!\n");
return;
}
if(on == 0){
regulator_disable(ldo_28);
regulator_put(ldo_28);
regulator_disable(ldo_18);
regulator_put(ldo_18);
mdelay(500);
}
else{
regulator_set_voltage(ldo_28, 2800000, 2800000);
regulator_enable(ldo_28);
// printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
regulator_put(ldo_28);
regulator_set_voltage(ldo_18, 1800000, 1800000);
// regulator_set_suspend_voltage(ldo, 1800000);
regulator_enable(ldo_18);
// printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
regulator_put(ldo_18);
}
}
#if CONFIG_SENSOR_POWER_IOCTL_USR
static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
{
//#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
rk_cif_power(on);
}
#endif
#if CONFIG_SENSOR_RESET_IOCTL_USR
static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
{
#error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
}
#endif
#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
{
#error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
}
#endif
#if CONFIG_SENSOR_FLASH_IOCTL_USR
static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
{
#error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!";
}
#endif
static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = {
#if CONFIG_SENSOR_POWER_IOCTL_USR
.sensor_power_cb = sensor_power_usr_cb,
#else
.sensor_power_cb = NULL,
#endif
#if CONFIG_SENSOR_RESET_IOCTL_USR
.sensor_reset_cb = sensor_reset_usr_cb,
#else
.sensor_reset_cb = NULL,
#endif
#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
.sensor_powerdown_cb = sensor_powerdown_usr_cb,
#else
.sensor_powerdown_cb = NULL,
#endif
#if CONFIG_SENSOR_FLASH_IOCTL_USR
.sensor_flash_cb = sensor_flash_usr_cb,
#else
.sensor_flash_cb = NULL,
#endif
};
#if CONFIG_SENSOR_IIC_ADDR_0
static struct reginfo_t rk_init_data_sensor_reg_0[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_1
static struct reginfo_t rk_init_data_sensor_reg_1[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_1[] =
{
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_01
static struct reginfo_t rk_init_data_sensor_reg_01[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_01[] =
{
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_02
static struct reginfo_t rk_init_data_sensor_reg_02[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_02[] =
{
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_11
static struct reginfo_t rk_init_data_sensor_reg_11[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_11[] =
{
{0x0000, 0x00,0,0}
};
#endif
#if CONFIG_SENSOR_IIC_ADDR_12
static struct reginfo_t rk_init_data_sensor_reg_12[] =
{
{0x0000, 0x00,0,0}
};
static struct reginfo_t rk_init_data_sensor_winseqreg_12[] =
{
{0x0000, 0x00,0,0}
};
#endif
static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] =
{
#if CONFIG_SENSOR_IIC_ADDR_0
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_0,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_1
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_1,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_01
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_01,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_02
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_02,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_11
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_11,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
#if CONFIG_SENSOR_IIC_ADDR_12
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = rk_init_data_sensor_reg_12,
.rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12,
.rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t),
.rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t),
},
#else
{
.rk_sensor_init_width = INVALID_VALUE,
.rk_sensor_init_height = INVALID_VALUE,
.rk_sensor_init_bus_param = INVALID_VALUE,
.rk_sensor_init_pixelcode = INVALID_VALUE,
.rk_sensor_init_data = NULL,
.rk_sensor_init_winseq = NULL,
.rk_sensor_winseq_size = 0,
.rk_sensor_init_data_size = 0,
},
#endif
};
#include "../../../drivers/media/video/rk30_camera.c"
#endif /* CONFIG_VIDEO_RK29 */
#include "board-rk30-sdk-camera.c"
#include "board-rk30-sdk-key.c"
#if defined(CONFIG_TOUCHSCREEN_GT8XX)
#define TOUCH_RESET_PIN RK30_PIN4_PD0
@ -865,6 +424,25 @@ static struct sensor_platform_data lis3dh_info = {
.init_platform_hw = lis3dh_init_platform_hw,
.orientation = {-1, 0, 0, 0, 0, 1, 0, -1, 0},
};
#endif
#if defined (CONFIG_GS_KXTIK)
#define KXTIK_INT_PIN RK30_PIN4_PC0
static int kxtik_init_platform_hw(void)
{
rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0);
return 0;
}
static struct sensor_platform_data kxtik_info = {
.type = SENSOR_TYPE_ACCEL,
.irq_enable = 1,
.poll_delay_ms = 30,
.init_platform_hw = kxtik_init_platform_hw,
.orientation = {0, 1, 0, 0, 0, -1, 1, 0, 0},
};
#endif
#if defined (CONFIG_COMPASS_AK8975)
static struct sensor_platform_data akm8975_info =
@ -936,6 +514,38 @@ static struct sensor_platform_data cm3217_info = {
#endif
#if defined(CONFIG_PS_AL3006)
static struct sensor_platform_data proximity_al3006_info = {
.type = SENSOR_TYPE_PROXIMITY,
.irq_enable = 1,
.poll_delay_ms = 200,
};
#endif
#if defined(CONFIG_PS_STK3171)
static struct sensor_platform_data proximity_stk3171_info = {
.type = SENSOR_TYPE_PROXIMITY,
.irq_enable = 1,
.poll_delay_ms = 200,
};
#endif
#if defined(CONFIG_LS_AL3006)
static struct sensor_platform_data light_al3006_info = {
.type = SENSOR_TYPE_LIGHT,
.irq_enable = 1,
.poll_delay_ms = 200,
};
#endif
#if defined(CONFIG_LS_STK3171)
static struct sensor_platform_data light_stk3171_info = {
.type = SENSOR_TYPE_LIGHT,
.irq_enable = 1,
.poll_delay_ms = 200,
};
#endif
#ifdef CONFIG_FB_ROCKCHIP
#define LCD_CS_MUX_NAME GPIO4C7_SMCDATA7_TRACEDATA7_NAME
@ -1163,14 +773,15 @@ static struct platform_device device_ion = {
#include "board-rk30-sdk-sdmmc.c"
#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB7 //According to your own project to set the value of write-protect-pin.
#define SDMMC0_WRITE_PROTECT_PIN RK30_PIN3_PB2 //According to your own project to set the value of write-protect-pin.
#endif
#if defined(CONFIG_SDMMC1_RK29_WRITE_PROTECT)
#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PC7 //According to your own project to set the value of write-protect-pin.
#define SDMMC1_WRITE_PROTECT_PIN RK30_PIN3_PB3 //According to your own project to set the value of write-protect-pin.
#endif
#define RK29SDK_WIFI_SDIO_CARD_DETECT_N RK30_PIN6_PB2
#define RK29SDK_WIFI_SDIO_CARD_INT RK30_PIN3_PD2
#endif //endif ---#ifdef CONFIG_SDMMC_RK29
@ -1226,6 +837,12 @@ struct rk29_sdmmc_platform_data default_sdmmc0_data = {
#else
.use_dma = 0,
#endif
#if defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
.status = rk29sdk_wifi_mmc0_status,
.register_status_notify = rk29sdk_wifi_mmc0_status_register,
#endif
.detect_irq = RK30_PIN3_PB6, // INVALID_GPIO
.enable_sd_wakeup = 0,
@ -1290,7 +907,7 @@ struct rk29_sdmmc_platform_data default_sdmmc1_data = {
#endif
#if !defined(CONFIG_USE_SDMMC1_FOR_WIFI_DEVELOP_BOARD)
#ifdef CONFIG_WIFI_CONTROL_FUNC
#if defined(CONFIG_WIFI_CONTROL_FUNC) || defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
.status = rk29sdk_wifi_status,
.register_status_notify = rk29sdk_wifi_status_register,
#endif
@ -1304,6 +921,10 @@ struct rk29_sdmmc_platform_data default_sdmmc1_data = {
.write_prt = INVALID_GPIO,
#endif
#if defined(CONFIG_RK29_SDIO_IRQ_FROM_GPIO)
.sdio_INT_gpio = RK29SDK_WIFI_SDIO_CARD_INT,
#endif
#else
.detect_irq = INVALID_GPIO,
.enable_sd_wakeup = 0,
@ -1316,7 +937,7 @@ struct rk29_sdmmc_platform_data default_sdmmc1_data = {
* the end of setting for SDMMC devices
**************************************************************************************************/
#ifdef CONFIG_BATTERY_RK30_ADC
#if defined(CONFIG_BATTERY_RK30_ADC)||defined(CONFIG_BATTERY_RK30_ADC_FAC)
static struct rk30_adc_battery_platform_data rk30_adc_battery_platdata = {
.dc_det_pin = RK30_PIN6_PA5,
.batt_low_pin = RK30_PIN6_PA0,
@ -1335,6 +956,60 @@ static struct platform_device rk30_device_adc_battery = {
};
#endif
#ifdef CONFIG_RK30_PWM_REGULATOR
const static int pwm_voltage_map[] = {
1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000, 1400000
};
static struct regulator_consumer_supply pwm_dcdc1_consumers[] = {
{
.supply = "vdd_core",
}
};
struct regulator_init_data pwm_regulator_init_dcdc[1] =
{
{
.constraints = {
.name = "PWM_DCDC1",
.min_uV = 600000,
.max_uV = 1800000, //0.6-1.8V
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(pwm_dcdc1_consumers),
.consumer_supplies = pwm_dcdc1_consumers,
},
};
static struct pwm_platform_data pwm_regulator_info[1] = {
{
.pwm_id = 3,
.pwm_gpio = RK30_PIN0_PD7,
.pwm_iomux_name = GPIO0D7_PWM3_NAME,
.pwm_iomux_pwm = GPIO0D_PWM3,
.pwm_iomux_gpio = GPIO0D_GPIO0D6,
.pwm_voltage = 1100000,
.suspend_voltage = 1050000,
.min_uV = 1000000,
.max_uV = 1400000,
.coefficient = 455, //45.5%
.pwm_voltage_map = pwm_voltage_map,
.init_data = &pwm_regulator_init_dcdc[0],
},
};
struct platform_device pwm_regulator_device[1] = {
{
.name = "pwm-voltage-regulator",
.id = 0,
.dev = {
.platform_data = &pwm_regulator_info[0],
}
},
};
#endif
#ifdef CONFIG_RK29_VMAC
#define PHY_PWR_EN_GPIO RK30_PIN1_PD6
#include "board-rk30-sdk-vmac.c"
@ -1421,9 +1096,14 @@ static struct platform_device *devices[] __initdata = {
#ifdef CONFIG_RK_IRDA
&irda_device,
#endif
#ifdef CONFIG_WIFI_CONTROL_FUNC
#if defined(CONFIG_WIFI_CONTROL_FUNC)||defined(CONFIG_WIFI_COMBO_MODULE_CONTROL_FUNC)
&rk29sdk_wifi_device,
#endif
#if defined(CONFIG_MT6620)
&mt3326_device_gps,
#endif
#ifdef CONFIG_RK29_SUPPORT_MODEM
&rk30_device_modem,
#endif
@ -1439,7 +1119,7 @@ static struct platform_device *devices[] __initdata = {
#if defined(CONFIG_SEW868)
&rk30_device_sew868,
#endif
#ifdef CONFIG_BATTERY_RK30_ADC
#if defined(CONFIG_BATTERY_RK30_ADC)||defined(CONFIG_BATTERY_RK30_ADC_FAC)
&rk30_device_adc_battery,
#endif
#ifdef CONFIG_RFKILL_RK
@ -1468,6 +1148,15 @@ static struct i2c_board_info __initdata i2c0_info[] = {
.platform_data = &lis3dh_info,
},
#endif
#if defined (CONFIG_GS_KXTIK)
{
.type = "gs_kxtik",
.addr = 0x0F,
.flags = 0,
.irq = KXTIK_INT_PIN,
.platform_data = &kxtik_info,
},
#endif
#if defined (CONFIG_COMPASS_AK8975)
{
.type = "ak8975",
@ -1486,6 +1175,45 @@ static struct i2c_board_info __initdata i2c0_info[] = {
.platform_data = &l3g4200d_info,
},
#endif
#if defined (CONFIG_LS_AL3006)
{
.type = "light_al3006",
.addr = 0x1c, //sel = 0; if sel =1, then addr = 0x1D
.flags = 0,
.irq = RK30_PIN6_PA2,
.platform_data = &light_al3006_info,
},
#endif
#if defined (CONFIG_LS_STK3171)
{
.type = "ls_stk3171",
.addr = 0x48,
.flags = 0,
.irq = RK30_PIN6_PA2,
.platform_data = &light_stk3171_info,
},
#endif
#if defined (CONFIG_PS_AL3006)
{
.type = "proximity_al3006",
.addr = 0x1c, //sel = 0; if sel =1, then addr = 0x1D
.flags = 0,
.irq = RK30_PIN6_PA2,
.platform_data = &proximity_al3006_info,
},
#endif
#if defined (CONFIG_PS_STK3171)
{
.type = "ps_stk3171",
.addr = 0x48,
.flags = 0,
.irq = RK30_PIN6_PA2,
.platform_data = &proximity_stk3171_info,
},
#endif
#if defined (CONFIG_SND_SOC_RK1000)
{
.type = "rk1000_i2c_codec",
@ -1538,9 +1266,17 @@ static struct i2c_board_info __initdata i2c0_info[] = {
};
#endif
#define PMIC_TYPE_WM8326 1
#define PMIC_TYPE_TPS65910 2
int __sramdata g_pmic_type = 0;
#ifdef CONFIG_I2C1_RK30
#ifdef CONFIG_MFD_WM831X_I2C
#include "board-rk30-sdk-wm8326.c"
#endif
#ifdef CONFIG_MFD_TPS65910
#define TPS65910_HOST_IRQ RK30_PIN6_PA4
#include "board-rk30-sdk-tps65910.c"
#endif
static struct i2c_board_info __initdata i2c1_info[] = {
#if defined (CONFIG_MFD_WM831X_I2C)
@ -1552,9 +1288,42 @@ static struct i2c_board_info __initdata i2c1_info[] = {
.platform_data = &wm831x_platdata,
},
#endif
#if defined (CONFIG_MFD_TPS65910)
{
.type = "tps65910",
.addr = TPS65910_I2C_ID0,
.flags = 0,
.irq = TPS65910_HOST_IRQ,
.platform_data = &tps65910_data,
},
#endif
};
#endif
void __sramfunc board_pmu_suspend(void)
{
#if defined (CONFIG_MFD_WM831X_I2C)
if(g_pmic_type == PMIC_TYPE_WM8326)
board_pmu_wm8326_suspend();
#endif
#if defined (CONFIG_MFD_TPS65910)
if(g_pmic_type == PMIC_TYPE_TPS65910)
board_pmu_tps65910_suspend();
#endif
}
void __sramfunc board_pmu_resume(void)
{
#if defined (CONFIG_MFD_WM831X_I2C)
if(g_pmic_type == PMIC_TYPE_WM8326)
board_pmu_wm8326_resume();
#endif
#if defined (CONFIG_MFD_TPS65910)
if(g_pmic_type == PMIC_TYPE_TPS65910)
board_pmu_tps65910_resume();
#endif
}
#ifdef CONFIG_I2C2_RK30
static struct i2c_board_info __initdata i2c2_info[] = {
#if defined (CONFIG_TOUCHSCREEN_GT8XX)
@ -1568,7 +1337,7 @@ static struct i2c_board_info __initdata i2c2_info[] = {
#endif
#if defined (CONFIG_LS_CM3217)
{
.type = "lightsensor",
.type = "light_cm3217",
.addr = 0x10,
.flags = 0,
.platform_data = &cm3217_info,
@ -1638,10 +1407,20 @@ static void rk30_pm_power_off(void)
{
printk(KERN_ERR "rk30_pm_power_off start...\n");
gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
#if defined(CONFIG_MFD_WM831X)
wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
wm831x_device_shutdown(Wm831x);//wm8326 shutdown
#endif
#if defined(CONFIG_MFD_WM831X)
if(g_pmic_type == PMIC_TYPE_WM8326)
{
wm831x_set_bits(Wm831x,WM831X_GPIO_LEVEL,0x0001,0x0000); //set sys_pwr 0
wm831x_device_shutdown(Wm831x);//wm8326 shutdown
}
#endif
#if defined(CONFIG_MFD_TPS65910)
if(g_pmic_type == PMIC_TYPE_TPS65910)
{
tps65910_device_shutdown();//tps65910 shutdown
}
#endif
while (1);
}
@ -1661,6 +1440,10 @@ static void __init machine_rk30_board_init(void)
#ifdef CONFIG_WIFI_CONTROL_FUNC
rk29sdk_wifi_bt_gpio_control_init();
#endif
#if defined(CONFIG_MT6620)
clk_set_rate(clk_get_sys("rk_serial.0", "uart"), 16*1000000);
#endif
}
static void __init rk30_reserve(void)

65
arch/arm/mach-rk30/board-rk3066b-sdk-key.c Normal file
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@ -0,0 +1,65 @@
#include <mach/gpio.h>
#include <plat/key.h>
#define EV_ENCALL KEY_F4
#define EV_MENU KEY_F1
#define PRESS_LEV_LOW 1
#define PRESS_LEV_HIGH 0
static struct rk29_keys_button key_button[] = {
{
.desc = "vol-",
.code = KEY_VOLUMEDOWN,
.gpio = RK30_PIN0_PB5,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "play",
.code = KEY_POWER,
.gpio = RK30_PIN0_PA4,
.active_low = PRESS_LEV_LOW,
.wakeup = 1,
},
{
.desc = "vol+",
.code = KEY_VOLUMEUP,
.adc_value = 1,
.gpio = INVALID_GPIO,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "menu",
.code = EV_MENU,
.adc_value = 155,
.gpio = INVALID_GPIO,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "home",
.code = KEY_HOME,
.adc_value = 630,
.gpio = INVALID_GPIO,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "esc",
.code = KEY_BACK,
.adc_value = 386,
.gpio = INVALID_GPIO,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "camera",
.code = KEY_CAMERA,
.adc_value = 827,
.gpio = INVALID_GPIO,
.active_low = PRESS_LEV_LOW,
},
};
struct rk29_keys_platform_data rk29_keys_pdata = {
.buttons = key_button,
.nbuttons = ARRAY_SIZE(key_button),
.chn = 1, //chn: 0-7, if do not use ADC,set 'chn' -1
};

532
arch/arm/mach-rk30/board-rk3066b-sdk-sdmmc.c Normal file
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@ -0,0 +1,532 @@
/* arch/arm/mach-rk30/board-rk30-sdk-sdmmc.c
*
* Copyright (C) 2012 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifdef CONFIG_SDMMC_RK29
#if !defined(CONFIG_SDMMC_RK29_OLD)
static void rk29_sdmmc_gpio_open(int device_id, int on)
{
switch(device_id)
{
case 0://mmc0
{
#ifdef CONFIG_SDMMC0_RK29
if(on)
{
#if defined(CONFIG_ARCH_RK30)
gpio_direction_output(GPIO3B_GPIO3B0,GPIO_HIGH);//set mmc0-clk to high
gpio_direction_output(GPIO3B_GPIO3B1,GPIO_HIGH);// set mmc0-cmd to high.
gpio_direction_output(GPIO3B_GPIO3B2,GPIO_HIGH);//set mmc0-data0 to high.
gpio_direction_output(GPIO3B_GPIO3B3,GPIO_HIGH);//set mmc0-data1 to high.
gpio_direction_output(GPIO3B_GPIO3B4,GPIO_HIGH);//set mmc0-data2 to high.
gpio_direction_output(GPIO3B_GPIO3B5,GPIO_HIGH);//set mmc0-data3 to high.
#elif defined(CONFIG_ARCH_RK31)
gpio_direction_output(RK30_PIN3_PA2,GPIO_HIGH);//set mmc0-clk to high
gpio_direction_output(RK30_PIN3_PA3,GPIO_HIGH);// set mmc0-cmd to high.
gpio_direction_output(RK30_PIN3_PA4,GPIO_HIGH);//set mmc0-data0 to high.
gpio_direction_output(RK30_PIN3_PA5,GPIO_HIGH);//set mmc0-data1 to high.
gpio_direction_output(RK30_PIN3_PA6,GPIO_HIGH);//set mmc0-data2 to high.
gpio_direction_output(RK30_PIN3_PA7,GPIO_HIGH);//set mmc0-data3 to high.
#endif
mdelay(30);
}
else
{
#if defined(CONFIG_ARCH_RK30)
rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_GPIO3B0);
gpio_request(RK30_PIN3_PB0, "mmc0-clk");
gpio_direction_output(RK30_PIN3_PB0,GPIO_LOW);//set mmc0-clk to low.
rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME, GPIO3B_GPIO3B1);
gpio_request(RK30_PIN3_PB1, "mmc0-cmd");
gpio_direction_output(RK30_PIN3_PB1,GPIO_LOW);//set mmc0-cmd to low.
rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B_GPIO3B2);
gpio_request(RK30_PIN3_PB2, "mmc0-data0");
gpio_direction_output(RK30_PIN3_PB2,GPIO_LOW);//set mmc0-data0 to low.
rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_GPIO3B3);
gpio_request(RK30_PIN3_PB3, "mmc0-data1");
gpio_direction_output(RK30_PIN3_PB3,GPIO_LOW);//set mmc0-data1 to low.
rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_GPIO3B4);
gpio_request(RK30_PIN3_PB4, "mmc0-data2");
gpio_direction_output(RK30_PIN3_PB4,GPIO_LOW);//set mmc0-data2 to low.
rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_GPIO3B5);
gpio_request(RK30_PIN3_PB5, "mmc0-data3");
gpio_direction_output(RK30_PIN3_PB5,GPIO_LOW);//set mmc0-data3 to low.
#elif defined(CONFIG_ARCH_RK31)
rk30_mux_api_set(GPIO3A2_SDMMC0CLKOUT_NAME, GPIO3A_GPIO3A2);
gpio_request(RK30_PIN3_PA2, "mmc0-clk");
gpio_direction_output(RK30_PIN3_PA2,GPIO_LOW);//set mmc0-clk to low.
rk30_mux_api_set(GPIO3A3_SDMMC0CMD_NAME, GPIO3A_GPIO3A3);
gpio_request(RK30_PIN3_PA3, "mmc0-cmd");
gpio_direction_output(RK30_PIN3_PA3,GPIO_LOW);//set mmc0-cmd to low.
rk30_mux_api_set(GPIO3A4_SDMMC0DATA0_NAME, GPIO3A_GPIO3A4);
gpio_request(RK30_PIN3_PA4, "mmc0-data0");
gpio_direction_output(RK30_PIN3_PA4,GPIO_LOW);//set mmc0-data0 to low.
rk30_mux_api_set(GPIO3A5_SDMMC0DATA1_NAME, GPIO3A_GPIO3A5);
gpio_request(RK30_PIN3_PA5, "mmc0-data1");
gpio_direction_output(RK30_PIN3_PA5,GPIO_LOW);//set mmc0-data1 to low.
rk30_mux_api_set(GPIO3A6_SDMMC0DATA2_NAME, GPIO3A_GPIO3A6);
gpio_request(RK30_PIN3_PA6, "mmc0-data2");
gpio_direction_output(RK30_PIN3_PA6,GPIO_LOW);//set mmc0-data2 to low.
rk30_mux_api_set(GPIO3A7_SDMMC0DATA3_NAME, GPIO3A_GPIO3A7);
gpio_request(RK30_PIN3_PA7, "mmc0-data3");
gpio_direction_output(RK30_PIN3_PA7,GPIO_LOW);//set mmc0-data3 to low.
#endif
mdelay(30);
}
#endif
}
break;
case 1://mmc1
{
#ifdef CONFIG_SDMMC1_RK29
if(on)
{
gpio_direction_output(RK30_PIN3_PC5,GPIO_HIGH);//set mmc1-clk to high
gpio_direction_output(RK30_PIN3_PC0,GPIO_HIGH);//set mmc1-cmd to high.
gpio_direction_output(RK30_PIN3_PC1,GPIO_HIGH);//set mmc1-data0 to high.
gpio_direction_output(RK30_PIN3_PC2,GPIO_HIGH);//set mmc1-data1 to high.
gpio_direction_output(RK30_PIN3_PC3,GPIO_HIGH);//set mmc1-data2 to high.
gpio_direction_output(RK30_PIN3_PC5,GPIO_HIGH);//set mmc1-data3 to high.
mdelay(100);
}
else
{
#if defined(CONFIG_ARCH_RK30)
rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C_GPIO3C5);
gpio_request(RK30_PIN3_PC5, "mmc1-clk");
gpio_direction_output(RK30_PIN3_PC5,GPIO_LOW);//set mmc1-clk to low.
rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME, GPIO3C_GPIO3C0);
gpio_request(RK30_PIN3_PC0, "mmc1-cmd");
gpio_direction_output(RK30_PIN3_PC0,GPIO_LOW);//set mmc1-cmd to low.
rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_GPIO3C1);
gpio_request(RK30_PIN3_PC1, "mmc1-data0");
gpio_direction_output(RK30_PIN3_PC1,GPIO_LOW);//set mmc1-data0 to low.
#elif defined(CONFIG_ARCH_RK31)
rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME, GPIO3C_GPIO3C5);
gpio_request(RK30_PIN3_PC5, "mmc1-clk");
gpio_direction_output(RK30_PIN3_PC5,GPIO_LOW);//set mmc1-clk to low.
rk30_mux_api_set(GPIO3C0_SDMMC1CMD_RMIITXEN_NAME, GPIO3C_GPIO3C0);
gpio_request(RK30_PIN3_PC0, "mmc1-cmd");
gpio_direction_output(RK30_PIN3_PC0,GPIO_LOW);//set mmc1-cmd to low.
rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME, GPIO3C_GPIO3C1);
gpio_request(RK30_PIN3_PC1, "mmc1-data0");
gpio_direction_output(RK30_PIN3_PC1,GPIO_LOW);//set mmc1-data0 to low.
#endif
mdelay(100);
}
#endif
}
break;
case 2: //mmc2
break;
default:
break;
}
}
static void rk29_sdmmc_set_iomux_mmc0(unsigned int bus_width)
{
switch (bus_width)
{
case 1://SDMMC_CTYPE_4BIT:
{
#if defined(CONFIG_ARCH_RK30)
rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_SDMMC0_DATA1);
rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_SDMMC0_DATA2);
rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_SDMMC0_DATA3);
#elif defined(CONFIG_ARCH_RK31)
rk30_mux_api_set(GPIO3A5_SDMMC0DATA1_NAME, GPIO3A_SDMMC0DATA1);
rk30_mux_api_set(GPIO3A6_SDMMC0DATA2_NAME, GPIO3A_SDMMC0DATA2);
rk30_mux_api_set(GPIO3A7_SDMMC0DATA3_NAME, GPIO3A_SDMMC0DATA3);
#endif
}
break;
case 0x10000://SDMMC_CTYPE_8BIT:
break;
case 0xFFFF: //gpio_reset
{
#if defined(CONFIG_ARCH_RK30)
rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME, GPIO3A_GPIO3A7);
gpio_request(RK30_PIN3_PA7,"sdmmc-power");
gpio_direction_output(RK30_PIN3_PA7,GPIO_HIGH); //power-off
rk29_sdmmc_gpio_open(0, 0);
gpio_direction_output(RK30_PIN3_PA7,GPIO_LOW); //power-on
rk29_sdmmc_gpio_open(0, 1);
#elif defined(CONFIG_ARCH_RK31)
rk30_mux_api_set(GPIO3A1_SDMMC0PWREN_NAME, GPIO3A_GPIO3A1);
gpio_request(RK30_PIN3_PA1,"sdmmc-power");
gpio_direction_output(RK30_PIN3_PA1,GPIO_HIGH); //power-off
rk29_sdmmc_gpio_open(0, 0);
gpio_direction_output(RK30_PIN3_PA1,GPIO_LOW); //power-on
rk29_sdmmc_gpio_open(0, 1);
#endif
}
break;
default: //case 0://SDMMC_CTYPE_1BIT:
{
#if defined(CONFIG_ARCH_RK30)
rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME, GPIO3B_SDMMC0_CMD);
rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_SDMMC0_CLKOUT);
rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B_SDMMC0_DATA0);
rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_GPIO3B3);
gpio_request(RK30_PIN3_PB3, "mmc0-data1");
gpio_direction_output(RK30_PIN3_PB3,GPIO_HIGH);//set mmc0-data1 to high.
rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_GPIO3B4);
gpio_request(RK30_PIN3_PB4, "mmc0-data2");
gpio_direction_output(RK30_PIN3_PB4,GPIO_HIGH);//set mmc0-data2 to high.
rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_GPIO3B5);
gpio_request(RK30_PIN3_PB5, "mmc0-data3");
gpio_direction_output(RK30_PIN3_PB5,GPIO_HIGH);//set mmc0-data3 to high.
#elif defined(CONFIG_ARCH_RK31)
rk30_mux_api_set(GPIO3A3_SDMMC0CMD_NAME, GPIO3A_SDMMC0CMD);
rk30_mux_api_set(GPIO3A2_SDMMC0CLKOUT_NAME, GPIO3A_SDMMC0CLKOUT);
rk30_mux_api_set(GPIO3A4_SDMMC0DATA0_NAME, GPIO3A_SDMMC0DATA0);
rk30_mux_api_set(GPIO3A5_SDMMC0DATA1_NAME, GPIO3A_GPIO3A5);
gpio_request(RK30_PIN3_PA5, "mmc0-data1");
gpio_direction_output(RK30_PIN3_PA5,GPIO_HIGH);//set mmc0-data1 to high.
rk30_mux_api_set(GPIO3A6_SDMMC0DATA2_NAME, GPIO3A_GPIO3A6);
gpio_request(RK30_PIN3_PA5, "mmc0-data2");
gpio_direction_output(RK30_PIN3_PA5,GPIO_HIGH);//set mmc0-data2 to high.
rk30_mux_api_set(GPIO3A7_SDMMC0DATA3_NAME, GPIO3A_GPIO3A7);
gpio_request(RK30_PIN3_PA7, "mmc0-data3");
gpio_direction_output(RK30_PIN3_PA7,GPIO_HIGH);//set mmc0-data3 to high.
#endif
}
break;
}
}
static void rk29_sdmmc_set_iomux_mmc1(unsigned int bus_width)
{
#if defined(CONFIG_ARCH_RK30)
rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME, GPIO3C_SMMC1_CMD);
rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C_SDMMC1_CLKOUT);
rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_SDMMC1_DATA0);
rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C_SDMMC1_DATA1);
rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C_SDMMC1_DATA2);
rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C_SDMMC1_DATA3);
#elif defined(CONFIG_ARCH_RK31)
rk30_mux_api_set(GPIO3C0_SDMMC1CMD_RMIITXEN_NAME, GPIO3C_SDMMC1CMD);
rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME, GPIO3C_SDMMC1CLKOUT);
rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME, GPIO3C_SDMMC1DATA0);
rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_RMIITXD0_NAME, GPIO3C_SDMMC1DATA1);
rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_RMIIRXD0_NAME, GPIO3C_SDMMC1DATA2);
rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_RMIIRXD1_NAME, GPIO3C_SDMMC1DATA3);
#endif
}
static void rk29_sdmmc_set_iomux_mmc2(unsigned int bus_width)
{
;//
}
static void rk29_sdmmc_set_iomux(int device_id, unsigned int bus_width)
{
switch(device_id)
{
case 0:
#ifdef CONFIG_SDMMC0_RK29
rk29_sdmmc_set_iomux_mmc0(bus_width);
#endif
break;
case 1:
#ifdef CONFIG_SDMMC1_RK29
rk29_sdmmc_set_iomux_mmc1(bus_width);
#endif
break;
case 2:
rk29_sdmmc_set_iomux_mmc2(bus_width);
break;
default:
break;
}
}
#endif
//int rk29sdk_wifi_power_state = 0;
//int rk29sdk_bt_power_state = 0;
#ifdef CONFIG_WIFI_CONTROL_FUNC
//#define RK29SDK_WIFI_BT_GPIO_POWER_N RK30_PIN3_PD0
//#define RK29SDK_WIFI_GPIO_RESET_N RK30_PIN3_PD0
//#define RK29SDK_BT_GPIO_RESET_N RK30_PIN3_PD1
#define RK30SDK_WIFI_GPIO_POWER_N RK30_PIN3_PC7
//#define RK30SDK_BT_GPIO_POWER_N RK30_PIN3_PD1
#define PREALLOC_WLAN_SEC_NUM 4
#define PREALLOC_WLAN_BUF_NUM 160
#define PREALLOC_WLAN_SECTION_HEADER 24
#define WLAN_SECTION_SIZE_0 (PREALLOC_WLAN_BUF_NUM * 128)
#define WLAN_SECTION_SIZE_1 (PREALLOC_WLAN_BUF_NUM * 128)
#define WLAN_SECTION_SIZE_2 (PREALLOC_WLAN_BUF_NUM * 512)
#define WLAN_SECTION_SIZE_3 (PREALLOC_WLAN_BUF_NUM * 1024)
#define WLAN_SKB_BUF_NUM 16
static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM];
struct wifi_mem_prealloc {
void *mem_ptr;
unsigned long size;
};
static struct wifi_mem_prealloc wifi_mem_array[PREALLOC_WLAN_SEC_NUM] = {
{NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)},
{NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)},
{NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)},
{NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)}
};
static void *rk29sdk_mem_prealloc(int section, unsigned long size)
{
if (section == PREALLOC_WLAN_SEC_NUM)
return wlan_static_skb;
if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM))
return NULL;
if (wifi_mem_array[section].size < size)
return NULL;
return wifi_mem_array[section].mem_ptr;
}
static int __init rk29sdk_init_wifi_mem(void)
{
int i;
int j;
for (i = 0 ; i < WLAN_SKB_BUF_NUM ; i++) {
wlan_static_skb[i] = dev_alloc_skb(
((i < (WLAN_SKB_BUF_NUM / 2)) ? 4096 : 8192));
if (!wlan_static_skb[i])
goto err_skb_alloc;
}
for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) {
wifi_mem_array[i].mem_ptr =
kmalloc(wifi_mem_array[i].size, GFP_KERNEL);
if (!wifi_mem_array[i].mem_ptr)
goto err_mem_alloc;
}
return 0;
err_mem_alloc:
pr_err("Failed to mem_alloc for WLAN\n");
for (j = 0 ; j < i ; j++)
kfree(wifi_mem_array[j].mem_ptr);
i = WLAN_SKB_BUF_NUM;
err_skb_alloc:
pr_err("Failed to skb_alloc for WLAN\n");
for (j = 0 ; j < i ; j++)
dev_kfree_skb(wlan_static_skb[j]);
return -ENOMEM;
}
static int rk29sdk_wifi_cd = 0; /* wifi virtual 'card detect' status */
static void (*wifi_status_cb)(int card_present, void *dev_id);
static void *wifi_status_cb_devid;
static int rk29sdk_wifi_status(struct device *dev)
{
return rk29sdk_wifi_cd;
}
static int rk29sdk_wifi_status_register(void (*callback)(int card_present, void *dev_id), void *dev_id)
{
if(wifi_status_cb)
return -EAGAIN;
wifi_status_cb = callback;
wifi_status_cb_devid = dev_id;
return 0;
}
static int __init rk29sdk_wifi_bt_gpio_control_init(void)
{
rk29sdk_init_wifi_mem();
rk29_mux_api_set(GPIO3D0_SDMMC1PWREN_NAME, GPIO3D_GPIO3D0);
if (gpio_request(RK30SDK_WIFI_GPIO_POWER_N, "wifi_power")) {
pr_info("%s: request wifi power gpio failed\n", __func__);
return -1;
}
/*if (gpio_request(RK29SDK_WIFI_GPIO_RESET_N, "wifi reset")) {
pr_info("%s: request wifi reset gpio failed\n", __func__);
gpio_free(RK30SDK_WIFI_GPIO_POWER_N);
return -1;
}
if (gpio_request(RK29SDK_BT_GPIO_RESET_N, "bt reset")) {
pr_info("%s: request bt reset gpio failed\n", __func__);
gpio_free(RK29SDK_WIFI_GPIO_RESET_N);
return -1;
}*/
gpio_direction_output(RK30SDK_WIFI_GPIO_POWER_N, GPIO_LOW);
//gpio_direction_output(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
//gpio_direction_output(RK29SDK_BT_GPIO_RESET_N, GPIO_LOW);
#if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
rk29_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C_GPIO3C2);
gpio_request(RK30_PIN3_PC2, "mmc1-data1");
gpio_direction_output(RK30_PIN3_PC2,GPIO_LOW);//set mmc1-data1 to low.
rk29_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C_GPIO3C3);
gpio_request(RK30_PIN3_PC3, "mmc1-data2");
gpio_direction_output(RK30_PIN3_PC3,GPIO_LOW);//set mmc1-data2 to low.
rk29_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C_GPIO3C4);
gpio_request(RK30_PIN3_PC4, "mmc1-data3");
gpio_direction_output(RK30_PIN3_PC4,GPIO_LOW);//set mmc1-data3 to low.
rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
#endif
pr_info("%s: init finished\n",__func__);
return 0;
}
static int rk29sdk_wifi_power(int on)
{
pr_info("%s: %d\n", __func__, on);
if (on){
gpio_set_value(RK30SDK_WIFI_GPIO_POWER_N, GPIO_HIGH);
#if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
rk29_sdmmc_gpio_open(1, 1); //added by xbw at 2011-10-13
#endif
//gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_HIGH);
mdelay(100);
pr_info("wifi turn on power\n");
}else{
// if (!rk29sdk_bt_power_state){
gpio_set_value(RK30SDK_WIFI_GPIO_POWER_N, GPIO_LOW);
#if defined(CONFIG_SDMMC1_RK29) && !defined(CONFIG_SDMMC_RK29_OLD)
rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13
#endif
mdelay(100);
pr_info("wifi shut off power\n");
// }else
// {
// pr_info("wifi shouldn't shut off power, bt is using it!\n");
// }
//gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, GPIO_LOW);
}
// rk29sdk_wifi_power_state = on;
return 0;
}
static int rk29sdk_wifi_reset_state;
static int rk29sdk_wifi_reset(int on)
{
pr_info("%s: %d\n", __func__, on);
//gpio_set_value(RK29SDK_WIFI_GPIO_RESET_N, on);
//mdelay(100);
rk29sdk_wifi_reset_state = on;
return 0;
}
int rk29sdk_wifi_set_carddetect(int val)
{
pr_info("%s:%d\n", __func__, val);
rk29sdk_wifi_cd = val;
if (wifi_status_cb){
wifi_status_cb(val, wifi_status_cb_devid);
}else {
pr_warning("%s, nobody to notify\n", __func__);
}
return 0;
}
EXPORT_SYMBOL(rk29sdk_wifi_set_carddetect);
#define WIFI_HOST_WAKE RK30_PIN3_PD2
static struct resource resources[] = {
{
.start = WIFI_HOST_WAKE,
.flags = IORESOURCE_IRQ,
.name = "bcmdhd_wlan_irq",
},
};
static struct wifi_platform_data rk29sdk_wifi_control = {
.set_power = rk29sdk_wifi_power,
.set_reset = rk29sdk_wifi_reset,
.set_carddetect = rk29sdk_wifi_set_carddetect,
.mem_prealloc = rk29sdk_mem_prealloc,
};
static struct platform_device rk29sdk_wifi_device = {
.name = "bcmdhd_wlan",
.id = 1,
.num_resources = ARRAY_SIZE(resources),
.resource = resources,
.dev = {
.platform_data = &rk29sdk_wifi_control,
},
};
#endif
#endif // endif --#ifdef CONFIG_SDMMC_RK29

842
arch/arm/mach-rk30/board-rk3066b-sdk-wm8326.c Normal file
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#include <linux/regulator/machine.h>
#include <linux/mfd/wm831x/pdata.h>
#include <linux/mfd/wm831x/core.h>
#include <linux/mfd/wm831x/gpio.h>
#include <linux/mfd/wm831x/pmu.h>
#include <mach/sram.h>
#define cru_readl(offset) readl_relaxed(RK30_CRU_BASE + offset)
#define cru_writel(v, offset) do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
#define grf_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
#define CRU_CLKGATE5_CON_ADDR 0x00e4
#define GRF_GPIO6L_DIR_ADDR 0x0030
#define GRF_GPIO6L_DO_ADDR 0x0068
#define GRF_GPIO6L_EN_ADDR 0x00a0
#define CRU_CLKGATE5_GRFCLK_ON 0x00100000
#define CRU_CLKGATE5_GRFCLK_OFF 0x00100010
#define GPIO6_PB1_DIR_OUT 0x02000200
#define GPIO6_PB1_DO_LOW 0x02000000
#define GPIO6_PB1_DO_HIGH 0x02000200
#define GPIO6_PB1_EN_MASK 0x02000200
#define GPIO6_PB1_UNEN_MASK 0x02000000
/* wm8326 pmu*/
#if defined(CONFIG_GPIO_WM831X)
static struct rk29_gpio_expander_info wm831x_gpio_settinginfo[] = {
{
.gpio_num = WM831X_P01, // tp3
.pin_type = GPIO_OUT,
.pin_value = GPIO_LOW,
},
{
.gpio_num = WM831X_P02, //tp4
.pin_type = GPIO_IN,
},
{
.gpio_num = WM831X_P03, //tp2
.pin_type = GPIO_OUT,
.pin_value = GPIO_HIGH,
},
{
.gpio_num = WM831X_P04, //tp1
.pin_type = GPIO_IN,
},
{
.gpio_num = WM831X_P05, //tp1
.pin_type = GPIO_IN,
},
{
.gpio_num = WM831X_P06, //tp1
.pin_type = GPIO_OUT,
.pin_value = GPIO_HIGH,
},
{
.gpio_num = WM831X_P07, //tp1
.pin_type = GPIO_IN,
},
{
.gpio_num = WM831X_P08, //tp1
.pin_type = GPIO_OUT,
.pin_value = GPIO_HIGH,
},
{
.gpio_num = WM831X_P09, //tp1
.pin_type = GPIO_OUT,
.pin_value = GPIO_HIGH,
},
{
.gpio_num = WM831X_P10, //tp1
.pin_type = GPIO_IN,
},
{
.gpio_num = WM831X_P11, //tp1
.pin_type = GPIO_OUT,
.pin_value = GPIO_HIGH,
},
{
.gpio_num = WM831X_P12,
.pin_type = GPIO_OUT,
.pin_value = GPIO_HIGH,
},
};
#endif
#if defined(CONFIG_MFD_WM831X)
#define UNLOCK_SECURITY_KEY ~(0x1<<5)
#define LOCK_SECURITY_KEY 0x00
#define PMU_POWER_SLEEP RK30_PIN0_PA1
static struct wm831x *Wm831x;
static int wm831x_pre_init(struct wm831x *parm)
{
int ret;
Wm831x = parm;
// printk("%s\n", __func__);
gpio_request(PMU_POWER_SLEEP, "NULL");
gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW);
#ifdef CONFIG_WM8326_VBAT_LOW_DETECTION
#ifdef CONFIG_BATTERY_RK30_VOL3V8
wm831x_set_bits(parm,WM831X_SYSVDD_CONTROL ,0xc077,0xc035); //pvdd power on dect vbat voltage
printk("+++The vbat is too low+++\n");
#endif
#endif
ret = wm831x_reg_read(parm, WM831X_POWER_STATE) & 0xffff;
wm831x_reg_write(parm, WM831X_POWER_STATE, (ret & 0xfff8) | 0x04);
wm831x_set_bits(parm, WM831X_RTC_CONTROL, WM831X_RTC_ALAM_ENA_MASK, 0x0400);//enable rtc alam
//BATT_FET_ENA = 1
wm831x_reg_write(parm, WM831X_SECURITY_KEY, 0x9716); // unlock security key
wm831x_set_bits(parm, WM831X_RESET_CONTROL, 0x1003, 0x1001);
ret = wm831x_reg_read(parm, WM831X_RESET_CONTROL) & 0xffff & UNLOCK_SECURITY_KEY; // enternal reset active in sleep
// printk("%s:WM831X_RESET_CONTROL=0x%x\n", __func__, ret);
wm831x_reg_write(parm, WM831X_RESET_CONTROL, ret);
wm831x_set_bits(parm,WM831X_DC1_ON_CONFIG ,0x0300,0x0000); //set dcdc mode is FCCM
wm831x_set_bits(parm,WM831X_DC2_ON_CONFIG ,0x0300,0x0000);
wm831x_set_bits(parm,WM831X_DC3_ON_CONFIG ,0x0300,0x0000);
wm831x_set_bits(parm,0x4066,0x0300,0x0000);
#ifndef CONFIG_MACH_RK3066_SDK
wm831x_set_bits(parm,WM831X_LDO10_CONTROL ,0x0040,0x0040);// set ldo10 in switch mode
#endif
wm831x_set_bits(parm,WM831X_STATUS_LED_1 ,0xc300,0xc100);// set led1 on(in manual mode)
wm831x_set_bits(parm,WM831X_STATUS_LED_2 ,0xc300,0xc000);//set led2 off(in manual mode)
wm831x_set_bits(parm,WM831X_LDO5_SLEEP_CONTROL ,0xe000,0x2000);// set ldo5 is disable in sleep mode
wm831x_set_bits(parm,WM831X_LDO1_SLEEP_CONTROL ,0xe000,0x2000);// set ldo1 is disable in sleep mode
wm831x_reg_write(parm, WM831X_SECURITY_KEY, LOCK_SECURITY_KEY); // lock security key
return 0;
}
static int wm831x_mask_interrupt(struct wm831x *Wm831x)
{
/**************************clear interrupt********************/
wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_1,0xffff);
wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_2,0xffff);
wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_3,0xffff);
wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_4,0xffff);
wm831x_reg_write(Wm831x,WM831X_INTERRUPT_STATUS_5,0xffff);
wm831x_reg_write(Wm831x,WM831X_SYSTEM_INTERRUPTS_MASK,0xbedc); //mask interrupt which not used
return 0;
/*****************************************************************/
}
#ifdef CONFIG_WM8326_VBAT_LOW_DETECTION
static int wm831x_low_power_detection(struct wm831x *wm831x)
{
#ifdef CONFIG_BATTERY_RK30_VOL3V8
wm831x_reg_write(wm831x,WM831X_SYSTEM_INTERRUPTS_MASK,0xbe5c);
wm831x_set_bits(wm831x,WM831X_INTERRUPT_STATUS_1_MASK,0x8000,0x0000);
wm831x_set_bits(wm831x,WM831X_SYSVDD_CONTROL ,0xc077,0x0035); //set pvdd low voltage is 3.1v hi voltage is 3.3v
#else
wm831x_reg_write(wm831x,WM831X_AUXADC_CONTROL,0x803f); //open adc
wm831x_reg_write(wm831x,WM831X_AUXADC_CONTROL,0xd03f);
wm831x_reg_write(wm831x,WM831X_AUXADC_SOURCE,0x0001);
wm831x_reg_write(wm831x,WM831X_COMPARATOR_CONTROL,0x0001);
wm831x_reg_write(wm831x,WM831X_COMPARATOR_1,0x2844); //set the low power is 3.1v
wm831x_reg_write(wm831x,WM831X_INTERRUPT_STATUS_1_MASK,0x99ee);
wm831x_set_bits(wm831x,WM831X_SYSTEM_INTERRUPTS_MASK,0x0100,0x0000);
if (wm831x_reg_read(wm831x,WM831X_AUXADC_DATA)< 0x1844){
printk("The vbat is too low.\n");
wm831x_device_shutdown(wm831x);
}
#endif
return 0;
}
#endif
#define AVS_BASE 172
int wm831x_post_init(struct wm831x *Wm831x)
{
struct regulator *dcdc;
struct regulator *ldo;
ldo = regulator_get(NULL, "ldo6"); //vcc_33
regulator_set_voltage(ldo, 3300000, 3300000);
regulator_set_suspend_voltage(ldo, 3300000);
regulator_enable(ldo);
// printk("%s set ldo6 vcc_33=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "ldo4"); // vdd_11
regulator_set_voltage(ldo, 1100000, 1100000);
regulator_set_suspend_voltage(ldo, 1000000);
regulator_enable(ldo);
// printk("%s set ldo4 vdd_11=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "ldo5"); //vcc_25
regulator_set_voltage(ldo, 2500000, 2500000);
regulator_set_suspend_voltage(ldo, 2500000);
regulator_enable(ldo);
// printk("%s set ldo5 vcc_25=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
dcdc = regulator_get(NULL, "dcdc4"); // vcc_io
#ifdef CONFIG_MACH_RK3066_SDK
regulator_set_voltage(dcdc, 3300000, 3300000);
regulator_set_suspend_voltage(dcdc, 3100000);
#else
regulator_set_voltage(dcdc, 3000000, 3000000);
regulator_set_suspend_voltage(dcdc, 2800000);
#endif
regulator_enable(dcdc);
// printk("%s set dcdc4 vcc_io=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
dcdc = regulator_get(NULL, "vdd_cpu"); // vdd_arm
regulator_set_voltage(dcdc, 1100000, 1100000);
regulator_set_suspend_voltage(dcdc, 1000000);
regulator_enable(dcdc);
printk("%s set dcdc2 vdd_cpu(vdd_arm)=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
dcdc = regulator_get(NULL, "vdd_core"); // vdd_log
/* Read avs value under logic 1.1V*/
regulator_set_voltage(dcdc, 1100000, 1100000);
avs_init_val_get(1,1100000,"wm8326 init");
udelay(600);
avs_set_scal_val(AVS_BASE);
regulator_set_voltage(dcdc, 1150000, 1150000);
regulator_set_suspend_voltage(dcdc, 1000000);
regulator_enable(dcdc);
printk("%s set dcdc1 vdd_core(vdd_log)=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
dcdc = regulator_get(NULL, "dcdc3"); // vcc_ddr
regulator_set_voltage(dcdc, 1150000, 1150000);
regulator_set_suspend_voltage(dcdc, 1150000);
regulator_enable(dcdc);
// printk("%s set dcdc3 vcc_ddr=%dmV end\n", __func__, regulator_get_voltage(dcdc));
regulator_put(dcdc);
udelay(100);
ldo = regulator_get(NULL, "ldo7"); // vcc28_cif
regulator_set_voltage(ldo, 2800000, 2800000);
regulator_set_suspend_voltage(ldo, 2800000);
regulator_enable(ldo);
// printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "ldo1"); // vcc18_cif
regulator_set_voltage(ldo, 1800000, 1800000);
regulator_set_suspend_voltage(ldo, 1800000);
regulator_enable(ldo);
// printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "ldo8"); // vcca_33
regulator_set_voltage(ldo, 3300000, 3300000);
regulator_set_suspend_voltage(ldo, 3300000);
regulator_enable(ldo);
// printk("%s set ldo8 vcca_33=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "ldo2"); //vccio_wl
regulator_set_voltage(ldo, 1800000, 1800000);
regulator_set_suspend_voltage(ldo, 1800000);
regulator_enable(ldo);
// printk("%s set ldo2 vccio_wl=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "ldo10"); //flash io
regulator_set_voltage(ldo, 1800000, 1800000);
regulator_set_suspend_voltage(ldo, 1800000);
regulator_enable(ldo);
// printk("%s set ldo10 vcca_wl=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
#ifdef CONFIG_MACH_RK3066_SDK
ldo = regulator_get(NULL, "ldo3"); //vdd11_hdmi
regulator_set_voltage(ldo, 1100000, 1100000);
regulator_set_suspend_voltage(ldo, 1100000);
#else
ldo = regulator_get(NULL, "ldo3"); //vdd_12
regulator_set_voltage(ldo, 1200000, 1200000);
regulator_set_suspend_voltage(ldo, 1200000);
#endif
regulator_enable(ldo);
// printk("%s set ldo3 vdd_12=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
ldo = regulator_get(NULL, "ldo9"); //vcc_tp
regulator_set_voltage(ldo, 3300000, 3300000);
regulator_set_suspend_voltage(ldo, 3300000);
regulator_enable(ldo);
// printk("%s set ldo9 vcc_tp=%dmV end\n", __func__, regulator_get_voltage(ldo));
regulator_put(ldo);
udelay(100);
wm831x_mask_interrupt(Wm831x);
#ifdef CONFIG_WM8326_VBAT_LOW_DETECTION
wm831x_low_power_detection(Wm831x);
#endif
printk("wm831x_post_init end");
return 0;
}
static int wm831x_last_deinit(struct wm831x *Wm831x)
{
struct regulator *ldo;
printk("%s\n", __func__);
ldo = regulator_get(NULL, "ldo1");
regulator_disable(ldo);
regulator_put(ldo);
ldo = regulator_get(NULL, "ldo2");
regulator_disable(ldo);
regulator_put(ldo);
ldo = regulator_get(NULL, "ldo3");
regulator_disable(ldo);
regulator_put(ldo);
ldo = regulator_get(NULL, "ldo4");
//regulator_disable(ldo);
regulator_put(ldo);
ldo = regulator_get(NULL, "ldo5");
// regulator_disable(ldo);
regulator_put(ldo);
ldo = regulator_get(NULL, "ldo6");
// regulator_disable(ldo);
regulator_put(ldo);
ldo = regulator_get(NULL, "ldo7");
regulator_disable(ldo);
regulator_put(ldo);
ldo = regulator_get(NULL, "ldo8");
regulator_disable(ldo);
regulator_put(ldo);
ldo = regulator_get(NULL, "ldo9");
regulator_disable(ldo);
regulator_put(ldo);
ldo = regulator_get(NULL, "ldo10");
regulator_disable(ldo);
regulator_put(ldo);
return 0;
}
struct wm831x_status_pdata wm831x_status_platdata[WM831X_MAX_STATUS] = {
{
.default_src = WM831X_STATUS_OTP,
.name = "wm831x_status0",
.default_trigger = "wm831x_otp",
},
{
.default_src = WM831X_STATUS_POWER,
.name = "wm831x_status1",
.default_trigger = "wm831x_power",
},
};
static struct regulator_consumer_supply dcdc1_consumers[] = {
{
.supply = "vdd_core",
}
};
static struct regulator_consumer_supply dcdc2_consumers[] = {
{
.supply = "vdd_cpu",
}
};
static struct regulator_consumer_supply dcdc3_consumers[] = {
{
.supply = "dcdc3",
}
};
static struct regulator_consumer_supply dcdc4_consumers[] = {
{
.supply = "dcdc4",
}
};
#if 0
static struct regulator_consumer_supply epe1_consumers[] = {
{
.supply = "epe1",
}
};
static struct regulator_consumer_supply epe2_consumers[] = {
{
.supply = "epe2",
}
};
#endif
static struct regulator_consumer_supply ldo1_consumers[] = {
{
.supply = "ldo1",
}
};
static struct regulator_consumer_supply ldo2_consumers[] = {
{
.supply = "ldo2",
}
};
static struct regulator_consumer_supply ldo3_consumers[] = {
{
.supply = "ldo3",
}
};
static struct regulator_consumer_supply ldo4_consumers[] = {
{
.supply = "ldo4",
}
};
static struct regulator_consumer_supply ldo5_consumers[] = {
{
.supply = "ldo5",
}
};
static struct regulator_consumer_supply ldo6_consumers[] = {
{
.supply = "ldo6",
}
};
static struct regulator_consumer_supply ldo7_consumers[] = {
{
.supply = "ldo7",
}
};
static struct regulator_consumer_supply ldo8_consumers[] = {
{
.supply = "ldo8",
}
};
static struct regulator_consumer_supply ldo9_consumers[] = {
{
.supply = "ldo9",
}
};
static struct regulator_consumer_supply ldo10_consumers[] = {
{
.supply = "ldo10",
}
};
static struct regulator_consumer_supply ldo11_consumers[] = {
{
.supply = "ldo11",
}
};
struct regulator_init_data wm831x_regulator_init_dcdc[WM831X_MAX_DCDC] = {
{
.constraints = {
.name = "DCDC1",
.min_uV = 600000,
.max_uV = 1800000, //0.6-1.8V
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(dcdc1_consumers),
.consumer_supplies = dcdc1_consumers,
},
{
.constraints = {
.name = "DCDC2",
.min_uV = 600000,
.max_uV = 1800000, //0.6-1.8V
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(dcdc2_consumers),
.consumer_supplies = dcdc2_consumers,
},
{
.constraints = {
.name = "DCDC3",
.min_uV = 850000,
.max_uV = 3400000, //0.85-3.4V
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(dcdc3_consumers),
.consumer_supplies = dcdc3_consumers,
},
{
.constraints = {
.name = "DCDC4",
.min_uV = 850000,
.max_uV = 3400000, //0.85-3.4V
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(dcdc4_consumers),
.consumer_supplies = dcdc4_consumers,
},
};
#if 0
struct regulator_init_data wm831x_regulator_init_epe[WM831X_MAX_EPE] = {
{
.constraints = {
.name = "EPE1",
.min_uV = 1200000,
.max_uV = 3000000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(epe1_consumers),
.consumer_supplies = epe1_consumers,
},
{
.constraints = {
.name = "EPE2",
.min_uV = 1200000,
.max_uV = 3000000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(epe2_consumers),
.consumer_supplies = epe2_consumers,
},
};
#endif
struct regulator_init_data wm831x_regulator_init_ldo[WM831X_MAX_LDO] = {
{
.constraints = {
.name = "LDO1",
.min_uV = 900000,
.max_uV = 3300000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo1_consumers),
.consumer_supplies = ldo1_consumers,
},
{
.constraints = {
.name = "LDO2",
.min_uV = 900000,
.max_uV = 3300000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
.consumer_supplies = ldo2_consumers,
},
{
.constraints = {
.name = "LDO3",
.min_uV = 900000,
.max_uV = 3300000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo3_consumers),
.consumer_supplies = ldo3_consumers,
},
{
.constraints = {
.name = "LDO4",
.min_uV = 900000,
.max_uV = 3300000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo4_consumers),
.consumer_supplies = ldo4_consumers,
},
{
.constraints = {
.name = "LDO5",
.min_uV = 900000,
.max_uV = 3300000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo5_consumers),
.consumer_supplies = ldo5_consumers,
},
{
.constraints = {
.name = "LDO6",
.min_uV = 900000,
.max_uV = 3300000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo6_consumers),
.consumer_supplies = ldo6_consumers,
},
{
.constraints = {
.name = "LDO7",
.min_uV = 1000000,
.max_uV = 3500000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo7_consumers),
.consumer_supplies = ldo7_consumers,
},
{
.constraints = {
.name = "LDO8",
.min_uV = 1000000,
.max_uV = 3500000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo8_consumers),
.consumer_supplies = ldo8_consumers,
},
{
.constraints = {
.name = "LDO9",
.min_uV = 1000000,
.max_uV = 3500000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo9_consumers),
.consumer_supplies = ldo9_consumers,
},
{
.constraints = {
.name = "LDO10",
.min_uV = 1000000,
.max_uV = 3500000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo10_consumers),
.consumer_supplies = ldo10_consumers,
},
{
.constraints = {
.name = "LDO11",
.min_uV = 800000,
.max_uV = 1550000,
.apply_uV = true,
.valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(ldo11_consumers),
.consumer_supplies = ldo11_consumers,
},
};
static int wm831x_init_pin_type(struct wm831x *wm831x)
{
struct wm831x_pdata *pdata;
struct rk29_gpio_expander_info *wm831x_gpio_settinginfo;
uint16_t wm831x_settingpin_num;
int i;
if (!wm831x || !wm831x->dev)
goto out;
pdata = wm831x->dev->platform_data;
if (!pdata)
goto out;
wm831x_gpio_settinginfo = pdata->settinginfo;
if (!wm831x_gpio_settinginfo)
goto out;
wm831x_settingpin_num = pdata->settinginfolen;
for (i = 0; i < wm831x_settingpin_num; i++) {
if (wm831x_gpio_settinginfo[i].pin_type == GPIO_IN) {
wm831x_set_bits(wm831x,
WM831X_GPIO1_CONTROL + i,
WM831X_GPN_DIR_MASK | WM831X_GPN_TRI_MASK,
1 << WM831X_GPN_DIR_SHIFT | 1 << WM831X_GPN_TRI_SHIFT);
if (i == 1) {
wm831x_set_bits(wm831x,
WM831X_GPIO1_CONTROL + i,
WM831X_GPN_POL_MASK,
0x0400);
wm831x_set_bits(wm831x,
WM831X_GPIO1_CONTROL + i,
WM831X_GPN_FN_MASK,
0x0003);
} // set gpio2 sleep/wakeup
if (i == 9) {
wm831x_set_bits(wm831x,
WM831X_GPIO1_CONTROL + i,
WM831X_GPN_PULL_MASK,
0x0000); //disable pullup/down
wm831x_set_bits(wm831x,
WM831X_GPIO1_CONTROL + i,
WM831X_GPN_PWR_DOM_MASK,
0x0800);
wm831x_set_bits(wm831x,
WM831X_GPIO1_CONTROL + i,
WM831X_GPN_ENA_MASK,
0x0000);
} //set gpio10 as adc input
} else {
wm831x_set_bits(wm831x,
WM831X_GPIO1_CONTROL + i,
WM831X_GPN_DIR_MASK | WM831X_GPN_TRI_MASK,
1 << WM831X_GPN_TRI_SHIFT);
if (wm831x_gpio_settinginfo[i].pin_value == GPIO_HIGH) {
wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, 1 << i, 1 << i);
} else {
wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, 1 << i, 0 << i);
}
if (i == 2) {
wm831x_set_bits(wm831x,
WM831X_GPIO1_CONTROL + i,
WM831X_GPN_PWR_DOM_MASK | WM831X_GPN_POL_MASK |WM831X_GPN_FN_MASK,
1 << WM831X_GPN_POL_SHIFT | 1 << WM831X_GPN_PWR_DOM_SHIFT | 1 << 0);
} // set gpio3 as clkout output 32.768K
}
}
#if 0
for (i = 0; i < pdata->gpio_pin_num; i++) {
wm831x_set_bits(wm831x,
WM831X_GPIO1_CONTROL + i,
WM831X_GPN_PULL_MASK | WM831X_GPN_POL_MASK | WM831X_GPN_OD_MASK | WM831X_GPN_TRI_MASK,
1 << WM831X_GPN_POL_SHIFT | 1 << WM831X_GPN_TRI_SHIFT);
ret = wm831x_reg_read(wm831x, WM831X_GPIO1_CONTROL + i);
printk("Gpio%d Pin Configuration = %x\n", i, ret);
}
#endif
out:
return 0;
}
void __sramfunc board_pmu_suspend(void)
{
cru_writel(CRU_CLKGATE5_GRFCLK_ON,CRU_CLKGATE5_CON_ADDR); //open grf clk
grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
grf_writel(GPIO6_PB1_DO_HIGH, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output low
grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
}
void __sramfunc board_pmu_resume(void)
{
grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
grf_writel(GPIO6_PB1_DO_LOW, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output high
grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
#ifdef CONFIG_CLK_SWITCH_TO_32K
sram_32k_udelay(10000);
#else
sram_udelay(10000);
#endif
}
static struct wm831x_pdata wm831x_platdata = {
/** Called before subdevices are set up */
.pre_init = wm831x_pre_init,
/** Called after subdevices are set up */
.post_init = wm831x_post_init,
/** Called before subdevices are power down */
.last_deinit = wm831x_last_deinit,
#if defined(CONFIG_GPIO_WM831X)
.gpio_base = WM831X_GPIO_EXPANDER_BASE,
.gpio_pin_num = WM831X_TOTOL_GPIO_NUM,
.settinginfo = wm831x_gpio_settinginfo,
.settinginfolen = ARRAY_SIZE(wm831x_gpio_settinginfo),
.pin_type_init = wm831x_init_pin_type,
.irq_base = NR_GIC_IRQS + NR_GPIO_IRQS,
#endif
/** LED1 = 0 and so on */
.status = { &wm831x_status_platdata[0], &wm831x_status_platdata[1] },
/** DCDC1 = 0 and so on */
.dcdc = {
&wm831x_regulator_init_dcdc[0],
&wm831x_regulator_init_dcdc[1],
&wm831x_regulator_init_dcdc[2],
&wm831x_regulator_init_dcdc[3],
},
/** EPE1 = 0 and so on */
//.epe = { &wm831x_regulator_init_epe[0], &wm831x_regulator_init_epe[1] },
/** LDO1 = 0 and so on */
.ldo = {
&wm831x_regulator_init_ldo[0],
&wm831x_regulator_init_ldo[1],
&wm831x_regulator_init_ldo[2],
&wm831x_regulator_init_ldo[3],
&wm831x_regulator_init_ldo[4],
&wm831x_regulator_init_ldo[5],
&wm831x_regulator_init_ldo[6],
&wm831x_regulator_init_ldo[7],
&wm831x_regulator_init_ldo[8],
&wm831x_regulator_init_ldo[9],
&wm831x_regulator_init_ldo[10],
},
};
#endif

1688
arch/arm/mach-rk30/board-rk3066b-sdk.c Normal file
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File diff suppressed because it is too large Load Diff

1148
arch/arm/mach-rk30/board-rk31-fpga.c Normal file
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File diff suppressed because it is too large Load Diff

2
arch/arm/mach-rk30/clock.h
View File

@ -1,7 +1,7 @@
#ifndef __MACH_CLOCK_H__
#define __MACH_CLOCK_H__
#ifndef CONFIG_ARCH_RK30
#if (!defined(CONFIG_ARCH_RK30) && !defined(CONFIG_ARCH_RK31))
#define RK30_CLK_OFFBOARD_TEST
#endif

37
arch/arm/mach-rk30/clock_data.c
View File

@ -26,6 +26,7 @@
#include "clock.h"
#include <mach/pmu.h>
#include <mach/dvfs.h>
#include <mach/ddr.h>
#define MHZ (1000*1000)
#define KHZ (1000)
@ -41,6 +42,8 @@
#define CLK_FLG_MAX_I2S_22579_2KHZ (1<<2)
#define CLK_FLG_MAX_I2S_24576KHZ (1<<3)
#define CLK_FLG_MAX_I2S_49152KHZ (1<<4)
//uart 1m\3m
#define CLK_FLG_UART_1_3M (1<<5)
@ -1080,6 +1083,7 @@ static const struct pll_clk_set cpll_clks[] = {
_PLL_SET_CLKS(552000, 1, 23, 1),
_PLL_SET_CLKS(600000, 1, 25, 1),
_PLL_SET_CLKS(742500, 8, 495, 2),
_PLL_SET_CLKS(768000, 1, 32, 1),
_PLL_SET_CLKS(798000, 4, 133, 1),
_PLL_SET_CLKS(1188000,2, 99, 1),
_PLL_SET_CLKS( 0, 4, 133, 1),
@ -1115,12 +1119,24 @@ static int ddr_clk_set_rate(struct clk *c, unsigned long rate)
return 0;
}
static long ddr_clk_round_rate(struct clk *clk, unsigned long rate)
{
return ddr_set_pll(rate/MHZ,0)*MHZ;
}
static unsigned long ddr_clk_recalc_rate(struct clk *clk)
{
u32 shift = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift);
unsigned long rate = clk->parent->recalc(clk->parent)>> shift;
pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
return rate;
}
static struct clk *clk_ddr_parents[2] = {&ddr_pll_clk, &general_pll_clk};
static struct clk clk_ddr = {
.name = "ddr",
.parent = &ddr_pll_clk,
.recalc = clksel_recalc_shift,
.recalc = ddr_clk_recalc_rate,
.set_rate = ddr_clk_set_rate,
.round_rate = ddr_clk_round_rate,
.clksel_con = CRU_CLKSELS_CON(26),
//CRU_DIV_SET(0x3,0,4),
//CRU_SRC_SET(1,8),
@ -1521,7 +1537,7 @@ static struct clk aclk_periph = {
.name = "aclk_periph",
.parent = &general_pll_clk,
.mode = gate_mode,
.gate_idx = CLK_GATE_ACLK_PEIRPH,
.gate_idx = CLK_GATE_ACLK_PERIPH,
.recalc = clksel_recalc_div,
.set_rate = clksel_set_rate_freediv,
.clksel_con = CRU_CLKSELS_CON(10),
@ -1529,13 +1545,13 @@ static struct clk aclk_periph = {
CRU_SRC_SET(1,15),
CRU_PARENTS_SET(aclk_periph_parents),
};
GATE_CLK(periph_src, aclk_periph, PEIRPH_SRC);
GATE_CLK(periph_src, aclk_periph, PERIPH_SRC);
static struct clk pclk_periph = {
.name = "pclk_periph",
.parent = &aclk_periph,
.mode = gate_mode,
.gate_idx = CLK_GATE_PCLK_PEIRPH,
.gate_idx = CLK_GATE_PCLK_PERIPH,
.recalc = clksel_recalc_shift,
.set_rate = clksel_set_rate_shift,
.clksel_con = CRU_CLKSELS_CON(10),
@ -1546,7 +1562,7 @@ static struct clk hclk_periph = {
.name = "hclk_periph",
.parent = &aclk_periph,
.mode = gate_mode,
.gate_idx = CLK_GATE_HCLK_PEIRPH,
.gate_idx = CLK_GATE_HCLK_PERIPH,
.recalc = clksel_recalc_shift,
.set_rate = clksel_set_rate_shift,
.clksel_con = CRU_CLKSELS_CON(10),
@ -1771,8 +1787,6 @@ static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
parent = clk->parents[UART_SRC_FRAC];
}
CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n",
clk->name,rate,parent->name,clk->parent->name);
@ -3290,11 +3304,10 @@ static void __init rk30_clock_common_init(unsigned long gpll_rate,unsigned long
clk_set_rate_nolock(&clk_spi1, clk_spi1.parent->rate);
// uart
#if 0
clk_set_parent_nolock(&clk_uart_pll, &codec_pll_clk);
#else
clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
#endif
if(rk30_clock_flags&CLK_FLG_UART_1_3M)
clk_set_parent_nolock(&clk_uart_pll, &codec_pll_clk);
else
clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
//mac
if(!(gpll_rate%(50*MHZ)))
clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);

28
arch/arm/mach-rk30/cpufreq.c Executable file → Normal file
View File

@ -31,6 +31,8 @@
#include <linux/earlysuspend.h>
#include <asm/unistd.h>
#include <asm/uaccess.h>
#include <mach/ddr.h>
#include <linux/cpu.h>
#ifdef DEBUG
#define FREQ_PRINTK_DBG(fmt, args...) pr_debug(fmt, ## args)
#define FREQ_PRINTK_LOG(fmt, args...) pr_debug(fmt, ## args)
@ -68,6 +70,7 @@ static struct clk *cpu_gpll;
static DEFINE_MUTEX(cpufreq_mutex);
static struct clk *gpu_clk;
static struct clk *ddr_clk;
#define GPU_MAX_RATE 350*1000*1000
static int cpufreq_scale_rate_for_dvfs(struct clk *clk, unsigned long rate, dvfs_set_rate_callback set_rate);
@ -220,11 +223,20 @@ static int rk30_verify_speed(struct cpufreq_policy *policy)
return cpufreq_frequency_table_verify(policy, freq_table);
}
uint32_t ddr_set_rate(uint32_t nMHz);
int ddr_scale_rate_for_dvfs(struct clk *clk, unsigned long rate, dvfs_set_rate_callback set_rate)
{
#if defined (CONFIG_DDR_FREQ)
ddr_set_rate(rate/(1000*1000));
#endif
return 0;
}
static int rk30_cpu_init(struct cpufreq_policy *policy)
{
if (policy->cpu == 0) {
int i;
struct clk *ddr_clk;
gpu_clk = clk_get(NULL, "gpu");
if (!IS_ERR(gpu_clk))
@ -233,8 +245,9 @@ static int rk30_cpu_init(struct cpufreq_policy *policy)
ddr_clk = clk_get(NULL, "ddr");
if (!IS_ERR(ddr_clk))
{
dvfs_clk_register_set_rate_callback(ddr_clk, ddr_scale_rate_for_dvfs);
clk_enable_dvfs(ddr_clk);
clk_set_rate(ddr_clk,clk_get_rate(ddr_clk)-1);
//clk_set_rate(ddr_clk,clk_get_rate(ddr_clk)-1);
}
cpu_clk = clk_get(NULL, "cpu");
@ -262,7 +275,7 @@ static int rk30_cpu_init(struct cpufreq_policy *policy)
freq_wq = create_singlethread_workqueue("rk30_cpufreqd");
#ifdef CONFIG_RK30_CPU_FREQ_LIMIT_BY_TEMP
if (rk30_cpufreq_is_ondemand_policy(policy)) {
queue_delayed_work(freq_wq, &rk30_cpufreq_temp_limit_work, 60*HZ);
queue_delayed_work(freq_wq, &rk30_cpufreq_temp_limit_work, 0*HZ);
}
cpufreq_register_notifier(&notifier_policy_block, CPUFREQ_POLICY_NOTIFIER);
#endif
@ -509,9 +522,18 @@ static void __exit ff_exit(void)
static unsigned int cpufreq_scale_limt(unsigned int target_freq, struct cpufreq_policy *policy)
{
bool is_ondemand = rk30_cpufreq_is_ondemand_policy(policy);
static bool is_booting = true;
if (is_ondemand && clk_get_rate(gpu_clk) > GPU_MAX_RATE) // high performance?
return max_freq;
if (is_ondemand && is_booting && target_freq >= 1600 * 1000) {
s64 boottime_ms = ktime_to_ms(ktime_get_boottime());
if (boottime_ms > 30 * MSEC_PER_SEC) {
is_booting = false;
} else {
target_freq = 1416 * 1000;
}
}
#ifdef CONFIG_RK30_CPU_FREQ_LIMIT_BY_TEMP
if (is_ondemand && target_freq > policy->cur && policy->cur >= TEMP_LIMIT_FREQ) {
unsigned int i;

119
arch/arm/mach-rk30/ddr.c
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@ -124,7 +124,7 @@ typedef uint32_t uint32;
//mr1 for ddr3
#define DDR3_DLL_ENABLE (0)
#define DDR3_DLL_DISABLE (1)
#define DDR3_MR1_AL(n) (((n)&0x7)<<3)
#define DDR3_MR1_AL(n) (((n)&0x3)<<3)
#define DDR3_DS_40 (0)
#define DDR3_DS_34 (1<<1)
@ -914,11 +914,11 @@ DDR_CONFIG_2_RBC_T ddr_cfg_2_rbc[16] =
{15,3,10} // bank ahead
};
uint32_t ddr_data_training_buf[32];
__attribute__((aligned(4096))) uint32_t ddr_data_training_buf[32];
uint32_t __sramdata ddr3_cl_cwl[22][4]={
/* 0~330 330~400 400~533 speed
* tCK >3 2.5~3 1.875~2.5 1.875~1.5
* tCK >3 2.5~3 1.875~2.5 1.5~1.875
* cl<<16, cwl cl<<16, cwl cl<<16, cwl */
{((5<<16)|5), ((5<<16)|5), 0 , 0}, //DDR3_800D
{((5<<16)|5), ((6<<16)|5), 0 , 0}, //DDR3_800E
@ -929,7 +929,7 @@ uint32_t __sramdata ddr3_cl_cwl[22][4]={
{((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((7<<16)|7)}, //DDR3_1333F
{((5<<16)|5), ((5<<16)|5), ((7<<16)|6), ((8<<16)|7)}, //DDR3_1333G
{((5<<16)|5), ((6<<16)|5), ((7<<16)|6), ((9<<16)|7)}, //DDR3_1333H
{((5<<16)|5), ((6<<16)|5), ((8<<16)|6), ((9<<16)|7)}, //DDR3_1333H
{((5<<16)|5), ((6<<16)|5), ((8<<16)|6), ((10<<16)|7)}, //DDR3_1333J
{((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((7<<16)|7)}, //DDR3_1600G
@ -993,13 +993,13 @@ Cpu highest frequency is 1.6 GHz
1 cycle = 1/1.6 ns
1 us = 1000 ns = 1000 * 1.6 cycles = 1600 cycles
*****************************************************************************/
static __sramdata uint32_t loops_per_us;
static __sramdata volatile uint32_t loops_per_us;
#define LPJ_100MHZ 999456UL
/*static*/ void __sramlocalfunc ddr_delayus(uint32_t us)
{
uint32_t count;
volatile uint32_t count;
count = loops_per_us*us;
while(count--) // 3 cycles
@ -1115,12 +1115,15 @@ __sramfunc void ddr_move_to_Lowpower_state(void)
{
case Init_mem:
pDDR_Reg->SCTL = CFG_STATE;
dsb();
while((pDDR_Reg->STAT.b.ctl_stat) != Config);
case Config:
pDDR_Reg->SCTL = GO_STATE;
dsb();
while((pDDR_Reg->STAT.b.ctl_stat) != Access);
case Access:
pDDR_Reg->SCTL = SLEEP_STATE;
dsb();
while((pDDR_Reg->STAT.b.ctl_stat) != Low_power);
break;
default: //Transitional state
@ -1135,6 +1138,7 @@ __sramfunc void ddr_move_to_Access_state(void)
//set auto self-refresh idle
pDDR_Reg->MCFG1=(pDDR_Reg->MCFG1&0xffffff00)|ddr_sr_idle;
dsb();
while(1)
{
@ -1148,14 +1152,17 @@ __sramfunc void ddr_move_to_Access_state(void)
{
case Low_power:
pDDR_Reg->SCTL = WAKEUP_STATE;
dsb();
while((pDDR_Reg->STAT.b.ctl_stat) != Access);
while((pPHY_Reg->PGSR & DLDONE) != DLDONE); //wait DLL lock
break;
case Init_mem:
pDDR_Reg->SCTL = CFG_STATE;
dsb();
while((pDDR_Reg->STAT.b.ctl_stat) != Config);
case Config:
pDDR_Reg->SCTL = GO_STATE;
dsb();
while(!(((pDDR_Reg->STAT.b.ctl_stat) == Access)
|| ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power))));
break;
@ -1187,11 +1194,13 @@ __sramfunc void ddr_move_to_Config_state(void)
{
case Low_power:
pDDR_Reg->SCTL = WAKEUP_STATE;
dsb();
while((pDDR_Reg->STAT.b.ctl_stat) != Access);
while((pPHY_Reg->PGSR & DLDONE) != DLDONE); //wait DLL lock
case Access:
case Init_mem:
pDDR_Reg->SCTL = CFG_STATE;
dsb();
while((pDDR_Reg->STAT.b.ctl_stat) != Config);
break;
default: //Transitional state
@ -1203,9 +1212,8 @@ __sramfunc void ddr_move_to_Config_state(void)
//arg°üÀ¨bank_addrºÍcmd_addr
void __sramlocalfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
{
uint32 i;
pDDR_Reg->MCMD = (start_cmd | (rank<<20) | arg | cmd);
for (i = 0; i < 10; i ++) {;}
dsb();
while(pDDR_Reg->MCMD & start_cmd);
}
@ -1214,17 +1222,18 @@ void __sramlocalfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
//!0 DTTʧ°Ü
uint32_t __sramlocalfunc ddr_data_training(void)
{
uint32 i,value,cs;
uint32 value,cs;
// disable auto refresh
value = pDDR_Reg->TREFI;
pDDR_Reg->TREFI = 0;
dsb();
// clear DTDONE status
pPHY_Reg->PIR |= CLRSR;
cs = ((pPHY_Reg->PGCR>>18) & 0xF);
// trigger DTT
pPHY_Reg->PIR |= INIT | QSTRN | LOCKBYP | ZCALBYP | CLRSR | ICPC;
for (i = 0; i < 10; i ++) {;}
dsb();
// wait echo byte DTDONE
while((pPHY_Reg->DATX8[0].DXGSR[0] & cs) != cs);
while((pPHY_Reg->DATX8[1].DXGSR[0] & cs) != cs);
@ -1343,14 +1352,14 @@ uint32_t __sramlocalfunc ddr_set_pll(uint32_t nMHz, uint32_t set)
else
{
pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x0<<(pll_id*4)); //PLL slow-mode
dsb();
pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_RESET;
pCRU_Reg->CRU_PLL_CON[pll_id][0] = NR(clkr) | NO(clkod);
pCRU_Reg->CRU_PLL_CON[pll_id][1] = NF(clkf);
pCRU_Reg->CRU_PLL_CON[pll_id][2] = NB(clkf>>1);
ddr_delayus(1);
pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_DE_RESET;
dsb();
while (delay > 0)
{
ddr_delayus(1);
@ -1364,6 +1373,7 @@ uint32_t __sramlocalfunc ddr_set_pll(uint32_t nMHz, uint32_t set)
| 0; //clk_ddr_src:clk_ddrphy = 1:1
pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x1<<(pll_id*4)); //PLL normal
dsb();
}
out:
return ret;
@ -1374,7 +1384,7 @@ uint32_t ddr_get_parameter(uint32_t nMHz)
uint32_t tmp;
uint32_t ret = 0;
uint32_t al;
uint32_t bl;
uint32_t bl,bl_tmp;
uint32_t cl;
uint32_t cwl;
PCTL_TIMING_T *p_pctl_timing=&(ddr_reg.pctl.pctl_timing);
@ -1561,7 +1571,8 @@ uint32_t ddr_get_parameter(uint32_t nMHz)
tmp = tmp - 4;
else
tmp = tmp>>1;
p_publ_timing->mr[0] = DDR3_BL8 | DDR3_CL(cl) | DDR3_WR(tmp);
bl_tmp = (bl == 8) ? DDR3_BL8 : DDR3_BC4;
p_publ_timing->mr[0] = bl_tmp | DDR3_CL(cl) | DDR3_WR(tmp);
/*
* tWTR, max(4 tCK,7.5ns)
@ -1901,7 +1912,8 @@ uint32_t ddr_get_parameter(uint32_t nMHz)
* tWR, 15ns
*/
p_pctl_timing->twr = ((LPDDR2_tWR*nMHz+999)/1000)&0x1F;
p_publ_timing->mr[1] = LPDDR2_BL8 | LPDDR2_nWR(((LPDDR2_tWR*nMHz+999)/1000));
bl_tmp = (bl == 16) ? LPDDR2_BL16 : ((bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4);
p_publ_timing->mr[1] = bl_tmp | LPDDR2_nWR(((LPDDR2_tWR*nMHz+999)/1000));
/*
* tWTR, 7.5ns(533-266MHz) 10ns(200-166MHz)
*/
@ -2194,7 +2206,8 @@ uint32_t ddr_get_parameter(uint32_t nMHz)
*/
tmp = ((DDR2_tWR*nMHz+999)/1000);
p_pctl_timing->twr = tmp&0x1F;
p_publ_timing->mr[0] = DDR2_BL4 | DDR2_CL(cl) | DDR2_WR(tmp);
bl_tmp = (bl == 8) ? DDR2_BL8 : DDR2_BL4;
p_publ_timing->mr[0] = bl_tmp | DDR2_CL(cl) | DDR2_WR(tmp);
/*
* tWTR, 10ns(200MHz) 7.5ns(>200MHz)
*/
@ -2360,7 +2373,8 @@ uint32_t ddr_get_parameter(uint32_t nMHz)
*/
cl = 3;
cwl = 1;
p_publ_timing->mr[0] = mDDR_BL4 | mDDR_CL(cl);
bl_tmp = (bl == 8) ? mDDR_BL8 : ((bl == 4) ? mDDR_BL4 : mDDR_BL2);
p_publ_timing->mr[0] = bl_tmp | mDDR_CL(cl);
p_publ_timing->mr[2] = mDDR_DS_3_4; //mr[2] is mDDR MR1
p_publ_timing->mr[1] = 0;
p_publ_timing->mr[3] = 0;
@ -2596,7 +2610,7 @@ uint32_t ddr_get_parameter(uint32_t nMHz)
uint32_t __sramlocalfunc ddr_update_timing(void)
{
uint32_t i;
uint32_t i,bl_tmp;
PCTL_TIMING_T *p_pctl_timing=&(ddr_reg.pctl.pctl_timing);
PHY_TIMING_T *p_publ_timing=&(ddr_reg.publ.phy_timing);
NOC_TIMING_T *p_noc_timing=&(ddr_reg.noc_timing);
@ -2607,15 +2621,28 @@ uint32_t __sramlocalfunc ddr_update_timing(void)
// Update PCTL BL
if(mem_type == DDR3)
{
pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | ddr2_ddr3_bl_8 | tfaw_cfg(5)|pd_exit_slow|pd_type(1);
bl_tmp = ((p_publ_timing->mr[0] & 0x3) == DDR3_BL8) ? ddr2_ddr3_bl_8 : ddr2_ddr3_bl_4;
pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_slow|pd_type(1);
pDDR_Reg->DFITRDDATAEN = pDDR_Reg->TCL-2;
pDDR_Reg->DFITPHYWRLAT = pDDR_Reg->TCWL-1;
}
else if(mem_type == LPDDR2)
{
switch(p_publ_timing->mr[1] & 0x7)
{
case LPDDR2_BL4:
bl_tmp = mddr_lpddr2_bl_4;
break;
case LPDDR2_BL8:
bl_tmp = mddr_lpddr2_bl_8;
break;
case LPDDR2_BL16:
bl_tmp = mddr_lpddr2_bl_16;
break;
}
if(ddr_freq>=200)
{
pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | mddr_lpddr2_bl_8 | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
}
else
{
@ -2628,11 +2655,24 @@ uint32_t __sramlocalfunc ddr_update_timing(void)
}
else if(mem_type == DDR2)
{
pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | ddr2_ddr3_bl_8 | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
bl_tmp = ((p_publ_timing->mr[0] & 0x3) == DDR2_BL8) ? ddr2_ddr3_bl_8 : ddr2_ddr3_bl_4;
pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
}
else// if(mem_type == LPDDR)
{
pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | mddr_lpddr2_bl_4 | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
switch(p_publ_timing->mr[0] & 0x7)
{
case mDDR_BL2:
bl_tmp = mddr_lpddr2_bl_2;
break;
case mDDR_BL4:
bl_tmp = mddr_lpddr2_bl_4;
break;
case mDDR_BL8:
bl_tmp = mddr_lpddr2_bl_8;
break;
}
pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
}
return 0;
}
@ -2640,15 +2680,16 @@ uint32_t __sramlocalfunc ddr_update_timing(void)
uint32_t __sramlocalfunc ddr_update_mr(void)
{
PHY_TIMING_T *p_publ_timing=&(ddr_reg.publ.phy_timing);
uint32_t cs;
uint32_t cs,dll_off;
cs = ((pPHY_Reg->PGCR>>18) & 0xF);
dll_off = (pPHY_Reg->MR[1] & DDR3_DLL_DISABLE) ? 1:0;
ddr_copy((uint32_t *)&(pPHY_Reg->MR[0]), (uint32_t*)&(p_publ_timing->mr[0]), 4);
if((mem_type == DDR3) || (mem_type == DDR2))
{
if(ddr_freq>DDR3_DDR2_DLL_DISABLE_FREQ)
{
if(pPHY_Reg->MR[1] & DDR3_DLL_DISABLE) // off -> on
if(dll_off) // off -> on
{
ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((uint8_t)(p_publ_timing->mr[1]))); //DLL enable
ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr(((uint8_t)(p_publ_timing->mr[0]))| DDR3_DLL_RESET)); //DLL reset
@ -2716,9 +2757,11 @@ void __sramlocalfunc ddr_update_odt(void)
cs = ((pPHY_Reg->PGCR>>18) & 0xF);
if(cs > 1)
{
pPHY_Reg->ZQ1CR[0] = tmp;
pPHY_Reg->ZQ1CR[1] = tmp;
dsb();
}
pPHY_Reg->ZQ0CR[0] = tmp;
dsb();
}
__sramfunc void ddr_adjust_config(uint32_t dram_type)
@ -2736,6 +2779,7 @@ __sramfunc void ddr_adjust_config(uint32_t dram_type)
flush_cache_all();
outer_flush_all();
flush_tlb_all();
isb();
DDR_SAVE_SP(save_sp);
for(i=0;i<16;i++)
@ -2796,30 +2840,35 @@ void __sramlocalfunc idle_port(void)
if ( (pPMU_Reg->PMU_PWRDN_ST & pd_a9_0_pwr_st) == 0 )
{
pPMU_Reg->PMU_MISC_CON1 |= idle_req_cpu_cfg;
dsb();
while( (pPMU_Reg->PMU_PWRDN_ST & idle_cpu) == 0 );
}
if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st) == 0 )
{
pPMU_Reg->PMU_MISC_CON1 |= idle_req_peri_cfg;
dsb();
while( (pPMU_Reg->PMU_PWRDN_ST & idle_peri) == 0 );
}
if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st) == 0 )
{
pPMU_Reg->PMU_MISC_CON1 |= idle_req_vio_cfg;
dsb();
while( (pPMU_Reg->PMU_PWRDN_ST & idle_vio) == 0 );
}
if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st) == 0 )
{
pPMU_Reg->PMU_MISC_CON1 |= idle_req_video_cfg;
dsb();
while( (pPMU_Reg->PMU_PWRDN_ST & idle_video) == 0 );
}
if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st) == 0 )
{
pPMU_Reg->PMU_MISC_CON1 |= idle_req_gpu_cfg;
dsb();
while( (pPMU_Reg->PMU_PWRDN_ST & idle_gpu) == 0 );
}
@ -2844,29 +2893,34 @@ void __sramlocalfunc deidle_port(void)
if ( (pPMU_Reg->PMU_PWRDN_ST & pd_a9_0_pwr_st) == 0 )
{
pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_cpu_cfg;
dsb();
while( (pPMU_Reg->PMU_PWRDN_ST & idle_cpu) != 0 );
}
if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st) == 0 )
{
pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_peri_cfg;
dsb();
while( (pPMU_Reg->PMU_PWRDN_ST & idle_peri) != 0 );
}
if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st) == 0 )
{
pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_vio_cfg;
dsb();
while( (pPMU_Reg->PMU_PWRDN_ST & idle_vio) != 0 );
}
if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st) == 0 )
{
pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_video_cfg;
dsb();
while( (pPMU_Reg->PMU_PWRDN_ST & idle_video) != 0 );
}
if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st) == 0 )
{
pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_gpu_cfg;
dsb();
while( (pPMU_Reg->PMU_PWRDN_ST & idle_gpu) != 0 );
}
@ -2948,6 +3002,7 @@ uint32_t __sramfunc ddr_change_freq(uint32_t nMHz)
flush_cache_all();
outer_flush_all();
flush_tlb_all();
isb();
DDR_SAVE_SP(save_sp);
for(i=0;i<16;i++)
{
@ -2978,7 +3033,6 @@ uint32_t __sramfunc ddr_change_freq(uint32_t nMHz)
DDR_RESTORE_SP(save_sp);
local_fiq_enable();
local_irq_restore(flags);
clk_set_rate(clk_get(NULL, "ddr_pll"), 0);
return ret;
}
@ -2998,10 +3052,10 @@ void __sramfunc ddr_suspend(void)
volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
/** 1. Make sure there is no host access */
flush_cache_all();
outer_flush_all();
flush_tlb_all();
//flush_cache_all();
//outer_flush_all();
//flush_tlb_all();
for(i=0;i<16;i++)
{
n=temp[1024*i];
@ -3171,7 +3225,7 @@ int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
uint32_t cs,die=1;
uint32_t gsr,dqstr;
ddr_print("version 1.00 20120608 \n");
ddr_print("version 1.00 20120820 \n");
mem_type = pPHY_Reg->DCR.b.DDRMD;
ddr_speed_bin = dram_speed_bin;
@ -3221,6 +3275,7 @@ int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
ddr_adjust_config(mem_type);
value=ddr_change_freq(freq);
clk_set_rate(clk_get(NULL, "ddr_pll"), 0);
ddr_print("init success!!! freq=%dMHz\n", value);
for(value=0;value<4;value++)
@ -3228,7 +3283,7 @@ int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
gsr = pPHY_Reg->DATX8[value].DXGSR[0];
dqstr = pPHY_Reg->DATX8[value].DXDQSTR;
ddr_print("DTONE=0x%x, DTERR=0x%x, DTIERR=0x%x, DTPASS=0x%x, DGSL=%d extra clock, DGPS=%d\n", \
(gsr&0xF), ((gsr>>4)&0xF), ((gsr>>8)&0xF), ((gsr>>13)&0xFFF), (dqstr&0x7), (((dqstr>>12)&0x3)*90));
(gsr&0xF), ((gsr>>4)&0xF), ((gsr>>8)&0xF), ((gsr>>13)&0xFFF), (dqstr&0x7), ((((dqstr>>12)&0x3)+1)*90));
}
ddr_print("ZERR=%x, ZDONE=%x, ZPD=0x%x, ZPU=0x%x, OPD=0x%x, OPU=0x%x\n", \
(pPHY_Reg->ZQ0SR[0]>>30)&0x1, \

130
arch/arm/mach-rk30/ddr_freq.c Executable file → Normal file
View File

@ -4,82 +4,132 @@
#include <linux/slab.h>
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/clk.h>
#define ddr_print(x...) printk( "DDR DEBUG: " x )
struct ddr{
int suspend;
struct early_suspend early_suspend;
struct ddr {
int suspend;
struct early_suspend early_suspend;
struct clk *ddr_pll;
};
struct ddr *ddr = NULL;
static void ddr_early_suspend(struct early_suspend *h);
static void ddr_late_resume(struct early_suspend *h);
static struct ddr ddr = {
.early_suspend = {
.suspend = ddr_early_suspend,
.resume = ddr_late_resume,
.level = EARLY_SUSPEND_LEVEL_DISABLE_FB + 50,
},
};
static volatile bool __sramdata cpu1_pause;
static inline bool is_cpu1_paused(void) { smp_rmb(); return cpu1_pause; }
static inline void set_cpu1_pause(bool pause) { cpu1_pause = pause; smp_wmb(); }
#define MAX_TIMEOUT (16000000UL << 6) //>0.64s
static void __ddr_change_freq(void *info)
{
uint32_t *value = info;
u32 timeout = MAX_TIMEOUT;
while (!is_cpu1_paused() && --timeout);
if (timeout == 0)
return;
*value = ddr_change_freq(*value);
set_cpu1_pause(false);
}
/* Do not use stack, safe on SMP */
static void __sramfunc pause_cpu1(void *info)
{
u32 timeout = MAX_TIMEOUT;
unsigned long flags;
local_irq_save(flags);
set_cpu1_pause(true);
while (is_cpu1_paused() && --timeout);
local_irq_restore(flags);
}
static uint32_t _ddr_change_freq(uint32_t nMHz)
{
int this_cpu = get_cpu();
set_cpu1_pause(false);
if (this_cpu == 0) {
if (smp_call_function_single(1, (smp_call_func_t)pause_cpu1, NULL, 0) == 0) {
u32 timeout = MAX_TIMEOUT;
while (!is_cpu1_paused() && --timeout);
if (timeout == 0)
goto out;
}
nMHz = ddr_change_freq(nMHz);
set_cpu1_pause(false);
} else {
smp_call_function_single(0, __ddr_change_freq, &nMHz, 0);
pause_cpu1(NULL);
}
clk_set_rate(ddr.ddr_pll, 0);
out:
put_cpu();
return nMHz;
}
uint32_t ddr_set_rate(uint32_t nMHz)
{
_ddr_change_freq(nMHz);
return 0;
}
#ifdef CONFIG_HAS_EARLYSUSPEND
static void ddr_early_suspend(struct early_suspend *h)
{
uint32_t value;
bool cpu1_online;
//Enable auto self refresh 0x01*32 DDR clk cycle
ddr_set_auto_self_refresh(true);
cpu1_online = cpu_online(1);
if(cpu1_online)
cpu_down(1);
value=ddr_change_freq(100);
value = _ddr_change_freq(100);
if(cpu1_online)
cpu_up(1);
ddr_print("init success!!! freq=%dMHz\n", value);
return;
}
static void ddr_early_resume(struct early_suspend *h)
static void ddr_late_resume(struct early_suspend *h)
{
uint32_t value;
bool cpu1_online;
//Disable auto self refresh
ddr_set_auto_self_refresh(false);
cpu1_online = cpu_online(1);
if(cpu1_online)
cpu_down(1);
value = _ddr_change_freq(DDR_FREQ);
value=ddr_change_freq(DDR_FREQ);
if(cpu1_online)
cpu_up(1);
ddr_print("init success!!! freq=%dMHz\n", value);
return;
}
#endif
static int rk30_ddr_late_init (void)
{
ddr = kmalloc(sizeof(struct ddr), GFP_KERNEL);
if(!ddr)
{
ddr_print("%s: kmalloc fail!\n",__FUNCTION__);
return -ENOMEM;
}
memset(ddr, 0, sizeof(struct ddr));
#ifdef CONFIG_HAS_EARLYSUSPEND
ddr->early_suspend.suspend = ddr_early_suspend;
ddr->early_suspend.resume = ddr_early_resume;
ddr->early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB + 50;
register_early_suspend(&ddr->early_suspend);
#endif
ddr.ddr_pll = clk_get(NULL, "ddr_pll");
register_early_suspend(&ddr.early_suspend);
return 0;
}
late_initcall(rk30_ddr_late_init);
#endif
#ifdef CONFIG_DDR_TEST
#include <linux/slab.h>

14
arch/arm/mach-rk30/devices.c
View File

@ -51,6 +51,7 @@ struct platform_device device_adc = {
};
#endif
#ifdef CONFIG_ARCH_RK30
static struct resource rk30_tsadc_resource[] = {
{
.start = IRQ_TSADC,
@ -64,12 +65,13 @@ static struct resource rk30_tsadc_resource[] = {
},
};
struct platform_device device_tsadc = {
static struct platform_device device_tsadc = {
.name = "rk30-tsadc",
.id = -1,
.num_resources = ARRAY_SIZE(rk30_tsadc_resource),
.resource = rk30_tsadc_resource,
};
#endif
static u64 dma_dmamask = DMA_BIT_MASK(32);
@ -909,7 +911,7 @@ static struct platform_device device_nand = {
};
#endif
#ifdef CONFIG_LCDC0_RK30
#if defined(CONFIG_LCDC0_RK30) || defined(CONFIG_LCDC0_RK31)
extern struct rk29fb_info lcdc0_screen_info;
static struct resource resource_lcdc0[] = {
[0] = {
@ -937,7 +939,7 @@ static struct platform_device device_lcdc0 = {
},
};
#endif
#ifdef CONFIG_LCDC1_RK30
#if defined(CONFIG_LCDC1_RK30) || defined(CONFIG_LCDC1_RK31)
extern struct rk29fb_info lcdc1_screen_info;
static struct resource resource_lcdc1[] = {
[0] = {
@ -1311,10 +1313,10 @@ static int __init rk30_init_devices(void)
platform_device_register(&device_rga);
#endif
platform_device_register(&device_ipp);
#ifdef CONFIG_LCDC0_RK30
#if defined(CONFIG_LCDC0_RK30) || defined(CONFIG_LCDC0_RK31)
platform_device_register(&device_lcdc0);
#endif
#ifdef CONFIG_LCDC1_RK30
#if defined(CONFIG_LCDC1_RK30) || defined(CONFIG_LCDC1_RK31)
platform_device_register(&device_lcdc1);
#endif
#ifdef CONFIG_HDMI_RK30
@ -1323,7 +1325,9 @@ static int __init rk30_init_devices(void)
#ifdef CONFIG_ADC_RK30
platform_device_register(&device_adc);
#endif
#ifdef CONFIG_ARCH_RK30
platform_device_register(&device_tsadc);
#endif
rk30_init_sdmmc();
#if defined(CONFIG_FIQ_DEBUGGER) && defined(DEBUG_UART_PHYS)
rk_serial_debug_init(DEBUG_UART_BASE, IRQ_DEBUG_UART, IRQ_UART_SIGNAL, -1);

31
arch/arm/mach-rk30/dvfs.c
View File

@ -33,6 +33,10 @@
#else
#define DVFS_DBG(fmt, args...) printk(KERN_DEBUG "DVFS DBG:\t"fmt, ##args)
#endif
#define DVFS_SET_VOLT_FAILURE 1
#define DVFS_SET_VOLT_SUCCESS 0
#define DVFS_ERR(fmt, args...) printk(KERN_ERR "DVFS ERR:\t"fmt, ##args)
#define DVFS_LOG(fmt, args...) printk(KERN_DEBUG "DVFS LOG:\t"fmt, ##args)
@ -394,6 +398,21 @@ int clk_enable_dvfs(struct clk *clk)
}
#endif
dvfs_vd_get_newvolt_byclk(dvfs_clk);
if(dvfs_clk->vd->cur_volt<dvfs_clk->set_volt)
{
int ret;
mutex_lock(&rk_dvfs_mutex);
ret = dvfs_regulator_set_voltage_readback(dvfs_clk->vd->regulator, dvfs_clk->set_volt, dvfs_clk->set_volt);
if (ret < 0) {
dvfs_clk->vd->volt_set_flag = DVFS_SET_VOLT_FAILURE;
dvfs_clk->enable_dvfs = 0;
DVFS_ERR("dvfs enable clk %s,set volt error \n", dvfs_clk->name);
mutex_unlock(&rk_dvfs_mutex);
return -1;
}
dvfs_clk->vd->volt_set_flag = DVFS_SET_VOLT_SUCCESS;
mutex_unlock(&rk_dvfs_mutex);
}
dvfs_clk->enable_dvfs++;
} else {
DVFS_ERR("dvfs already enable clk enable = %d!\n", dvfs_clk->enable_dvfs);
@ -694,8 +713,7 @@ static int dvfs_set_depend_post(struct clk_node *dvfs_clk, unsigned long rate_ol
return 0;
}
#endif
#define DVFS_SET_VOLT_FAILURE 1
#define DVFS_SET_VOLT_SUCCESS 0
#define ARM_HIGHER_LOGIC (150 * 1000)
#define LOGIC_HIGHER_ARM (100 * 1000)
@ -911,7 +929,7 @@ int dvfs_scale_volt_bystep(struct vd_node *vd_clk, struct vd_node *vd_dep, int v
if (check_volt_correct(volt_old, &volt_new, volt_dep_old, &volt_dep_new,
clk_biger_than_dep, dep_biger_than_clk) < 0) {
DVFS_ERR("CURRENT VOLT INCORRECT\n");
DVFS_ERR("CURRENT VOLT INCORRECT, VD=%s, VD_DEP=%s\n", vd_clk->name, vd_dep->name);
return -1;
}
DVFS_DBG("ENTER %s, volt=%d(old=%d), volt_dep=%d(dep_old=%d)\n", __func__,
@ -1019,6 +1037,8 @@ int dvfs_target_cpu(struct clk *clk, unsigned long rate_hz)
/* need round rate */
rate_old = clk_get_rate(clk);
rate_new = clk_round_rate_nolock(clk, rate_hz);
if(rate_new==rate_old)
return 0;
DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu) old (%lu)\n",
dvfs_clk->name, rate_hz, rate_new, rate_old);
@ -1145,6 +1165,8 @@ int dvfs_target_core(struct clk *clk, unsigned long rate_hz)
/* need round rate */
rate_old = clk_get_rate(clk);
rate_new = clk_round_rate_nolock(clk, rate_hz);
if(rate_new==rate_old)
return 0;
DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu) old (%lu)\n",
dvfs_clk->name, rate_hz, rate_new, rate_old);
@ -1270,18 +1292,21 @@ static struct cpufreq_frequency_table dep_cpu2core_table[] = {
static struct vd_node vd_cpu = {
.name = "vd_cpu",
.regulator_name = "vdd_cpu",
.volt_set_flag =DVFS_SET_VOLT_FAILURE,
.vd_dvfs_target = dvfs_target_cpu,
};
static struct vd_node vd_core = {
.name = "vd_core",
.regulator_name = "vdd_core",
.volt_set_flag =DVFS_SET_VOLT_FAILURE,
.vd_dvfs_target = dvfs_target_core,
};
static struct vd_node vd_rtc = {
.name = "vd_rtc",
.regulator_name = "vdd_rtc",
.volt_set_flag =DVFS_SET_VOLT_FAILURE,
.vd_dvfs_target = NULL,
};

354
arch/arm/mach-rk30/i2c_sram.c Executable file
View File

@ -0,0 +1,354 @@
#include <linux/io.h>
#include <mach/board.h>
#include <mach/sram.h>
#include <mach/iomux.h>
#include <mach/cru.h>
#include <asm/io.h>
#include <mach/gpio.h>
#define cru_readl(offset) readl_relaxed(RK30_CRU_BASE + offset)
#define cru_writel(v, offset) do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
#if defined(CONFIG_RK30_I2C_INSRAM)
/******************need set when you use i2c*************************/
#define I2C_SPEED 100
#define I2C_SADDR (0x2D) /* slave address ,wm8310 addr is 0x34*/
#define SRAM_I2C_CH 1 //CH==0, i2c0,CH==1, i2c1,CH==2, i2c2,CH==3, i2c3
#define SRAM_I2C_ADDRBASE (RK30_I2C1_BASE + SZ_4K )//RK29_I2C0_BASE\RK29_I2C2_BASE\RK29_I2C3_BASE
#define I2C_SLAVE_ADDR_LEN 1 // 2:slav addr is 10bit ,1:slav addr is 7bit
#define I2C_SLAVE_REG_LEN 1 // 2:slav reg addr is 16 bit ,1:is 8 bit
#define SRAM_I2C_DATA_BYTE 1 //i2c transmission data is 1bit(8wei) or 2bit(16wei)
#define GRF_GPIO_IOMUX 0xd4 //GRF_GPIO2D_IOMUX
/*ch=0:GRF_GPIO2L_IOMUX,ch=1:GRF_GPIO1L_IOMUX,ch=2:GRF_GPIO5H_IOMUX,ch=3:GRF_GPIO2L_IOMUX*/
#define I2C_GRF_GPIO_IOMUX (0x01<<14)|(0x01<<12)
/*CH=0:(~(0x03<<30))&(~(0x03<<28))|(0x01<<30)|(0x01<<28),CH=1:(~(0x03<<14))&(~(0x03<<12))|(0x01<<14)|(0x01<<12),
CH=2:(~(0x03<<24))&(~(0x03<<22))|(0x01<<24)|(0x01<<22),CH=3:(~(0x03<<26))&(~(0x03<<24))|(0x02<<26)|(0x02<<24)*/
/***************************************/
#define I2C_SLAVE_TYPE (((I2C_SLAVE_ADDR_LEN-1)<<4)|((I2C_SLAVE_REG_LEN-1)))
#define uint8 unsigned char
#define uint16 unsigned short
#define uint32 unsigned int
uint32 __sramdata data[5];
uint8 __sramdata arm_voltage = 0;
#define CRU_CLKGATE0_CON 0xd0
#define CRU_CLKGATE8_CON 0xf0
#define CRU_CLKSEL1_CON 0x48
#define GRF_GPIO5H_IOMUX 0x74
#define GRF_GPIO2L_IOMUX 0x58
#define GRF_GPIO1L_IOMUX 0x50
#define COMPLETE_READ (1<<STATE_START|1<<STATE_READ|1<<STATE_STOP)
#define COMPLETE_WRITE (1<<STATE_START|1<<STATE_WRITE|1<<STATE_STOP)
/* Control register */
#define I2C_CON 0x0000
#define I2C_CON_EN (1 << 0)
#define I2C_CON_MOD(mod) ((mod) << 1)
#define I2C_CON_MASK (3 << 1)
enum{
I2C_CON_MOD_TX = 0,
I2C_CON_MOD_TRX,
I2C_CON_MOD_RX,
I2C_CON_MOD_RRX,
};
#define I2C_CON_START (1 << 3)
#define I2C_CON_STOP (1 << 4)
#define I2C_CON_LASTACK (1 << 5)
#define I2C_CON_ACTACK (1 << 6)
/* Clock dividor register */
#define I2C_CLKDIV 0x0004
#define I2C_CLKDIV_VAL(divl, divh) (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000))
#define rk30_ceil(x, y) \
({ unsigned long __x = (x), __y = (y); (__x + __y - 1) / __y; })
/* the slave address accessed for master rx mode */
#define I2C_MRXADDR 0x0008
#define I2C_MRXADDR_LOW (1 << 24)
#define I2C_MRXADDR_MID (1 << 25)
#define I2C_MRXADDR_HIGH (1 << 26)
/* the slave register address accessed for master rx mode */
#define I2C_MRXRADDR 0x000c
#define I2C_MRXRADDR_LOW (1 << 24)
#define I2C_MRXRADDR_MID (1 << 25)
#define I2C_MRXRADDR_HIGH (1 << 26)
/* master tx count */
#define I2C_MTXCNT 0x0010
/* master rx count */
#define I2C_MRXCNT 0x0014
/* interrupt enable register */
#define I2C_IEN 0x0018
#define I2C_BTFIEN (1 << 0)
#define I2C_BRFIEN (1 << 1)
#define I2C_MBTFIEN (1 << 2)
#define I2C_MBRFIEN (1 << 3)
#define I2C_STARTIEN (1 << 4)
#define I2C_STOPIEN (1 << 5)
#define I2C_NAKRCVIEN (1 << 6)
#define IRQ_MST_ENABLE (I2C_MBTFIEN | I2C_MBRFIEN | I2C_NAKRCVIEN | I2C_STARTIEN | I2C_STOPIEN)
#define IRQ_ALL_DISABLE 0
/* interrupt pending register */
#define I2C_IPD 0x001c
#define I2C_BTFIPD (1 << 0)
#define I2C_BRFIPD (1 << 1)
#define I2C_MBTFIPD (1 << 2)
#define I2C_MBRFIPD (1 << 3)
#define I2C_STARTIPD (1 << 4)
#define I2C_STOPIPD (1 << 5)
#define I2C_NAKRCVIPD (1 << 6)
#define I2C_IPD_ALL_CLEAN 0x7f
/* finished count */
#define I2C_FCNT 0x0020
/* I2C tx data register */
#define I2C_TXDATA_BASE 0X0100
/* I2C rx data register */
#define I2C_RXDATA_BASE 0x0200
void __sramfunc sram_i2c_enable(void);
void __sramfunc sram_i2c_disenable(void);
void __sramfunc sram_printch(char byte);
void __sramfunc sram_printhex(unsigned int hex);
#define sram_udelay(usecs) SRAM_LOOP((usecs)*SRAM_LOOPS_PER_USEC)
/*-------------------------------------------------------------------------------------------------------
Name : sram_i2c_init
Desc : initialize the necessary registers
Params : channel-determine which I2C bus we used
Return : none
------------------------------------------------------------------------------------------------------*/
void __sramfunc sram_i2c_init()
{
unsigned int div, divl, divh;
//enable cru_clkgate8 clock
data[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_CLKID(8)));
cru_writel(CLK_GATE_W_MSK(CLK_GATE_PCLK_I2C1)|CLK_UN_GATE(CLK_GATE_PCLK_I2C1),
CLK_GATE_CLKID_CONS(CLK_GATE_PCLK_I2C1));
data[2] = readl_relaxed(RK30_GRF_BASE + GRF_GPIO_IOMUX);
writel_relaxed(data[2]| I2C_GRF_GPIO_IOMUX, RK30_GRF_BASE + GRF_GPIO_IOMUX);
div = rk30_ceil(24*1000*1000, I2C_SPEED*1000 * 8);
divh = divl = rk30_ceil(div, 2);
writel_relaxed(I2C_CLKDIV_VAL(divl, divh), SRAM_I2C_ADDRBASE + I2C_CLKDIV);
data[3] = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CLKDIV);
}
/*-------------------------------------------------------------------------------------------------------
Name : sram_i2c_deinit
Desc : de-initialize the necessary registers
Params : noe
Return : none
------------------------------------------------------------------------------------------------------*/
void __sramfunc sram_i2c_deinit(void)
{
//restore iomux reg
writel_relaxed(data[2], RK30_GRF_BASE + GRF_GPIO_IOMUX);
//restore scu clock reg
cru_writel(data[1], CLK_GATE_CLKID_CONS(CLK_GATE_PCLK_I2C1));
}
/*-------------------------------------------------------------------------------------------------------
Name : sram_i2c_start
Desc : start i2c
Params : none
Return : none
------------------------------------------------------------------------------------------------------*/
void __sramfunc sram_i2c_read_enable(void)
{
writel_relaxed(((((I2C_CON_EN | I2C_CON_MOD(1)) | I2C_CON_LASTACK) )| I2C_CON_START) & (~(I2C_CON_STOP)) , SRAM_I2C_ADDRBASE + I2C_CON);
}
void __sramfunc sram_i2c_write_enable(void)
{
writel_relaxed(((((I2C_CON_EN | I2C_CON_MOD(0)) | I2C_CON_LASTACK) )| I2C_CON_START) & (~(I2C_CON_STOP)) , SRAM_I2C_ADDRBASE + I2C_CON);
}
void __sramfunc sram_i2c_disenable(void)
{
writel_relaxed(0, SRAM_I2C_ADDRBASE + I2C_CON);
}
void __sramfunc sram_i2c_clean_start(void)
{
unsigned int con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CON);
con = (con & (~I2C_CON_START)) ;
writel_relaxed(con, SRAM_I2C_ADDRBASE + I2C_CON);
}
void __sramfunc sram_i2c_send_start(void)
{
unsigned int con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CON);
con |= I2C_CON_START;
if(con & I2C_CON_STOP)
sram_printch('E');
writel_relaxed(con, SRAM_I2C_ADDRBASE + I2C_CON);
}
void __sramfunc sram_i2c_send_stop(void)
{
unsigned int con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CON);
con &= ~I2C_CON_START;
con |= I2C_CON_STOP;
if(con & I2C_CON_START)
sram_printch('E');
writel_relaxed(con, SRAM_I2C_ADDRBASE + I2C_CON);
}
void __sramfunc sram_i2c_clean_stop(void)
{
unsigned int con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CON);
con = (con & (~I2C_CON_STOP)) ;
writel_relaxed(con, SRAM_I2C_ADDRBASE + I2C_CON);
}
void __sramfunc sram_i2c_get_ipd_event(int type)
{
int time = 2000;
unsigned int con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_IPD);
writel_relaxed(type, SRAM_I2C_ADDRBASE + I2C_IEN);
do{
sram_udelay(10);
con = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_IPD);
}while(((--time) & (~(con & type))));
writel_relaxed(type,SRAM_I2C_ADDRBASE + I2C_IPD);
if(time <= 0){
sram_printch('T');
}
}
void __sramfunc sram_i2c_write_prepare(uint8 I2CSlaveAddr, uint8 regAddr,uint8 pdata)
{
u32 data = 0;
unsigned int addr = (I2CSlaveAddr & 0x7f) << 1;
data = (addr | (regAddr << 8))|(pdata << 16);
writel_relaxed(data , SRAM_I2C_ADDRBASE + I2C_TXDATA_BASE);
writel_relaxed(3, SRAM_I2C_ADDRBASE + I2C_MTXCNT);
}
uint8 __sramfunc sram_i2c_read_prepare(uint8 I2CSlaveAddr, uint8 regAddr)
{
unsigned int addr = (I2CSlaveAddr & 0x7f) << 1;
writel_relaxed(addr | I2C_MRXADDR_LOW, SRAM_I2C_ADDRBASE + I2C_MRXADDR);
writel_relaxed(regAddr | I2C_MRXADDR_LOW, SRAM_I2C_ADDRBASE + I2C_MRXRADDR);
writel_relaxed(SRAM_I2C_DATA_BYTE, SRAM_I2C_ADDRBASE + I2C_MRXCNT);
return 0;
}
uint8 __sramfunc sram_i2c_read_get_data(uint8 I2CSlaveAddr, uint8 regAddr)
{
unsigned int ret;
ret = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_RXDATA_BASE);
ret = ret & 0x000000ff;
return ret;
}
uint8 __sramfunc sram_i2c_write(uint8 I2CSlaveAddr, uint8 regAddr,uint8 data)
{
sram_i2c_write_enable();
sram_i2c_get_ipd_event(I2C_STARTIPD);
sram_i2c_clean_start();
sram_i2c_write_prepare(I2CSlaveAddr,regAddr,data);
sram_i2c_get_ipd_event(I2C_MBTFIPD);
sram_i2c_send_stop();
sram_i2c_get_ipd_event(I2C_STOPIPD);
sram_i2c_clean_stop();
sram_i2c_disenable();
return 0;
}
uint8 __sramfunc sram_i2c_read(uint8 I2CSlaveAddr, uint8 regAddr)
{
unsigned int data;
sram_i2c_read_enable();
sram_i2c_get_ipd_event(I2C_STARTIPD);
sram_i2c_clean_start();
sram_i2c_read_prepare(I2CSlaveAddr,regAddr);
sram_i2c_get_ipd_event(I2C_MBRFIPD);
data = sram_i2c_read_get_data(I2CSlaveAddr,regAddr);
sram_i2c_send_stop();
sram_i2c_get_ipd_event(I2C_STOPIPD);
sram_i2c_clean_stop();
sram_i2c_disenable();
return data;
}
void __sramfunc rk30_suspend_voltage_set(unsigned int vol)
{
uint8 slaveaddr;
uint16 slavereg;
uint8 data,ret = 0;
uint8 rtc_status_reg = 0x11;
slaveaddr = I2C_SADDR; //slave device addr
slavereg = 0x22; // reg addr
data = 0x23; //set arm 1.0v
sram_i2c_init(); //init i2c device
ret = sram_i2c_read(slaveaddr, rtc_status_reg);
sram_i2c_write(slaveaddr, rtc_status_reg, ret);
arm_voltage = sram_i2c_read(slaveaddr, slavereg);
// sram_printhex(ret);
sram_i2c_write(slaveaddr, slavereg, data);//
sram_i2c_deinit(); //deinit i2c device
}
void __sramfunc rk30_suspend_voltage_resume(unsigned int vol)
{
uint8 slaveaddr;
uint16 slavereg;
uint8 data,ret = 0;
slaveaddr = I2C_SADDR; //slave device addr
slavereg = 0x22; // reg addr
sram_i2c_init(); //init i2c device
if (arm_voltage >= 0x3b ){ // set arm <= 1.3v
data = 0x3b;
}
else if(arm_voltage <= 0x1f){
data = 0x1f; // set arm >= 0.95v
}
else
data = arm_voltage;
sram_i2c_write(slaveaddr, slavereg, data);
sram_i2c_deinit(); //deinit i2c device
}
#else
void __sramfunc rk30_suspend_voltage_set(unsigned int vol)
{
}
void __sramfunc rk30_suspend_voltage_resume(unsigned int vol)
{
}
#endif

16
arch/arm/mach-rk30/include/mach/board.h
View File

@ -91,6 +91,13 @@ void board_gpio_resume(void);
void __sramfunc board_pmu_suspend(void);
void __sramfunc board_pmu_resume(void);
#ifdef CONFIG_RK30_PWM_REGULATOR
void rk30_pwm_suspend_voltage_set(void);
void rk30_pwm_resume_voltage_set(void);
void __sramfunc rk30_pwm_logic_suspend_voltage(void);
void __sramfunc rk30_pwm_logic_resume_voltage(void);
#endif
extern struct sys_timer rk30_timer;
enum _periph_pll {
@ -107,6 +114,7 @@ enum _codec_pll {
codec_pll_552mhz = 552000000, /* for HDMI */
codec_pll_600mhz = 600000000,
codec_pll_742_5khz = 742500000,
codec_pll_768mhz = 768000000,
codec_pll_798mhz = 798000000,
codec_pll_1188mhz = 1188000000,
};
@ -118,6 +126,8 @@ enum _codec_pll {
#define CLK_FLG_MAX_I2S_22579_2KHZ (1<<2)
#define CLK_FLG_MAX_I2S_24576KHZ (1<<3)
#define CLK_FLG_MAX_I2S_49152KHZ (1<<4)
//uart 1m\3m
#define CLK_FLG_UART_1_3M (1<<5)
@ -129,8 +139,14 @@ enum _codec_pll {
#else
#define RK30_CLOCKS_DEFAULT_FLAGS (CLK_FLG_MAX_I2S_12288KHZ/*|CLK_FLG_EXT_27MHZ*/)
#if (RK30_CLOCKS_DEFAULT_FLAGS&CLK_FLG_UART_1_3M)
#define codec_pll_default codec_pll_768mhz
#else
#define codec_pll_default codec_pll_798mhz
#endif
#define periph_pll_default periph_pll_297mhz
#endif

8
arch/arm/mach-rk30/include/mach/cru.h
View File

@ -210,10 +210,10 @@ enum cru_clk_gate {
CLK_GATE_UART3,
CLK_GATE_FRAC_UART3,
CLK_GATE_PEIRPH_SRC = CLK_GATE_CLKID(2),
CLK_GATE_ACLK_PEIRPH,
CLK_GATE_HCLK_PEIRPH,
CLK_GATE_PCLK_PEIRPH,
CLK_GATE_PERIPH_SRC = CLK_GATE_CLKID(2),
CLK_GATE_ACLK_PERIPH,
CLK_GATE_HCLK_PERIPH,
CLK_GATE_PCLK_PERIPH,
CLK_GATE_SMC,
CLK_GATE_MAC,
CLK_GATE_HSADC,

4
arch/arm/mach-rk30/include/mach/ddr.h
View File

@ -22,7 +22,7 @@
#ifdef CONFIG_DDR_SDRAM_FREQ
#define DDR_FREQ (CONFIG_DDR_SDRAM_FREQ)
#else
#define DDR_FREQ 400
#define DDR_FREQ 360
#endif
#define DDR3_800D (0) // 5-5-5
@ -149,5 +149,7 @@ void __sramfunc ddr_resume(void);
uint32_t __sramfunc ddr_change_freq(uint32_t nMHz);
int ddr_init(uint32_t dram_type, uint32_t freq);
void ddr_set_auto_self_refresh(bool en);
uint32_t __sramlocalfunc ddr_set_pll(uint32_t nMHz, uint32_t set);
#endif

19
arch/arm/mach-rk30/include/mach/gpio.h
View File

@ -40,25 +40,36 @@
#else
#define TCA6424_TOTOL_GPIO_NUM 0
#define TCA6424_TOTOL_GPIO_IRQ_NUM 0
#define TCA6424_GPIO_EXPANDER_BASE GPIO_EXPANDER_BASE
#endif
#if defined(CONFIG_GPIO_WM831X)
#define WM831X_TOTOL_GPIO_NUM 12
#define WM831X_GPIO_EXPANDER_BASE (GPIO_EXPANDER_BASE+TCA6424_TOTOL_GPIO_NUM)
#define WM831X_GPIO_EXPANDER_BASE (TCA6424_GPIO_EXPANDER_BASE+TCA6424_TOTOL_GPIO_NUM)
#else
#define WM831X_TOTOL_GPIO_NUM 0
#define WM831X_GPIO_EXPANDER_BASE (GPIO_EXPANDER_BASE+TCA6424_TOTOL_GPIO_NUM)
#define WM831X_GPIO_EXPANDER_BASE (TCA6424_GPIO_EXPANDER_BASE+TCA6424_TOTOL_GPIO_NUM)
#endif
#if defined (CONFIG_GPIO_WM8994)
#define CONFIG_GPIO_WM8994_NUM 11
#define WM8994_GPIO_EXPANDER_BASE (GPIO_EXPANDER_BASE+WM831X_TOTOL_GPIO_NUM)
#define WM8994_GPIO_EXPANDER_BASE (WM831X_GPIO_EXPANDER_BASE+WM831X_TOTOL_GPIO_NUM)
#else
#define CONFIG_GPIO_WM8994_NUM 0
#define WM8994_GPIO_EXPANDER_BASE (WM831X_GPIO_EXPANDER_BASE+WM831X_TOTOL_GPIO_NUM)
#endif
#if defined (CONFIG_GPIO_TPS65910)
#define CONFIG_GPIO_TPS65910_NUM 9
#define TPS65910_GPIO_EXPANDER_BASE (WM8994_GPIO_EXPANDER_BASE+CONFIG_GPIO_WM8994_NUM)
#else
#define CONFIG_GPIO_TPS65910_NUM 0
#define TPS65910_GPIO_EXPANDER_BASE (WM8994_GPIO_EXPANDER_BASE+CONFIG_GPIO_WM8994_NUM)
#endif
//定义GPIO的PIN口最大数目。CONFIG_SPI_FPGA_GPIO_NUM表示FPGA的PIN脚数。
#define ARCH_NR_GPIOS (PIN_BASE + RK30_TOTOL_GPIO_NUM + TCA6424_TOTOL_GPIO_NUM + WM831X_TOTOL_GPIO_NUM + CONFIG_SPI_FPGA_GPIO_NUM+CONFIG_GPIO_WM8994_NUM)
#define ARCH_NR_GPIOS (PIN_BASE + RK30_TOTOL_GPIO_NUM + TCA6424_TOTOL_GPIO_NUM + WM831X_TOTOL_GPIO_NUM + CONFIG_SPI_FPGA_GPIO_NUM+CONFIG_GPIO_WM8994_NUM+CONFIG_GPIO_TPS65910_NUM)
#define INVALID_GPIO -1

14
arch/arm/mach-rk30/include/mach/io.h Normal file → Executable file
View File

@ -26,7 +26,11 @@
#define RK30_IMEM_PHYS 0x10080000
#define RK30_IMEM_BASE IOMEM(0xFEF00000)
#define RK30_IMEM_NONCACHED RK30_IO_TO_VIRT0(RK30_IMEM_PHYS)
#ifdef CONFIG_ARCH_RK31
#define RK30_IMEM_SIZE SZ_16K
#else
#define RK30_IMEM_SIZE SZ_64K
#endif
#define RK30_GPU_PHYS 0x10090000
#define RK30_GPU_SIZE SZ_64K
@ -155,11 +159,16 @@
#define RK30_I2C0_PHYS 0x2002c000
#define RK30_I2C0_SIZE SZ_8K
#define RK30_I2C1_PHYS 0x2002e000
#define RK30_I2C1_BASE RK30_IO_TO_VIRT1(RK30_I2C1_PHYS)
#define RK30_I2C1_SIZE SZ_8K
#define RK30_PWM01_PHYS 0x20030000
#define RK30_PWM01_BASE RK30_IO_TO_VIRT1(RK30_PWM01_PHYS)
#define RK30_PWM01_SIZE SZ_16K
#ifdef CONFIG_ARCH_RK31
#define RK30_GPIO0_PHYS 0x2000a000
#else
#define RK30_GPIO0_PHYS 0x20034000
#endif
#define RK30_GPIO0_BASE RK30_IO_TO_VIRT1(RK30_GPIO0_PHYS)
#define RK30_GPIO0_SIZE SZ_16K
#define RK30_TIMER0_PHYS 0x20038000
@ -214,6 +223,11 @@
#define RK30_GPIO4_BASE RK30_IO_TO_VIRT1(RK30_GPIO4_PHYS)
#define RK30_GPIO4_SIZE SZ_16K
#define RK31_GPS_PHYS 0x10230000
#define RK31_GPS_SIZE SZ_64K
#define RK31_HSIC_PHYS 0x10240000
#define RK31_HSIC_SIZE SZ_256K
#if CONFIG_RK_DEBUG_UART == 0
#define DEBUG_UART_PHYS RK30_UART0_PHYS
#define DEBUG_UART_BASE RK30_UART0_BASE

547
arch/arm/mach-rk30/include/mach/iomux.h
View File

@ -18,6 +18,8 @@
#include <linux/init.h>
#if defined(CONFIG_ARCH_RK30)
//GPIO0A
#define GPIO0A_GPIO0A7 0
#define GPIO0A_I2S_8CH_SDI 1
@ -482,11 +484,6 @@
#define GPIO6B_GPIO6B7 0
#define GPIO6B_TEST_CLOCK_OUT 1
#define DEFAULT 0
#define INITIAL 1
#define GRF_GPIO0L_DIR 0x0000
#define GRF_GPIO0H_DIR 0x0004
#define GRF_GPIO1L_DIR 0x0008
@ -805,6 +802,546 @@
//GPIO6B
#define GPIO6B7_TESTCLOCKOUT_NAME "gpio6b7_testclockout_name"
#elif defined(CONFIG_ARCH_RK31)
//GPIO0C
#define GPIO0C_GPIO0C0 0
#define GPIO0C_FLASHDATA8 1
#define GPIO0C_GPIO0C1 0
#define GPIO0C_FLASHDATA9 1
#define GPIO0C_GPIO0C2 0
#define GPIO0C_FLASHDATA10 1
#define GPIO0C_GPIO0C3 0
#define GPIO0C_FLASHDATA11 1
#define GPIO0C_GPIO0C4 0
#define GPIO0C_FLASHDATA12 1
#define GPIO0C_GPIO0C5 0
#define GPIO0C_FLASHDATA13 1
#define GPIO0C_GPIO0C6 0
#define GPIO0C_FLASHDATA14 1
#define GPIO0C_GPIO0C7 0
#define GPIO0C_FLASHDATA15 1
//GPIO0D
#define GPIO0D_GPIO0D0 0
#define GPIO0D_FLASHDQS 1
#define GPIO0D_EMMCCLKOUT 2
#define GPIO0D_GPIO0D1 0
#define GPIO0D_FLASHCSN1 1
#define GPIO0D_GPIO0D2 0
#define GPIO0D_FLASHCSN2 1
#define GPIO0D_EMMCCMD 2
#define GPIO0D_GPIO0D3 0
#define GPIO0D_FLASHCSN3 1
#define GPIO0D_EMMCRSTNOUT 2
#define GPIO0D_GPIO0D4 0
#define GPIO0D_SPI1RXD 1
#define GPIO0D_GPIO0D5 0
#define GPIO0D_SPI1TXD 1
#define GPIO0D_GPIO0D6 0
#define GPIO0D_SPI1CLK 1
#define GPIO0D_GPIO0D7 0
#define GPIO0D_SPI1CSN0 1
//GPIO1A
#define GPIO1A_GPIO1A0 0
#define GPIO1A_UART0SIN 1
#define GPIO1A_GPIO1A1 0
#define GPIO1A_UART0SOUT 1
#define GPIO1A_GPIO1A2 0
#define GPIO1A_UART0CTSN 1
#define GPIO1A_GPIO1A3 0
#define GPIO1A_UART0RTSN 1
#define GPIO1A_GPIO1A4 0
#define GPIO1A_UART1SIN 1
#define GPIO1A_SPI0RXD 2
#define GPIO1A_GPIO1A5 0
#define GPIO1A_UART1SOUT 1
#define GPIO1A_SPI0TXD 2
#define GPIO1A_GPIO1A6 0
#define GPIO1A_UART1CTSN 1
#define GPIO1A_SPI0CLK 2
#define GPIO1A_GPIO1A7 0
#define GPIO1A_UART1RTSN 1
#define GPIO1A_SPI0CSN0 2
//GPIO1B
#define GPIO1B_GPIO1B0 0
#define GPIO1B_UART2SIN 1
#define GPIO1B_JTAGTDI 2
#define GPIO1B_GPIO1B1 0
#define GPIO1B_UART2SOUT 1
#define GPIO1B_JTAGTDO 2
#define GPIO1B_GPIO1B2 0
#define GPIO1B_UART3SIN 1
#define GPIO1B_GPSMAG 2
#define GPIO1B_GPIO1B3 0
#define GPIO1B_UART3SOUT 1
#define GPIO1B_GPSSIG 2
#define GPIO1B_GPIO1B4 0
#define GPIO1B_UART3CTSN 1
#define GPIO1B_GPSRFCLK 2
#define GPIO1B_GPIO1B5 0
#define GPIO1B_UART3RTSN 1
#define GPIO1B_GPIO1B6 0
#define GPIO1B_SPDIFTX 1
#define GPIO1B_SPI1CSN1 2
#define GPIO1B_GPIO1B7 0
#define GPIO1B_SPI0CSN1 1
//GPIO1C
#define GPIO1C_GPIO1C0 0
#define GPIO1C_I2SCLK 1
#define GPIO1C_GPIO1C1 0
#define GPIO1C_I2SSCLK 1
#define GPIO1C_GPIO1C2 0
#define GPIO1C_I2SLRCLKRX 1
#define GPIO1C_GPIO1C3 0
#define GPIO1C_I2SLRCLKTX 1
#define GPIO1C_GPIO1C4 0
#define GPIO1C_I2SSDI 1
#define GPIO1C_GPIO1C5 0
#define GPIO1C_I2SSDO 1
//GPIO1D
#define GPIO1D_GPIO1D0 0
#define GPIO1D_I2C0SDA 1
#define GPIO1D_GPIO1D1 0
#define GPIO1D_I2C0SCL 1
#define GPIO1D_GPIO1D2 0
#define GPIO1D_I2C1SDA 1
#define GPIO1D_GPIO1D3 0
#define GPIO1D_I2C1SCL 1
#define GPIO1D_GPIO1D4 0
#define GPIO1D_I2C2SDA 1
#define GPIO1D_GPIO1D5 0
#define GPIO1D_I2C2SCL 1
#define GPIO1D_GPIO1D6 0
#define GPIO1D_I2C4SDA 1
#define GPIO1D_GPIO1D7 0
#define GPIO1D_I2C4SCL 1
//GPIO2A
#define GPIO2A_GPIO2A0 0
#define GPIO2A_LCDC1DATA0 1
#define GPIO2A_SMCDATA0 2
#define GPIO2A_TRACEDATA0 3
#define GPIO2A_GPIO2A1 0
#define GPIO2A_LCDC1DATA1 1
#define GPIO2A_SMCDATA1 2
#define GPIO2A_TRACEDATA1 3
#define GPIO2A_GPIO2A2 0
#define GPIO2A_LCDC1DATA2 1
#define GPIO2A_SMCDATA2 2
#define GPIO2A_TRACEDATA2 3
#define GPIO2A_GPIO2A3 0
#define GPIO2A_LCDC1DATA3 1
#define GPIO2A_SMCDATA3 2
#define GPIO2A_TRACEDATA3 3
#define GPIO2A_GPIO2A4 0
#define GPIO2A_LCDC1DATA4 1
#define GPIO2A_SMCDATA4 2
#define GPIO2A_TRACEDATA4 3
#define GPIO2A_GPIO2A5 0
#define GPIO2A_LCDC1DATA5 1
#define GPIO2A_SMCDATA5 2
#define GPIO2A_TRACEDATA5 3
#define GPIO2A_GPIO2A6 0
#define GPIO2A_LCDC1DATA6 1
#define GPIO2A_SMCDATA6 2
#define GPIO2A_TRACEDATA6 3
#define GPIO2A_GPIO2A7 0
#define GPIO2A_LCDC1DATA7 1
#define GPIO2A_SMCDATA7 2
#define GPIO2A_TRACEDATA7 3
//GPIO2B
#define GPIO2B_GPIO2B0 0
#define GPIO2B_LCDC1DATA8 1
#define GPIO2B_SMCDATA8 2
#define GPIO2B_TRACEDATA8 3
#define GPIO2B_GPIO2B1 0
#define GPIO2B_LCDC1DATA9 1
#define GPIO2B_SMCDATA9 2
#define GPIO2B_TRACEDATA9 3
#define GPIO2B_GPIO2B2 0
#define GPIO2B_LCDC1DATA10 1
#define GPIO2B_SMCDATA10 2
#define GPIO2B_TRACEDATA10 3
#define GPIO2B_GPIO2B3 0
#define GPIO2B_LCDC1DATA11 1
#define GPIO2B_SMCDATA11 2
#define GPIO2B_TRACEDATA11 3
#define GPIO2B_GPIO2B4 0
#define GPIO2B_LCDC1DATA12 1
#define GPIO2B_SMCDATA12 2
#define GPIO2B_TRACEDATA12 3
#define GPIO2B_GPIO2B5 0
#define GPIO2B_LCDC1DATA13 1
#define GPIO2B_SMCDATA13 2
#define GPIO2B_TRACEDATA13 3
#define GPIO2B_GPIO2B6 0
#define GPIO2B_LCDC1DATA14 1
#define GPIO2B_SMCDATA14 2
#define GPIO2B_TRACEDATA14 3
#define GPIO2B_GPIO2B7 0
#define GPIO2B_LCDC1DATA15 1
#define GPIO2B_SMCDATA15 2
#define GPIO2B_TRACEDATA15 3
//GPIO2C
#define GPIO2C_GPIO2C0 0
#define GPIO2C_LCDC1DATA16 1
#define GPIO2C_SMCADDR0 2
#define GPIO2C_GPIO2C1 0
#define GPIO2C_LCDC1DATA17 1
#define GPIO2C_SMCADDR1 2
#define GPIO2C_GPIO2C2 0
#define GPIO2C_LCDC1DATA18 1
#define GPIO2C_SMCADDR2 2
#define GPIO2C_GPIO2C3 0
#define GPIO2C_LCDC1DATA19 1
#define GPIO2C_SMCADDR3 2
#define GPIO2C_GPIO2C4 0
#define GPIO2C_LCDC1DATA20 1
#define GPIO2C_SMCADDR4 2
#define GPIO2C_GPIO2C5 0
#define GPIO2C_LCDC1DATA21 1
#define GPIO2C_SMCADDR5 2
#define GPIO2C_GPIO2C6 0
#define GPIO2C_LCDC1DATA22 1
#define GPIO2C_SMCADDR6 2
#define GPIO2C_GPIO2C7 0
#define GPIO2C_LCDC1DATA23 1
#define GPIO2C_SMCADDR7 2
//GPIO2D
#define GPIO2D_GPIO2D0 0
#define GPIO2D_LCDC1DCLK 1
#define GPIO2D_SMCCSN0 2
#define GPIO2D_GPIO2D1 0
#define GPIO2D_LCDC1DEN 1
#define GPIO2D_SMCWEN 2
#define GPIO2D_GPIO2D2 0
#define GPIO2D_LCDC1HSYNC 1
#define GPIO2D_SMCOEN 2
#define GPIO2D_GPIO2D3 0
#define GPIO2D_LCDC1VSYNC 1
#define GPIO2D_SMCADVN 2
#define GPIO2D_GPIO2D4 0
#define GPIO2D_SMCBLSN0 1
#define GPIO2D_GPIO2D5 0
#define GPIO2D_SMCBLSN1 1
#define GPIO2D_GPIO2D6 0
#define GPIO2D_SMCCSN1 1
#define GPIO2D_GPIO2D7 0
#define GPIO2D_TESTCLOCKOUT 1
//GPIO3A
#define GPIO3A_GPIO3A0 0
#define GPIO3A_SDMMC0RSTNOUT 1
#define GPIO3A_GPIO3A1 0
#define GPIO3A_SDMMC0PWREN 1
#define GPIO3A_GPIO3A2 0
#define GPIO3A_SDMMC0CLKOUT 1
#define GPIO3A_GPIO3A3 0
#define GPIO3A_SDMMC0CMD 1
#define GPIO3A_GPIO3A4 0
#define GPIO3A_SDMMC0DATA0 1
#define GPIO3A_GPIO3A5 0
#define GPIO3A_SDMMC0DATA1 1
#define GPIO3A_GPIO3A6 0
#define GPIO3A_SDMMC0DATA2 1
#define GPIO3A_GPIO3A7 0
#define GPIO3A_SDMMC0DATA3 1
//GPIO3B
#define GPIO3B_GPIO3B0 0
#define GPIO3B_SDMMC0DETECTN 1
#define GPIO3B_GPIO3B1 0
#define GPIO3B_SDMMC0WRITEPRT 1
#define GPIO3B_GPIO3B3 0
#define GPIO3B_CIFCLKOUT 1
#define GPIO3B_GPIO3B4 0
#define GPIO3B_CIFDATA0 1
#define GPIO3B_HSADCDATA8 2
#define GPIO3B_GPIO3B5 0
#define GPIO3B_CIFDATA1 1
#define GPIO3B_HSADCDATA9 2
#define GPIO3B_GPIO3B6 0
#define GPIO3B_CIFDATA10 1
#define GPIO3B_I2C3SDA 2
#define GPIO3B_GPIO3B7 0
#define GPIO3B_CIFDATA11 1
#define GPIO3B_I2C3SCL 2
//GPIO3C
#define GPIO3C_GPIO3C0 0
#define GPIO3C_SDMMC1CMD 1
#define GPIO3C_RMIITXEN 2
#define GPIO3C_GPIO3C1 0
#define GPIO3C_SDMMC1DATA0 1
#define GPIO3C_RMIITXD1 2
#define GPIO3C_GPIO3C2 0
#define GPIO3C_SDMMC1DATA1 1
#define GPIO3C_RMIITXD0 2
#define GPIO3C_GPIO3C3 0
#define GPIO3C_SDMMC1DATA2 1
#define GPIO3C_RMIIRXD0 2
#define GPIO3C_GPIO3C4 0
#define GPIO3C_SDMMC1DATA3 1
#define GPIO3C_RMIIRXD1 2
#define GPIO3C_GPIO3C5 0
#define GPIO3C_SDMMC1CLKOUT 1
#define GPIO3C_RMIICLKOUT 2
#define GPIO3C_RMIICLKIN 3
#define GPIO3C_GPIO3C6 0
#define GPIO3C_SDMMC1DETECTN 1
#define GPIO3C_RMIIRXERR 2
#define GPIO3C_GPIO3C7 0
#define GPIO3C_SDMMC1WRITEPRT 1
#define GPIO3C_RMIICRS 2
//GPIO3D
#define GPIO3D_GPIO3D0 0
#define GPIO3D_SDMMC1PWREN 1
#define GPIO3D_MIIMD 2
#define GPIO3D_GPIO3D1 0
#define GPIO3D_SDMMC1BACKENPWR 1
#define GPIO3D_MIIMDCLK 2
#define GPIO3D_GPIO3D2 0
#define GPIO3D_SDMMC1INTN 1
#define GPIO3D_GPIO3D3 0
#define GPIO3D_PWM0 1
#define GPIO3D_GPIO3D4 0
#define GPIO3D_PWM1 1
#define GPIO3D_JTAGTRSTN 2
#define GPIO3D_GPIO3D5 0
#define GPIO3D_PWM2 1
#define GPIO3D_JTAGTCK 2
#define GPIO3D_OTGDRVVBUS 3
#define GPIO3D_GPIO3D6 0
#define GPIO3D_PWM3 1
#define GPIO3D_JTAGTMS 2
#define GPIO3D_HOSTDRVVBUS 3
#define GRF_GPIO0L_DIR 0x0000
#define GRF_GPIO0H_DIR 0x0004
#define GRF_GPIO1L_DIR 0x0008
#define GRF_GPIO1H_DIR 0x000c
#define GRF_GPIO2L_DIR 0x0010
#define GRF_GPIO2H_DIR 0x0014
#define GRF_GPIO3L_DIR 0x0018
#define GRF_GPIO3H_DIR 0x001c
#define GRF_GPIO0L_DO 0x0020
#define GRF_GPIO0H_DO 0x0024
#define GRF_GPIO1L_DO 0x0028
#define GRF_GPIO1H_DO 0x002c
#define GRF_GPIO2L_DO 0x0030
#define GRF_GPIO2H_DO 0x0034
#define GRF_GPIO3L_DO 0x0038
#define GRF_GPIO3H_DO 0x003c
#define GRF_GPIO0L_EN 0x0040
#define GRF_GPIO0H_EN 0x0044
#define GRF_GPIO1L_EN 0x0048
#define GRF_GPIO1H_EN 0x004c
#define GRF_GPIO2L_EN 0x0050
#define GRF_GPIO2H_EN 0x0054
#define GRF_GPIO3L_EN 0x0058
#define GRF_GPIO3H_EN 0x005c
#define GRF_GPIO0A_IOMUX RK30_GRF_BASE+0x0060
#define GRF_GPIO0B_IOMUX RK30_GRF_BASE+0x0064
#define GRF_GPIO0C_IOMUX RK30_GRF_BASE+0x0068
#define GRF_GPIO0D_IOMUX RK30_GRF_BASE+0x006c
#define GRF_GPIO1A_IOMUX RK30_GRF_BASE+0x0070
#define GRF_GPIO1B_IOMUX RK30_GRF_BASE+0x0074
#define GRF_GPIO1C_IOMUX RK30_GRF_BASE+0x0078
#define GRF_GPIO1D_IOMUX RK30_GRF_BASE+0x007c
#define GRF_GPIO2A_IOMUX RK30_GRF_BASE+0x0080
#define GRF_GPIO2B_IOMUX RK30_GRF_BASE+0x0084
#define GRF_GPIO2C_IOMUX RK30_GRF_BASE+0x0088
#define GRF_GPIO2D_IOMUX RK30_GRF_BASE+0x008c
#define GRF_GPIO3A_IOMUX RK30_GRF_BASE+0x0090
#define GRF_GPIO3B_IOMUX RK30_GRF_BASE+0x0094
#define GRF_GPIO3C_IOMUX RK30_GRF_BASE+0x0098
#define GRF_GPIO3D_IOMUX RK30_GRF_BASE+0x009c
#define GRF_SOC_CON0 0x00a0
#define GRF_SOC_CON1 0x00a4
#define GRF_SOC_CON2 0x00a8
#define GRF_SOC_STATUS0 0x00ac
#define GRF_DMAC1_CON0 0x00b0
#define GRF_DMAC1_CON1 0x00b4
#define GRF_DMAC1_CON2 0x00b8
#define GRF_DMAC2_CON0 0x00bc
#define GRF_DMAC2_CON1 0x00c0
#define GRF_DMAC2_CON2 0x00c4
#define GRF_DMAC2_CON3 0x00c8
#define GRF_UOC0_CON0 0x010c
#define GRF_UOC0_CON1 0x0110
#define GRF_UOC0_CON2 0x0114
#define GRF_UOC0_CON3 0x0118
#define GRF_UOC1_CON0 0x011c
#define GRF_UOC1_CON1 0x0120
#define GRF_UOC1_CON2 0x0124
#define GRF_UOC1_CON3 0x0128
#define GRF_UOC2_CON0 0x012c
#define GRF_UOC2_CON1 0x0130
#define GRF_UOC3_CON0 0x0138
#define GRF_UOC3_CON1 0x013c
#define GRF_HSIC_STAT 0x0140
#define GRF_DDRC_CON0 0x00ec
#define GRF_DDRC_STAT 0x00f0
#define GRF_OS_REG0 0x0144
#define GRF_OS_REG1 0x0148
#define GRF_OS_REG2 0x014c
#define GRF_OS_REG3 0x0150
#define GRF_OS_REG4 0x0154
#define GRF_OS_REG5 0x0158
#define GRF_OS_REG6 0x015c
#define GRF_OS_REG7 0x0160
//GPIO0C
#define GPIO0C0_FLASHDATA8_NAME "gpio0c0_flashdata8_name"
#define GPIO0C1_FLASHDATA9_NAME "gpio0c1_flashdata9_name"
#define GPIO0C2_FLASHDATA10_NAME "gpio0c2_flashdata10_name"
#define GPIO0C3_FLASHDATA11_NAME "gpio0c3_flashdata11_name"
#define GPIO0C4_FLASHDATA12_NAME "gpio0c4_flashdata12_name"
#define GPIO0C5_FLASHDATA13_NAME "gpio0c5_flashdata13_name"
#define GPIO0C6_FLASHDATA14_NAME "gpio0c6_flashdata14_name"
#define GPIO0C7_FLASHDATA15_NAME "gpio0c7_flashdata15_name"
//GPIO0D
#define GPIO0D0_FLASHDQS_EMMCCLKOUT_NAME "gpio0d0_flashdqs_emmcclkout_name"
#define GPIO0D1_FLASHCSN1_NAME "gpio0d1_flashcsn1_name"
#define GPIO0D2_FLASHCSN2_EMMCCMD_NAME "gpio0d2_flashcsn2_emmccmd_name"
#define GPIO0D3_FLASHCSN3_EMMCRSTNOUT_NAME "gpio0d3_flashcsn3_emmcrstnout_name"
#define GPIO0D4_SPI1RXD_NAME "gpio0d4_spi1rxd_name"
#define GPIO0D5_SPI1TXD_NAME "gpio0d5_spi1txd_name"
#define GPIO0D6_SPI1CLK_NAME "gpio0d6_spi1clk_name"
#define GPIO0D7_SPI1CSN0_NAME "gpio0d7_spi1csn0_name"
//GPIO1A
#define GPIO1A0_UART0SIN_NAME "gpio1a0_uart0sin_name"
#define GPIO1A1_UART0SOUT_NAME "gpio1a1_uart0sout_name"
#define GPIO1A2_UART0CTSN_NAME "gpio1a2_uart0ctsn_name"
#define GPIO1A3_UART0RTSN_NAME "gpio1a3_uart0rtsn_name"
#define GPIO1A4_UART1SIN_SPI0RXD_NAME "gpio1a4_uart1sin_spi0rxd_name"
#define GPIO1A5_UART1SOUT_SPI0TXD_NAME "gpio1a5_uart1sout_spi0txd_name"
#define GPIO1A6_UART1CTSN_SPI0CLK_NAME "gpio1a6_uart1ctsn_spi0clk_name"
#define GPIO1A7_UART1RTSN_SPI0CSN0_NAME "gpio1a7_uart1rtsn_spi0csn0_name"
//GPIO1B
#define GPIO1B0_UART2SIN_JTAGTDI_NAME "gpio1b0_uart2sin_jtagtdi_name"
#define GPIO1B1_UART2SOUT_JTAGTDO_NAME "gpio1b1_uart2sout_jtagtdo_name"
#define GPIO1B2_UART3SIN_GPSMAG_NAME "gpio1b2_uart3sin_gpsmag_name"
#define GPIO1B3_UART3SOUT_GPSSIG_NAME "gpio1b3_uart3sout_gpssig_name"
#define GPIO1B4_UART3CTSN_GPSRFCLK_NAME "gpio1b4_uart3ctsn_gpsrfclk_name"
#define GPIO1B5_UART3RTSN_NAME "gpio1b5_uart3rtsn_name"
#define GPIO1B6_SPDIFTX_SPI1CSN1_NAME "gpio1b6_spdiftx_spi1csn1_name"
#define GPIO1B7_SPI0CSN1_NAME "gpio1b7_spi0csn1_name"
//GPIO1C
#define GPIO1C0_I2SCLK_NAME "gpio1c0_i2sclk_name"
#define GPIO1C1_I2SSCLK_NAME "gpio1c1_i2ssclk_name"
#define GPIO1C2_I2SLRCLKRX_NAME "gpio1c2_i2slrclkrx_name"
#define GPIO1C3_I2SLRCLKTX_NAME "gpio1c3_i2slrclktx_name"
#define GPIO1C4_I2SSDI_NAME "gpio1c4_i2ssdi_name"
#define GPIO1C5_I2SSDO_NAME "gpio1c5_i2ssdo_name"
//GPIO1D
#define GPIO1D0_I2C0SDA_NAME "gpio1d0_i2c0sda_name"
#define GPIO1D1_I2C0SCL_NAME "gpio1d1_i2c0scl_name"
#define GPIO1D2_I2C1SDA_NAME "gpio1d2_i2c1sda_name"
#define GPIO1D3_I2C1SCL_NAME "gpio1d3_i2c1scl_name"
#define GPIO1D4_I2C2SDA_NAME "gpio1d4_i2c2sda_name"
#define GPIO1D5_I2C2SCL_NAME "gpio1d5_i2c2scl_name"
#define GPIO1D6_I2C4SDA_NAME "gpio1d6_i2c4sda_name"
#define GPIO1D7_I2C4SCL_NAME "gpio1d7_i2c4scl_name"
//GPIO2A
#define GPIO2A0_LCDC1DATA0_SMCDATA0_TRACEDATA0_NAME "gpio2a0_lcdc1data0_smcdata0_tracedata0_name"
#define GPIO2A1_LCDC1DATA1_SMCDATA1_TRACEDATA1_NAME "gpio2a1_lcdc1data1_smcdata1_tracedata1_name"
#define GPIO2A2_LCDC1DATA2_SMCDATA2_TRACEDATA2_NAME "gpio2a2_lcdc1data2_smcdata2_tracedata2_name"
#define GPIO2A3_LCDC1DATA3_SMCDATA3_TRACEDATA3_NAME "gpio2a3_lcdc1data3_smcdata3_tracedata3_name"
#define GPIO2A4_LCDC1DATA4_SMCDATA4_TRACEDATA4_NAME "gpio2a4_lcdc1data4_smcdata4_tracedata4_name"
#define GPIO2A5_LCDC1DATA5_SMCDATA5_TRACEDATA5_NAME "gpio2a5_lcdc1data5_smcdata5_tracedata5_name"
#define GPIO2A6_LCDC1DATA6_SMCDATA6_TRACEDATA6_NAME "gpio2a6_lcdc1data6_smcdata6_tracedata6_name"
#define GPIO2A7_LCDC1DATA7_SMCDATA7_TRACEDATA7_NAME "gpio2a7_lcdc1data7_smcdata7_tracedata7_name"
//GPIO2B
#define GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME "gpio2b0_lcdc1data8_smcdata8_tracedata8_name"
#define GPIO2B1_LCDC1DATA9_SMCDATA9_TRACEDATA9_NAME "gpio2b1_lcdc1data9_smcdata9_tracedata9_name"
#define GPIO2B2_LCDC1DATA10_SMCDATA10_TRACEDATA10_NAME "gpio2b2_lcdc1data10_smcdata10_tracedata10_name"
#define GPIO2B3_LCDC1DATA11_SMCDATA11_TRACEDATA11_NAME "gpio2b3_lcdc1data11_smcdata11_tracedata11_name"
#define GPIO2B4_LCDC1DATA12_SMCDATA12_TRACEDATA12_NAME "gpio2b4_lcdc1data12_smcdata12_tracedata12_name"
#define GPIO2B5_LCDC1DATA13_SMCDATA13_TRACEDATA13_NAME "gpio2b5_lcdc1data13_smcdata13_tracedata13_name"
#define GPIO2B6_LCDC1DATA14_SMCDATA14_TRACEDATA14_NAME "gpio2b6_lcdc1data14_smcdata14_tracedata14_name"
#define GPIO2B7_LCDC1DATA15_SMCDATA15_TRACEDATA15_NAME "gpio2b7_lcdc1data15_smcdata15_tracedata15_name"
//GPIO2C
#define GPIO2C0_LCDC1DATA16_SMCADDR0_TRACECLK_NAME "gpio2c0_lcdc1data16_smcaddr0_traceclk_name"
#define GPIO2C1_LCDC1DATA17_SMCADDR1_TRACECTL_NAME "gpio2c1_lcdc1data17_smcaddr1_tracectl_name"
#define GPIO2C2_LCDC1DATA18_SMCADDR2_NAME "gpio2c2_lcdc1data18_smcaddr2_name"
#define GPIO2C3_LCDC1DATA19_SMCADDR3_NAME "gpio2c3_lcdc1data19_smcaddr3_name"
#define GPIO2C4_LCDC1DATA20_SMCADDR4_NAME "gpio2c4_lcdc1data20_smcaddr4_name"
#define GPIO2C5_LCDC1DATA21_SMCADDR5_NAME "gpio2c5_lcdc1data21_smcaddr5_name"
#define GPIO2C6_LCDC1DATA22_SMCADDR6_NAME "gpio2c6_lcdc1data22_smcaddr6_name"
#define GPIO2C7_LCDC1DATA23_SMCADDR7_NAME "gpio2c7_lcdc1data23_smcaddr7_name"
//GPIO2D
#define GPIO2D0_LCDC1DCLK_SMCCSN0_NAME "gpio2d0_lcdc1dclk_smccsn0_name"
#define GPIO2D1_LCDC1DEN_SMCWEN_NAME "gpio2d1_lcdc1den_smcwen_name"
#define GPIO2D2_LCDC1HSYNC_SMCOEN_NAME "gpio2d2_lcdc1hsync_smcoen_name"
#define GPIO2D3_LCDC1VSYNC_SMCADVN_NAME "gpio2d3_lcdc1vsync_smcadvn_name"
#define GPIO2D4_SMCBLSN0_NAME "gpio2d4_smcblsn0_name"
#define GPIO2D5_SMCBLSN1_NAME "gpio2d5_smcblsn1_name"
#define GPIO2D6_SMCCSN1_NAME "gpio2d6_smccsn1_name"
#define GPIO2D7_TESTCLOCKOUT_NAME "gpio2d7_testclockout_name"
//GPIO3A
#define GPIO3A0_SDMMC0RSTNOUT_NAME "gpio3a0_sdmmc0rstnout_name"
#define GPIO3A1_SDMMC0PWREN_NAME "gpio3a1_sdmmc0pwren_name"
#define GPIO3A2_SDMMC0CLKOUT_NAME "gpio3a2_sdmmc0clkout_name"
#define GPIO3A3_SDMMC0CMD_NAME "gpio3a3_sdmmc0cmd_name"
#define GPIO3A4_SDMMC0DATA0_NAME "gpio3a4_sdmmc0data0_name"
#define GPIO3A5_SDMMC0DATA1_NAME "gpio3a5_sdmmc0data1_name"
#define GPIO3A6_SDMMC0DATA2_NAME "gpio3a6_sdmmc0data2_name"
#define GPIO3A7_SDMMC0DATA3_NAME "gpio3a7_sdmmc0data3_name"
//GPIO3B
#define GPIO3B0_SDMMC0DETECTN_NAME "gpio3b0_sdmmc0detectn_name"
#define GPIO3B1_SDMMC0WRITEPRT_NAME "gpio3b1_sdmmc0writeprt_name"
#define GPIO3B3_CIFCLKOUT_NAME "gpio3b3_cifclkout_name"
#define GPIO3B4_CIFDATA0_HSADCDATA8_NAME "gpio3b4_cifdata0_hsadcdata8_name"
#define GPIO3B5_CIFDATA1_HSADCDATA9_NAME "gpio3b5_cifdata1_hsadcdata9_name"
#define GPIO3B6_CIFDATA10_I2C3SDA_NAME "gpio3b6_cifdata10_i2c3sda_name"
#define GPIO3B7_CIFDATA11_I2C3SCL_NAME "gpio3b7_cifdata11_i2c3scl_name"
//GPIO3C
#define GPIO3C0_SDMMC1CMD_RMIITXEN_NAME "gpio3c0_sdmmc1cmd_rmiitxen_name"
#define GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME "gpio3c1_sdmmc1data0_rmiitxd1_name"
#define GPIO3C2_SDMMC1DATA1_RMIITXD0_NAME "gpio3c2_sdmmc1data1_rmiitxd0_name"
#define GPIO3C3_SDMMC1DATA2_RMIIRXD0_NAME "gpio3c3_sdmmc1data2_rmiirxd0_name"
#define GPIO3C4_SDMMC1DATA3_RMIIRXD1_NAME "gpio3c4_sdmmc1data3_rmiirxd1_name"
#define GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME "gpio3c5_sdmmc1clkout_rmiiclkout_rmiiclkin_name"
#define GPIO3C6_SDMMC1DETECTN_RMIIRXERR_NAME "gpio3c6_sdmmc1detectn_rmiirxerr_name"
#define GPIO3C7_SDMMC1WRITEPRT_RMIICRS_NAME "gpio3c7_sdmmc1writeprt_rmiicrs_name"
//GPIO3D
#define GPIO3D0_SDMMC1PWREN_MIIMD_NAME "gpio3d0_sdmmc1pwren_miimd_name"
#define GPIO3D1_SDMMC1BACKENDPWR_MIIMDCLK_NAME "gpio3d1_sdmmc1backendpwr_miimdclk_name"
#define GPIO3D2_SDMMC1INTN_NAME "gpio3d2_sdmmc1intn_name"
#define GPIO3D3_PWM0_NAME "gpio3d3_pwm0_name"
#define GPIO3D4_PWM1_JTAGTRSTN_NAME "gpio3d4_pwm1_jtagtrstn_name"
#define GPIO3D5_PWM2_JTAGTCK_OTGDRVVBUS_NAME "gpio3d5_pwm2_jtagtck_otgdrvvbus_name"
#define GPIO3D6_PWM3_JTAGTMS_HOSTDRVVBUS_NAME "gpio3d6_pwm3_jtagtms_hostdrvvbus_name"
#endif
#define DEFAULT 0
#define INITIAL 1
#define MUX_CFG(desc,reg,off,interl,mux_mode,bflags) \
{ \
.name = desc, \

5
arch/arm/mach-rk30/include/mach/irqs.h
View File

@ -12,6 +12,8 @@
#define IRQ_DMAC2_0 RK30XX_IRQ(2)
#define IRQ_DMAC2_1 RK30XX_IRQ(3)
#define IRQ_DDR_PCTL RK30XX_IRQ(4)
#define IRQ_HSIC 37
#define IRQ_GPU 39
#define IRQ_GPU_GP RK30XX_IRQ(5)
#define IRQ_GPU_MMU RK30XX_IRQ(6)
#define IRQ_GPU_PP RK30XX_IRQ(7)
@ -25,7 +27,7 @@
#define IRQ_IPP RK30XX_IRQ(15)
#define IRQ_USB_OTG RK30XX_IRQ(16)
#define IRQ_USB_HOST RK30XX_IRQ(17)
#define IRQ_GPS 50
#define IRQ_MAC RK30XX_IRQ(19)
#define IRQ_I2S2_2CH RK30XX_IRQ(20)
#define IRQ_TSADC RK30XX_IRQ(21)
@ -79,6 +81,7 @@
#define IRQ_PMU_STOP_EXIT_INT RK30XX_IRQ(69)
#define IRQ_OBSERVER_MAINFAULT RK30XX_IRQ(70)
#define IRQ_VPU_OBSRV_MAINFAULT RK30XX_IRQ(71)
#define IRQ_ARM_PMU 103
#define IRQ_PERI_OBSRV_MAINFAULT RK30XX_IRQ(72)
#define IRQ_VIO1_OBSRV_MAINFAULT RK30XX_IRQ(73)
#define IRQ_VIO0_OBSRV_MAINFAULT RK30XX_IRQ(74)

36
arch/arm/mach-rk30/include/mach/loader.h
View File

@ -1,35 +1 @@
/* arch/arm/mach-rk29/include/mach/loader.h
*
* Copyright (C) 2011 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_RK30_LOADER_H
#define __ASM_ARCH_RK30_LOADER_H
#define SYS_LOADER_REBOOT_FLAG 0x5242C300 //high 24 bits is tag, low 8 bits is type
#define SYS_KERNRL_REBOOT_FLAG 0xC3524200 //high 24 bits is tag, low 8 bits is type
enum {
BOOT_NORMAL = 0, /* normal boot */
BOOT_LOADER, /* enter loader rockusb mode */
BOOT_MASKROM, /* enter maskrom rockusb mode (not support now) */
BOOT_RECOVER, /* enter recover */
BOOT_NORECOVER, /* do not enter recover */
BOOT_SECONDOS, /* boot second OS (not support now)*/
BOOT_WIPEDATA, /* enter recover and wipe data. */
BOOT_WIPEALL, /* enter recover and wipe all data. */
BOOT_CHECKIMG, /* check firmware img with backup part(in loader mode)*/
BOOT_FASTBOOT, /* enter fast boot mode (not support now) */
BOOT_MAX /* MAX VALID BOOT TYPE.*/
};
#endif
#include <plat/loader.h>

213
arch/arm/mach-rk30/include/mach/mtk_wcn_cmb_stub.h Executable file
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@ -0,0 +1,213 @@
/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
* Without the prior written permission of MediaTek inc. and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
*
* MediaTek Inc. (C) 2010. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
* The following software/firmware and/or related documentation ("MediaTek Software")
* have been modified by MediaTek Inc. All revisions are subject to any receiver's
* applicable license agreements with MediaTek Inc.
*/
/*! \file
\brief Declaration of library functions
Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
/*******************************************************************************
* Copyright (c) 2009 MediaTek Inc.
*
* All rights reserved. Copying, compilation, modification, distribution
* or any other use whatsoever of this material is strictly prohibited
* except in accordance with a Software License Agreement with
* MediaTek Inc.
********************************************************************************
*/
/*******************************************************************************
* LEGAL DISCLAIMER
*
* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND
* AGREES THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK
* SOFTWARE") RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE
* PROVIDED TO BUYER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY
* DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT
* LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE OR NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE
* ANY WARRANTY WHATSOEVER WITH RESPECT TO THE SOFTWARE OF ANY THIRD PARTY
* WHICH MAY BE USED BY, INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK
* SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY
* WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE
* FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S SPECIFICATION OR TO
* CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
*
* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL
* BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT
* ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
* BUYER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT
* OF LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING
* THEREOF AND RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN
* FRANCISCO, CA, UNDER THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE
* (ICC).
********************************************************************************
*/
#ifndef _MTK_WCN_CMB_STUB_H_
#define _MTK_WCN_CMB_STUB_H_
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
typedef enum {
CMB_STUB_AIF_0 = 0, /* 0000: BT_PCM_OFF & FM analog (line in/out) */
CMB_STUB_AIF_1 = 1, /* 0001: BT_PCM_ON & FM analog (in/out) */
CMB_STUB_AIF_2 = 2, /* 0010: BT_PCM_OFF & FM digital (I2S) */
CMB_STUB_AIF_3 = 3, /* 0011: BT_PCM_ON & FM digital (I2S) (invalid in 73evb & 1.2 phone configuration) */
CMB_STUB_AIF_MAX = 4,
} CMB_STUB_AIF_X;
/*COMBO_CHIP_AUDIO_PIN_CTRL*/
typedef enum {
CMB_STUB_AIF_CTRL_DIS = 0,
CMB_STUB_AIF_CTRL_EN = 1,
CMB_STUB_AIF_CTRL_MAX = 2,
} CMB_STUB_AIF_CTRL;
#if 1 /* copied from mt_combo.h */
typedef enum {
COMBO_AUDIO_STATE_0 = 0, /* 0000: BT_PCM_OFF & FM analog (line in/out) */
COMBO_AUDIO_STATE_1 = 1, /* 0001: BT_PCM_ON & FM analog (in/out) */
COMBO_AUDIO_STATE_2 = 2, /* 0010: BT_PCM_OFF & FM digital (I2S) */
COMBO_AUDIO_STATE_3 = 3, /* 0011: BT_PCM_ON & FM digital (I2S) (invalid in 73evb & 1.2 phone configuration) */
COMBO_AUDIO_STATE_MAX = 4,
} COMBO_AUDIO_STATE;
typedef enum {
COMBO_FUNC_TYPE_BT = 0,
COMBO_FUNC_TYPE_FM = 1,
COMBO_FUNC_TYPE_GPS = 2,
COMBO_FUNC_TYPE_WIFI = 3,
COMBO_FUNC_TYPE_WMT = 4,
COMBO_FUNC_TYPE_STP = 5,
COMBO_FUNC_TYPE_NUM = 6
} COMBO_FUNC_TYPE;
typedef enum {
COMBO_IF_UART = 0,
COMBO_IF_MSDC = 1,
COMBO_IF_MAX,
} COMBO_IF;
#endif
typedef void (*wmt_bgf_eirq_cb)(void);
typedef int (*wmt_aif_ctrl_cb)(CMB_STUB_AIF_X, CMB_STUB_AIF_CTRL);
typedef void (*wmt_func_ctrl_cb)(unsigned int, unsigned int);
typedef struct _CMB_STUB_CB_ {
unsigned int size; //structure size
/*wmt_bgf_eirq_cb bgf_eirq_cb;*//* remove bgf_eirq_cb from stub. handle it in platform */
wmt_aif_ctrl_cb aif_ctrl_cb;
wmt_func_ctrl_cb func_ctrl_cb;
} CMB_STUB_CB, *P_CMB_STUB_CB;
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
extern int mtk_wcn_cmb_stub_reg (P_CMB_STUB_CB p_stub_cb);
extern int mtk_wcn_cmb_stub_unreg (void);
extern int mtk_wcn_cmb_stub_aif_ctrl (CMB_STUB_AIF_X state, CMB_STUB_AIF_CTRL ctrl);
#if 0 /* remove obsolete audio_ctrl APIs. Use stub_aif_ctrl()! */
/* [GeorgeKuo] Stub functions for other kernel built-in modules to call.
* Keep them unchanged temporarily. Move mt_combo functions to mtk_wcn_combo.
*/
extern int mtk_wcn_cmb_stub_audio_ctrl_ex(COMBO_AUDIO_STATE state, u32 clt_ctrl);
static inline int mtk_wcn_cmb_stub_audio_ctrl(COMBO_AUDIO_STATE state) {
return mtk_wcn_cmb_stub_audio_ctrl_ex(state, 1);
}
#endif
/* Use new mtk_wcn_stub APIs instead of old mt_combo ones for kernel to control
* function on/off.
*/
extern void mtk_wcn_cmb_stub_func_ctrl (unsigned int type, unsigned int on);
extern int mt_combo_plt_enter_deep_idle(COMBO_IF src);
extern int mt_combo_plt_exit_deep_idle(COMBO_IF src);
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
#endif /* _MTK_WCN_CMB_STUB_H_ */

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