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watchdog: mediatek: Add support for mt8167 toprgu/watchdog

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Add support for the Top Reset Generation Unit/Watchdog Timer found on
mt8167.

Since according to its data sheet mt8167 toprgu reset bits are not
contiguous, add support for a reset table to the driver. This lets us
define reset identifiers as contiguous indexes in the binding headers.

Also address a preexisting Sashiko finding that noticed that the
has_swsysrst_en configuration was set after the reset controller
registration.

Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
Link: https://patch.msgid.link/20260908174259.9009-5-l.scorcia@gmail.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
This commit is contained in:
Luca Leonardo Scorcia 2026-09-08 19:38:31 +02:00 committed by Guenter Roeck
parent 2c3e4e818c
commit b2937ea44b
1 changed files with 43 additions and 4 deletions
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47
drivers/watchdog/mtk_wdt.c
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@ -12,6 +12,7 @@
#include <dt-bindings/reset/mt2712-resets.h>
#include <dt-bindings/reset/mediatek,mt6735-wdt.h>
#include <dt-bindings/reset/mediatek,mt6795-resets.h>
#include <dt-bindings/reset/mediatek,mt8167-wdt.h>
#include <dt-bindings/reset/mt7986-resets.h>
#include <dt-bindings/reset/mt8183-resets.h>
#include <dt-bindings/reset/mt8186-resets.h>
@ -80,11 +81,14 @@ struct mtk_wdt_dev {
bool disable_wdt_extrst;
bool reset_by_toprgu;
bool has_swsysrst_en;
const u8 *toprgu_sw_rst_tb;
int toprgu_sw_rst_num;
};
struct mtk_wdt_data {
int toprgu_sw_rst_num;
bool has_swsysrst_en;
const u8 *toprgu_sw_rst_tb;
const int toprgu_sw_rst_num;
const bool has_swsysrst_en;
};
static const struct mtk_wdt_data mt2712_data = {
@ -132,6 +136,29 @@ static const struct mtk_wdt_data mt8195_data = {
.toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM,
};
static const u8 mt8167_toprgu_sw_rst_tb[] = {
[MT8167_TOPRGU_DDRPHY_FLASH_RST] = 0,
[MT8167_TOPRGU_AUD_PAD_RST] = 1,
[MT8167_TOPRGU_MM_RST] = 2,
[MT8167_TOPRGU_MFG_RST] = 3,
[MT8167_TOPRGU_MDSYS_RST] = 4,
[MT8167_TOPRGU_CONN_RST] = 5,
[MT8167_TOPRGU_PAD2CAM_DIG_MIPI_RX_RST] = 6,
[MT8167_TOPRGU_DIG_MIPI_TX_RST] = 7,
[MT8167_TOPRGU_SPI_PAD_MACRO_RST] = 8,
/* The data sheet describes bit 9 as "reserved, unused" */
[MT8167_TOPRGU_APMIXED_RST] = 10,
[MT8167_TOPRGU_VDEC_RST] = 11,
[MT8167_TOPRGU_CONN_MCU_RST] = 12,
[MT8167_TOPRGU_EFUSE_RST] = 13,
[MT8167_TOPRGU_PWRAP_SPICTL_RST] = 14
};
static const struct mtk_wdt_data mt8167_data = {
.toprgu_sw_rst_tb = mt8167_toprgu_sw_rst_tb,
.toprgu_sw_rst_num = ARRAY_SIZE(mt8167_toprgu_sw_rst_tb),
};
/**
* toprgu_reset_sw_en_unlocked() - enable/disable software control for reset bit
* @data: Pointer to instance of driver data.
@ -162,6 +189,15 @@ static int toprgu_reset_update(struct reset_controller_dev *rcdev,
struct mtk_wdt_dev *data =
container_of(rcdev, struct mtk_wdt_dev, rcdev);
if (data->toprgu_sw_rst_tb) {
if (id >= data->toprgu_sw_rst_num) {
dev_err(rcdev->dev, "Invalid reset ID: %lu (>=%u)\n",
id, data->toprgu_sw_rst_num);
return -EINVAL;
}
id = data->toprgu_sw_rst_tb[id];
}
spin_lock_irqsave(&data->lock, flags);
if (assert && data->has_swsysrst_en)
@ -507,12 +543,14 @@ static int mtk_wdt_probe(struct platform_device *pdev)
wdt_data = of_device_get_match_data(dev);
if (wdt_data) {
mtk_wdt->toprgu_sw_rst_num = wdt_data->toprgu_sw_rst_num;
mtk_wdt->toprgu_sw_rst_tb = wdt_data->toprgu_sw_rst_tb;
mtk_wdt->has_swsysrst_en = wdt_data->has_swsysrst_en;
err = toprgu_register_reset_controller(pdev,
wdt_data->toprgu_sw_rst_num);
if (err)
return err;
mtk_wdt->has_swsysrst_en = wdt_data->has_swsysrst_en;
}
mtk_wdt->disable_wdt_extrst =
@ -553,6 +591,7 @@ static const struct of_device_id mtk_wdt_dt_ids[] = {
{ .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data },
{ .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
{ .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data },
{ .compatible = "mediatek,mt8167-wdt", .data = &mt8167_data },
{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
{ .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data },
{ .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data },