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KVM: x86: Introduce EM_ASM_2
Replace the FASTOP2 instructions. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Sean Christopherson <seanjc@google.com> Link: https://lkml.kernel.org/r/20250714103439.903697475@infradead.org
This commit is contained in:
Peter Zijlstra
parent
6204aea36b
commit
b26deb0cad
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@ -317,6 +317,15 @@ static int em_##op(struct x86_emulate_ctxt *ctxt) \
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ON64(case 8: __EM_ASM_1(op##q, rax); break;) \
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EM_ASM_END
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/* 2-operand, using "a" (dst), "d" (src) */
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#define EM_ASM_2(op) \
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EM_ASM_START(op) \
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case 1: __EM_ASM_2(op##b, al, dl); break; \
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case 2: __EM_ASM_2(op##w, ax, dx); break; \
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case 4: __EM_ASM_2(op##l, eax, edx); break; \
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ON64(case 8: __EM_ASM_2(op##q, rax, rdx); break;) \
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EM_ASM_END
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/*
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* fastop functions have a special calling convention:
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*
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@ -1027,15 +1036,16 @@ static int read_descriptor(struct x86_emulate_ctxt *ctxt,
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return rc;
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}
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FASTOP2(add);
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FASTOP2(or);
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FASTOP2(adc);
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FASTOP2(sbb);
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FASTOP2(and);
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FASTOP2(sub);
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FASTOP2(xor);
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FASTOP2(cmp);
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FASTOP2(test);
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EM_ASM_2(add);
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EM_ASM_2(or);
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EM_ASM_2(adc);
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EM_ASM_2(sbb);
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EM_ASM_2(and);
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EM_ASM_2(sub);
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EM_ASM_2(xor);
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EM_ASM_2(cmp);
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EM_ASM_2(test);
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EM_ASM_2(xadd);
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FASTOP1SRC2(mul, mul_ex);
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FASTOP1SRC2(imul, imul_ex);
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@ -1067,7 +1077,6 @@ FASTOP2W(bts);
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FASTOP2W(btr);
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FASTOP2W(btc);
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FASTOP2(xadd);
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FASTOP2R(cmp, cmp_r);
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@ -2304,7 +2313,7 @@ static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
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ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
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ctxt->src.orig_val = ctxt->src.val;
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ctxt->src.val = ctxt->dst.orig_val;
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fastop(ctxt, em_cmp);
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em_cmp(ctxt);
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if (ctxt->eflags & X86_EFLAGS_ZF) {
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/* Success: write back to memory; no update of EAX */
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@ -3069,7 +3078,7 @@ static int em_das(struct x86_emulate_ctxt *ctxt)
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ctxt->src.type = OP_IMM;
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ctxt->src.val = 0;
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ctxt->src.bytes = 1;
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fastop(ctxt, em_or);
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em_or(ctxt);
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ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
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if (cf)
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ctxt->eflags |= X86_EFLAGS_CF;
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@ -3095,7 +3104,7 @@ static int em_aam(struct x86_emulate_ctxt *ctxt)
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ctxt->src.type = OP_IMM;
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ctxt->src.val = 0;
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ctxt->src.bytes = 1;
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fastop(ctxt, em_or);
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em_or(ctxt);
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return X86EMUL_CONTINUE;
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}
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@ -3113,7 +3122,7 @@ static int em_aad(struct x86_emulate_ctxt *ctxt)
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ctxt->src.type = OP_IMM;
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ctxt->src.val = 0;
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ctxt->src.bytes = 1;
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fastop(ctxt, em_or);
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em_or(ctxt);
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return X86EMUL_CONTINUE;
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}
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@ -3998,9 +4007,9 @@ static int check_perm_out(struct x86_emulate_ctxt *ctxt)
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#define I2bvIP(_f, _e, _i, _p) \
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IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
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#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
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F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
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F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
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#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
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I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
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I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
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static const struct opcode group7_rm0[] = {
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N,
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@ -4038,14 +4047,14 @@ static const struct opcode group7_rm7[] = {
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};
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static const struct opcode group1[] = {
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F(Lock, em_add),
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F(Lock | PageTable, em_or),
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F(Lock, em_adc),
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F(Lock, em_sbb),
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F(Lock | PageTable, em_and),
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F(Lock, em_sub),
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F(Lock, em_xor),
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F(NoWrite, em_cmp),
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I(Lock, em_add),
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I(Lock | PageTable, em_or),
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I(Lock, em_adc),
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I(Lock, em_sbb),
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I(Lock | PageTable, em_and),
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I(Lock, em_sub),
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I(Lock, em_xor),
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I(NoWrite, em_cmp),
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};
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static const struct opcode group1A[] = {
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@ -4064,8 +4073,8 @@ static const struct opcode group2[] = {
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};
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static const struct opcode group3[] = {
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F(DstMem | SrcImm | NoWrite, em_test),
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F(DstMem | SrcImm | NoWrite, em_test),
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I(DstMem | SrcImm | NoWrite, em_test),
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I(DstMem | SrcImm | NoWrite, em_test),
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I(DstMem | SrcNone | Lock, em_not),
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I(DstMem | SrcNone | Lock, em_neg),
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F(DstXacc | Src2Mem, em_mul_ex),
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@ -4258,29 +4267,29 @@ static const struct instr_dual instr_dual_8d = {
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static const struct opcode opcode_table[256] = {
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/* 0x00 - 0x07 */
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F6ALU(Lock, em_add),
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I6ALU(Lock, em_add),
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I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
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I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
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/* 0x08 - 0x0F */
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F6ALU(Lock | PageTable, em_or),
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I6ALU(Lock | PageTable, em_or),
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I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
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N,
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/* 0x10 - 0x17 */
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F6ALU(Lock, em_adc),
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I6ALU(Lock, em_adc),
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I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
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I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
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/* 0x18 - 0x1F */
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F6ALU(Lock, em_sbb),
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I6ALU(Lock, em_sbb),
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I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
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I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
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/* 0x20 - 0x27 */
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F6ALU(Lock | PageTable, em_and), N, N,
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I6ALU(Lock | PageTable, em_and), N, N,
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/* 0x28 - 0x2F */
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F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
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I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
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/* 0x30 - 0x37 */
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F6ALU(Lock, em_xor), N, N,
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I6ALU(Lock, em_xor), N, N,
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/* 0x38 - 0x3F */
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F6ALU(NoWrite, em_cmp), N, N,
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I6ALU(NoWrite, em_cmp), N, N,
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/* 0x40 - 0x4F */
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X8(I(DstReg, em_inc)), X8(I(DstReg, em_dec)),
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/* 0x50 - 0x57 */
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@ -4306,7 +4315,7 @@ static const struct opcode opcode_table[256] = {
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G(DstMem | SrcImm, group1),
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G(ByteOp | DstMem | SrcImm | No64, group1),
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G(DstMem | SrcImmByte, group1),
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F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
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I2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
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I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
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/* 0x88 - 0x8F */
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I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
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@ -4329,7 +4338,7 @@ static const struct opcode opcode_table[256] = {
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I2bv(SrcSI | DstDI | Mov | String | TwoMemOp, em_mov),
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F2bv(SrcSI | DstDI | String | NoWrite | TwoMemOp, em_cmp_r),
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/* 0xA8 - 0xAF */
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F2bv(DstAcc | SrcImm | NoWrite, em_test),
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I2bv(DstAcc | SrcImm | NoWrite, em_test),
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I2bv(SrcAcc | DstDI | Mov | String, em_mov),
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I2bv(SrcSI | DstAcc | Mov | String, em_mov),
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F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
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@ -4467,7 +4476,7 @@ static const struct opcode twobyte_table[256] = {
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I(DstReg | SrcMem | ModRM, em_bsr_c),
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D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
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/* 0xC0 - 0xC7 */
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F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
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I2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
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N, ID(0, &instr_dual_0f_c3),
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N, N, N, GD(0, &group9),
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/* 0xC8 - 0xCF */
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