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drm/i915/dmc: Add PIPEDMC_EVT_CTL register definition

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To implement workaround for underrun on idle PSR HW issue (Wa_16025596647)
we need PIPEDMC_EVT_CTL_4 register. Add PIPEDMC_EVT_CTL_4 register
definitions.

Bspec: 67576

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250414100508.1208774-4-jouni.hogander@intel.com
This commit is contained in:
Jouni Högander 2025-04-14 13:04:58 +03:00
parent a99b050ca7
commit b23c157d46
1 changed files with 6 additions and 0 deletions
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6
drivers/gpu/drm/i915/display/intel_dmc_regs.h
View File

@ -21,6 +21,12 @@
#define MTL_PIPEDMC_CONTROL _MMIO(0x45250)
#define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4)
#define _MTL_PIPEDMC_EVT_CTL_4_A 0x5f044
#define _MTL_PIPEDMC_EVT_CTL_4_B 0x5f444
#define MTL_PIPEDMC_EVT_CTL_4(pipe) _MMIO_PIPE(pipe, \
_MTL_PIPEDMC_EVT_CTL_4_A, \
_MTL_PIPEDMC_EVT_CTL_4_B)
#define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000
#define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000