github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-24 07:03:03 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

drm/amdgpu: Add se cac method to register block

Browse Source 
Move se cac access callbacks to register access block.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lijo Lazar 2025-12-08 19:04:47 +05:30 committed by Alex Deucher
parent d2de787f2d
commit b1a516a5df
5 changed files with 36 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/drm/amd/amdgpu/amdgpu.h
View File

@ -914,10 +914,6 @@ struct amdgpu_device {
amdgpu_wreg64_t pcie_wreg64;
amdgpu_rreg64_ext_t pcie_rreg64_ext;
amdgpu_wreg64_ext_t pcie_wreg64_ext;
/* protects concurrent se_cac register access */
spinlock_t se_cac_idx_lock;
amdgpu_rreg_t se_cac_rreg;
amdgpu_wreg_t se_cac_wreg;
/* protects concurrent ENDPOINT (audio) register access */
spinlock_t audio_endpt_idx_lock;
amdgpu_block_rreg_t audio_endpt_rreg;
@ -1334,8 +1330,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
#define WREG32_DIDT(reg, v) amdgpu_reg_didt_wr32(adev, (reg), (v))
#define RREG32_GC_CAC(reg) amdgpu_reg_gc_cac_rd32(adev, (reg))
#define WREG32_GC_CAC(reg, v) amdgpu_reg_gc_cac_wr32(adev, (reg), (v))
#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
#define RREG32_SE_CAC(reg) amdgpu_reg_se_cac_rd32(adev, (reg))
#define WREG32_SE_CAC(reg, v) amdgpu_reg_se_cac_wr32(adev, (reg), (v))
#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
#define WREG32_P(reg, val, mask) \

1
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
View File

@ -3889,7 +3889,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
spin_lock_init(&adev->mmio_idx_lock);
spin_lock_init(&adev->pcie_idx_lock);
spin_lock_init(&adev->se_cac_idx_lock);
spin_lock_init(&adev->audio_endpt_idx_lock);
spin_lock_init(&adev->mm_stats.lock);
spin_lock_init(&adev->virt.rlcg_reg_lock);

24
drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c
View File

@ -50,6 +50,10 @@ void amdgpu_reg_access_init(struct amdgpu_device *adev)
spin_lock_init(&adev->reg.gc_cac.lock);
adev->reg.gc_cac.rreg = NULL;
adev->reg.gc_cac.wreg = NULL;
spin_lock_init(&adev->reg.se_cac.lock);
adev->reg.se_cac.rreg = NULL;
adev->reg.se_cac.wreg = NULL;
}
uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg)
@ -129,6 +133,26 @@ void amdgpu_reg_gc_cac_wr32(struct amdgpu_device *adev, uint32_t reg,
adev->reg.gc_cac.wreg(adev, reg, v);
}
uint32_t amdgpu_reg_se_cac_rd32(struct amdgpu_device *adev, uint32_t reg)
{
if (!adev->reg.se_cac.rreg) {
dev_err_once(adev->dev, "SE_CAC register read not supported\n");
return 0;
}
return adev->reg.se_cac.rreg(adev, reg);
}
void amdgpu_reg_se_cac_wr32(struct amdgpu_device *adev, uint32_t reg,
uint32_t v)
{
if (!adev->reg.se_cac.wreg) {
dev_err_once(adev->dev,
"SE_CAC register write not supported\n");
return;
}
adev->reg.se_cac.wreg(adev, reg, v);
}
/*
* register access helper functions.
*/

4
drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h
View File

@ -43,6 +43,7 @@ struct amdgpu_reg_access {
struct amdgpu_reg_ind uvd_ctx;
struct amdgpu_reg_ind didt;
struct amdgpu_reg_ind gc_cac;
struct amdgpu_reg_ind se_cac;
};
void amdgpu_reg_access_init(struct amdgpu_device *adev);
@ -55,6 +56,9 @@ void amdgpu_reg_didt_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
uint32_t amdgpu_reg_gc_cac_rd32(struct amdgpu_device *adev, uint32_t reg);
void amdgpu_reg_gc_cac_wr32(struct amdgpu_device *adev, uint32_t reg,
uint32_t v);
uint32_t amdgpu_reg_se_cac_rd32(struct amdgpu_device *adev, uint32_t reg);
void amdgpu_reg_se_cac_wr32(struct amdgpu_device *adev, uint32_t reg,
uint32_t v);
typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t);
typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t);

12
drivers/gpu/drm/amd/amdgpu/soc15.c
View File

@ -320,10 +320,10 @@ static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
unsigned long flags;
u32 r;
spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
spin_lock_irqsave(&adev->reg.se_cac.lock, flags);
WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
spin_unlock_irqrestore(&adev->reg.se_cac.lock, flags);
return r;
}
@ -331,10 +331,10 @@ static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
{
unsigned long flags;
spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
spin_lock_irqsave(&adev->reg.se_cac.lock, flags);
WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
spin_unlock_irqrestore(&adev->reg.se_cac.lock, flags);
}
static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
@ -975,8 +975,8 @@ static int soc15_common_early_init(struct amdgpu_ip_block *ip_block)
adev->reg.didt.wreg = &soc15_didt_wreg;
adev->reg.gc_cac.rreg = &soc15_gc_cac_rreg;
adev->reg.gc_cac.wreg = &soc15_gc_cac_wreg;
adev->se_cac_rreg = &soc15_se_cac_rreg;
adev->se_cac_wreg = &soc15_se_cac_wreg;
adev->reg.se_cac.rreg = &soc15_se_cac_rreg;
adev->reg.se_cac.wreg = &soc15_se_cac_wreg;
adev->rev_id = amdgpu_device_get_rev_id(adev);
adev->external_rev_id = 0xFF;