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drm/i915/gt: Update RC6 mask for mtl_drpc

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It has been observed sometimes RC6 status register's unused bits are
being set by h/w, without affecting RC6 functionality therefore updating
the mask with used bits accordingly.
As mtl_drpc is debugfs function, removing MISSING_CASE from default case as
it doesn't make sense to panic (panic_on_warn=1) the CI system if register
is reporting unsupported state.

Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230920090620.3255091-1-badal.nilawar@intel.com
This commit is contained in:
Badal Nilawar 2023-09-20 14:36:20 +05:30 committed by Anshuman Gupta
parent 26a8e32e6d
commit b17e684088
2 changed files with 1 additions and 2 deletions
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1
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
View File

@ -290,7 +290,6 @@ static int mtl_drpc(struct seq_file *m)
seq_puts(m, "RC6\n");
break;
default:
MISSING_CASE(REG_FIELD_GET(MTL_CC_MASK, gt_core_status));
seq_puts(m, "Unknown\n");
break;
}

2
drivers/gpu/drm/i915/gt/intel_gt_regs.h
View File

@ -26,7 +26,7 @@
#define MTL_CAGF_MASK REG_GENMASK(8, 0)
#define MTL_CC0 0x0
#define MTL_CC6 0x3
#define MTL_CC_MASK REG_GENMASK(12, 9)
#define MTL_CC_MASK REG_GENMASK(10, 9)
/* RPM unit config (Gen8+) */
#define RPM_CONFIG0 _MMIO(0xd00)