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KVM: arm64: Drop bogus CPTR_EL2.E0POE trap routing
It took me some time to realise it, but CPTR_EL2.E0POE does not apply to a guest, only to EL0 when InHost(). And when InHost(), CPCR_EL2 is mapped to CPACR_EL1, maning that the E0POE bit naturally takes effect without any trap. To sum it up, this trap bit is better left ignored, we will never have to hanedle it. Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20241023145345.1613824-29-maz@kernel.org Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
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@ -79,7 +79,6 @@ enum cgt_group_id {
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CGT_MDCR_E2TB,
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CGT_MDCR_TDCC,
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CGT_CPACR_E0POE,
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CGT_CPTR_TAM,
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CGT_CPTR_TCPAC,
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@ -362,12 +361,6 @@ static const struct trap_bits coarse_trap_bits[] = {
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.mask = MDCR_EL2_TDCC,
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.behaviour = BEHAVE_FORWARD_ANY,
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},
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[CGT_CPACR_E0POE] = {
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.index = CPTR_EL2,
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.value = CPACR_ELx_E0POE,
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.mask = CPACR_ELx_E0POE,
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.behaviour = BEHAVE_FORWARD_ANY,
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},
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[CGT_CPTR_TAM] = {
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.index = CPTR_EL2,
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.value = CPTR_EL2_TAM,
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@ -1141,7 +1134,6 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = {
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SR_TRAP(SYS_AMEVTYPER1_EL0(13), CGT_CPTR_TAM),
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SR_TRAP(SYS_AMEVTYPER1_EL0(14), CGT_CPTR_TAM),
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SR_TRAP(SYS_AMEVTYPER1_EL0(15), CGT_CPTR_TAM),
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SR_TRAP(SYS_POR_EL0, CGT_CPACR_E0POE),
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/* op0=2, op1=1, and CRn<0b1000 */
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SR_RANGE_TRAP(sys_reg(2, 1, 0, 0, 0),
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sys_reg(2, 1, 7, 15, 7), CGT_CPTR_TTA),
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