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Qualcomm clock updates for v6.16

Browse Source 
Introduce support for the camera clock controller on QCS8300.
 
 Correct wait_val values for a variety of GDSCs, fix X Elite UFS clock
 settings, and allow clkaN to be optional in the rpmh clock controller
 driver if command db doesn't define it.
 -----BEGIN PGP SIGNATURE-----
 
 iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmgxK7sVHGFuZGVyc3Nv
 bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3Fo20P+wQKTPuGRNx6M2qGZFsT13VHvLdW
 lyVRohi3V0eKcpOkGo+3w1ez41+gvPQSCwQSFE2KACql1topKbOE7OtGp98QzFnE
 inzslYkO9pfh6Q7EZXHXcNFfTEZ1kDEj3IfFy/FLJo3UA4SsKCoWcNcKoqh0KMUi
 ojDDqSwkR1lwPmwzHNzp3QyTtP7O9AkdAJDEoIdR6xXqe3ehqHyKuLs9ptm/Wge1
 bsiWnwJQlN8wHJEMFyBkT8TbGT98ZMq5Jcza/jaGZppGgGaP6OKJBCtcGVjFpRJV
 9qzgi6xDWxdaduJ1yZ7zNFDu8R/CSyFvVdKcIg2O6uCNg8ALN+VjtOXFcZ1FwFBr
 hcggUjQgeNWgZ89/V0WdnNnC3HVF930f+iFz136ey7xB3g9+I+wXxAE6Unj+F83m
 5khfKp9a4x6RSalpCYzJ5Nlaafi54d9cNpmCyjCY0YjOkHcEb6TEkDAe5QDyFPh7
 /k+LCo4H9zXz7+kp1H8o4z55beFFrXa8FrebqvDcanf4gMKeyqzMgyP+L37W6oA1
 BBGIHeQ3/MJzYLx/jF/Zp952kCF56QpPiGUniC+Qide2Nw41x2uoQWDooRn7zd2I
 qLdO/HSXbswph7+H0nd39E+Sr8+hH/ynFSAhS6CbK0J2i+Ecjn1DUI0HFQeN8A38
 w/cEvkqSNPl7AxuQ
 =Yk2c
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmg3+O4UHHN3Ym95ZEBj
 aHJvbWl1bS5vcmcACgkQrQKIl8bklSXSXQ//d0dr77ZCSBtdCuqm0r/+PcO2kZ3s
 Qzxa3yYJyqp+MvOfoKK8JzcnnLCQELO26j5R6ZXd/BUSkmVgZ/5/JXOrDRsl0zd9
 JqXiVUcuOUytRbEobmBcp1C7dfnIVxoDnuGvdbaR+N1FIWixawc4+nktiKFzjpp3
 UOez7tWRPFdO0pLX0Uriajmk5Zu/1AsYSmfFJBSzczqQEEcWpJEOr7xLuw2wmlp7
 jFjCnrQw5SLwutev9UBnEqS9z4Pngfi9UWZm3S7afhtQUm/e/NyJCjFGqi0u/7p7
 fK3+SFndl6ecB0UeaHnWmxKQjfgeD4V3dpUE+bXSeux6OXyuvNSQctImlcDIcegD
 gKPP7nVmaXHvbAGCxFJNjEylSJeLSkIhMCIY0izFNqGzSDDsXENhfxrJKjI5+wS4
 FHhtpjM+cHkZW98y4spc/Pj+U2VRmClZ8s0CHzMN9l/KUVp23dC2xlAke5HAfgmB
 qttDfhKgoO4KPuuK4SN/6cH9zm289FTYgHddYArapQAZFQOm4SR3KsGLve/WOXeI
 w5MLLKvIf9yggxt5rAOH8PVyN+yP/1A6JUX87SR05S/CovZuYxKmwtYIjos6k9rR
 5lKpQCdp1qneY9pD9izNYAHcOW6dvcN/6r2r0ZDeaIU8HckX/eNJHWC0HwpsthRa
 u5j6RtNRpzl1fOo=
 =GqNK
 -----END PGP SIGNATURE-----

Merge tag 'qcom-clk-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Pull Qualcomm clk driver updates from Bjorn Andersson:

 - Camera clock controller driver for Qualcomm QCS8300
 - Correct wait_val values for a variety of Qualcomm GDSCs
 - Fix Qualcomm X Elite UFS clock settings
 - Allow clkaN to be optional in the Qualcomm RPMh clock controller
   driver if command db doesn't define it
This commit is contained in:
Stephen Boyd 2025-05-28 23:03:20 -07:00
commit b176dab238
13 changed files with 204 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
Documentation/devicetree/bindings/clock/qcom,videocc.yaml
View File

@ -14,6 +14,7 @@ description: |
domains on Qualcomm SoCs.
See also::
include/dt-bindings/clock/qcom,sm6350-videocc.h
include/dt-bindings/clock/qcom,videocc-sc7180.h
include/dt-bindings/clock/qcom,videocc-sc7280.h
include/dt-bindings/clock/qcom,videocc-sdm845.h
@ -26,6 +27,7 @@ properties:
- qcom,sc7180-videocc
- qcom,sc7280-videocc
- qcom,sdm845-videocc
- qcom,sm6350-videocc
- qcom,sm8150-videocc
- qcom,sm8250-videocc
@ -87,6 +89,24 @@ allOf:
- const: bi_tcxo
- const: bi_tcxo_ao
- if:
properties:
compatible:
enum:
- qcom,sm6350-videocc
then:
properties:
clocks:
items:
- description: Video AHB clock from GCC
- description: Board XO source
- description: Sleep Clock source
clock-names:
items:
- const: iface
- const: bi_tcxo
- const: sleep_clk
- if:
properties:
compatible:

6
drivers/clk/qcom/apcs-sdx55.c
View File

@ -111,7 +111,11 @@ static int qcom_apcs_sdx55_clk_probe(struct platform_device *pdev)
* driver, there seems to be no better place to do this. So do it here!
*/
cpu_dev = get_cpu_device(0);
dev_pm_domain_attach(cpu_dev, true);
ret = dev_pm_domain_attach(cpu_dev, true);
if (ret) {
dev_err_probe(dev, ret, "can't get PM domain: %d\n", ret);
goto err;
}
return 0;

103
drivers/clk/qcom/camcc-sa8775p.c
View File

@ -10,7 +10,7 @@
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
#include <dt-bindings/clock/qcom,qcs8300-camcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
@ -1681,6 +1681,24 @@ static struct clk_branch cam_cc_sm_obs_clk = {
},
};
static struct clk_branch cam_cc_titan_top_accu_shift_clk = {
.halt_reg = 0x131f0,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x131f0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_titan_top_accu_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc cam_cc_titan_top_gdsc = {
.gdscr = 0x131bc,
.en_rest_wait_val = 0x2,
@ -1775,6 +1793,7 @@ static struct clk_regmap *cam_cc_sa8775p_clocks[] = {
[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
[CAM_CC_SM_OBS_CLK] = &cam_cc_sm_obs_clk.clkr,
[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] = NULL,
[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
[CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
};
@ -1811,6 +1830,7 @@ static const struct qcom_cc_desc cam_cc_sa8775p_desc = {
};
static const struct of_device_id cam_cc_sa8775p_match_table[] = {
{ .compatible = "qcom,qcs8300-camcc" },
{ .compatible = "qcom,sa8775p-camcc" },
{ }
};
@ -1841,10 +1861,83 @@ static int cam_cc_sa8775p_probe(struct platform_device *pdev)
clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
/* Keep some clocks always enabled */
qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */
qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */
if (device_is_compatible(&pdev->dev, "qcom,qcs8300-camcc")) {
cam_cc_camnoc_axi_clk_src.cmd_rcgr = 0x13154;
cam_cc_camnoc_axi_clk.halt_reg = 0x1316c;
cam_cc_camnoc_axi_clk.clkr.enable_reg = 0x1316c;
cam_cc_camnoc_dcd_xo_clk.halt_reg = 0x13174;
cam_cc_camnoc_dcd_xo_clk.clkr.enable_reg = 0x13174;
cam_cc_csi0phytimer_clk_src.cmd_rcgr = 0x15054;
cam_cc_csi1phytimer_clk_src.cmd_rcgr = 0x15078;
cam_cc_csi2phytimer_clk_src.cmd_rcgr = 0x15098;
cam_cc_csid_clk_src.cmd_rcgr = 0x13134;
cam_cc_mclk0_clk_src.cmd_rcgr = 0x15000;
cam_cc_mclk1_clk_src.cmd_rcgr = 0x1501c;
cam_cc_mclk2_clk_src.cmd_rcgr = 0x15038;
cam_cc_fast_ahb_clk_src.cmd_rcgr = 0x13104;
cam_cc_slow_ahb_clk_src.cmd_rcgr = 0x1311c;
cam_cc_xo_clk_src.cmd_rcgr = 0x131b8;
cam_cc_sleep_clk_src.cmd_rcgr = 0x131d4;
cam_cc_core_ahb_clk.halt_reg = 0x131b4;
cam_cc_core_ahb_clk.clkr.enable_reg = 0x131b4;
cam_cc_cpas_ahb_clk.halt_reg = 0x130f4;
cam_cc_cpas_ahb_clk.clkr.enable_reg = 0x130f4;
cam_cc_cpas_fast_ahb_clk.halt_reg = 0x130fc;
cam_cc_cpas_fast_ahb_clk.clkr.enable_reg = 0x130fc;
cam_cc_csi0phytimer_clk.halt_reg = 0x1506c;
cam_cc_csi0phytimer_clk.clkr.enable_reg = 0x1506c;
cam_cc_csi1phytimer_clk.halt_reg = 0x15090;
cam_cc_csi1phytimer_clk.clkr.enable_reg = 0x15090;
cam_cc_csi2phytimer_clk.halt_reg = 0x150b0;
cam_cc_csi2phytimer_clk.clkr.enable_reg = 0x150b0;
cam_cc_csid_clk.halt_reg = 0x1314c;
cam_cc_csid_clk.clkr.enable_reg = 0x1314c;
cam_cc_csid_csiphy_rx_clk.halt_reg = 0x15074;
cam_cc_csid_csiphy_rx_clk.clkr.enable_reg = 0x15074;
cam_cc_csiphy0_clk.halt_reg = 0x15070;
cam_cc_csiphy0_clk.clkr.enable_reg = 0x15070;
cam_cc_csiphy1_clk.halt_reg = 0x15094;
cam_cc_csiphy1_clk.clkr.enable_reg = 0x15094;
cam_cc_csiphy2_clk.halt_reg = 0x150b4;
cam_cc_csiphy2_clk.clkr.enable_reg = 0x150b4;
cam_cc_mclk0_clk.halt_reg = 0x15018;
cam_cc_mclk0_clk.clkr.enable_reg = 0x15018;
cam_cc_mclk1_clk.halt_reg = 0x15034;
cam_cc_mclk1_clk.clkr.enable_reg = 0x15034;
cam_cc_mclk2_clk.halt_reg = 0x15050;
cam_cc_mclk2_clk.clkr.enable_reg = 0x15050;
cam_cc_qdss_debug_xo_clk.halt_reg = 0x1319c;
cam_cc_qdss_debug_xo_clk.clkr.enable_reg = 0x1319c;
cam_cc_titan_top_gdsc.gdscr = 0x131a0;
cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK] = NULL;
cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK_SRC] = NULL;
cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK] = NULL;
cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK_SRC] = NULL;
cam_cc_sa8775p_clocks[CAM_CC_CSIPHY3_CLK] = NULL;
cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK] = NULL;
cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK_SRC] = NULL;
cam_cc_sa8775p_clocks[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] =
&cam_cc_titan_top_accu_shift_clk.clkr;
/* Keep some clocks always enabled */
qcom_branch_set_clk_en(regmap, 0x13178); /* CAM_CC_CAMNOC_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x131d0); /* CAM_CC_GDSC_CLK */
qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_SLEEP_CLK */
} else {
/* Keep some clocks always enabled */
qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */
qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */
}
ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sa8775p_desc, regmap);

18
drivers/clk/qcom/camcc-sm6350.c
View File

@ -1695,6 +1695,9 @@ static struct clk_branch camcc_sys_tmr_clk = {
static struct gdsc bps_gdsc = {
.gdscr = 0x6004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "bps_gdsc",
},
@ -1704,6 +1707,9 @@ static struct gdsc bps_gdsc = {
static struct gdsc ipe_0_gdsc = {
.gdscr = 0x7004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "ipe_0_gdsc",
},
@ -1713,6 +1719,9 @@ static struct gdsc ipe_0_gdsc = {
static struct gdsc ife_0_gdsc = {
.gdscr = 0x9004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "ife_0_gdsc",
},
@ -1721,6 +1730,9 @@ static struct gdsc ife_0_gdsc = {
static struct gdsc ife_1_gdsc = {
.gdscr = 0xa004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "ife_1_gdsc",
},
@ -1729,6 +1741,9 @@ static struct gdsc ife_1_gdsc = {
static struct gdsc ife_2_gdsc = {
.gdscr = 0xb004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "ife_2_gdsc",
},
@ -1737,6 +1752,9 @@ static struct gdsc ife_2_gdsc = {
static struct gdsc titan_top_gdsc = {
.gdscr = 0x14004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "titan_top_gdsc",
},

11
drivers/clk/qcom/clk-rpmh.c
View File

@ -66,6 +66,8 @@ struct clk_rpmh {
struct clk_rpmh_desc {
struct clk_hw **clks;
size_t num_clks;
/* RPMh clock clkaN are optional for this platform */
bool clka_optional;
};
static DEFINE_MUTEX(rpmh_clk_lock);
@ -648,6 +650,7 @@ static struct clk_hw *sm8550_rpmh_clocks[] = {
static const struct clk_rpmh_desc clk_rpmh_sm8550 = {
.clks = sm8550_rpmh_clocks,
.num_clks = ARRAY_SIZE(sm8550_rpmh_clocks),
.clka_optional = true,
};
static struct clk_hw *sm8650_rpmh_clocks[] = {
@ -679,6 +682,7 @@ static struct clk_hw *sm8650_rpmh_clocks[] = {
static const struct clk_rpmh_desc clk_rpmh_sm8650 = {
.clks = sm8650_rpmh_clocks,
.num_clks = ARRAY_SIZE(sm8650_rpmh_clocks),
.clka_optional = true,
};
static struct clk_hw *sc7280_rpmh_clocks[] = {
@ -847,6 +851,7 @@ static struct clk_hw *sm8750_rpmh_clocks[] = {
static const struct clk_rpmh_desc clk_rpmh_sm8750 = {
.clks = sm8750_rpmh_clocks,
.num_clks = ARRAY_SIZE(sm8750_rpmh_clocks),
.clka_optional = true,
};
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
@ -890,6 +895,12 @@ static int clk_rpmh_probe(struct platform_device *pdev)
rpmh_clk = to_clk_rpmh(hw_clks[i]);
res_addr = cmd_db_read_addr(rpmh_clk->res_name);
if (!res_addr) {
hw_clks[i] = NULL;
if (desc->clka_optional &&
!strncmp(rpmh_clk->res_name, "clka", sizeof("clka") - 1))
continue;
dev_err(&pdev->dev, "missing RPMh resource address for %s\n",
rpmh_clk->res_name);
return -ENODEV;

3
drivers/clk/qcom/dispcc-sm6350.c
View File

@ -681,6 +681,9 @@ static struct clk_branch disp_cc_xo_clk = {
static struct gdsc mdss_gdsc = {
.gdscr = 0x1004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "mdss_gdsc",
},

4
drivers/clk/qcom/gcc-msm8939.c
View File

@ -432,7 +432,7 @@ static const struct parent_map gcc_xo_gpll0_gpll1a_gpll6_sleep_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL1_AUX, 2 },
{ P_GPLL6, 2 },
{ P_GPLL6, 3 },
{ P_SLEEP_CLK, 6 },
};
@ -1113,7 +1113,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
};
static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
F(24000000, P_GPLL0, 1, 1, 45),
F(24000000, P_GPLL6, 1, 1, 45),
F(66670000, P_GPLL0, 12, 0, 0),
{ }
};

6
drivers/clk/qcom/gcc-sm6350.c
View File

@ -2320,6 +2320,9 @@ static struct clk_branch gcc_video_xo_clk = {
static struct gdsc usb30_prim_gdsc = {
.gdscr = 0x1a004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "usb30_prim_gdsc",
},
@ -2328,6 +2331,9 @@ static struct gdsc usb30_prim_gdsc = {
static struct gdsc ufs_phy_gdsc = {
.gdscr = 0x3a004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "ufs_phy_gdsc",
},

2
drivers/clk/qcom/gcc-sm8650.c
View File

@ -3817,7 +3817,9 @@ static int gcc_sm8650_probe(struct platform_device *pdev)
qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */
/* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
regmap_write(regmap, 0x52150, 0x0);

3
drivers/clk/qcom/gcc-sm8750.c
View File

@ -3244,8 +3244,9 @@ static int gcc_sm8750_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x52010, BIT(20), BIT(20));
regmap_update_bits(regmap, 0x52010, BIT(21), BIT(21));
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
/* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
return qcom_cc_really_probe(&pdev->dev, &gcc_sm8750_desc, regmap);
}

4
drivers/clk/qcom/gcc-x1e80100.c
View File

@ -6753,6 +6753,10 @@ static int gcc_x1e80100_probe(struct platform_device *pdev)
/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
regmap_write(regmap, 0x52224, 0x0);
/* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
return qcom_cc_really_probe(&pdev->dev, &gcc_x1e80100_desc, regmap);
}

6
drivers/clk/qcom/gpucc-sm6350.c
View File

@ -413,6 +413,9 @@ static struct clk_branch gpu_cc_gx_vsense_clk = {
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x106c,
.gds_hw_ctrl = 0x1540,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x8,
.pd = {
.name = "gpu_cx_gdsc",
},
@ -423,6 +426,9 @@ static struct gdsc gpu_cx_gdsc = {
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x100c,
.clamp_io_ctrl = 0x1508,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gpu_gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,

27
include/dt-bindings/clock/qcom,sm6350-videocc.h Normal file
View File

@ -0,0 +1,27 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
*/
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM6350_H
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM6350_H
/* VIDEO_CC clocks */
#define VIDEO_PLL0 0
#define VIDEO_PLL0_OUT_EVEN 1
#define VIDEO_CC_IRIS_AHB_CLK 2
#define VIDEO_CC_IRIS_CLK_SRC 3
#define VIDEO_CC_MVS0_AXI_CLK 4
#define VIDEO_CC_MVS0_CORE_CLK 5
#define VIDEO_CC_MVSC_CORE_CLK 6
#define VIDEO_CC_MVSC_CTL_AXI_CLK 7
#define VIDEO_CC_SLEEP_CLK 8
#define VIDEO_CC_SLEEP_CLK_SRC 9
#define VIDEO_CC_VENUS_AHB_CLK 10
/* GDSCs */
#define MVSC_GDSC 0
#define MVS0_GDSC 1
#endif