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ice: remove ice_tspll_params_e825 definitions

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Remove ice_tspll_params_e825 definitions as according to EDS (Electrical
Design Specification) doc, E825 devices support only 156.25 MHz TSPLL
frequency for both TCXO and TIME_REF clock source.

Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
This commit is contained in:
Karol Kolacinski 2025-05-01 15:54:15 -07:00 committed by Tony Nguyen
parent bf12bc4394
commit b14b2d076c
2 changed files with 11 additions and 117 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

107
drivers/net/ethernet/intel/ice/ice_tspll.c
View File

@ -80,93 +80,6 @@ ice_tspll_params_e82x e82x_tspll_params[NUM_ICE_TSPLL_FREQ] = {
},
};
static const struct
ice_tspll_params_e825c e825c_tspll_params[NUM_ICE_TSPLL_FREQ] = {
/* ICE_TSPLL_FREQ_25_000 -> 25 MHz */
{
/* ck_refclkfreq */
0x19,
/* ndivratio */
1,
/* fbdiv_intgr */
320,
/* fbdiv_frac */
0,
/* ref1588_ck_div */
0,
},
/* ICE_TSPLL_FREQ_122_880 -> 122.88 MHz */
{
/* ck_refclkfreq */
0x29,
/* ndivratio */
3,
/* fbdiv_intgr */
195,
/* fbdiv_frac */
1342177280UL,
/* ref1588_ck_div */
0,
},
/* ICE_TSPLL_FREQ_125_000 -> 125 MHz */
{
/* ck_refclkfreq */
0x3E,
/* ndivratio */
2,
/* fbdiv_intgr */
128,
/* fbdiv_frac */
0,
/* ref1588_ck_div */
0,
},
/* ICE_TSPLL_FREQ_153_600 -> 153.6 MHz */
{
/* ck_refclkfreq */
0x33,
/* ndivratio */
3,
/* fbdiv_intgr */
156,
/* fbdiv_frac */
1073741824UL,
/* ref1588_ck_div */
0,
},
/* ICE_TSPLL_FREQ_156_250 -> 156.25 MHz */
{
/* ck_refclkfreq */
0x1F,
/* ndivratio */
5,
/* fbdiv_intgr */
256,
/* fbdiv_frac */
0,
/* ref1588_ck_div */
0,
},
/* ICE_TSPLL_FREQ_245_760 -> 245.76 MHz */
{
/* ck_refclkfreq */
0x52,
/* ndivratio */
3,
/* fbdiv_intgr */
97,
/* fbdiv_frac */
2818572288UL,
/* ref1588_ck_div */
0,
},
};
/**
* ice_tspll_clk_freq_str - Convert time_ref_freq to string
* @clk_freq: Clock frequency
@ -402,7 +315,6 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
union ice_cgu_r16 dw16;
union ice_cgu_r23 dw23;
union ice_cgu_r22 dw22;
union ice_cgu_r24 dw24;
union ice_cgu_r9 dw9;
int err;
@ -418,9 +330,8 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
return -EINVAL;
}
if (clk_src == ICE_CLK_SRC_TCXO && clk_freq != ICE_TSPLL_FREQ_156_250) {
dev_warn(ice_hw_to_dev(hw),
"TCXO only supports 156.25 MHz frequency\n");
if (clk_freq != ICE_TSPLL_FREQ_156_250) {
dev_warn(ice_hw_to_dev(hw), "Adapter only supports 156.25 MHz frequency\n");
return -EINVAL;
}
@ -472,7 +383,7 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
return err;
/* Choose the referenced frequency */
dw16.ck_refclkfreq = e825c_tspll_params[clk_freq].ck_refclkfreq;
dw16.ck_refclkfreq = ICE_TSPLL_CK_REFCLKFREQ_E825;
err = ice_write_cgu_reg(hw, ICE_CGU_R16, dw16.val);
if (err)
return err;
@ -482,8 +393,8 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
if (err)
return err;
dw19.tspll_fbdiv_intgr = e825c_tspll_params[clk_freq].fbdiv_intgr;
dw19.tspll_ndivratio = e825c_tspll_params[clk_freq].ndivratio;
dw19.tspll_fbdiv_intgr = ICE_TSPLL_FBDIV_INTGR_E825;
dw19.tspll_ndivratio = ICE_TSPLL_NDIVRATIO_E825;
err = ice_write_cgu_reg(hw, ICE_CGU_R19, dw19.val);
if (err)
@ -507,17 +418,15 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
if (err)
return err;
dw23.ref1588_ck_div = e825c_tspll_params[clk_freq].ref1588_ck_div;
dw23.ref1588_ck_div = 0;
dw23.time_ref_sel = clk_src;
err = ice_write_cgu_reg(hw, ICE_CGU_R23, dw23.val);
if (err)
return err;
dw24.val = 0;
dw24.fbdiv_frac = e825c_tspll_params[clk_freq].fbdiv_frac;
err = ice_write_cgu_reg(hw, ICE_CGU_R24, dw24.val);
/* Clear the R24 register. */
err = ice_write_cgu_reg(hw, ICE_CGU_R24, 0);
if (err)
return err;

21
drivers/net/ethernet/intel/ice/ice_tspll.h
View File

@ -21,24 +21,9 @@ struct ice_tspll_params_e82x {
u32 post_pll_div;
};
/**
* struct ice_tspll_params_e825c - E825-C TSPLL parameters
* @ck_refclkfreq: ck_refclkfreq selection
* @ndivratio: ndiv ratio that goes directly to the PLL
* @fbdiv_intgr: TSPLL integer feedback divisor
* @fbdiv_frac: TSPLL fractional feedback divisor
* @ref1588_ck_div: clock divisor for tspll ref
*
* Clock Generation Unit parameters used to program the PLL based on the
* selected TIME_REF/TCXO frequency.
*/
struct ice_tspll_params_e825c {
u32 ck_refclkfreq;
u32 ndivratio;
u32 fbdiv_intgr;
u32 fbdiv_frac;
u32 ref1588_ck_div;
};
#define ICE_TSPLL_CK_REFCLKFREQ_E825 0x1F
#define ICE_TSPLL_NDIVRATIO_E825 5
#define ICE_TSPLL_FBDIV_INTGR_E825 256
int ice_tspll_cfg_pps_out_e825c(struct ice_hw *hw, bool enable);
int ice_tspll_init(struct ice_hw *hw);