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interconnect: qcom: Add EPSS L3 scaling support for Shikra SoC

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Add Epoch Subsystem (EPSS) L3 interconnect provider support on
Qualcomm Shikra SoC.

The EPSS L3 block on Shikra SoC is similar to existing Qualcomm EPSS/OSM
L3 providers, but supports only up to 12 frequency lookup table entries.
Reading beyond the supported LUT entries can expose incorrect frequencies.
Add shikra-specific EPSS descriptor shikra_epss_l3_perf_state that reuses
existing EPSS configuration with appropriate LUT entries limit.

Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Link: https://patch.msgid.link/20260603-shikra_epss_l3-v3-2-3c2e0b796e78@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
Raviteja Laggyshetty 2026-06-03 11:26:13 +00:00 committed by Georgi Djakov
parent 070c42f9e6
commit b148c1f785
1 changed files with 15 additions and 1 deletions
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16
drivers/interconnect/qcom/osm-l3.c
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@ -60,6 +60,7 @@ struct qcom_osm_l3_desc {
unsigned int lut_row_size;
unsigned int reg_freq_lut;
unsigned int reg_perf_state;
unsigned int lut_max_entries;
};
#define DEFINE_QNODE(_name, _buswidth) \
@ -90,6 +91,7 @@ static const struct qcom_osm_l3_desc osm_l3 = {
.lut_row_size = OSM_LUT_ROW_SIZE,
.reg_freq_lut = OSM_REG_FREQ_LUT,
.reg_perf_state = OSM_REG_PERF_STATE,
.lut_max_entries = LUT_MAX_ENTRIES,
};
static const struct qcom_osm_l3_desc epss_l3_perf_state = {
@ -98,6 +100,16 @@ static const struct qcom_osm_l3_desc epss_l3_perf_state = {
.lut_row_size = EPSS_LUT_ROW_SIZE,
.reg_freq_lut = EPSS_REG_FREQ_LUT,
.reg_perf_state = EPSS_REG_PERF_STATE,
.lut_max_entries = LUT_MAX_ENTRIES,
};
static const struct qcom_osm_l3_desc shikra_epss_l3_perf_state = {
.nodes = epss_l3_nodes,
.num_nodes = ARRAY_SIZE(epss_l3_nodes),
.lut_row_size = EPSS_LUT_ROW_SIZE,
.reg_freq_lut = EPSS_REG_FREQ_LUT,
.reg_perf_state = EPSS_REG_PERF_STATE,
.lut_max_entries = 12,
};
static const struct qcom_osm_l3_desc epss_l3_l3_vote = {
@ -106,6 +118,7 @@ static const struct qcom_osm_l3_desc epss_l3_l3_vote = {
.lut_row_size = EPSS_LUT_ROW_SIZE,
.reg_freq_lut = EPSS_REG_FREQ_LUT,
.reg_perf_state = EPSS_REG_L3_VOTE,
.lut_max_entries = LUT_MAX_ENTRIES,
};
static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst)
@ -189,7 +202,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
qp->reg_perf_state = desc->reg_perf_state;
for (i = 0; i < LUT_MAX_ENTRIES; i++) {
for (i = 0; i < desc->lut_max_entries; i++) {
info = readl_relaxed(qp->base + desc->reg_freq_lut +
i * desc->lut_row_size);
src = FIELD_GET(LUT_SRC, info);
@ -272,6 +285,7 @@ static const struct of_device_id osm_l3_of_match[] = {
{ .compatible = "qcom,sc7180-osm-l3", .data = &osm_l3 },
{ .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3_perf_state },
{ .compatible = "qcom,sdm845-osm-l3", .data = &osm_l3 },
{ .compatible = "qcom,shikra-epss-l3", .data = &shikra_epss_l3_perf_state },
{ .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 },
{ .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 },
{ .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3_perf_state },