From 343ea11a2fe32550c1d37b947803f4087a3a94c4 Mon Sep 17 00:00:00 2001 From: Mun Yew Tham Date: Mon, 18 Aug 2025 09:39:32 -0700 Subject: [PATCH 1/2] arm64: dts: Agilex5 Add gmac nodes to DTSI for Agilex5 Add the base device tree nodes for gmac0, gmac1, and gmac2 to the DTSI for the Agilex5 SOCFPGA. Agilex5 has three Ethernet controllers based on Synopsys DWC XGMAC IP version 2.10. Signed-off-by: Mun Yew Tham Signed-off-by: Matthew Gerlach Signed-off-by: Dinh Nguyen --- .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 336 ++++++++++++++++++ 1 file changed, 336 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 7d9394a04302..04e99cd7e74b 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -486,5 +486,341 @@ qspi: spi@108d2000 { clocks = <&qspi_clk>; status = "disabled"; }; + + gmac0: ethernet@10810000 { + compatible = "altr,socfpga-stmmac-agilex5", + "snps,dwxgmac-2.10"; + reg = <0x10810000 0x3500>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names = "stmmaceth", "ahb"; + clocks = <&clkmgr AGILEX5_EMAC0_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + mac-address = [00 00 00 00 00 00]; + tx-fifo-depth = <32768>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <64>; + snps,axi-config = <&stmmac_axi_emac0_setup>; + snps,mtl-rx-config = <&mtl_rx_emac0_setup>; + snps,mtl-tx-config = <&mtl_tx_emac0_setup>; + snps,pbl = <32>; + snps,tso; + altr,sysmgr-syscon = <&sysmgr 0x44 0>; + snps,clk-csr = <0>; + status = "disabled"; + + stmmac_axi_emac0_setup: stmmac-axi-config { + snps,wr_osr_lmt = <31>; + snps,rd_osr_lmt = <31>; + snps,blen = <0 0 0 32 16 8 4>; + }; + + mtl_rx_emac0_setup: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x7>; + }; + }; + + mtl_tx_emac0_setup: tx-queues-config { + snps,tx-queues-to-use = <8>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x09>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight = <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight = <0x0B>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue3 { + snps,weight = <0x0C>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue4 { + snps,weight = <0x0D>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue5 { + snps,weight = <0x0E>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue6 { + snps,weight = <0x0F>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue7 { + snps,weight = <0x10>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + }; + }; + + gmac1: ethernet@10820000 { + compatible = "altr,socfpga-stmmac-agilex5", + "snps,dwxgmac-2.10"; + reg = <0x10820000 0x3500>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; + reset-names = "stmmaceth", "ahb"; + clocks = <&clkmgr AGILEX5_EMAC1_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + mac-address = [00 00 00 00 00 00]; + tx-fifo-depth = <32768>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <64>; + snps,axi-config = <&stmmac_axi_emac1_setup>; + snps,mtl-rx-config = <&mtl_rx_emac1_setup>; + snps,mtl-tx-config = <&mtl_tx_emac1_setup>; + snps,pbl = <32>; + snps,tso; + altr,sysmgr-syscon = <&sysmgr 0x48 0>; + snps,clk-csr = <0>; + status = "disabled"; + + stmmac_axi_emac1_setup: stmmac-axi-config { + snps,wr_osr_lmt = <31>; + snps,rd_osr_lmt = <31>; + snps,blen = <0 0 0 32 16 8 4>; + }; + + mtl_rx_emac1_setup: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x7>; + }; + }; + + mtl_tx_emac1_setup: tx-queues-config { + snps,tx-queues-to-use = <8>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x09>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight = <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight = <0x0B>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue3 { + snps,weight = <0x0C>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue4 { + snps,weight = <0x0D>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue5 { + snps,weight = <0x0E>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue6 { + snps,weight = <0x0F>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue7 { + snps,weight = <0x10>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + }; + }; + + gmac2: ethernet@10830000 { + compatible = "altr,socfpga-stmmac-agilex5", + "snps,dwxgmac-2.10"; + reg = <0x10830000 0x3500>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; + reset-names = "stmmaceth", "ahb"; + clocks = <&clkmgr AGILEX5_EMAC2_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + mac-address = [00 00 00 00 00 00]; + tx-fifo-depth = <32768>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <64>; + snps,axi-config = <&stmmac_axi_emac2_setup>; + snps,mtl-rx-config = <&mtl_rx_emac2_setup>; + snps,mtl-tx-config = <&mtl_tx_emac2_setup>; + snps,pbl = <32>; + snps,tso; + altr,sysmgr-syscon = <&sysmgr 0x4c 0>; + snps,clk-csr = <0>; + status = "disabled"; + + stmmac_axi_emac2_setup: stmmac-axi-config { + snps,wr_osr_lmt = <31>; + snps,rd_osr_lmt = <31>; + snps,blen = <0 0 0 32 16 8 4>; + }; + + mtl_rx_emac2_setup: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x7>; + }; + }; + + mtl_tx_emac2_setup: tx-queues-config { + snps,tx-queues-to-use = <8>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x09>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight = <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight = <0x0B>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue3 { + snps,weight = <0x0C>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue4 { + snps,weight = <0x0D>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue5 { + snps,weight = <0x0E>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue6 { + snps,weight = <0x0F>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue7 { + snps,weight = <0x10>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + }; + }; }; }; From 9cb76813425956f82cf598c357da0c9f36a1d9a8 Mon Sep 17 00:00:00 2001 From: Matthew Gerlach Date: Mon, 18 Aug 2025 09:39:33 -0700 Subject: [PATCH 2/2] arm64: dts: socfpga: agilex5: enable gmac2 on the Agilex5 dev kit Enable gmac2 on the Agilex5 SOCFGPA Development Kit. The MAC is connected to a RGMII PHY on a daughter card. There are no RGMII clock delays implemented the on PCB. Signed-off-by: Matthew Gerlach Signed-off-by: Dinh Nguyen --- .../boot/dts/intel/socfpga_agilex5_socdk.dts | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts index d3b913b7902c..e9776e1cdc9a 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts @@ -10,6 +10,9 @@ / { aliases { serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; }; chosen { @@ -37,6 +40,23 @@ &gpio0 { status = "okay"; }; +&gmac2 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&emac2_phy0>; + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + emac2_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + &gpio1 { status = "okay"; };