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dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells support

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Add optional nvmem-cells and nvmem-cell-names properties to support
reading silicon revision information from alternate location using
NVMEM providers. This is used on AM62P to read GP_SW1 register for
accurate silicon revision detection.

Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260209172330.53623-2-jm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Judith Mendez 2026-02-09 11:23:29 -06:00 committed by Nishanth Menon
parent 254f49634e
commit b0ea517535
1 changed files with 11 additions and 0 deletions
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11
Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
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@ -15,6 +15,9 @@ description: |
represented by CTRLMMR_xxx_JTAGID register which contains information about
SoC id and revision.
On some SoCs like AM62P, the silicon revision is determined by reading
alternative registers via NVMEM cells.
properties:
$nodename:
pattern: "^chipid@[0-9a-f]+$"
@ -26,6 +29,14 @@ properties:
reg:
maxItems: 1
nvmem-cells:
items:
- description: Alternate silicon revision register
nvmem-cell-names:
items:
- const: gpsw1
required:
- compatible
- reg