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drm/amd/pm/swsmu/smu11/navi10_ppt: Remove unused 'struct i2c_algorithm navi10_i2c_algo'
Fixes the following W=1 kernel build warning(s): Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Evan Quan <evan.quan@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lee Jones
Alex Deucher
parent
fecc72f181
commit
b0da6cc198
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@ -2325,210 +2325,6 @@ static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
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return 0;
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}
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static void navi10_fill_i2c_req(SwI2cRequest_t *req, bool write,
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uint8_t address, uint32_t numbytes,
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uint8_t *data)
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{
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int i;
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req->I2CcontrollerPort = 0;
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req->I2CSpeed = 2;
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req->SlaveAddress = address;
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req->NumCmds = numbytes;
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for (i = 0; i < numbytes; i++) {
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SwI2cCmd_t *cmd = &req->SwI2cCmds[i];
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/* First 2 bytes are always write for lower 2b EEPROM address */
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if (i < 2)
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cmd->Cmd = 1;
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else
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cmd->Cmd = write;
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/* Add RESTART for read after address filled */
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cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
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/* Add STOP in the end */
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cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
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/* Fill with data regardless if read or write to simplify code */
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cmd->RegisterAddr = data[i];
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}
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}
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static int navi10_i2c_read_data(struct i2c_adapter *control,
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uint8_t address,
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uint8_t *data,
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uint32_t numbytes)
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{
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uint32_t i, ret = 0;
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SwI2cRequest_t req;
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struct amdgpu_device *adev = to_amdgpu_device(control);
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struct smu_table_context *smu_table = &adev->smu.smu_table;
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struct smu_table *table = &smu_table->driver_table;
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if (numbytes > MAX_SW_I2C_COMMANDS) {
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dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
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numbytes, MAX_SW_I2C_COMMANDS);
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return -EINVAL;
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}
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memset(&req, 0, sizeof(req));
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navi10_fill_i2c_req(&req, false, address, numbytes, data);
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mutex_lock(&adev->smu.mutex);
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/* Now read data starting with that address */
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ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
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true);
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mutex_unlock(&adev->smu.mutex);
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if (!ret) {
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SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
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/* Assume SMU fills res.SwI2cCmds[i].Data with read bytes */
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for (i = 0; i < numbytes; i++)
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data[i] = res->SwI2cCmds[i].Data;
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dev_dbg(adev->dev, "navi10_i2c_read_data, address = %x, bytes = %d, data :",
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(uint16_t)address, numbytes);
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print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
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8, 1, data, numbytes, false);
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} else
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dev_err(adev->dev, "navi10_i2c_read_data - error occurred :%x", ret);
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return ret;
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}
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static int navi10_i2c_write_data(struct i2c_adapter *control,
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uint8_t address,
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uint8_t *data,
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uint32_t numbytes)
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{
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uint32_t ret;
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SwI2cRequest_t req;
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struct amdgpu_device *adev = to_amdgpu_device(control);
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if (numbytes > MAX_SW_I2C_COMMANDS) {
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dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
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numbytes, MAX_SW_I2C_COMMANDS);
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return -EINVAL;
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}
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memset(&req, 0, sizeof(req));
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navi10_fill_i2c_req(&req, true, address, numbytes, data);
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mutex_lock(&adev->smu.mutex);
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ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
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mutex_unlock(&adev->smu.mutex);
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if (!ret) {
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dev_dbg(adev->dev, "navi10_i2c_write(), address = %x, bytes = %d , data: ",
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(uint16_t)address, numbytes);
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print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
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8, 1, data, numbytes, false);
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/*
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* According to EEPROM spec there is a MAX of 10 ms required for
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* EEPROM to flush internal RX buffer after STOP was issued at the
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* end of write transaction. During this time the EEPROM will not be
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* responsive to any more commands - so wait a bit more.
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*/
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msleep(10);
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} else
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dev_err(adev->dev, "navi10_i2c_write- error occurred :%x", ret);
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return ret;
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}
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static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap,
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struct i2c_msg *msgs, int num)
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{
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uint32_t i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
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uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
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for (i = 0; i < num; i++) {
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/*
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* SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
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* once and hence the data needs to be spliced into chunks and sent each
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* chunk separately
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*/
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data_size = msgs[i].len - 2;
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data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
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next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
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data_ptr = msgs[i].buf + 2;
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for (j = 0; j < data_size / data_chunk_size; j++) {
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/* Insert the EEPROM dest addess, bits 0-15 */
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data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
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data_chunk[1] = (next_eeprom_addr & 0xff);
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if (msgs[i].flags & I2C_M_RD) {
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ret = navi10_i2c_read_data(i2c_adap,
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(uint8_t)msgs[i].addr,
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data_chunk, MAX_SW_I2C_COMMANDS);
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memcpy(data_ptr, data_chunk + 2, data_chunk_size);
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} else {
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memcpy(data_chunk + 2, data_ptr, data_chunk_size);
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ret = navi10_i2c_write_data(i2c_adap,
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(uint8_t)msgs[i].addr,
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data_chunk, MAX_SW_I2C_COMMANDS);
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}
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if (ret) {
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num = -EIO;
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goto fail;
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}
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next_eeprom_addr += data_chunk_size;
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data_ptr += data_chunk_size;
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}
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if (data_size % data_chunk_size) {
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data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
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data_chunk[1] = (next_eeprom_addr & 0xff);
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if (msgs[i].flags & I2C_M_RD) {
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ret = navi10_i2c_read_data(i2c_adap,
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(uint8_t)msgs[i].addr,
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data_chunk, (data_size % data_chunk_size) + 2);
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memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
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} else {
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memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
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ret = navi10_i2c_write_data(i2c_adap,
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(uint8_t)msgs[i].addr,
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data_chunk, (data_size % data_chunk_size) + 2);
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}
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if (ret) {
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num = -EIO;
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goto fail;
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}
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}
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}
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fail:
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return num;
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}
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static u32 navi10_i2c_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static const struct i2c_algorithm navi10_i2c_algo = {
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.master_xfer = navi10_i2c_xfer,
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.functionality = navi10_i2c_func,
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};
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static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
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void **table)
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{
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