drm/rockchip: csi: Add support RK1808

Change-Id: Ia908f1a8c0a4f72b61bacf98ab6e4ed9a3e3ebed
Signed-off-by: Sandy Huang <hjc@rock-chips.com>

Documentation/devicetree/bindings/display/rockchip/rockchip_mipi_csi_tx.txt

@@ -0,0 +1,56 @@
+Rockchip MIPI CSI HOST
+================================
+
+Required properties:
+- compatible: must be one of:
+	"rockchip,rk1808-mipi-csi".
+- reg: Represent the physical address range of the controller.
+- interrupts: Represent the controller's interrupt to the CPU(s).
+- clocks, clock-names: Phandles to the controller's APB clock(pclk) as
+  described in [1].
+- resets : phandle to the reset of MIPI CSI APB Clock.
+- reset-names : should be "apb".
+- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
+- #address-cells: Should be <1>.
+- #size-cells: Should be <0>.
+- ports: contain a port node with endpoint definitions as defined in [2].
+  For vopb,set the reg = <0> and set the reg = <1> for vopl.
+
+Optional properties
+- clocks, clock-names:
+  phandle to the SNPS-PHY config clock, name should be "phy_cfg".
+  phandle to the SNPS-PHY PLL reference clock, name should be "ref".
+  phandle to the Non-SNPS PHY high speed clock, name should be "hs_clk".
+  phandle to the h2p bridge clock, name should be "h2p".
+- phys: phandle to Non-SNPS PHY node
+- phy-names: the string "mipi_dphy" when is found in a node, along with "phys"
+  attribute, provides phandle to MIPI PHY node
+- rockchip,dual-channel: for dual-channel panel, if not, don't configure
+- rockchip,lane-rate: manually configure lane-rate, not necessary.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/media/video-interfaces.txt
+[3] Documentation/devicetree/bindings/reset/reset.txt
+
+Example:
+
+For Rockchip RK1808:
+
+	csi: csi@ffb20000 {
+		compatible = "rockchip,rk1808-mipi-csi";
+		clocks = <&cru PCLK_MIPI_CSI0>, <&mipi_dphy>;
+		clock-names = "pclk", "hs_clk";
+		phys = <&mipi_dphy>;
+		phy-names = "mipi_dphy";
+		resets = <&cru SRST_MIPICSI>;
+		reset-names = "apb";
+		...
+
+		ports {
+			port {
+				csi_in_vop: endpoint {
+					remote-endpoint = <&vop_out_csi>;
+				};
+			};
+		};
+	};

drivers/gpu/drm/rockchip/Kconfig

@@ -60,6 +60,16 @@ config ROCKCHIP_DW_MIPI_DSI
 	 enable MIPI DSI on RK3288 based SoC, you should selet this
 	 option.
 
+config ROCKCHIP_MIPI_CSI_TX
+	tristate "Rockchip specific extensions for MIPI CSI TX"
+	depends on DRM_ROCKCHIP
+	select DRM_MIPI_DSI
+	help
+	  This selects support for Rockchip SoC specific extensions
+	  for the rocckhip mipi CSI TX driver. If you want to
+	  enable MIPI CSI on RK1808 based SoC, you should selet this
+	  option.
+
 config ROCKCHIP_ANALOGIX_DP
 	tristate "Rockchip specific extensions for Analogix DP driver"
 	depends on DRM_ROCKCHIP

drivers/gpu/drm/rockchip/Makefile

@@ -10,6 +10,7 @@ obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
 obj-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp.o
 cdn-dp-objs := cdn-dp-core.o cdn-dp-reg.o cdn-dp-link-training.o
 obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
+obj-$(CONFIG_ROCKCHIP_MIPI_CSI_TX) += rockchip-mipi-csi-tx.o
 obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
 obj-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
 obj-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o

drivers/gpu/drm/rockchip/rockchip-mipi-csi-tx.h

@@ -0,0 +1,244 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+#ifndef ROCKCHIP_MIPI_CSI_TX
+#define ROCKCHIP_MIPI_CSI_TX
+
+#define DRIVER_NAME    "rockchip-mipi-csi"
+
+#define CSITX_CONFIG_DONE		0x0000
+#define m_CONFIG_DONE			BIT(0)
+#define m_CONFIG_DONE_IMD		BIT(4)
+#define m_CONFIG_DONE_MODE		BIT(8)
+#define v_CONFIG_DONE(x)		(((x) & 0x1) << 0)
+#define v_CONFIG_DONE_IMD(x)		(((x) & 0x1) << 4)
+#define v_CONFIG_DONE_MODE(x)		(((x) & 0x1) << 8)
+enum CONFIG_DONE_MODE {
+	FRAME_END_RX_MODE,
+	FRAME_END_TX_MODE
+};
+
+#define CSITX_ENABLE			0x0004
+#define m_CSITX_EN			BIT(0)
+#define m_CPHY_EN			BIT(1)
+#define m_DPHY_EN			BIT(2)
+#define m_LANE_NUM			GENMASK(5, 4)
+#define m_IDI_48BIT_EN			BIT(9)
+#define v_CSITX_EN(x)			(((x) & 0x1) << 0)
+#define v_CPHY_EN(x)			(((x) & 0x1) << 1)
+#define v_DPHY_EN(x)			(((x) & 0x1) << 2)
+#define v_LANE_NUM(x)			(((x) & 0x3) << 4)
+#define v_IDI_48BIT_EN(x)		(((x) & 0x1) << 9)
+
+#define CSITX_VERSION			0x0008
+#define CSITX_SYS_CTRL0			0x0010
+#define m_SOFT_RESET			BIT(0)
+#define v_SOFT_RESET(x)			(((x) & 0x1) << 0)
+
+#define CSITX_SYS_CTRL1			0x0014
+#define m_BYPASS_SELECT			BIT(0)
+#define v_BYPASS_SELECT(x)		(((x) & 0x1) << 0)
+
+#define CSITX_SYS_CTRL2			0x0018
+#define m_VSYNC_ENABLE			BIT(0)
+#define m_HSYNC_ENABLE			BIT(1)
+#define m_IDI_WHOLE_FRM_EN		BIT(4)
+#define m_VOP_WHOLE_FRM_EN		BIT(5)
+#define v_VSYNC_ENABLE(x)		(((x) & 0x1) << 0)
+#define v_HSYNC_ENABLE(x)		(((x) & 0x1) << 1)
+#define v_IDI_WHOLE_FRM_EN(x)		(((x) & 0x1) << 4)
+#define v_VOP_WHOLE_FRM_EN(x)		(((x) & 0x1) << 5)
+
+#define CSITX_SYS_CTRL3			0x001c
+#define m_NON_CONTINUES_MODE_EN		BIT(0)
+#define m_CONT_MODE_CLK_SET		BIT(4)
+#define m_CONT_MODE_CLK_CLR		BIT(8)
+#define v_NON_CONTINUES_MODE_EN(x)	(((x) & 0x1) << 0)
+#define v_CONT_MODE_CLK_SET(x)		(((x) & 0x1) << 4)
+#define v_CONT_MODE_CLK_CLR(x)		(((x) & 0x1) << 8)
+
+#define CSITX_TIMING_CTRL		0x0020
+#define CSITX_TIMING_VPW_NUM		0x0024
+#define CSITX_TIMING_VBP_NUM		0x0028
+#define CSITX_TIMING_VFP_NUM		0x002c
+#define CSITX_TIMING_HPW_PADDING_NUM	0x0030
+
+#define CSITX_VOP_PATH_CTRL		0x0040
+#define m_VOP_PATH_EN			BIT(0)
+#define m_VOP_DT_USERDEFINE_EN		BIT(1)
+#define m_VOP_VC_USERDEFINE_EN		BIT(2)
+#define m_VOP_WC_USERDEFINE_EN		BIT(3)
+#define m_PIXEL_FORMAT			GENMASK(7, 4)
+#define m_VOP_DT_USERDEFINE		GENMASK(13, 8)
+#define m_VOP_VC_USERDEFINE		GENMASK(15, 14)
+#define m_VOP_WC_USERDEFINE		GENMASK(31, 16)
+#define v_VOP_PATH_EN(x)		(((x) & 0x1) << 0)
+#define v_VOP_DT_USERDEFINE_EN(x)	(((x) & 0x1) << 1)
+#define v_VOP_VC_USERDEFINE_EN(x)	(((x) & 0x1) << 2)
+#define v_VOP_WC_USERDEFINE_EN(x)	(((x) & 0x1) << 3)
+#define v_PIXEL_FORMAT(x)		(((x) & 0xf) << 4)
+#define v_VOP_DT_USERDEFINE(x)		(((x) & 0x3f) << 8)
+#define v_VOP_VC_USERDEFINE(x)		(((x) & 0x3) << 14)
+#define v_VOP_WC_USERDEFINE(x)		(((x) & 0xffff) << 16)
+
+#define CSITX_VOP_PATH_PKT_CTRL		0x0050
+#define m_VOP_LINE_PADDING_EN		BIT(4)
+#define m_VOP_LINE_PADDING_NUM		GENMASK(7, 5)
+#define m_VOP_PKT_PADDING_EN		BIT(8)
+#define m_VOP_WC_ACTIVE			GENMASK(31, 16)
+#define v_VOP_LINE_PADDING_EN(x)	(((x) & 0x1) << 4)
+#define v_VOP_LINE_PADDING_NUM(x)	(((x) & 0x7) << 5)
+#define v_VOP_PKT_PADDING_EN(x)		(((x) & 0x1) << 8)
+#define v_VOP_WC_ACTIVE(x)		(((x) & 0xff) << 16)
+
+#define CSITX_BYPASS_PATH_CTRL		0x0060
+#define m_BYPASS_PATH_EN		BIT(0)
+#define m_BYPASS_DT_USERDEFINE_EN	BIT(1)
+#define m_BYPASS_VC_USERDEFINE_EN	BIT(2)
+#define m_BYPASS_WC_USERDEFINE_EN	BIT(3)
+#define m_CAM_FORMAT			GENMASK(7, 4)
+#define m_BYPASS_DT_USERDEFINE		GENMASK(13, 8)
+#define m_BYPASS_VC_USERDEFINE		GENMASK(15, 14)
+#define m_BYPASS_WC_USERDEFINE		GENMASK(31, 16)
+#define v_BYPASS_PATH_EN(x)		(((x) & 0x1) << 0)
+#define v_BYPASS_DT_USERDEFINE_EN(x)	(((x) & 0x1) << 1)
+#define v_BYPASS_VC_USERDEFINE_EN(x)	(((x) & 0x1) << 2)
+#define v_BYPASS_WC_USERDEFINE_EN(x)	(((x) & 0x1) << 3)
+#define v_CAM_FORMAT(x)			(((x) & 0xf) << 4)
+#define v_BYPASS_DT_USERDEFINE(x)	(((x) & 0x3f) << 8)
+#define v_BYPASS_VC_USERDEFINE(x)	(((x) & 0x3) << 14)
+#define v_BYPASS_WC_USERDEFINE(x)	(((x) & 0xff) << 16)
+
+#define CSITX_BYPASS_PATH_PKT_CTRL	0x0064
+#define m_BYPASS_LINE_PADDING_EN	BIT(4)
+#define m_BYPASS_LINE_PADDING_NUM	GENMASK(7, 5)
+#define m_BYPASS_PKT_PADDING_EN		BIT(8)
+#define m_BYPASS_WC_ACTIVE		GENMASK(31, 16)
+#define v_BYPASS_LINE_PADDING_EN(x)	(((x) & 0x1) << 4)
+#define v_BYPASS_LINE_PADDING_NUM(x)	(((x) & 0x7) << 5)
+#define v_BYPASS_PKT_PADDING_EN(x)	(((x) & 0x1) << 8)
+#define v_BYPASS_WC_ACTIVE(x)		(((x) & 0xff) << 16)
+
+#define CSITX_STATUS0			0x0070
+#define CSITX_STATUS1			0x0074
+#define m_DPHY_PLL_LOCK			BIT(0)
+#define m_STOPSTATE_CLK			BIT(1)
+#define m_STOPSTATE_LANE		GENMASK(7, 4)
+#define PHY_STOPSTATELANE		(m_STOPSTATE_CLK | m_STOPSTATE_LANE)
+
+#define CSITX_STATUS2			0x0078
+#define CSITX_LINE_FLAG_NUM		0x007c
+#define CSITX_INTR_EN			0x0080
+#define CSITX_INTR_CLR			0x0084
+#define CSITX_INTR_STATUS		0x0088
+#define CSITX_INTR_RAW_STATUS		0x008c
+#define CSITX_ERR_INTR_EN		0x0090
+#define CSITX_ERR_INTR_CLR		0x0094
+#define CSITX_ERR_INTR_STATUS		0x0098
+#define CSITX_ERR_INTR_RAW_STATUS	0x009c
+#define CSITX_ULPS_CTRL			0x00a0
+#define CSITX_LPDT_CTRL			0x00a4
+#define CSITX_LPDT_DATA			0x00a8
+#define CSITX_DPHY_CTRL			0x00b0
+#define m_CSITX_ENABLE_PHY		GENMASK(7, 3)
+#define v_CSITX_ENABLE_PHY(x)		(((x) & 0x1f) << 3)
+#define CSITX_DPHY_PPI_CTRL		0x00b4
+#define CSITX_DPHY_TEST_CTRL		0x00b8
+#define CSITX_DPHY_ERROR		0x00bc
+#define CSITX_DPHY_SCAN_CTRL		0x00c0
+#define CSITX_DPHY_SCANIN		0x00c4
+#define CSITX_DPHY_SCANOUT		0x00c8
+#define CSITX_DPHY_BIST			0x00d0
+
+#define MIPI_CSI_FMT_RAW8		0
+#define MIPI_CSI_FMT_RAW10		1
+
+#define PHY_STATUS_TIMEOUT_US		10000
+#define CMD_PKT_STATUS_TIMEOUT_US	20000
+
+enum soc_type {
+	RK1808,
+};
+
+enum csi_path_mode {
+	VOP_PATH,
+	BYPASS_PATH
+};
+
+#define GRF_REG_FIELD(reg, lsb, msb)	((reg << 16) | (lsb << 8) | (msb))
+
+enum grf_reg_fields {
+	DPIUPDATECFG,
+	DPISHUTDN,
+	DPICOLORM,
+	VOPSEL,
+	TURNREQUEST,
+	TURNDISABLE,
+	FORCETXSTOPMODE,
+	FORCERXMODE,
+	ENABLE_N,
+	MASTERSLAVEZ,
+	ENABLECLK,
+	BASEDIR,
+	DPHY_SEL,
+	TXSKEWCALHS,
+	MAX_FIELDS,
+};
+
+struct rockchip_mipi_csi_plat_data {
+	const u32 *csi0_grf_reg_fields;
+	const u32 *csi1_grf_reg_fields;
+	unsigned long max_bit_rate_per_lane;
+	enum soc_type soc_type;
+};
+
+struct mipi_dphy {
+	/* SNPS PHY */
+	struct clk *cfg_clk;
+	struct clk *ref_clk;
+	u16 input_div;
+	u16 feedback_div;
+
+	/* Non-SNPS PHY */
+	struct phy *phy;
+	struct clk *hs_clk;
+};
+
+struct rockchip_mipi_csi {
+	struct drm_encoder encoder;
+	struct drm_connector connector;
+	struct device_node *client;
+	struct mipi_dsi_host dsi_host;
+	struct mipi_dphy dphy;
+	struct drm_panel *panel;
+	struct device *dev;
+	struct regmap *grf;
+	struct reset_control *rst;
+	void __iomem *regs;
+	void __iomem *test_code_regs;
+	struct regmap *regmap;
+	u32 *regsbak;
+	u32 regs_len;
+	struct clk *pclk;
+	struct clk *ref_clk;
+
+	unsigned long mode_flags;
+	unsigned int lane_mbps; /* per lane */
+	u32 channel;
+	u32 lanes;
+	u32 format;
+	struct drm_display_mode mode;
+	u32 path_mode; /* vop path or bypass path */
+	struct drm_property *csi_tx_path_property;
+
+	const struct rockchip_mipi_csi_plat_data *pdata;
+};
+
+enum rockchip_mipi_csi_mode {
+	DSI_COMMAND_MODE,
+	DSI_VIDEO_MODE,
+};
+
+#endif

include/dt-bindings/display/drm_mipi_dsi.h

@@ -47,4 +47,7 @@
 #define MIPI_DSI_FMT_RGB666_PACKED	2
 #define MIPI_DSI_FMT_RGB565		3
 
+#define MIPI_CSI_FMT_RAW8		0
+#define MIPI_CSI_FMT_RAW10		1
+
 #endif /* __DRM_MIPI_DSI__ */