mirror of
https://github.com/torvalds/linux.git
synced 2026-06-03 03:53:37 +02:00
IOMMU Fixes for Linux v7.1-rc5
Including: - Fix compile warning with gcc-16.1 - Intel VT-d: Simplify calculate_psi_aligned_address() - MAINTAINERS updates -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEr9jSbILcajRFYWYyK/BELZcBGuMFAmoZc8cACgkQK/BELZcB GuMbLw/9GslX8hEm6d/x71pZXIC5T/xqwnnMI7C8QjFSjwcIpKI9tAidKTQsC8cu j7QWrT++/yx3gpnWjyBpv/ISpQlUOTy7/ynU/YecdKBLATHRD323NAbNErNmwznJ 2re6GuUCNGKcKTEJ7ZUABEKrQW1BFqZf0X4/pT4kFjvJBJQ+HFeRp/bimQrPltbR Bv9zi8BVyiPCzfHpII2MKinp39z/Ia1+fC7o4QV7LLvlVegbrtmNy42Fu9+29a0X 3TlnfFPJ3JNXpOjY12o3FoClONxvEiu81P7zKQSRJUiieEK8x4NoejyPocR1DghR Hxfa+l+JLV134su/PxZxQEB+gZJLU9aodz/sFAlWyVaQRBZESSPzxmc4pB9q2IZ/ 3XAl5rYH02lvKthsgyHfoEmn4DnIK7q0PFy43Z0bzDSdUbIgNG9cKtz+tjssZXI8 peSMFFVWGslj9tasfFI7H4LPtfx32HqTRNymcKLu/eBOQNvut7lxLL8X40jxcHX1 p8ernQaEyW4bObq4tQbYfvBc0Hub4tA39TCPX215SzDYqpNO4GcSmdG6ixUSfMrI lERjhPvqq9YEVrPU5Qu3c/ULZuaknOWJW435DDkwcsFceqO7AxO6zk5Vh2PD7hIp yEDP+LNbdu/9glFmlBNlw1XHKDzvNPC+tzKehQh3obtR8v5nGPo= =UwDK -----END PGP SIGNATURE----- Merge tag 'iommu-fixes-v7.1-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux Pull iommu fixes from Joerg Roedel: - Fix compile warning with gcc-16.1 - Intel VT-d: Simplify calculate_psi_aligned_address() - MAINTAINERS updates * tag 'iommu-fixes-v7.1-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux: MAINTAINERS: Add my employer to my entries MAINTAINERS: Add Vasant Hegde to reviewers of AMD IOMMU iommu, debugobjects: avoid gcc-16.1 section mismatch warnings iommu/vt-d: Simplify calculate_psi_aligned_address()
This commit is contained in:
Linus Torvalds
commit
b0ab604210
|
|
@ -1150,8 +1150,9 @@ F: Documentation/arch/x86/amd-hfi.rst
|
|||
F: drivers/platform/x86/amd/hfi/
|
||||
|
||||
AMD IOMMU (AMD-VI)
|
||||
M: Joerg Roedel <joro@8bytes.org>
|
||||
M: Joerg Roedel (AMD) <joro@8bytes.org>
|
||||
R: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
|
||||
R: Vasant Hegde <vasant.hegde@amd.com>
|
||||
L: iommu@lists.linux.dev
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux.git
|
||||
|
|
@ -13483,7 +13484,7 @@ F: include/linux/iommu-dma.h
|
|||
F: include/linux/iova.h
|
||||
|
||||
IOMMU SUBSYSTEM
|
||||
M: Joerg Roedel <joro@8bytes.org>
|
||||
M: Joerg Roedel (AMD) <joro@8bytes.org>
|
||||
M: Will Deacon <will@kernel.org>
|
||||
R: Robin Murphy <robin.murphy@arm.com>
|
||||
L: iommu@lists.linux.dev
|
||||
|
|
|
|||
|
|
@ -254,37 +254,29 @@ void cache_tag_unassign_domain(struct dmar_domain *domain,
|
|||
}
|
||||
|
||||
static unsigned long calculate_psi_aligned_address(unsigned long start,
|
||||
unsigned long end,
|
||||
unsigned long *_mask)
|
||||
unsigned long last,
|
||||
unsigned long *size_order)
|
||||
{
|
||||
unsigned long pages = aligned_nrpages(start, end - start + 1);
|
||||
unsigned long aligned_pages = __roundup_pow_of_two(pages);
|
||||
unsigned long bitmask = aligned_pages - 1;
|
||||
unsigned long mask = ilog2(aligned_pages);
|
||||
unsigned long pfn = IOVA_PFN(start);
|
||||
|
||||
/*
|
||||
* PSI masks the low order bits of the base address. If the
|
||||
* address isn't aligned to the mask, then compute a mask value
|
||||
* needed to ensure the target range is flushed.
|
||||
*/
|
||||
if (unlikely(bitmask & pfn)) {
|
||||
unsigned long end_pfn = pfn + pages - 1, shared_bits;
|
||||
unsigned int sz_lg2;
|
||||
|
||||
/* Compute a sz_lg2 that spans start and last */
|
||||
start &= GENMASK(BITS_PER_LONG - 1, VTD_PAGE_SHIFT);
|
||||
sz_lg2 = fls_long(start ^ last);
|
||||
if (sz_lg2 <= 12) {
|
||||
*size_order = 0;
|
||||
return start;
|
||||
}
|
||||
if (unlikely(sz_lg2 >= BITS_PER_LONG)) {
|
||||
/*
|
||||
* Since end_pfn <= pfn + bitmask, the only way bits
|
||||
* higher than bitmask can differ in pfn and end_pfn is
|
||||
* by carrying. This means after masking out bitmask,
|
||||
* high bits starting with the first set bit in
|
||||
* shared_bits are all equal in both pfn and end_pfn.
|
||||
* MAX_AGAW_PFN_WIDTH triggers full invalidation in all
|
||||
* downstream users.
|
||||
*/
|
||||
shared_bits = ~(pfn ^ end_pfn) & ~bitmask;
|
||||
mask = shared_bits ? __ffs(shared_bits) : MAX_AGAW_PFN_WIDTH;
|
||||
*size_order = MAX_AGAW_PFN_WIDTH;
|
||||
return 0;
|
||||
}
|
||||
|
||||
*_mask = mask;
|
||||
|
||||
return ALIGN_DOWN(start, VTD_PAGE_SIZE << mask);
|
||||
*size_order = sz_lg2 - VTD_PAGE_SHIFT;
|
||||
return start & GENMASK(BITS_PER_LONG - 1, sz_lg2);
|
||||
}
|
||||
|
||||
static void qi_batch_flush_descs(struct intel_iommu *iommu, struct qi_batch *batch)
|
||||
|
|
@ -441,12 +433,7 @@ void cache_tag_flush_range(struct dmar_domain *domain, unsigned long start,
|
|||
struct cache_tag *tag;
|
||||
unsigned long flags;
|
||||
|
||||
if (start == 0 && end == ULONG_MAX) {
|
||||
addr = 0;
|
||||
mask = MAX_AGAW_PFN_WIDTH;
|
||||
} else {
|
||||
addr = calculate_psi_aligned_address(start, end, &mask);
|
||||
}
|
||||
addr = calculate_psi_aligned_address(start, end, &mask);
|
||||
|
||||
spin_lock_irqsave(&domain->cache_lock, flags);
|
||||
list_for_each_entry(tag, &domain->cache_tags, node) {
|
||||
|
|
|
|||
|
|
@ -777,21 +777,27 @@ struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns = {
|
|||
|
||||
static struct io_pgtable_cfg *cfg_cookie __initdata;
|
||||
|
||||
static void __init dummy_tlb_flush_all(void *cookie)
|
||||
/*
|
||||
* __noipa prevents gcc from turning indirect iommu_flush_ops calls
|
||||
* into direct calls from a specialized __arm_v7s_unmap() that triggers
|
||||
* a build time section mismatch assertion.
|
||||
*/
|
||||
static __noipa void __init dummy_tlb_flush_all(void *cookie)
|
||||
{
|
||||
WARN_ON(cookie != cfg_cookie);
|
||||
}
|
||||
|
||||
static void __init dummy_tlb_flush(unsigned long iova, size_t size,
|
||||
size_t granule, void *cookie)
|
||||
static __noipa void __init dummy_tlb_flush(unsigned long iova, size_t size,
|
||||
size_t granule, void *cookie)
|
||||
{
|
||||
WARN_ON(cookie != cfg_cookie);
|
||||
WARN_ON(!(size & cfg_cookie->pgsize_bitmap));
|
||||
}
|
||||
|
||||
static void __init dummy_tlb_add_page(struct iommu_iotlb_gather *gather,
|
||||
unsigned long iova, size_t granule,
|
||||
void *cookie)
|
||||
static __noipa void __init dummy_tlb_add_page(struct iommu_iotlb_gather *gather,
|
||||
unsigned long iova,
|
||||
size_t granule,
|
||||
void *cookie)
|
||||
{
|
||||
dummy_tlb_flush(iova, granule, granule, cookie);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -396,6 +396,17 @@
|
|||
# define __disable_sanitizer_instrumentation
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Optional: not supported by clang
|
||||
*
|
||||
* gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Attributes.html#index-noipa
|
||||
*/
|
||||
#if __has_attribute(noipa)
|
||||
# define __noipa __attribute__((noipa))
|
||||
#else
|
||||
# define __noipa
|
||||
#endif
|
||||
|
||||
/*
|
||||
* gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-weak-function-attribute
|
||||
* gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-weak-variable-attribute
|
||||
|
|
|
|||
|
|
@ -1222,7 +1222,7 @@ struct self_test {
|
|||
|
||||
static __initconst const struct debug_obj_descr descr_type_test;
|
||||
|
||||
static bool __init is_static_object(void *addr)
|
||||
static __noipa bool __init is_static_object(void *addr)
|
||||
{
|
||||
struct self_test *obj = addr;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user