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net: dsa: lantiq_gswip: harmonize gswip_mii_mask_*() parameters

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The 'clear' parameter of gswip_mii_mask_cfg() and gswip_mii_mask_pcdu()
is inconsistent with the semantics of regmap_write_bits() which also
applies the mask to the value to be written.
Change the semantic mask/set of the functions gswip_mii_mask_cfg() and
gswip_mii_mask_pcdu() to follow the regmap_write_bits() pattern.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Acked-by; Hauke Mehrtens <hauke@hauke-m.de>:
Acked-by; Hauke Mehrtens <hauke@hauke-m.de>:
Link: https://patch.msgid.link/218854236c97a152af071852bda83d02ff2dd918.1761045000.git.daniel@makrotopia.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Daniel Golle 2025-10-21 12:17:33 +01:00 committed by Jakub Kicinski
parent 1d88358303
commit b0911b9e01
1 changed files with 7 additions and 10 deletions
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17
drivers/net/dsa/lantiq/lantiq_gswip.c
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@ -120,7 +120,7 @@ static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset,
!(val & cleared), 20, 50000);
}
static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set,
static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 mask, u32 set,
int port)
{
int reg_port;
@ -131,11 +131,11 @@ static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set,
reg_port = port + priv->hw_info->mii_port_reg_offset;
regmap_write_bits(priv->mii, GSWIP_MII_CFGp(reg_port), clear | set,
regmap_write_bits(priv->mii, GSWIP_MII_CFGp(reg_port), mask,
set);
}
static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set,
static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 mask, u32 set,
int port)
{
int reg_port;
@ -148,16 +148,13 @@ static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set,
switch (reg_port) {
case 0:
regmap_write_bits(priv->mii, GSWIP_MII_PCDU0, clear | set,
set);
regmap_write_bits(priv->mii, GSWIP_MII_PCDU0, mask, set);
break;
case 1:
regmap_write_bits(priv->mii, GSWIP_MII_PCDU1, clear | set,
set);
regmap_write_bits(priv->mii, GSWIP_MII_PCDU1, mask, set);
break;
case 5:
regmap_write_bits(priv->mii, GSWIP_MII_PCDU5, clear | set,
set);
regmap_write_bits(priv->mii, GSWIP_MII_PCDU5, mask, set);
break;
}
}
@ -1501,7 +1498,7 @@ static void gswip_phylink_mac_link_up(struct phylink_config *config,
gswip_port_set_pause(priv, port, tx_pause, rx_pause);
}
gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port);
gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, GSWIP_MII_CFG_EN, port);
}
static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset,