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arm64: dts: imx8mm-var-som-symphony: Enable PCIe

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Enable PCIe support on the VAR-SOM Symphony carrier board by adding the
external reference clock, configuring the PHY and providing the required
clock and reset properties.

Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Stefano Radaelli 2026-03-19 19:40:31 +01:00 committed by Frank Li
parent 47fc77cb04
commit b06c76fcd8
1 changed files with 30 additions and 0 deletions
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30
arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts
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@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mm-var-som.dtsi"
#include "imx8mm-var-som-wifi-bt-iw61x.dtsi"
@ -17,6 +18,12 @@ chosen {
stdout-path = &uart4;
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -198,6 +205,29 @@ &i2c4 {
status = "okay";
};
&pcie_phy {
clocks = <&pcie0_refclk>;
clock-names = "ref";
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,tx-deemph-gen1 = <0x2d>;
fsl,tx-deemph-gen2 = <0xf>;
fsl,clkreq-unsupported;
status = "okay";
};
&pcie0 {
reset-gpio = <&pca6408 1 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
clock-names = "pcie", "pcie_bus", "pcie_aux";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
status = "okay";
};
/* Header */
&uart1 {
pinctrl-names = "default";