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drm/i915/mst: add beginnings of DP MST documentation
Add a little bit of documentation around DP MST. This is nowhere near complete nor does it have enough detail. But it's better than nothing, and hopefully gives people a basic grasp of what's going on. Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241125151933.2382910-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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#include "intel_vdsc.h"
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#include "skl_scaler.h"
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/*
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* DP MST (DisplayPort Multi-Stream Transport)
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*
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* MST support on the source depends on the platform and port. DP initialization
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* sets up MST for each MST capable encoder. This will become the primary
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* encoder for the port.
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*
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* MST initialization of each primary encoder creates MST stream encoders, one
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* per pipe, and initializes the MST topology manager. The MST stream encoders
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* are sometimes called "fake encoders", because they're virtual, not
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* physical. Thus there are (number of MST capable ports) x (number of pipes)
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* MST stream encoders in total.
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*
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* Decision to use MST for a sink happens at detect on the connector attached to
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* the primary encoder, and this will not change while the sink is connected. We
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* always use MST when possible, including for SST sinks with sideband messaging
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* support.
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*
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* The connectors for the MST streams are added and removed dynamically by the
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* topology manager. Their connection status is also determined by the topology
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* manager.
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*
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* On hardware, each transcoder may be associated with a single DDI
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* port. Multiple transcoders may be associated with the same DDI port only if
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* the port is in MST mode.
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*
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* On TGL+, all the transcoders streaming on the same DDI port will indicate a
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* primary transcoder; the TGL_DP_TP_CTL and TGL_DP_TP_STATUS registers are
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* relevant only on the primary transcoder. Prior to that, they are port
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* registers.
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*/
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/* From fake MST stream encoder to primary encoder */
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static struct intel_encoder *to_primary_encoder(struct intel_encoder *encoder)
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{
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