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rk29: implement sched_clock()
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2455208a7a
commit
b02fd5a7e6
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@ -721,10 +721,10 @@ config ARCH_RK2818
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config ARCH_RK29
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bool "Rockchip Soc Rk29"
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select HAVE_CLK
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select CPU_V7
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select HAVE_CLK
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select COMMON_CLKDEV
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select HAVE_SCHED_CLOCK
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select ARCH_HAS_CPUFREQ
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select GENERIC_TIME
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select GENERIC_CLOCKEVENTS
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@ -21,6 +21,7 @@
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <asm/sched_clock.h>
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#include <asm/mach/time.h>
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#include <mach/rk29_iomap.h>
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@ -166,12 +167,20 @@ static cycle_t rk29_timer_read(struct clocksource *cs)
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return ~RK_TIMER_READVALUE(TIMER_CLKSRC);
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}
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/*
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* Constants generated by clocksource_hz2mult(24000000, 26).
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* This gives a resolution of about 41ns and a wrap period of about 178s.
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*/
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#define MULT 2796202667u
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#define SHIFT 26
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#define MASK (u32)~0
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static struct clocksource rk29_timer_clocksource = {
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.name = TIMER_CLKSRC_NAME,
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.rating = 200,
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.read = rk29_timer_read,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 26,
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.shift = SHIFT,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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@ -189,15 +198,36 @@ static void __init rk29_timer_init_clocksource(void)
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RK_TIMER_SETCOUNT(TIMER_CLKSRC, 0xFFFFFFFF);
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RK_TIMER_ENABLE_FREE_RUNNING(TIMER_CLKSRC);
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cs->mult = clocksource_hz2mult(24000000, cs->shift);
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cs->mult = MULT;
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if (clocksource_register(cs))
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printk(err, cs->name);
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}
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static DEFINE_CLOCK_DATA(cd);
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unsigned long long notrace sched_clock(void)
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{
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u32 cyc = ~RK_TIMER_READVALUE(TIMER_CLKSRC);
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return cyc_to_fixed_sched_clock(&cd, cyc, MASK, MULT, SHIFT);
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}
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static void notrace rk29_update_sched_clock(void)
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{
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u32 cyc = ~RK_TIMER_READVALUE(TIMER_CLKSRC);
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update_sched_clock(&cd, cyc, MASK);
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}
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static void __init rk29_sched_clock_init(void)
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{
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init_fixed_sched_clock(&cd, rk29_update_sched_clock,
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32, 24000000, MULT, SHIFT);
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}
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static void __init rk29_timer_init(void)
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{
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rk29_timer_init_clocksource();
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rk29_timer_init_clockevent();
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rk29_sched_clock_init();
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}
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struct sys_timer rk29_timer = {
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