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arm64: dts: s32g: add PIT support for s32g2 and s32g3

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Add PIT0 and PIT1 for S32G2 and S32G3 SoCs

Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
Reviewed-by: Enric Balletbo i Serra <eballetb@redhat.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Khristine Andreea Barbulescu 2026-05-18 08:35:47 +02:00 committed by Frank Li
parent 95f5bc1632
commit afb61965f3
2 changed files with 38 additions and 2 deletions
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20
arch/arm64/boot/dts/freescale/s32g2.dtsi
View File

@ -3,7 +3,7 @@
* NXP S32G2 SoC family
*
* Copyright (c) 2021 SUSE LLC
* Copyright 2017-2021, 2024-2025 NXP
* Copyright 2017-2021, 2024-2026 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -417,6 +417,15 @@ edma0: dma-controller@40144000 {
clock-names = "dmamux0", "dmamux1";
};
pit0: timer@40188000 {
compatible = "nxp,s32g2-pit";
reg = <0x40188000 0x3000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 61>;
clock-names = "pit";
status = "disabled";
};
can0: can@401b4000 {
compatible = "nxp,s32g2-flexcan";
reg = <0x401b4000 0xa000>;
@ -622,6 +631,15 @@ edma1: dma-controller@40244000 {
clock-names = "dmamux0", "dmamux1";
};
pit1: timer@40288000 {
compatible = "nxp,s32g2-pit";
reg = <0x40288000 0x3000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 61>;
clock-names = "pit";
status = "disabled";
};
can2: can@402a8000 {
compatible = "nxp,s32g2-flexcan";
reg = <0x402a8000 0xa000>;

20
arch/arm64/boot/dts/freescale/s32g3.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright 2021-2025 NXP
* Copyright 2021-2026 NXP
*
* Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
* Ciprian Costea <ciprianmarian.costea@nxp.com>
@ -475,6 +475,15 @@ edma0: dma-controller@40144000 {
clock-names = "dmamux0", "dmamux1";
};
pit0: pit@40188000 {
compatible = "nxp,s32g3-pit", "nxp,s32g2-pit";
reg = <0x40188000 0x3000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 61>;
clock-names = "pit";
status = "disabled";
};
can0: can@401b4000 {
compatible = "nxp,s32g3-flexcan",
"nxp,s32g2-flexcan";
@ -693,6 +702,15 @@ edma1: dma-controller@40244000 {
clock-names = "dmamux0", "dmamux1";
};
pit1: pit@40288000 {
compatible = "nxp,s32g3-pit", "nxp,s32g2-pit";
reg = <0x40288000 0x3000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 61>;
clock-names = "pit";
status = "disabled";
};
can2: can@402a8000 {
compatible = "nxp,s32g3-flexcan",
"nxp,s32g2-flexcan";