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net: phy: mediatek: Add token ring access helper functions in mtk-phy-lib
This patch adds TR(token ring) manipulations and adds correct macro names for those magic numbers. TR is a way to access proprietary registers on page 52b5. Use these helper functions so we can see which fields we're going to modify/set/clear. TR functions with __* prefix mean that the operations inside aren't wrapped by page select/restore functions. This patch doesn't really change registers' settings but just enhances readability and maintainability. Signed-off-by: Sky Huang <skylake.huang@mediatek.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20250213080553.921434-3-SkyLake.Huang@mediatek.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Sky Huang
Jakub Kicinski
parent
2f435137a0
commit
afa08fde7c
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@ -25,6 +25,90 @@
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#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
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/* Registers on Token Ring debug nodes */
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/* ch_addr = 0x0, node_addr = 0x7, data_addr = 0x15 */
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/* NormMseLoThresh */
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#define NORMAL_MSE_LO_THRESH_MASK GENMASK(15, 8)
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/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */
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/* RemAckCntLimitCtrl */
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#define REMOTE_ACK_COUNT_LIMIT_CTRL_MASK GENMASK(2, 1)
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/* ch_addr = 0x1, node_addr = 0xd, data_addr = 0x20 */
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/* VcoSlicerThreshBitsHigh */
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#define VCO_SLICER_THRESH_HIGH_MASK GENMASK(23, 0)
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/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x0 */
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/* DfeTailEnableVgaThresh1000 */
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#define DFE_TAIL_EANBLE_VGA_TRHESH_1000 GENMASK(5, 1)
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/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x1 */
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/* MrvlTrFix100Kp */
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#define MRVL_TR_FIX_100KP_MASK GENMASK(22, 20)
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/* MrvlTrFix100Kf */
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#define MRVL_TR_FIX_100KF_MASK GENMASK(19, 17)
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/* MrvlTrFix1000Kp */
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#define MRVL_TR_FIX_1000KP_MASK GENMASK(16, 14)
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/* MrvlTrFix1000Kf */
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#define MRVL_TR_FIX_1000KF_MASK GENMASK(13, 11)
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/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x12 */
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/* VgaDecRate */
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#define VGA_DECIMATION_RATE_MASK GENMASK(8, 5)
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/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */
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/* SlvDSPreadyTime */
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#define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15)
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/* MasDSPreadyTime */
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#define MASTER_DSP_READY_TIME_MASK GENMASK(14, 7)
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/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x20 */
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/* ResetSyncOffset */
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#define RESET_SYNC_OFFSET_MASK GENMASK(11, 8)
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/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x0 */
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/* FfeUpdGainForceVal */
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#define FFE_UPDATE_GAIN_FORCE_VAL_MASK GENMASK(9, 7)
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/* FfeUpdGainForce */
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#define FFE_UPDATE_GAIN_FORCE BIT(6)
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/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x6 */
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/* SS: Steady-state, KP: Proportional Gain */
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/* SSTrKp100 */
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#define SS_TR_KP100_MASK GENMASK(21, 19)
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/* SSTrKf100 */
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#define SS_TR_KF100_MASK GENMASK(18, 16)
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/* SSTrKp1000Mas */
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#define SS_TR_KP1000_MASTER_MASK GENMASK(15, 13)
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/* SSTrKf1000Mas */
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#define SS_TR_KF1000_MASTER_MASK GENMASK(12, 10)
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/* SSTrKp1000Slv */
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#define SS_TR_KP1000_SLAVE_MASK GENMASK(9, 7)
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/* SSTrKf1000Slv */
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#define SS_TR_KF1000_SLAVE_MASK GENMASK(6, 4)
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/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xd */
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/* RegEEE_st2TrKf1000 */
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#define EEE1000_STAGE2_TR_KF_MASK GENMASK(13, 11)
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/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xf */
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/* RegEEE_slv_waketr_timer_tar */
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#define SLAVE_WAKETR_TIMER_MASK GENMASK(20, 11)
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/* RegEEE_slv_remtx_timer_tar */
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#define SLAVE_REMTX_TIMER_MASK GENMASK(10, 1)
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/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x10 */
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/* RegEEE_slv_wake_int_timer_tar */
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#define SLAVE_WAKEINT_TIMER_MASK GENMASK(10, 1)
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/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x14 */
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/* RegEEE_trfreeze_timer2 */
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#define TR_FREEZE_TIMER2_MASK GENMASK(9, 0)
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/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x1c */
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/* RegEEE100Stg1_tar */
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#define EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK GENMASK(8, 0)
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#define ANALOG_INTERNAL_OPERATION_MAX_US 20
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#define TXRESERVE_MIN 0
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#define TXRESERVE_MAX 7
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@ -700,40 +784,41 @@ static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
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static void mt798x_phy_common_finetune(struct phy_device *phydev)
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{
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phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
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/* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
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__phy_write(phydev, 0x11, 0xc71);
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__phy_write(phydev, 0x12, 0xc);
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__phy_write(phydev, 0x10, 0x8fae);
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__mtk_tr_modify(phydev, 0x1, 0xf, 0x17,
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SLAVE_DSP_READY_TIME_MASK | MASTER_DSP_READY_TIME_MASK,
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FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x18) |
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FIELD_PREP(MASTER_DSP_READY_TIME_MASK, 0x18));
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/* EnabRandUpdTrig = 1 */
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__phy_write(phydev, 0x11, 0x2f00);
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__phy_write(phydev, 0x12, 0xe);
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__phy_write(phydev, 0x10, 0x8fb0);
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/* NormMseLoThresh = 85 */
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__phy_write(phydev, 0x11, 0x55a0);
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__phy_write(phydev, 0x12, 0x0);
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__phy_write(phydev, 0x10, 0x83aa);
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__mtk_tr_modify(phydev, 0x0, 0x7, 0x15,
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NORMAL_MSE_LO_THRESH_MASK,
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FIELD_PREP(NORMAL_MSE_LO_THRESH_MASK, 0x55));
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/* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
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__phy_write(phydev, 0x11, 0x240);
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__phy_write(phydev, 0x12, 0x0);
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__phy_write(phydev, 0x10, 0x9680);
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__mtk_tr_modify(phydev, 0x2, 0xd, 0x0,
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FFE_UPDATE_GAIN_FORCE_VAL_MASK,
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FIELD_PREP(FFE_UPDATE_GAIN_FORCE_VAL_MASK, 0x4) |
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FFE_UPDATE_GAIN_FORCE);
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/* TrFreeze = 0 (mt7988 default) */
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__phy_write(phydev, 0x11, 0x0);
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__phy_write(phydev, 0x12, 0x0);
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__phy_write(phydev, 0x10, 0x9686);
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/* SSTrKp100 = 5 */
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/* SSTrKf100 = 6 */
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/* SSTrKp1000Mas = 5 */
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/* SSTrKf1000Mas = 6 */
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/* SSTrKp1000Slv = 5 */
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/* SSTrKf1000Slv = 6 */
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__phy_write(phydev, 0x11, 0xbaef);
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__phy_write(phydev, 0x12, 0x2e);
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__phy_write(phydev, 0x10, 0x968c);
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__mtk_tr_modify(phydev, 0x2, 0xd, 0x6,
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SS_TR_KP100_MASK | SS_TR_KF100_MASK |
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SS_TR_KP1000_MASTER_MASK | SS_TR_KF1000_MASTER_MASK |
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SS_TR_KP1000_SLAVE_MASK | SS_TR_KF1000_SLAVE_MASK,
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FIELD_PREP(SS_TR_KP100_MASK, 0x5) |
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FIELD_PREP(SS_TR_KF100_MASK, 0x6) |
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FIELD_PREP(SS_TR_KP1000_MASTER_MASK, 0x5) |
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FIELD_PREP(SS_TR_KF1000_MASTER_MASK, 0x6) |
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FIELD_PREP(SS_TR_KP1000_SLAVE_MASK, 0x5) |
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FIELD_PREP(SS_TR_KF1000_SLAVE_MASK, 0x6));
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phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
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}
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@ -756,27 +841,29 @@ static void mt7981_phy_finetune(struct phy_device *phydev)
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}
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phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
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/* ResetSyncOffset = 6 */
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__phy_write(phydev, 0x11, 0x600);
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__phy_write(phydev, 0x12, 0x0);
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__phy_write(phydev, 0x10, 0x8fc0);
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__mtk_tr_modify(phydev, 0x1, 0xf, 0x20,
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RESET_SYNC_OFFSET_MASK,
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FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x6));
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/* VgaDecRate = 1 */
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__phy_write(phydev, 0x11, 0x4c2a);
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__phy_write(phydev, 0x12, 0x3e);
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__phy_write(phydev, 0x10, 0x8fa4);
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__mtk_tr_modify(phydev, 0x1, 0xf, 0x12,
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VGA_DECIMATION_RATE_MASK,
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FIELD_PREP(VGA_DECIMATION_RATE_MASK, 0x1));
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/* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
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* MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
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*/
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__phy_write(phydev, 0x11, 0xd10a);
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__phy_write(phydev, 0x12, 0x34);
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__phy_write(phydev, 0x10, 0x8f82);
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__mtk_tr_modify(phydev, 0x1, 0xf, 0x1,
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MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK |
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MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK,
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FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x3) |
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FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x2) |
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FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x3) |
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FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x2));
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/* VcoSlicerThreshBitsHigh */
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__phy_write(phydev, 0x11, 0x5555);
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__phy_write(phydev, 0x12, 0x55);
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__phy_write(phydev, 0x10, 0x8ec0);
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__mtk_tr_modify(phydev, 0x1, 0xd, 0x20,
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VCO_SLICER_THRESH_HIGH_MASK,
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FIELD_PREP(VCO_SLICER_THRESH_HIGH_MASK, 0x555555));
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phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
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/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
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@ -828,25 +915,23 @@ static void mt7988_phy_finetune(struct phy_device *phydev)
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phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
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phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
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/* ResetSyncOffset = 5 */
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__phy_write(phydev, 0x11, 0x500);
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__phy_write(phydev, 0x12, 0x0);
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__phy_write(phydev, 0x10, 0x8fc0);
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__mtk_tr_modify(phydev, 0x1, 0xf, 0x20,
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RESET_SYNC_OFFSET_MASK,
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FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x5));
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/* VgaDecRate is 1 at default on mt7988 */
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/* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
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* MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
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*/
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__phy_write(phydev, 0x11, 0xb90a);
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__phy_write(phydev, 0x12, 0x6f);
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__phy_write(phydev, 0x10, 0x8f82);
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/* RemAckCntLimitCtrl = 1 */
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__phy_write(phydev, 0x11, 0xfbba);
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__phy_write(phydev, 0x12, 0xc3);
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__phy_write(phydev, 0x10, 0x87f8);
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__mtk_tr_modify(phydev, 0x1, 0xf, 0x1,
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MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK |
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MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK,
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FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x6) |
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FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x7) |
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FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x6) |
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FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x7));
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__mtk_tr_modify(phydev, 0x0, 0xf, 0x3c,
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REMOTE_ACK_COUNT_LIMIT_CTRL_MASK,
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FIELD_PREP(REMOTE_ACK_COUNT_LIMIT_CTRL_MASK, 0x1));
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phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
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/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
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@ -927,40 +1012,36 @@ static void mt798x_phy_eee(struct phy_device *phydev)
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__phy_write(phydev, 0x12, 0x0);
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__phy_write(phydev, 0x10, 0x9690);
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/* REG_EEE_st2TrKf1000 = 2 */
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__phy_write(phydev, 0x11, 0x114f);
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__phy_write(phydev, 0x12, 0x2);
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__phy_write(phydev, 0x10, 0x969a);
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__mtk_tr_modify(phydev, 0x2, 0xd, 0xd,
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EEE1000_STAGE2_TR_KF_MASK,
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FIELD_PREP(EEE1000_STAGE2_TR_KF_MASK, 0x2));
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/* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
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__phy_write(phydev, 0x11, 0x3028);
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__phy_write(phydev, 0x12, 0x0);
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__phy_write(phydev, 0x10, 0x969e);
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__mtk_tr_modify(phydev, 0x2, 0xd, 0xf,
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SLAVE_WAKETR_TIMER_MASK | SLAVE_REMTX_TIMER_MASK,
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FIELD_PREP(SLAVE_WAKETR_TIMER_MASK, 0x6) |
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FIELD_PREP(SLAVE_REMTX_TIMER_MASK, 0x14));
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/* RegEEE_slv_wake_int_timer_tar = 8 */
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__phy_write(phydev, 0x11, 0x5010);
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__phy_write(phydev, 0x12, 0x0);
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__phy_write(phydev, 0x10, 0x96a0);
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__mtk_tr_modify(phydev, 0x2, 0xd, 0x10,
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SLAVE_WAKEINT_TIMER_MASK,
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FIELD_PREP(SLAVE_WAKEINT_TIMER_MASK, 0x8));
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/* RegEEE_trfreeze_timer2 = 586 */
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__phy_write(phydev, 0x11, 0x24a);
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__phy_write(phydev, 0x12, 0x0);
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__phy_write(phydev, 0x10, 0x96a8);
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__mtk_tr_modify(phydev, 0x2, 0xd, 0x14,
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TR_FREEZE_TIMER2_MASK,
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FIELD_PREP(TR_FREEZE_TIMER2_MASK, 0x24a));
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/* RegEEE100Stg1_tar = 16 */
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__phy_write(phydev, 0x11, 0x3210);
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__phy_write(phydev, 0x12, 0x0);
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__phy_write(phydev, 0x10, 0x96b8);
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__mtk_tr_modify(phydev, 0x2, 0xd, 0x1c,
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EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK,
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FIELD_PREP(EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK,
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0x10));
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/* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
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__phy_write(phydev, 0x11, 0x1463);
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__phy_write(phydev, 0x12, 0x0);
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__phy_write(phydev, 0x10, 0x96ca);
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/* DfeTailEnableVgaThresh1000 = 27 */
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__phy_write(phydev, 0x11, 0x36);
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__phy_write(phydev, 0x12, 0x0);
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__phy_write(phydev, 0x10, 0x8f80);
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__mtk_tr_modify(phydev, 0x1, 0xf, 0x0,
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DFE_TAIL_EANBLE_VGA_TRHESH_1000,
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FIELD_PREP(DFE_TAIL_EANBLE_VGA_TRHESH_1000, 0x1b));
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phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
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phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
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@ -18,6 +18,10 @@
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#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
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/* Registers on Token Ring debug nodes */
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/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */
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#define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15)
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/* Registers on MDIO_MMD_VEND1 */
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#define MTK_PHY_GBE_MODE_TX_DELAY_SEL 0x13
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#define MTK_PHY_TEST_MODE_TX_DELAY_SEL 0x14
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@ -42,11 +46,8 @@ static void mtk_gephy_config_init(struct phy_device *phydev)
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0, MTK_PHY_ENABLE_DOWNSHIFT);
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/* Increase SlvDPSready time */
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phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
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__phy_write(phydev, 0x10, 0xafae);
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__phy_write(phydev, 0x12, 0x2f);
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__phy_write(phydev, 0x10, 0x8fae);
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phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
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mtk_tr_modify(phydev, 0x1, 0xf, 0x17, SLAVE_DSP_READY_TIME_MASK,
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FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x5e));
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/* Adjust 100_mse_threshold */
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phy_modify_mmd(phydev, MDIO_MMD_VEND1,
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@ -6,6 +6,69 @@
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#include "mtk.h"
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|
||||
/* Difference between functions with mtk_tr* and __mtk_tr* prefixes is
|
||||
* mtk_tr* functions: wrapped by page switching operations
|
||||
* __mtk_tr* functions: no page switching operations
|
||||
*/
|
||||
|
||||
static void __mtk_tr_access(struct phy_device *phydev, bool read, u8 ch_addr,
|
||||
u8 node_addr, u8 data_addr)
|
||||
{
|
||||
u16 tr_cmd = BIT(15); /* bit 14 & 0 are reserved */
|
||||
|
||||
if (read)
|
||||
tr_cmd |= BIT(13);
|
||||
|
||||
tr_cmd |= (((ch_addr & 0x3) << 11) |
|
||||
((node_addr & 0xf) << 7) |
|
||||
((data_addr & 0x3f) << 1));
|
||||
dev_dbg(&phydev->mdio.dev, "tr_cmd: 0x%x\n", tr_cmd);
|
||||
__phy_write(phydev, 0x10, tr_cmd);
|
||||
}
|
||||
|
||||
static void __mtk_tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
|
||||
u8 data_addr, u16 *tr_high, u16 *tr_low)
|
||||
{
|
||||
__mtk_tr_access(phydev, true, ch_addr, node_addr, data_addr);
|
||||
*tr_low = __phy_read(phydev, 0x11);
|
||||
*tr_high = __phy_read(phydev, 0x12);
|
||||
dev_dbg(&phydev->mdio.dev, "tr_high read: 0x%x, tr_low read: 0x%x\n",
|
||||
*tr_high, *tr_low);
|
||||
}
|
||||
|
||||
static void __mtk_tr_write(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
|
||||
u8 data_addr, u32 tr_data)
|
||||
{
|
||||
__phy_write(phydev, 0x11, tr_data & 0xffff);
|
||||
__phy_write(phydev, 0x12, tr_data >> 16);
|
||||
dev_dbg(&phydev->mdio.dev, "tr_high write: 0x%x, tr_low write: 0x%x\n",
|
||||
tr_data >> 16, tr_data & 0xffff);
|
||||
__mtk_tr_access(phydev, false, ch_addr, node_addr, data_addr);
|
||||
}
|
||||
|
||||
void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
|
||||
u8 data_addr, u32 mask, u32 set)
|
||||
{
|
||||
u32 tr_data;
|
||||
u16 tr_high;
|
||||
u16 tr_low;
|
||||
|
||||
__mtk_tr_read(phydev, ch_addr, node_addr, data_addr, &tr_high, &tr_low);
|
||||
tr_data = (tr_high << 16) | tr_low;
|
||||
tr_data = (tr_data & ~mask) | set;
|
||||
__mtk_tr_write(phydev, ch_addr, node_addr, data_addr, tr_data);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(__mtk_tr_modify);
|
||||
|
||||
void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
|
||||
u8 data_addr, u32 mask, u32 set)
|
||||
{
|
||||
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
|
||||
__mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, mask, set);
|
||||
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mtk_tr_modify);
|
||||
|
||||
int mtk_phy_read_page(struct phy_device *phydev)
|
||||
{
|
||||
return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
|
||||
|
|
|
|||
|
|
@ -68,6 +68,11 @@ struct mtk_socphy_priv {
|
|||
unsigned long led_state;
|
||||
};
|
||||
|
||||
void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
|
||||
u8 data_addr, u32 mask, u32 set);
|
||||
void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
|
||||
u8 data_addr, u32 mask, u32 set);
|
||||
|
||||
int mtk_phy_read_page(struct phy_device *phydev);
|
||||
int mtk_phy_write_page(struct phy_device *phydev, int page);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user