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media: qcom: camss: csiphy-3ph: Add Gen2 v2.1.2 two-phase MIPI CSI-2 DPHY support
Add a PHY configuration sequence and PHY resource for the sm8550 which uses a Qualcomm Gen 2 version 2.1.2 CSI-2 PHY. The PHY can be configured as two phase or three phase in C-PHY or D-PHY mode. This configuration supports two-phase D-PHY mode. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Depeng Shao <quic_depengs@quicinc.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
This commit is contained in:
Depeng Shao
Hans Verkuil
parent
ea2ccca0a2
commit
af4c004d59
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@ -318,6 +318,111 @@ csiphy_lane_regs lane_regs_sm8250[] = {
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{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
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};
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/* GEN2 2.1.2 2PH DPHY mode */
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static const struct
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csiphy_lane_regs lane_regs_sm8550[] = {
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{0x0E90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0E94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
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{0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0090, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0094, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
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{0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0490, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0494, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
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{0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0890, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0894, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
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{0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0C90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0C94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
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{0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0E08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
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{0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0000, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
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{0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0400, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
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{0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0800, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0808, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
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{0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0C00, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0C38, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0C08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
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{0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0094, 0xD7, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x005C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0060, 0xBD, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0494, 0xD7, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x045C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0460, 0xBD, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0894, 0xD7, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x085C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0860, 0xBD, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0864, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0C94, 0xD7, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0C5C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0C60, 0xBD, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0C64, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
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};
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static void csiphy_hw_version_read(struct csiphy_device *csiphy,
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struct device *dev)
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{
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@ -520,6 +625,7 @@ static bool csiphy_is_gen2(u32 version)
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case CAMSS_8250:
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case CAMSS_8280XP:
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case CAMSS_845:
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case CAMSS_8550:
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ret = true;
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break;
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}
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@ -608,6 +714,11 @@ static int csiphy_init(struct csiphy_device *csiphy)
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regs->lane_regs = &lane_regs_sc8280xp[0];
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regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
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break;
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case CAMSS_8550:
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regs->lane_regs = &lane_regs_sm8550[0];
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regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
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regs->offset = 0x1000;
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break;
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default:
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WARN(1, "unknown csiphy version\n");
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return -ENODEV;
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@ -1943,6 +1943,113 @@ static const struct resources_icc icc_res_sc8280xp[] = {
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},
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};
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static const struct camss_subdev_resources csiphy_res_8550[] = {
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/* CSIPHY0 */
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{
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.regulators = { "vdda-phy", "vdda-pll" },
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.clock = { "csiphy0", "csiphy0_timer" },
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.clock_rate = { { 400000000, 480000000 },
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{ 400000000 } },
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.reg = { "csiphy0" },
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.interrupt = { "csiphy0" },
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.csiphy = {
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.hw_ops = &csiphy_ops_3ph_1_0,
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.formats = &csiphy_formats_sdm845
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}
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},
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/* CSIPHY1 */
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{
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.regulators = { "vdda-phy", "vdda-pll" },
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.clock = { "csiphy1", "csiphy1_timer" },
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.clock_rate = { { 400000000, 480000000 },
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{ 400000000 } },
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.reg = { "csiphy1" },
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.interrupt = { "csiphy1" },
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.csiphy = {
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.hw_ops = &csiphy_ops_3ph_1_0,
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.formats = &csiphy_formats_sdm845
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}
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},
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/* CSIPHY2 */
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{
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.regulators = { "vdda-phy", "vdda-pll" },
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.clock = { "csiphy2", "csiphy2_timer" },
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.clock_rate = { { 400000000, 480000000 },
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{ 400000000 } },
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.reg = { "csiphy2" },
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.interrupt = { "csiphy2" },
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.csiphy = {
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.hw_ops = &csiphy_ops_3ph_1_0,
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.formats = &csiphy_formats_sdm845
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}
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},
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/* CSIPHY3 */
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{
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.regulators = { "vdda-phy", "vdda-pll" },
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.clock = { "csiphy3", "csiphy3_timer" },
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.clock_rate = { { 400000000, 480000000 },
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{ 400000000 } },
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.reg = { "csiphy3" },
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.interrupt = { "csiphy3" },
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.csiphy = {
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.hw_ops = &csiphy_ops_3ph_1_0,
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.formats = &csiphy_formats_sdm845
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}
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},
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/* CSIPHY4 */
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{
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.regulators = { "vdda-phy", "vdda-pll" },
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.clock = { "csiphy4", "csiphy4_timer" },
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.clock_rate = { { 400000000, 480000000 },
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{ 400000000 } },
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.reg = { "csiphy4" },
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.interrupt = { "csiphy4" },
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.csiphy = {
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.hw_ops = &csiphy_ops_3ph_1_0,
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.formats = &csiphy_formats_sdm845
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}
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},
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/* CSIPHY5 */
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{
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.regulators = { "vdda-phy", "vdda-pll" },
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.clock = { "csiphy5", "csiphy5_timer" },
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.clock_rate = { { 400000000, 480000000 },
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{ 400000000 } },
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.reg = { "csiphy5" },
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.interrupt = { "csiphy5" },
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.csiphy = {
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.hw_ops = &csiphy_ops_3ph_1_0,
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.formats = &csiphy_formats_sdm845
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}
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},
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/* CSIPHY6 */
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{
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.regulators = { "vdda-phy", "vdda-pll" },
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.clock = { "csiphy6", "csiphy6_timer" },
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.clock_rate = { { 400000000, 480000000 },
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{ 400000000 } },
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.reg = { "csiphy6" },
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.interrupt = { "csiphy6" },
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.csiphy = {
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.hw_ops = &csiphy_ops_3ph_1_0,
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.formats = &csiphy_formats_sdm845
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}
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},
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/* CSIPHY7 */
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{
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.regulators = { "vdda-phy", "vdda-pll" },
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.clock = { "csiphy7", "csiphy7_timer" },
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.clock_rate = { { 400000000, 480000000 },
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{ 400000000 } },
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.reg = { "csiphy7" },
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.interrupt = { "csiphy7" },
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.csiphy = {
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.hw_ops = &csiphy_ops_3ph_1_0,
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.formats = &csiphy_formats_sdm845
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}
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}
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};
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static const struct resources_icc icc_res_sm8550[] = {
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{
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.name = "ahb",
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@ -2995,8 +3102,10 @@ static const struct camss_resources sc7280_resources = {
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static const struct camss_resources sm8550_resources = {
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.version = CAMSS_8550,
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.pd_name = "top",
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.csiphy_res = csiphy_res_8550,
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.icc_res = icc_res_sm8550,
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.icc_path_num = ARRAY_SIZE(icc_res_sm8550),
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.csiphy_num = ARRAY_SIZE(csiphy_res_8550),
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.link_entities = camss_link_entities
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};
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