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ALSA: oxygen: add HT-Omega eClaro (7284:9783) support
The HT-Omega eClaro is a PCI sound card built on the C-Media CMI8788 (Oxygen HD) controller, with PCI subsystem ID 7284:9783. Output hardware: - AK4396VF stereo DAC: front L/R output, connected via SPI CE0 - CS4362A 6-channel DAC: surround, center/LFE, and side outputs, connected via SPI CE1 with a 3-byte [0x30, reg, val] frame The CS4362A uses inverse attenuation encoding (0 = 0 dB, 127 = max attenuation) and a 0.5 dB/step logarithmic scale. Volume TLV is set to TLV_DB_SCALE(-6350, 50, 0) to match the hardware. The channel-to- register mapping was verified by listening test: - Pair 1 (regs 7/8): side L/R (ALSA channels 6/7) - Pair 2 (regs 10/11): center/LFE (ALSA channels 4/5) - Pair 3 (regs 13/14): rear L/R (ALSA channels 2/3) Input hardware: - CS5361 stereo ADC: Line In and Mic In capture GPIO assignments: - GPIO 0 (0x0001): CS4362A RESET# (active-low, driven high) - GPIO 2/3: CS5361 M0/M1 (sample rate mode) - GPIO 5 (0x0020): front output stage enable (driven high) - GPIO 8 (0x0100): headphone amplifier enable Signed-off-by: Ferus Castor <feruscastor@proton.me> Assisted-by: Claude:claude-sonnet-4-6 Link: https://patch.msgid.link/20260601015848.128566-1-feruscastor@proton.me Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Ferus Castor
Takashi Iwai
parent
e9c82f767f
commit
af31e980de
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@ -25,6 +25,11 @@
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* GPIO 6 -> S/PDIF from optical (0) or coaxial (1) input
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* GPIO 8 -> enable headphone amplifier
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*
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* eClaro model:
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* GPIO 2 -> M0 of CS5361
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* GPIO 3 -> M1 of CS5361
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* GPIO 8 -> enable headphone amplifier
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*
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* CM9780:
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*
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* LINE_OUT -> input of ADC
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@ -51,6 +56,7 @@
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#include "oxygen.h"
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#include "xonar_dg.h"
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#include "ak4396.h"
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#include "cs4362a.h"
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#include "wm8785.h"
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MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
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@ -74,6 +80,7 @@ enum {
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MODEL_MERIDIAN_2G,
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MODEL_CLARO,
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MODEL_CLARO_HALO,
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MODEL_ECLARO,
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MODEL_FANTASIA,
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MODEL_SERENADE,
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MODEL_2CH_OUTPUT,
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@ -113,6 +120,8 @@ static const struct pci_device_id oxygen_ids[] = {
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{ OXYGEN_PCI_SUBID(0x7284, 0x9761), .driver_data = MODEL_CLARO },
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/* HT-Omega Claro halo */
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{ OXYGEN_PCI_SUBID(0x7284, 0x9781), .driver_data = MODEL_CLARO_HALO },
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/* HT-Omega eClaro */
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{ OXYGEN_PCI_SUBID(0x7284, 0x9783), .driver_data = MODEL_ECLARO },
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{ }
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};
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MODULE_DEVICE_TABLE(pci, oxygen_ids);
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@ -130,27 +139,35 @@ MODULE_DEVICE_TABLE(pci, oxygen_ids);
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#define GPIO_CLARO_DIG_COAX 0x0040
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#define GPIO_CLARO_HP 0x0100
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#define GPIO_ECLARO_CS4362A_NRESET 0x0001 /* GPIO 0: CS4362A RESET# (active-low) */
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#define GPIO_ECLARO_FRONT_ENABLE 0x0020 /* GPIO 5: front output stage enable */
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/* CS4362A SPI: 3-byte frame [0x30, reg, value] on CE1, 1280 ns/bit clock */
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#define ECLARO_CS4362A_SPI_CONTROL \
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(OXYGEN_SPI_TRIGGER | OXYGEN_SPI_DATA_LENGTH_3 | \
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OXYGEN_SPI_CLOCK_1280 | (1 << OXYGEN_SPI_CODEC_SHIFT) | \
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OXYGEN_SPI_CEN_LATCH_CLOCK_HI)
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struct generic_data {
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unsigned int dacs;
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u8 spi_map[4];
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u16 spi_prefix[4];
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u8 ak4396_regs[4][5];
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u8 cs4362a_regs[15];
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u16 wm8785_regs[3];
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};
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static void ak4396_write(struct oxygen *chip, unsigned int codec,
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u8 reg, u8 value)
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{
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/* maps ALSA channel pair number to SPI output */
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static const u8 codec_spi_map[4] = {
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0, 1, 2, 4
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};
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struct generic_data *data = chip->model_data;
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oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
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OXYGEN_SPI_DATA_LENGTH_2 |
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OXYGEN_SPI_CLOCK_160 |
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(codec_spi_map[codec] << OXYGEN_SPI_CODEC_SHIFT) |
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(data->spi_map[codec] << OXYGEN_SPI_CODEC_SHIFT) |
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OXYGEN_SPI_CEN_LATCH_CLOCK_HI,
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AK4396_WRITE | (reg << 8) | value);
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data->spi_prefix[codec] | (reg << 8) | value);
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data->ak4396_regs[codec][reg] = value;
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}
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@ -163,6 +180,51 @@ static void ak4396_write_cached(struct oxygen *chip, unsigned int codec,
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ak4396_write(chip, codec, reg, value);
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}
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static void eclaro_cs4362a_write(struct oxygen *chip, u8 reg, u8 value)
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{
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struct generic_data *data = chip->model_data;
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int err;
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if (reg < ARRAY_SIZE(data->cs4362a_regs))
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data->cs4362a_regs[reg] = value;
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err = oxygen_write_spi(chip, ECLARO_CS4362A_SPI_CONTROL,
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(0x30u << 16) | ((u32)reg << 8) | value);
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if (err)
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dev_err(chip->card->dev,
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"CS4362A SPI timeout: reg=0x%02x val=0x%02x\n",
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reg, value);
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}
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static void eclaro_cs4362a_write_cached(struct oxygen *chip, u8 reg, u8 value)
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{
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struct generic_data *data = chip->model_data;
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if (value != data->cs4362a_regs[reg])
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eclaro_cs4362a_write(chip, reg, value);
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}
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static void eclaro_cs4362a_registers_init(struct oxygen *chip)
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{
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struct generic_data *data = chip->model_data;
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eclaro_cs4362a_write(chip, 1, CS4362A_CPEN | CS4362A_PDN);
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eclaro_cs4362a_write(chip, 2, CS4362A_DIF_LJUST);
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eclaro_cs4362a_write(chip, 3, CS4362A_SOFT_RAMP | CS4362A_AMUTE);
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eclaro_cs4362a_write(chip, 4, data->cs4362a_regs[4]);
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eclaro_cs4362a_write(chip, 5, 0);
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eclaro_cs4362a_write(chip, 6, data->cs4362a_regs[6]);
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eclaro_cs4362a_write(chip, 7, data->cs4362a_regs[7]);
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eclaro_cs4362a_write(chip, 8, data->cs4362a_regs[8]);
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eclaro_cs4362a_write(chip, 9, data->cs4362a_regs[9]);
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eclaro_cs4362a_write(chip, 10, data->cs4362a_regs[10]);
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eclaro_cs4362a_write(chip, 11, data->cs4362a_regs[11]);
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eclaro_cs4362a_write(chip, 12, data->cs4362a_regs[12]);
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eclaro_cs4362a_write(chip, 13, data->cs4362a_regs[13]);
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eclaro_cs4362a_write(chip, 14, data->cs4362a_regs[14]);
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eclaro_cs4362a_write(chip, 1, CS4362A_CPEN);
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}
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static void wm8785_write(struct oxygen *chip, u8 reg, unsigned int value)
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{
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struct generic_data *data = chip->model_data;
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@ -199,8 +261,13 @@ static void ak4396_registers_init(struct oxygen *chip)
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static void ak4396_init(struct oxygen *chip)
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{
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struct generic_data *data = chip->model_data;
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static const u8 default_spi_map[4] = { 0, 1, 2, 4 };
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unsigned int i;
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data->dacs = chip->model.dac_channels_pcm / 2;
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memcpy(data->spi_map, default_spi_map, sizeof(default_spi_map));
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for (i = 0; i < 4; ++i)
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data->spi_prefix[i] = AK4396_WRITE;
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data->ak4396_regs[0][AK4396_CONTROL_2] =
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AK4396_SMUTE | AK4396_DEM_OFF | AK4396_DFS_NORMAL;
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ak4396_registers_init(chip);
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@ -322,6 +389,102 @@ static void claro_resume(struct oxygen *chip)
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claro_enable_hp(chip);
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}
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#define GPIO_CS5361_M_MASK 0x000c
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#define GPIO_CS5361_M_SINGLE 0x0000
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#define GPIO_CS5361_M_DOUBLE 0x0004
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#define GPIO_CS5361_M_QUAD 0x0008
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static void cs5361_init(struct oxygen *chip)
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{
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oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_CS5361_M_MASK);
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oxygen_write16_masked(chip, OXYGEN_GPIO_DATA,
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GPIO_CS5361_M_SINGLE, GPIO_CS5361_M_MASK);
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}
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static void set_cs5361_params(struct oxygen *chip,
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struct snd_pcm_hw_params *params)
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{
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unsigned int value;
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if (params_rate(params) <= 54000)
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value = GPIO_CS5361_M_SINGLE;
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else if (params_rate(params) <= 108000)
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value = GPIO_CS5361_M_DOUBLE;
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else
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value = GPIO_CS5361_M_QUAD;
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oxygen_write16_masked(chip, OXYGEN_GPIO_DATA,
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value, GPIO_CS5361_M_MASK);
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}
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static void eclaro_init(struct oxygen *chip)
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{
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struct generic_data *data = chip->model_data;
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oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_CLARO_DIG_COAX);
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oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_DIG_COAX);
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/* Single AK4396VF on SPI CE0/CA=00 handles front L/R */
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data->dacs = 1;
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data->spi_map[0] = 0;
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data->spi_prefix[0] = AK4396_WRITE;
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data->ak4396_regs[0][AK4396_CONTROL_2] =
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AK4396_SMUTE | AK4396_DEM_OFF | AK4396_DFS_NORMAL;
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ak4396_write(chip, 0, AK4396_CONTROL_1, AK4396_DIF_24_MSB | AK4396_ACKS);
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ak4396_write(chip, 0, AK4396_CONTROL_2,
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data->ak4396_regs[0][AK4396_CONTROL_2]);
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ak4396_write(chip, 0, AK4396_CONTROL_3, AK4396_PCM);
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ak4396_write(chip, 0, AK4396_LCH_ATT, chip->dac_volume[0] * 2);
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ak4396_write(chip, 0, AK4396_RCH_ATT, chip->dac_volume[1] * 2);
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ak4396_write(chip, 0, AK4396_CONTROL_1, AK4396_DIF_24_MSB | AK4396_ACKS | AK4396_RSTN);
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/* CS4362A (SPI CE1): surround/center-LFE/side L/R.
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* GPIO 0 (RESET#, active-low) and GPIO 5 (front output enable) must
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* be driven high. GPIOs 1 and 7 are outputs driven high.
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*/
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oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, 0x00a3);
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oxygen_set_bits16(chip, OXYGEN_GPIO_DATA, 0x00a3);
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usleep_range(1000, 2000);
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data->cs4362a_regs[4] = CS4362A_RMP_DN | CS4362A_DEM_NONE;
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data->cs4362a_regs[6] = CS4362A_FM_SINGLE |
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CS4362A_ATAPI_B_R | CS4362A_ATAPI_A_L;
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data->cs4362a_regs[7] = CS4362A_MUTE;
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data->cs4362a_regs[9] = data->cs4362a_regs[6];
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data->cs4362a_regs[12] = data->cs4362a_regs[6];
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eclaro_cs4362a_registers_init(chip);
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snd_component_add(chip->card, "AK4396");
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snd_component_add(chip->card, "CS4362A");
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cs5361_init(chip);
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claro_enable_hp(chip);
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snd_component_add(chip->card, "CS5361");
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}
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static void eclaro_resume(struct oxygen *chip)
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{
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struct generic_data *data = chip->model_data;
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oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL,
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GPIO_ECLARO_CS4362A_NRESET | GPIO_ECLARO_FRONT_ENABLE);
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oxygen_set_bits16(chip, OXYGEN_GPIO_DATA,
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GPIO_ECLARO_CS4362A_NRESET | GPIO_ECLARO_FRONT_ENABLE);
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/* AK4396 chip 0 */
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ak4396_write(chip, 0, AK4396_CONTROL_1, AK4396_DIF_24_MSB | AK4396_ACKS | AK4396_RSTN);
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ak4396_write(chip, 0, AK4396_CONTROL_2,
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data->ak4396_regs[0][AK4396_CONTROL_2]);
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ak4396_write(chip, 0, AK4396_CONTROL_3, AK4396_PCM);
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ak4396_write(chip, 0, AK4396_LCH_ATT, chip->dac_volume[0] * 2);
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ak4396_write(chip, 0, AK4396_RCH_ATT, chip->dac_volume[1] * 2);
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eclaro_cs4362a_registers_init(chip);
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cs5361_init(chip);
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claro_enable_hp(chip);
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}
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static void stereo_resume(struct oxygen *chip)
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{
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ak4396_registers_init(chip);
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@ -355,6 +518,76 @@ static void set_ak4396_params(struct oxygen *chip,
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}
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}
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static void eclaro_set_dac_params(struct oxygen *chip,
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struct snd_pcm_hw_params *params)
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{
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struct generic_data *data = chip->model_data;
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u8 ak_value, cs_fm;
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ak_value = data->ak4396_regs[0][AK4396_CONTROL_2] & ~AK4396_DFS_MASK;
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if (params_rate(params) <= 54000) {
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ak_value |= AK4396_DFS_NORMAL;
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cs_fm = CS4362A_FM_SINGLE;
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} else if (params_rate(params) <= 108000) {
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ak_value |= AK4396_DFS_DOUBLE;
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cs_fm = CS4362A_FM_DOUBLE;
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} else {
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ak_value |= AK4396_DFS_QUAD;
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cs_fm = CS4362A_FM_QUAD;
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}
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usleep_range(1000, 2000);
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if (ak_value != data->ak4396_regs[0][AK4396_CONTROL_2]) {
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ak4396_write(chip, 0, AK4396_CONTROL_1, AK4396_DIF_24_MSB | AK4396_ACKS);
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ak4396_write(chip, 0, AK4396_CONTROL_2, ak_value);
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ak4396_write(chip, 0, AK4396_CONTROL_1,
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AK4396_DIF_24_MSB | AK4396_ACKS | AK4396_RSTN);
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data->ak4396_regs[0][AK4396_CONTROL_2] = ak_value;
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}
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/* Update CS4362A FM mode for all three DAC pairs */
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cs_fm |= data->cs4362a_regs[6] & ~CS4362A_FM_MASK;
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eclaro_cs4362a_write_cached(chip, 6, cs_fm);
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eclaro_cs4362a_write_cached(chip, 12, cs_fm);
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cs_fm &= CS4362A_FM_MASK;
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cs_fm |= data->cs4362a_regs[9] & ~CS4362A_FM_MASK;
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eclaro_cs4362a_write_cached(chip, 9, cs_fm);
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}
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static void update_eclaro_volume(struct oxygen *chip)
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{
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u8 mute = chip->dac_mute ? CS4362A_MUTE : 0;
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ak4396_write_cached(chip, 0, AK4396_LCH_ATT, chip->dac_volume[0] * 2);
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ak4396_write_cached(chip, 0, AK4396_RCH_ATT, chip->dac_volume[1] * 2);
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/* CS4362A attenuation is inverse: 0 = 0 dB, 127 = max attenuation.
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* Pair 1 (regs 7/8) is wired to the side outputs (ALSA ch 6/7);
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* pair 3 (regs 13/14) is wired to the rear outputs (ALSA ch 2/3).
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*/
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eclaro_cs4362a_write_cached(chip, 7, mute | (127 - chip->dac_volume[6]));
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eclaro_cs4362a_write_cached(chip, 8, mute | (127 - chip->dac_volume[7]));
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eclaro_cs4362a_write_cached(chip, 10, mute | (127 - chip->dac_volume[4]));
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eclaro_cs4362a_write_cached(chip, 11, mute | (127 - chip->dac_volume[5]));
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eclaro_cs4362a_write_cached(chip, 13, mute | (127 - chip->dac_volume[2]));
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eclaro_cs4362a_write_cached(chip, 14, mute | (127 - chip->dac_volume[3]));
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}
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static void update_eclaro_mute(struct oxygen *chip)
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{
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struct generic_data *data = chip->model_data;
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u8 value;
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value = data->ak4396_regs[0][AK4396_CONTROL_2] & ~AK4396_SMUTE;
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if (chip->dac_mute)
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value |= AK4396_SMUTE;
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ak4396_write_cached(chip, 0, AK4396_CONTROL_2, value);
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/* Re-apply volume+mute to CS4362A so the mute bit is set correctly */
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update_eclaro_volume(chip);
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}
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static void update_ak4396_volume(struct oxygen *chip)
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{
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struct generic_data *data = chip->model_data;
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@ -702,6 +935,8 @@ static void dump_oxygen_registers(struct oxygen *chip,
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}
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static const DECLARE_TLV_DB_LINEAR(ak4396_db_scale, TLV_DB_GAIN_MUTE, 0);
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/* CS4362A: 0.5 dB/step, raw=127 -> 0 dB, raw=0 -> -63.5 dB */
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static const DECLARE_TLV_DB_SCALE(eclaro_db_scale, -6350, 50, 0);
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static const struct oxygen_model model_generic = {
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.shortname = "C-Media CMI8788",
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@ -745,6 +980,7 @@ static int get_oxygen_model(struct oxygen *chip,
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[MODEL_MERIDIAN_2G] = "AuzenTech X-Meridian 2G",
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[MODEL_CLARO] = "HT-Omega Claro",
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[MODEL_CLARO_HALO] = "HT-Omega Claro halo",
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[MODEL_ECLARO] = "HT-Omega eClaro",
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[MODEL_FANTASIA] = "TempoTec HiFier Fantasia",
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[MODEL_SERENADE] = "TempoTec HiFier Serenade",
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[MODEL_HG2PCI] = "CMI8787-HG2PCI",
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@ -788,6 +1024,28 @@ static int get_oxygen_model(struct oxygen *chip,
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CAPTURE_0_FROM_I2S_2 |
|
||||
CAPTURE_1_FROM_SPDIF;
|
||||
break;
|
||||
case MODEL_ECLARO:
|
||||
chip->model.init = eclaro_init;
|
||||
chip->model.mixer_init = generic_mixer_init;
|
||||
chip->model.cleanup = claro_cleanup;
|
||||
chip->model.suspend = claro_suspend;
|
||||
chip->model.resume = eclaro_resume;
|
||||
chip->model.set_dac_params = eclaro_set_dac_params;
|
||||
chip->model.set_adc_params = set_cs5361_params;
|
||||
chip->model.update_dac_volume = update_eclaro_volume;
|
||||
chip->model.update_dac_mute = update_eclaro_mute;
|
||||
chip->model.dump_registers = dump_ak4396_registers;
|
||||
chip->model.device_config = PLAYBACK_0_TO_I2S |
|
||||
PLAYBACK_1_TO_SPDIF |
|
||||
CAPTURE_0_FROM_I2S_2 |
|
||||
CAPTURE_1_FROM_SPDIF;
|
||||
chip->model.function_flags = OXYGEN_FUNCTION_SPI |
|
||||
OXYGEN_FUNCTION_ENABLE_SPI_4_5;
|
||||
chip->model.dac_mclks = OXYGEN_MCLKS(256, 128, 128);
|
||||
chip->model.dac_volume_min = 0;
|
||||
chip->model.dac_volume_max = 127;
|
||||
chip->model.dac_tlv = eclaro_db_scale;
|
||||
break;
|
||||
case MODEL_FANTASIA:
|
||||
case MODEL_SERENADE:
|
||||
case MODEL_2CH_OUTPUT:
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user