diff --git a/arch/arm64/boot/dts/rockchip/rk3368-dram-default-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-dram-default-timing.dtsi new file mode 100644 index 000000000000..5e86bfa57175 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3368-dram-default-timing.dtsi @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include + +/ { + ddr_timing: ddr_timing { + compatible = "rockchip,ddr-timing"; + dram_spd_bin = ; + sr_idle = <1>; + pd_idle = <0x20>; + dram_dll_disb_freq = <300>; + phy_dll_disb_freq = <400>; + dram_odt_disb_freq = <333>; + phy_odt_disb_freq = <333>; + ddr3_drv = ; + ddr3_odt = ; + lpddr3_drv = ; + lpddr3_odt = ; + lpddr2_drv = ; /* lpddr2 not supported odt */ + phy_clk_drv = ; + phy_cmd_drv = ; + phy_dqs_drv = ; + phy_odt = ; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 614f64f13695..00e73d6b585a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -53,6 +53,8 @@ #include #include +#include "rk3368-dram-default-timing.dtsi" + / { compatible = "rockchip,rk3368"; interrupt-parent = <&gic>; @@ -1181,6 +1183,50 @@ u2phy_host: host-port { status = "disabled"; }; }; + + dfi: dfi { + compatible = "rockchip,rk3368-dfi"; + status = "disabled"; + }; + }; + + dmc: dmc { + compatible = "rockchip,rk3368-dmc"; + devfreq-events = <&dfi>; + clocks = <&cru SCLK_DDRCLK>, <&cru PCLK_DDRPHY>, + <&cru PCLK_DDRUPCTL>; + clock-names = "dmc_clk", "pclk_phy", "pclk_upctl"; + ddr_timing = <&ddr_timing>; + upthreshold = <50>; + downdifferential = <20>; + operating-points-v2 = <&dmc_opp_table>; + vop-dclk-mode = <0>; + status = "disabled"; + }; + + dmc_opp_table: opp_table2 { + compatible = "operating-points-v2"; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + opp-microvolt = <1100000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1100000>; + }; + opp-396000000 { + opp-hz = /bits/ 64 <396000000>; + opp-microvolt = <1100000>; + }; + opp-528000000 { + opp-hz = /bits/ 64 <528000000>; + opp-microvolt = <1100000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000>; + }; }; wdt: watchdog@ff800000 { diff --git a/include/dt-bindings/memory/rk3368-dram.h b/include/dt-bindings/memory/rk3368-dram.h new file mode 100644 index 000000000000..400f7b52a59f --- /dev/null +++ b/include/dt-bindings/memory/rk3368-dram.h @@ -0,0 +1,106 @@ +/* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H +#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H + +#define DDR3_DS_34ohm (0x2) +#define DDR3_DS_40ohm (0x0) + +#define LP2_DS_34ohm (0x1) +#define LP2_DS_40ohm (0x2) +#define LP2_DS_48ohm (0x3) +#define LP2_DS_60ohm (0x4) +#define LP2_DS_68_6ohm (0x5)/* optional */ +#define LP2_DS_80ohm (0x6) +#define LP2_DS_120ohm (0x7)/* optional */ + +#define LP3_DS_34ohm (0x1) +#define LP3_DS_40ohm (0x2) +#define LP3_DS_48ohm (0x3) +#define LP3_DS_60ohm (0x4) +#define LP3_DS_80ohm (0x6) +#define LP3_DS_34D_40U (0x9) +#define LP3_DS_40D_48U (0xa) +#define LP3_DS_34D_48U (0xb) + +#define DDR3_ODT_DIS (0) +#define DDR3_ODT_40ohm (0x44) +#define DDR3_ODT_60ohm (0x4) +#define DDR3_ODT_120ohm (0x40) + +#define LP3_ODT_DIS (0) +#define LP3_ODT_60ohm (1) +#define LP3_ODT_120ohm (2) +#define LP3_ODT_240ohm (3) + +#define PHY_RON_DISABLE (0) +#define PHY_RON_272ohm (1) +#define PHY_RON_135ohm (2) +#define PHY_RON_91ohm (3) +#define PHY_RON_38ohm (7) +#define PHY_RON_68ohm (8) +#define PHY_RON_54ohm (9) +#define PHY_RON_45ohm (10) +#define PHY_RON_39ohm (11) +#define PHY_RON_34ohm (12) +#define PHY_RON_30ohm (13) +#define PHY_RON_27ohm (14) +#define PHY_RON_25ohm (15) + +#define PHY_RTT_DISABLE (0) +#define PHY_RTT_1116ohm (1) +#define PHY_RTT_558ohm (2) +#define PHY_RTT_372ohm (3) +#define PHY_RTT_279ohm (4) +#define PHY_RTT_223ohm (5) +#define PHY_RTT_186ohm (6) +#define PHY_RTT_159ohm (7) +#define PHY_RTT_139ohm (8) +#define PHY_RTT_124ohm (9) +#define PHY_RTT_112ohm (10) +#define PHY_RTT_101ohm (11) +#define PHY_RTT_93ohm (12) +#define PHY_RTT_86ohm (13) +#define PHY_RTT_80ohm (14) +#define PHY_RTT_74ohm (15) + +#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H*/