From af14a79ae3e531ed80293e1adc2fea7541b58fc8 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Fri, 30 Sep 2022 15:18:16 +0800 Subject: [PATCH] clk: rockchip: rk3588: support aclk_vop_sub_src set parent to aclk_vop_div2_src Signed-off-by: Elaine Zhang Change-Id: If493c3918bd8022accf089d69cce4cb93326d9e5 --- drivers/clk/rockchip/clk-rk3588.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index 99bb5111d695..ee2826a70742 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -1890,6 +1890,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0, RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(52), 0, GFLAGS), + FACTOR(0, "aclk_vop_div2_src", "aclk_vop_root", 0, 1, 2), COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0, RK3588_CLKSEL_CON(110), 8, 2, MFLAGS, RK3588_CLKGATE_CON(52), 1, GFLAGS), @@ -1905,7 +1906,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE_NODIV(HCLK_VO1USB_TOP_ROOT, "hclk_vo1usb_top_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, RK3588_CLKSEL_CON(170), 6, 2, MFLAGS, RK3588_CLKGATE_CON(74), 2, GFLAGS), - MUX(ACLK_VOP_SUB_SRC, "aclk_vop_sub_src", aclk_vop_sub_src_p, CLK_SET_RATE_PARENT, + MUX(ACLK_VOP_SUB_SRC, "aclk_vop_sub_src", aclk_vop_sub_src_p, 0, RK3588_CLKSEL_CON(115), 9, 1, MFLAGS), GATE(PCLK_EDP0, "pclk_edp0", "pclk_vo1_root", 0, RK3588_CLKGATE_CON(62), 0, GFLAGS),