i2c: cadence: Relocate cdns_i2c_runtime_suspend and cdns_i2c_runtime_resume to facilitate atomic mode

Relocate cdns_i2c_runtime_suspend, cdns_i2c_runtime_resume and
cdns_i2c_init functions to avoid prototype statement in atomic
mode changes.

Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
Reviewed-by: Andi Shyti <andi.shyti@kernel.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
This commit is contained in:
Manikanta Guntupalli 2024-09-11 16:08:50 +05:30 committed by Andi Shyti
parent 2d5404caa8
commit ae8ec9dd19

View File

@ -228,6 +228,66 @@ struct cdns_platform_data {
#define to_cdns_i2c(_nb) container_of(_nb, struct cdns_i2c, \
clk_rate_change_nb)
/**
* cdns_i2c_init - Controller initialisation
* @id: Device private data structure
*
* Initialise the i2c controller.
*
*/
static void cdns_i2c_init(struct cdns_i2c *id)
{
cdns_i2c_writereg(id->ctrl_reg, CDNS_I2C_CR_OFFSET);
/*
* Cadence I2C controller has a bug wherein it generates
* invalid read transaction after HW timeout in master receiver mode.
* HW timeout is not used by this driver and the interrupt is disabled.
* But the feature itself cannot be disabled. Hence maximum value
* is written to this register to reduce the chances of error.
*/
cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET);
}
/**
* cdns_i2c_runtime_suspend - Runtime suspend method for the driver
* @dev: Address of the platform_device structure
*
* Put the driver into low power mode.
*
* Return: 0 always
*/
static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev)
{
struct cdns_i2c *xi2c = dev_get_drvdata(dev);
clk_disable(xi2c->clk);
return 0;
}
/**
* cdns_i2c_runtime_resume - Runtime resume
* @dev: Address of the platform_device structure
*
* Runtime resume callback.
*
* Return: 0 on success and error value on error
*/
static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev)
{
struct cdns_i2c *xi2c = dev_get_drvdata(dev);
int ret;
ret = clk_enable(xi2c->clk);
if (ret) {
dev_err(dev, "Cannot enable clock.\n");
return ret;
}
cdns_i2c_init(xi2c);
return 0;
}
/**
* cdns_i2c_clear_bus_hold - Clear bus hold bit
* @id: Pointer to driver data struct
@ -1158,23 +1218,6 @@ static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
}
}
/**
* cdns_i2c_runtime_suspend - Runtime suspend method for the driver
* @dev: Address of the platform_device structure
*
* Put the driver into low power mode.
*
* Return: 0 always
*/
static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev)
{
struct cdns_i2c *xi2c = dev_get_drvdata(dev);
clk_disable(xi2c->clk);
return 0;
}
static int __maybe_unused cdns_i2c_suspend(struct device *dev)
{
struct cdns_i2c *xi2c = dev_get_drvdata(dev);
@ -1187,49 +1230,6 @@ static int __maybe_unused cdns_i2c_suspend(struct device *dev)
return 0;
}
/**
* cdns_i2c_init - Controller initialisation
* @id: Device private data structure
*
* Initialise the i2c controller.
*
*/
static void cdns_i2c_init(struct cdns_i2c *id)
{
cdns_i2c_writereg(id->ctrl_reg, CDNS_I2C_CR_OFFSET);
/*
* Cadence I2C controller has a bug wherein it generates
* invalid read transaction after HW timeout in master receiver mode.
* HW timeout is not used by this driver and the interrupt is disabled.
* But the feature itself cannot be disabled. Hence maximum value
* is written to this register to reduce the chances of error.
*/
cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET);
}
/**
* cdns_i2c_runtime_resume - Runtime resume
* @dev: Address of the platform_device structure
*
* Runtime resume callback.
*
* Return: 0 on success and error value on error
*/
static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev)
{
struct cdns_i2c *xi2c = dev_get_drvdata(dev);
int ret;
ret = clk_enable(xi2c->clk);
if (ret) {
dev_err(dev, "Cannot enable clock.\n");
return ret;
}
cdns_i2c_init(xi2c);
return 0;
}
static int __maybe_unused cdns_i2c_resume(struct device *dev)
{
struct cdns_i2c *xi2c = dev_get_drvdata(dev);