From 635e425c0771ec2ba09b0ef69bb9814e2554374e Mon Sep 17 00:00:00 2001 From: Manuel Ebner Date: Thu, 3 Sep 2026 11:55:45 +0200 Subject: [PATCH 001/149] docs: dmaengine: Fix bracket Add missing ')' to sentence. Signed-off-by: Manuel Ebner Link: https://patch.msgid.link/20260903095545.729607-3-manuelebnerli@mailbox.org Signed-off-by: Vinod Koul --- Documentation/driver-api/dmaengine/provider.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/driver-api/dmaengine/provider.rst b/Documentation/driver-api/dmaengine/provider.rst index f4ed98f701c9..22d235fb478f 100644 --- a/Documentation/driver-api/dmaengine/provider.rst +++ b/Documentation/driver-api/dmaengine/provider.rst @@ -321,7 +321,7 @@ to use. - DESC_METADATA_CLIENT The metadata buffer is allocated/provided by the client driver and it is - attached (via the dmaengine_desc_attach_metadata() helper to the descriptor. + attached (via the dmaengine_desc_attach_metadata() helper) to the descriptor. From the DMA driver the following is expected for this mode: From e99f446c47318f4489eb3a675d53d4047951a6d0 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Tue, 14 Jul 2026 16:47:42 -0700 Subject: [PATCH 002/149] dmaengine: txx9dmac: use devm_platform_ioremap_resource() Replace the open-coded platform_get_resource() plus devm_request_mem_region() and devm_ioremap() sequence with a single devm_platform_ioremap_resource() call, which folds the resource lookup, region reservation and mapping into one step and returns an ERR_PTR on failure, checked with IS_ERR() and propagated via PTR_ERR(). This is behaviorally equivalent: the driver already reserved the region with devm_request_mem_region(), so the non-overlapping reg requirement of devm_platform_ioremap_resource() was already satisfied. The txx9dmac platform device (arch/mips/txx9/generic/setup.c) provides a single IORESOURCE_MEM window per DMAC instance, and the child txx9dmac-chan devices carry only IRQ resources, so no region conflict is introduced. Assisted-by: opencode:hy3-free Signed-off-by: Rosen Penev Reviewed-by: Frank Li Link: https://patch.msgid.link/20260714234742.908956-1-rosenp@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/txx9dmac.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c index 05622b68a936..6595a54a4b97 100644 --- a/drivers/dma/txx9dmac.c +++ b/drivers/dma/txx9dmac.c @@ -1167,26 +1167,20 @@ static void txx9dmac_chan_remove(struct platform_device *pdev) static int __init txx9dmac_probe(struct platform_device *pdev) { struct txx9dmac_platform_data *pdata = dev_get_platdata(&pdev->dev); - struct resource *io; struct txx9dmac_dev *ddev; + void __iomem *regs; u32 mcr; int err; - io = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!io) - return -EINVAL; + regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); ddev = devm_kzalloc(&pdev->dev, sizeof(*ddev), GFP_KERNEL); if (!ddev) return -ENOMEM; - if (!devm_request_mem_region(&pdev->dev, io->start, resource_size(io), - dev_name(&pdev->dev))) - return -EBUSY; - - ddev->regs = devm_ioremap(&pdev->dev, io->start, resource_size(io)); - if (!ddev->regs) - return -ENOMEM; + ddev->regs = regs; ddev->have_64bit_regs = pdata->have_64bit_regs; if (__is_dmac64(ddev)) ddev->descsize = sizeof(struct txx9dmac_hwdesc); From 62c267ce97444f8a381f2bb3cd5d534eb362c540 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Fri, 17 Jul 2026 22:30:10 -0700 Subject: [PATCH 003/149] dmaengine: fsl_raid: don't invoke client callback under desc_lock fsl_re_dequeue() holds re_chan->desc_lock while calling fsl_re_desc_done(), which synchronously invokes the DMA client completion callback via dmaengine_desc_get_callback_invoke(). If that callback submits new work (e.g. fsl_re_tx_submit()), it tries to reacquire the same desc_lock and deadlocks on the spinlock. Collect completed descriptors into a local list under the lock, then release the lock and invoke the callbacks before moving the descriptors to the ack queue. Fixes: ad80da658bbc ("dmaengine: Driver support for FSL RaidEngine device.") Assisted-by: opencode:hy3-free Signed-off-by: Rosen Penev Reviewed-by: Frank Li Link: https://patch.msgid.link/20260718053010.3074329-1-rosenp@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/fsl_raid.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/dma/fsl_raid.c b/drivers/dma/fsl_raid.c index 2d86f61105e5..bfaef6245695 100644 --- a/drivers/dma/fsl_raid.c +++ b/drivers/dma/fsl_raid.c @@ -162,6 +162,7 @@ static void fsl_re_dequeue(struct tasklet_struct *t) struct fsl_re_hw_desc *hwdesc; unsigned long flags; unsigned int count, oub_count; + LIST_HEAD(completed); int found; fsl_re_cleanup_descs(re_chan); @@ -182,8 +183,7 @@ static void fsl_re_dequeue(struct tasklet_struct *t) } if (found) { - fsl_re_desc_done(desc); - list_move_tail(&desc->node, &re_chan->ack_q); + list_move_tail(&desc->node, &completed); } else { dev_err(re_chan->dev, "found hwdesc not in sw queue, discard it\n"); @@ -196,6 +196,17 @@ static void fsl_re_dequeue(struct tasklet_struct *t) FSL_RE_RMVD_JOB(1)); } spin_unlock_irqrestore(&re_chan->desc_lock, flags); + + /* Invoke the client callbacks outside the channel lock. The callback + * may submit new work which re-acquires desc_lock, so holding it here + * would deadlock. + */ + list_for_each_entry_safe(desc, _desc, &completed, node) { + fsl_re_desc_done(desc); + spin_lock_irqsave(&re_chan->desc_lock, flags); + list_move_tail(&desc->node, &re_chan->ack_q); + spin_unlock_irqrestore(&re_chan->desc_lock, flags); + } } /* Per Job Ring interrupt handler */ From d805aa5b6088b193debabaa80cc0991bfa2bd057 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sat, 18 Jul 2026 16:52:27 -0700 Subject: [PATCH 004/149] dmaengine: fsl_raid: avoid free_q underflow in free_chan_resources fsl_re_free_chan_resources() loops alloc_count times calling list_first_entry() on free_q without checking whether the list still has entries. If descriptors remain un-acked or pending in submit_q / active_q / ack_q when the channel resources are freed, free_q becomes smaller than alloc_count and list_first_entry() returns the list head, causing list_del() to corrupt the list head and dereference a bogus pointer. Walk free_q with list_for_each_entry_safe() until it is empty, decrementing alloc_count per freed descriptor, instead of relying on the alloc_count count. Fixes: ad80da658bbc ("dmaengine: Driver support for FSL RaidEngine device.") Assisted-by: opencode:hy3-free Signed-off-by: Rosen Penev Reviewed-by: Frank Li Link: https://patch.msgid.link/20260718235227.385108-1-rosenp@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/fsl_raid.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/dma/fsl_raid.c b/drivers/dma/fsl_raid.c index bfaef6245695..e698c40b2ebc 100644 --- a/drivers/dma/fsl_raid.c +++ b/drivers/dma/fsl_raid.c @@ -614,18 +614,15 @@ static int fsl_re_alloc_chan_resources(struct dma_chan *chan) static void fsl_re_free_chan_resources(struct dma_chan *chan) { struct fsl_re_chan *re_chan; - struct fsl_re_desc *desc; + struct fsl_re_desc *desc, *_desc; re_chan = container_of(chan, struct fsl_re_chan, chan); - while (re_chan->alloc_count--) { - desc = list_first_entry(&re_chan->free_q, - struct fsl_re_desc, - node); - + list_for_each_entry_safe(desc, _desc, &re_chan->free_q, node) { list_del(&desc->node); dma_pool_free(re_chan->re_dev->cf_desc_pool, desc->cf_addr, desc->cf_paddr); kfree(desc); + re_chan->alloc_count--; } if (!list_empty(&re_chan->free_q)) From 68e26bc0b7b26c614639f1d13d160c51ff81799f Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 24 Jul 2026 00:17:39 +0300 Subject: [PATCH 005/149] dmaengine: pl08x: Create debugfs stats file under device folder If parent folder for a debug file is not set, then this file is created right in top debugfs mountpoint directory, which is undesired. However for every DMA controller device its dedicated folder below 'dmaengine' is created by dma_async_device_register(), and this particular folder is expected to store all device specific debug files. The new name "stats" is selected as the most popular debugfs file name found in other DMA controller device drivers, and the macro constant for file mode is replaced by the octal value. Signed-off-by: Vladimir Zapolskiy Reviewed-by: Frank Li Link: https://patch.msgid.link/20260723211739.289699-1-vz@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/amba-pl08x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c index 5e88fd44812d..543c2eb8cfa8 100644 --- a/drivers/dma/amba-pl08x.c +++ b/drivers/dma/amba-pl08x.c @@ -2500,8 +2500,8 @@ DEFINE_SHOW_ATTRIBUTE(pl08x_debugfs); static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) { /* Expose a simple debugfs interface to view all clocks */ - debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO, - NULL, pl08x, &pl08x_debugfs_fops); + debugfs_create_file("stats", 0444, pl08x->memcpy.dbg_dev_root, + pl08x, &pl08x_debugfs_fops); } #else From fdae0d0f096c92dd05d3722759fd614ea341e0dc Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Fri, 24 Jul 2026 15:59:58 -0700 Subject: [PATCH 006/149] dmaengine: at_hdmac: fix sparse '__iomem' cast warning in memset helpers Both atc_prep_dma_memset() and atc_prep_dma_memset_sg() declare vaddr as 'void __iomem *' but assign the return of dma_pool_alloc(), which returns 'void *' (not iomem memory). This causes sparse to warn about a cast removing the __iomem address space at the dereference site. The struct field memset_vaddr is also typed as 'int *', which is neither the type returned by dma_pool_alloc() nor the type used for the actual writes. Fix by declaring vaddr as 'u32 *' in both functions and changing memset_vaddr in struct at_desc from 'int *' to 'u32 *'. This matches the actual usage and eliminates the need for the (u32 *) cast. Fixes: 5d8c5bea0da9 ("dmaengine: at_hdmac: add COMPILE_TEST support") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202607231110.8MqNRj0Q-lkp@intel.com/ Assisted-by: opencode:big-pickle Signed-off-by: Rosen Penev Link: https://lore.kernel.org/oe-kbuild-all/202607231110.8MqNRj0Q-lkp@intel.com/ Reviewed-by: Frank Li Link: https://patch.msgid.link/20260724225958.43925-1-rosenp@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/at_hdmac.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c index e5b30a57c477..7c071e649637 100644 --- a/drivers/dma/at_hdmac.c +++ b/drivers/dma/at_hdmac.c @@ -244,7 +244,7 @@ struct at_desc { /* Memset temporary buffer */ bool memset_buffer; dma_addr_t memset_paddr; - int *memset_vaddr; + u32 *memset_vaddr; struct atdma_sg sg[] __counted_by(sglen); }; @@ -1097,7 +1097,7 @@ atc_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value, struct at_dma_chan *atchan = to_at_dma_chan(chan); struct at_dma *atdma = to_at_dma(chan->device); struct at_desc *desc; - void __iomem *vaddr; + u32 *vaddr; dma_addr_t paddr; char fill_pattern; int ret; @@ -1126,10 +1126,10 @@ atc_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value, /* Only the first byte of value is to be used according to dmaengine */ fill_pattern = (char)value; - *(u32*)vaddr = (fill_pattern << 24) | - (fill_pattern << 16) | - (fill_pattern << 8) | - fill_pattern; + *vaddr = (fill_pattern << 24) | + (fill_pattern << 16) | + (fill_pattern << 8) | + fill_pattern; desc = kzalloc_flex(*desc, sg, 1, GFP_ATOMIC); if (!desc) @@ -1168,7 +1168,7 @@ atc_prep_dma_memset_sg(struct dma_chan *chan, struct at_dma *atdma = to_at_dma(chan->device); struct at_desc *desc; struct scatterlist *sg; - void __iomem *vaddr; + u32 *vaddr; dma_addr_t paddr; size_t total_len = 0; int i; @@ -1189,7 +1189,7 @@ atc_prep_dma_memset_sg(struct dma_chan *chan, __func__); return NULL; } - *(u32*)vaddr = value; + *vaddr = value; desc = kzalloc_flex(*desc, sg, sg_len, GFP_ATOMIC); if (!desc) From d2d5b3dbd97e50261c1ad6a5f0eb09963f421848 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Sat, 25 Jul 2026 22:43:43 +0300 Subject: [PATCH 007/149] dmaengine: pl330: Move device specific debugfs file to its directory Under DMA framework every DMA device gets its dedicated directory dmaengine/$device_name in debugfs to store any supplementary data accessible from userspace. This change moves a single registered debugfs file of each PL330 device from debugfs top directory to the device specific directory, the file is renamed to "stats" to match the most popular name among all DMA device debugfs files. The S_IFREG mask is dropped as excessive for debugfs_create_file() function. Signed-off-by: Vladimir Zapolskiy Reviewed-by: Frank Li Link: https://patch.msgid.link/20260725194343.494973-1-vz@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/pl330.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c index 6214d9000db8..c2d0b473b8f4 100644 --- a/drivers/dma/pl330.c +++ b/drivers/dma/pl330.c @@ -2953,8 +2953,8 @@ DEFINE_SHOW_ATTRIBUTE(pl330_debugfs); static inline void init_pl330_debugfs(struct pl330_dmac *pl330) { - pl330->dbgfs = debugfs_create_file(dev_name(pl330->ddma.dev), - S_IFREG | 0444, NULL, pl330, + pl330->dbgfs = debugfs_create_file("stats", 0444, + pl330->ddma.dbg_dev_root, pl330, &pl330_debugfs_fops); } From be9bb4b4a3c4611ecfbe3d785894a09d331c6f25 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Sun, 26 Jul 2026 13:24:24 +0300 Subject: [PATCH 008/149] dmaengine: imx-sdma: Remove unused imx_dma_is_ipu() inline function The last user of the inline helper function imx_dma_is_ipu() was removed by commit bfac19e239a7 ("fbdev: mx3fb: Remove the driver") a few years ago, and this helper also can be safely removed. Signed-off-by: Vladimir Zapolskiy Reviewed-by: Frank Li Link: https://patch.msgid.link/20260726102424.547951-1-vz@kernel.org Signed-off-by: Vinod Koul --- include/linux/dma/imx-dma.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/include/linux/dma/imx-dma.h b/include/linux/dma/imx-dma.h index 76a8de9ae151..16e491f63883 100644 --- a/include/linux/dma/imx-dma.h +++ b/include/linux/dma/imx-dma.h @@ -57,11 +57,6 @@ struct imx_dma_data { int priority; }; -static inline int imx_dma_is_ipu(struct dma_chan *chan) -{ - return !strcmp(dev_name(chan->device->dev), "ipu-core"); -} - static inline int imx_dma_is_general_purpose(struct dma_chan *chan) { return !strcmp(chan->device->dev->driver->name, "imx-sdma") || From f472919f4c0650d7fb22bb230eacaada0c6ee951 Mon Sep 17 00:00:00 2001 From: Hongling Zeng Date: Mon, 27 Jul 2026 14:11:42 +0800 Subject: [PATCH 009/149] dmaengine: sun6i-dma: Fix use-after-free in error handling paths In error handling paths, the for loop frees v_lli in the loop body, then accesses v_lli->v_lli_next and v_lli->p_lli_next in the increment expression, which is use-after-free. Fix by refactoring the cleanup into a helper function sun6i_dma_free_desc() that saves both the next virtual and physical pointers before freeing the current node, preventing the use-after-free. Fixes: 555859308723 ("dmaengine: sun6i: Add driver for the Allwinner A31 DMA controller") Signed-off-by: Hongling Zeng Suggested-by: Jernej Skrabec Reviewed-by: Jernej Skrabec Reviewed-by: Frank Li Link: https://patch.msgid.link/20260727061142.44195-1-zenghongling@kylinos.cn Signed-off-by: Vinod Koul --- drivers/dma/sun6i-dma.c | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index f47a326dd7ff..c248c2dec956 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -406,16 +406,12 @@ static inline void sun6i_dma_dump_lli(struct sun6i_vchan *vchan, v_lli->len, v_lli->para, v_lli->p_lli_next); } -static void sun6i_dma_free_desc(struct virt_dma_desc *vd) +static void sun6i_dma_free_desc(struct sun6i_dma_dev *sdev, + struct sun6i_desc *txd) { - struct sun6i_desc *txd = to_sun6i_desc(&vd->tx); - struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vd->tx.chan->device); struct sun6i_dma_lli *v_lli, *v_next; dma_addr_t p_lli, p_next; - if (unlikely(!txd)) - return; - p_lli = txd->p_lli; v_lli = txd->v_lli; @@ -432,6 +428,17 @@ static void sun6i_dma_free_desc(struct virt_dma_desc *vd) kfree(txd); } +static void sun6i_dma_free_desc_virt(struct virt_dma_desc *vd) +{ + struct sun6i_desc *txd = to_sun6i_desc(&vd->tx); + struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vd->tx.chan->device); + + if (unlikely(!txd)) + return; + + sun6i_dma_free_desc(sdev, txd); +} + static int sun6i_dma_start_desc(struct sun6i_vchan *vchan) { struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vchan->vc.chan.device); @@ -788,10 +795,7 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg( return vchan_tx_prep(&vchan->vc, &txd->vd, flags); err_lli_free: - for (p_lli = txd->p_lli, v_lli = txd->v_lli; v_lli; - p_lli = v_lli->p_lli_next, v_lli = v_lli->v_lli_next) - dma_pool_free(sdev->pool, v_lli, p_lli); - kfree(txd); + sun6i_dma_free_desc(sdev, txd); return NULL; } @@ -869,10 +873,7 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_cyclic( return vchan_tx_prep(&vchan->vc, &txd->vd, flags); err_lli_free: - for (p_lli = txd->p_lli, v_lli = txd->v_lli; v_lli; - p_lli = v_lli->p_lli_next, v_lli = v_lli->v_lli_next) - dma_pool_free(sdev->pool, v_lli, p_lli); - kfree(txd); + sun6i_dma_free_desc(sdev, txd); return NULL; } @@ -1428,7 +1429,7 @@ static int sun6i_dma_probe(struct platform_device *pdev) struct sun6i_vchan *vchan = &sdc->vchans[i]; INIT_LIST_HEAD(&vchan->node); - vchan->vc.desc_free = sun6i_dma_free_desc; + vchan->vc.desc_free = sun6i_dma_free_desc_virt; vchan_init(&vchan->vc, &sdc->slave); } From 13f2d32a09609d083ace2d589fbdc68e970ae34c Mon Sep 17 00:00:00 2001 From: Hongling Zeng Date: Mon, 27 Jul 2026 14:17:05 +0800 Subject: [PATCH 010/149] dmaengine: at_hdmac: Fix use-after-free by proper tasklet cleanup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Current cleanup paths have a use-after-free vulnerability: - vchan_init() creates tasklets that access at_dma_chan memory - free_irq() only waits for IRQ handler, NOT tasklets - atdma is devm-managed and freed after probe/remove - Running tasklets accessing freed memory → Use-After-Free! The fix requires careful ordering: - free_irq() FIRST to synchronize with running IRQ handlers and prevent them from scheduling new tasklets - Then kill tasklets to wait for already-scheduled ones to complete - Only then free other resources Fixes: ac803b56860f ("dmaengine: at_hdmac: Convert driver to use virt-dma") Reported-by: sashiko-bot@kernel.org Closes: https://lore.kernel.org/all/20260604073945.54B311F00898@smtp.kernel.org/ Signed-off-by: Hongling Zeng Suggested-by: Frank Li Reviewed-by: Frank Li Link: https://patch.msgid.link/20260727061705.45169-1-zenghongling@kylinos.cn Signed-off-by: Vinod Koul --- drivers/dma/at_hdmac.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c index 7c071e649637..7fa6af973fd8 100644 --- a/drivers/dma/at_hdmac.c +++ b/drivers/dma/at_hdmac.c @@ -1940,6 +1940,20 @@ static void at_dma_off(struct at_dma *atdma) cpu_relax(); } +static void at_dma_cleanup_channels(struct at_dma *atdma) +{ + struct dma_chan *chan, *_chan; + int i = 0; + + list_for_each_entry_safe(chan, _chan, &atdma->dma_device.channels, + device_node) { + /* Disable interrupts */ + atc_disable_chan_irq(atdma, i++); + tasklet_kill(&to_at_dma_chan(chan)->vc.task); + list_del(&chan->device_node); + } +} + static int __init at_dma_probe(struct platform_device *pdev) { struct at_dma *atdma; @@ -2105,6 +2119,8 @@ static int __init at_dma_probe(struct platform_device *pdev) err_of_dma_controller_register: dma_async_device_unregister(&atdma->dma_device); err_dma_async_device_register: + disable_irq(platform_get_irq(pdev, 0)); + at_dma_cleanup_channels(atdma); dma_pool_destroy(atdma->memset_pool); err_memset_pool_create: dma_pool_destroy(atdma->lli_pool); @@ -2118,23 +2134,17 @@ static int __init at_dma_probe(struct platform_device *pdev) static void at_dma_remove(struct platform_device *pdev) { struct at_dma *atdma = platform_get_drvdata(pdev); - struct dma_chan *chan, *_chan; at_dma_off(atdma); if (pdev->dev.of_node) of_dma_controller_free(pdev->dev.of_node); dma_async_device_unregister(&atdma->dma_device); - dma_pool_destroy(atdma->memset_pool); - dma_pool_destroy(atdma->lli_pool); free_irq(platform_get_irq(pdev, 0), atdma); - list_for_each_entry_safe(chan, _chan, &atdma->dma_device.channels, - device_node) { - /* Disable interrupts */ - atc_disable_chan_irq(atdma, chan->chan_id); - list_del(&chan->device_node); - } + at_dma_cleanup_channels(atdma); + dma_pool_destroy(atdma->memset_pool); + dma_pool_destroy(atdma->lli_pool); clk_disable_unprepare(atdma->clk); } From 97e1f00b7bca84c0b7094f65533cb353adba66f2 Mon Sep 17 00:00:00 2001 From: Hongling Zeng Date: Mon, 27 Jul 2026 14:29:17 +0800 Subject: [PATCH 011/149] dmaengine: at_hdmac: Use stored IRQ in error path When request_irq() succeeds but a later error occurs in at_dma_probe(), the error handling path attempts to free the IRQ by calling platform_get_irq() again instead of using the already stored IRQ number in the local variable 'irq'. Use the stored 'irq' variable directly in free_irq() to make the code clearer and eliminate smatch warnings about potential IRQ leaks. While platform_get_irq() is deterministic, using the stored value makes the error handling more robust against future code changes and clearly shows the relationship between request_irq() and free_irq(). Reviewed-by: Frank Li Signed-off-by: Hongling Zeng Link: https://patch.msgid.link/20260727062917.46905-1-zenghongling@kylinos.cn Signed-off-by: Vinod Koul --- drivers/dma/at_hdmac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c index 7fa6af973fd8..f4d0c72787d1 100644 --- a/drivers/dma/at_hdmac.c +++ b/drivers/dma/at_hdmac.c @@ -2125,7 +2125,7 @@ static int __init at_dma_probe(struct platform_device *pdev) err_memset_pool_create: dma_pool_destroy(atdma->lli_pool); err_desc_pool_create: - free_irq(platform_get_irq(pdev, 0), atdma); + free_irq(irq, atdma); err_irq: clk_disable_unprepare(atdma->clk); return err; From f10d96b1c549a2f43506e9bf847196839808b8dc Mon Sep 17 00:00:00 2001 From: Myeonghun Pak Date: Wed, 5 Aug 2026 00:39:24 +0900 Subject: [PATCH 012/149] dmaengine: mediatek: hsdma: fix runtime PM leak on init failure mtk_hsdma_hw_init() enables runtime PM and gets a runtime PM reference before enabling the HSDMA clock. It currently ignores failures from pm_runtime_get_sync(); if runtime resume fails, the usage count remains held. If clk_prepare_enable() then fails, the usage count remains held. Use devm_pm_runtime_enable() to manage runtime PM enablement, and use pm_runtime_resume_and_get() so resume failures do not leak the usage count. If clk_prepare_enable() fails after a successful runtime resume, drop the runtime PM reference before returning. The probe path also ignores the return value from mtk_hsdma_hw_init(), so a failed hardware init can continue as a successful probe. Propagate mtk_hsdma_hw_init() failures from probe, while keeping a separate unwind label so mtk_hsdma_hw_deinit() is only called after hardware init succeeds. Fixes: 548c4597e984 ("dmaengine: mediatek: Add MediaTek High-Speed DMA controller for MT7622 and MT7623 SoC") Co-developed-by: Ijae Kim Signed-off-by: Ijae Kim Signed-off-by: Myeonghun Pak Reviewed-by: Frank Li Link: https://patch.msgid.link/20260804153924.49627-1-mhun512@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/mediatek/mtk-hsdma.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/dma/mediatek/mtk-hsdma.c b/drivers/dma/mediatek/mtk-hsdma.c index a43412ff5edd..27cb370106c7 100644 --- a/drivers/dma/mediatek/mtk-hsdma.c +++ b/drivers/dma/mediatek/mtk-hsdma.c @@ -848,17 +848,27 @@ static int mtk_hsdma_hw_init(struct mtk_hsdma_device *hsdma) { int err; - pm_runtime_enable(hsdma2dev(hsdma)); - pm_runtime_get_sync(hsdma2dev(hsdma)); + err = devm_pm_runtime_enable(hsdma2dev(hsdma)); + if (err) + return err; + + err = pm_runtime_resume_and_get(hsdma2dev(hsdma)); + if (err < 0) + return err; err = clk_prepare_enable(hsdma->clk); if (err) - return err; + goto err_put_pm; mtk_dma_write(hsdma, MTK_HSDMA_INT_ENABLE, 0); mtk_dma_write(hsdma, MTK_HSDMA_GLO, MTK_HSDMA_GLO_DEFAULT); return 0; + +err_put_pm: + pm_runtime_put_sync(hsdma2dev(hsdma)); + + return err; } static int mtk_hsdma_hw_deinit(struct mtk_hsdma_device *hsdma) @@ -868,7 +878,6 @@ static int mtk_hsdma_hw_deinit(struct mtk_hsdma_device *hsdma) clk_disable_unprepare(hsdma->clk); pm_runtime_put_sync(hsdma2dev(hsdma)); - pm_runtime_disable(hsdma2dev(hsdma)); return 0; } @@ -983,7 +992,9 @@ static int mtk_hsdma_probe(struct platform_device *pdev) goto err_unregister; } - mtk_hsdma_hw_init(hsdma); + err = mtk_hsdma_hw_init(hsdma); + if (err) + goto err_free; err = devm_request_irq(&pdev->dev, hsdma->irq, mtk_hsdma_irq, 0, @@ -991,7 +1002,7 @@ static int mtk_hsdma_probe(struct platform_device *pdev) if (err) { dev_err(&pdev->dev, "request_irq failed with err %d\n", err); - goto err_free; + goto err_deinit; } platform_set_drvdata(pdev, hsdma); @@ -1000,8 +1011,9 @@ static int mtk_hsdma_probe(struct platform_device *pdev) return 0; -err_free: +err_deinit: mtk_hsdma_hw_deinit(hsdma); +err_free: of_dma_controller_free(pdev->dev.of_node); err_unregister: dma_async_device_unregister(dd); From 4a1a2d8b8529cc569b769b92fcd71c53805cbeb2 Mon Sep 17 00:00:00 2001 From: Ruoyu Wang Date: Thu, 13 Aug 2026 23:31:43 +0800 Subject: [PATCH 013/149] dmaengine: img-mdc: Fix runtime PM usage counter leak pm_runtime_get_sync() leaves the IMG MDC device's usage counter incremented when runtime resume fails. mdc_alloc_chan_resources() returns that error to the DMA core, so the channel's client count is not incremented and mdc_free_chan_resources() is not called to drop the reference. Repeated allocation attempts can therefore accumulate usage references and prevent runtime suspend. Use pm_runtime_resume_and_get() so a failed resume does not retain a usage reference while successful allocations remain paired with mdc_free_chan_resources(). DMA core only treats negative return values as allocation failures, so the helper's zero success return preserves behavior. This issue was found by a static analysis checker and confirmed by manual source review. Fixes: 56d355e6f586 ("dmaengine: img-mdc: Add runtime PM") Signed-off-by: Ruoyu Wang Reviewed-by: Frank Li Link: https://patch.msgid.link/20260813153143.3953303-1-ruoyuw560@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/img-mdc-dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/img-mdc-dma.c b/drivers/dma/img-mdc-dma.c index b3765ba15803..a3192d49b6c8 100644 --- a/drivers/dma/img-mdc-dma.c +++ b/drivers/dma/img-mdc-dma.c @@ -738,7 +738,7 @@ static int mdc_alloc_chan_resources(struct dma_chan *chan) struct mdc_chan *mchan = to_mdc_chan(chan); struct device *dev = mdma2dev(mchan->mdma); - return pm_runtime_get_sync(dev); + return pm_runtime_resume_and_get(dev); } static void mdc_free_chan_resources(struct dma_chan *chan) From f2f44b952ea6e0c600e92ea21fcaa83cafeedf6e Mon Sep 17 00:00:00 2001 From: Golla Nagendra Date: Fri, 14 Aug 2026 10:26:09 +0530 Subject: [PATCH 014/149] dmaengine: zynqmp_dma: Fix PM rollback on sw_desc_pool alloc failure If sw_desc_pool allocation fails after pm_runtime_resume_and_get() succeeds in zynqmp_dma_alloc_chan_resources(), the error path returns without dropping the runtime PM reference. Route that failure path through err_pm so the runtime PM reference is balanced before returning the error. Fixes: 8982d48af36d ("dmaengine: zynqmp_dma: Fix PM reference leak in zynqmp_dma_alloc_chan_resourc()") Signed-off-by: Golla Nagendra Reviewed-by: Frank Li Link: https://patch.msgid.link/20260814045616.1661199-2-nagendra.golla@amd.com Signed-off-by: Vinod Koul --- drivers/dma/xilinx/zynqmp_dma.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/dma/xilinx/zynqmp_dma.c b/drivers/dma/xilinx/zynqmp_dma.c index 2b03584102ac..3a4deab0593c 100644 --- a/drivers/dma/xilinx/zynqmp_dma.c +++ b/drivers/dma/xilinx/zynqmp_dma.c @@ -483,8 +483,10 @@ static int zynqmp_dma_alloc_chan_resources(struct dma_chan *dchan) return ret; chan->sw_desc_pool = kzalloc_objs(*desc, ZYNQMP_DMA_NUM_DESCS); - if (!chan->sw_desc_pool) - return -ENOMEM; + if (!chan->sw_desc_pool) { + ret = -ENOMEM; + goto err_pm; + } chan->idle = true; chan->desc_free_cnt = ZYNQMP_DMA_NUM_DESCS; @@ -516,6 +518,10 @@ static int zynqmp_dma_alloc_chan_resources(struct dma_chan *dchan) } return ZYNQMP_DMA_NUM_DESCS; + +err_pm: + pm_runtime_put_autosuspend(chan->dev); + return ret; } /** From 4ea99b14b3bd955d768666941e2e03ba186b52f5 Mon Sep 17 00:00:00 2001 From: Golla Nagendra Date: Fri, 14 Aug 2026 10:26:10 +0530 Subject: [PATCH 015/149] dmaengine: zynqmp_dma: Free sw_desc_pool on desc_pool_v alloc failure In zynqmp_dma_alloc_chan_resources(), sw_desc_pool is allocated before desc_pool_v. If dma_alloc_coherent() for desc_pool_v fails, the function currently exits through the runtime PM rollback path but leaves the already allocated sw_desc_pool behind. Add a dedicated err_free_sw_desc_pool label for the desc_pool_v failure path, free sw_desc_pool there, then fall through to err_pm for pm_runtime_put_autosuspend(). This keeps the error unwind symmetric and avoids leaking the software descriptor pool on coherent descriptor allocation failure. Fixes: b0cc417c1637 ("dmaengine: Add Xilinx zynqmp dma engine driver support") Signed-off-by: Golla Nagendra Reviewed-by: Frank Li Link: https://patch.msgid.link/20260814045616.1661199-3-nagendra.golla@amd.com Signed-off-by: Vinod Koul --- drivers/dma/xilinx/zynqmp_dma.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/dma/xilinx/zynqmp_dma.c b/drivers/dma/xilinx/zynqmp_dma.c index 3a4deab0593c..0d868181e6f4 100644 --- a/drivers/dma/xilinx/zynqmp_dma.c +++ b/drivers/dma/xilinx/zynqmp_dma.c @@ -504,8 +504,10 @@ static int zynqmp_dma_alloc_chan_resources(struct dma_chan *dchan) (2 * ZYNQMP_DMA_DESC_SIZE(chan) * ZYNQMP_DMA_NUM_DESCS), &chan->desc_pool_p, GFP_KERNEL); - if (!chan->desc_pool_v) - return -ENOMEM; + if (!chan->desc_pool_v) { + ret = -ENOMEM; + goto err_free_sw_desc_pool; + } for (i = 0; i < ZYNQMP_DMA_NUM_DESCS; i++) { desc = chan->sw_desc_pool + i; @@ -519,6 +521,9 @@ static int zynqmp_dma_alloc_chan_resources(struct dma_chan *dchan) return ZYNQMP_DMA_NUM_DESCS; +err_free_sw_desc_pool: + kfree(chan->sw_desc_pool); + chan->sw_desc_pool = NULL; err_pm: pm_runtime_put_autosuspend(chan->dev); return ret; From 0266dac57019201a14a81245d22750ab221d6c66 Mon Sep 17 00:00:00 2001 From: Golla Nagendra Date: Fri, 14 Aug 2026 10:26:11 +0530 Subject: [PATCH 016/149] dmaengine: zynqmp_dma: Fix chan probe/remove error handling Keep the real platform_get_irq() error by returning ret directly, stage IRQ setup via a local ret variable, and assign chan->irq only after devm_request_irq() succeeds. Initialize chan->irq to -1 and initialize chan->common.device_node before it may be touched by teardown. In channel remove, free IRQ only for valid IRQ numbers and delete the channel node only when it is linked. Register the channel node only after successful IRQ setup. On channel probe failure in zynqmp_dma_probe(), route cleanup through the existing free_chan_resources teardown path. Fixes: b0cc417c1637 ("dmaengine: Add Xilinx zynqmp dma engine driver support") Signed-off-by: Golla Nagendra Reviewed-by: Frank Li Link: https://patch.msgid.link/20260814045616.1661199-4-nagendra.golla@amd.com Signed-off-by: Vinod Koul --- drivers/dma/xilinx/zynqmp_dma.c | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/drivers/dma/xilinx/zynqmp_dma.c b/drivers/dma/xilinx/zynqmp_dma.c index 0d868181e6f4..81a60bb1ced4 100644 --- a/drivers/dma/xilinx/zynqmp_dma.c +++ b/drivers/dma/xilinx/zynqmp_dma.c @@ -205,7 +205,7 @@ struct zynqmp_dma_desc_sw { * @desc_pool_p: Physical allocated descriptor base * @desc_free_cnt: Descriptor available count * @dev: The dma device - * @irq: Channel IRQ + * @irq: Linux IRQ number, or -1 when not registered * @is_dmacoherent: Tells whether dma operations are coherent or not * @tasklet: Cleanup work after irq * @idle : Channel status; @@ -896,10 +896,11 @@ static void zynqmp_dma_chan_remove(struct zynqmp_dma_chan *chan) if (!chan) return; - if (chan->irq) + if (chan->irq >= 0) devm_free_irq(chan->zdev->dev, chan->irq, chan); tasklet_kill(&chan->tasklet); - list_del(&chan->common.device_node); + if (!list_empty(&chan->common.device_node)) + list_del(&chan->common.device_node); } /** @@ -915,13 +916,14 @@ static int zynqmp_dma_chan_probe(struct zynqmp_dma_device *zdev, struct zynqmp_dma_chan *chan; struct device_node *node = pdev->dev.of_node; const struct zynqmp_dma_config *match_data; - int err; + int err, ret; chan = devm_kzalloc(zdev->dev, sizeof(*chan), GFP_KERNEL); if (!chan) return -ENOMEM; chan->dev = zdev->dev; chan->zdev = zdev; + chan->irq = -1; chan->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(chan->regs)) @@ -954,22 +956,26 @@ static int zynqmp_dma_chan_probe(struct zynqmp_dma_device *zdev, INIT_LIST_HEAD(&chan->pending_list); INIT_LIST_HEAD(&chan->done_list); INIT_LIST_HEAD(&chan->free_list); + INIT_LIST_HEAD(&chan->common.device_node); dma_cookie_init(&chan->common); chan->common.device = &zdev->common; - list_add_tail(&chan->common.device_node, &zdev->common.channels); - zynqmp_dma_init(chan); - chan->irq = platform_get_irq(pdev, 0); - if (chan->irq < 0) - return -ENXIO; - err = devm_request_irq(&pdev->dev, chan->irq, zynqmp_dma_irq_handler, 0, + ret = platform_get_irq(pdev, 0); + if (ret < 0) + return ret; + + err = devm_request_irq(&pdev->dev, ret, zynqmp_dma_irq_handler, 0, "zynqmp-dma", chan); if (err) return err; + chan->irq = ret; + chan->desc_size = sizeof(struct zynqmp_dma_desc_ll); chan->idle = true; + list_add_tail(&chan->common.device_node, &zdev->common.channels); + return 0; } @@ -1134,7 +1140,7 @@ static int zynqmp_dma_probe(struct platform_device *pdev) ret = zynqmp_dma_chan_probe(zdev, pdev); if (ret) { dev_err_probe(&pdev->dev, ret, "Probing channel failed\n"); - goto err_disable_pm; + goto free_chan_resources; } p->dst_addr_widths = BIT(zdev->chan->bus_width / 8); From 67bb1c0e00cfd6988bad3c29491b753945431e8a Mon Sep 17 00:00:00 2001 From: Golla Nagendra Date: Fri, 14 Aug 2026 10:26:12 +0530 Subject: [PATCH 017/149] dmaengine: zynqmp_dma: Fix stale kerneldoc comments Correct kerneldoc comments that no longer matched the code. Signed-off-by: Golla Nagendra Reviewed-by: Frank Li Link: https://patch.msgid.link/20260814045616.1661199-5-nagendra.golla@amd.com Signed-off-by: Vinod Koul --- drivers/dma/xilinx/zynqmp_dma.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/dma/xilinx/zynqmp_dma.c b/drivers/dma/xilinx/zynqmp_dma.c index 81a60bb1ced4..6c1fc2120186 100644 --- a/drivers/dma/xilinx/zynqmp_dma.c +++ b/drivers/dma/xilinx/zynqmp_dma.c @@ -208,7 +208,7 @@ struct zynqmp_dma_desc_sw { * @irq: Linux IRQ number, or -1 when not registered * @is_dmacoherent: Tells whether dma operations are coherent or not * @tasklet: Cleanup work after irq - * @idle : Channel status; + * @idle: Channel status * @desc_size: Size of the low level descriptor * @err: Channel has errors * @bus_width: Bus width @@ -435,7 +435,7 @@ zynqmp_dma_get_descriptor(struct zynqmp_dma_chan *chan) } /** - * zynqmp_dma_free_descriptor - Issue pending transactions + * zynqmp_dma_free_descriptor - Return a descriptor to the free pool * @chan: ZynqMP DMA channel pointer * @sdesc: Transaction descriptor pointer */ @@ -617,7 +617,6 @@ static void zynqmp_dma_start_transfer(struct zynqmp_dma_chan *chan) zynqmp_dma_start(chan); } - /** * zynqmp_dma_chan_desc_cleanup - Cleanup the completed descriptors * @chan: ZynqMP DMA channel @@ -908,7 +907,7 @@ static void zynqmp_dma_chan_remove(struct zynqmp_dma_chan *chan) * @zdev: Driver specific device structure * @pdev: Pointer to the platform_device structure * - * Return: '0' on success and failure value on error + * Return: 0 on success and negative error code on failure */ static int zynqmp_dma_chan_probe(struct zynqmp_dma_device *zdev, struct platform_device *pdev) @@ -1042,11 +1041,11 @@ static int __maybe_unused zynqmp_dma_runtime_suspend(struct device *dev) } /** - * zynqmp_dma_runtime_resume - Runtime suspend method for the driver + * zynqmp_dma_runtime_resume - Runtime resume method for the driver * @dev: Address of the device structure * - * Put the driver into low power mode. - * Return: 0 always + * Enable device clocks. + * Return: 0 on success and failure value on error */ static int __maybe_unused zynqmp_dma_runtime_resume(struct device *dev) { From 20070b2161aeddb43e9985f31b2cbc2d83ac7aed Mon Sep 17 00:00:00 2001 From: Golla Nagendra Date: Fri, 14 Aug 2026 10:26:13 +0530 Subject: [PATCH 018/149] dmaengine: zynqmp_dma: Fix minor whitespace Add a blank line in zynqmp_dma_chan_probe() to separate channel initialization from hardware setup. Signed-off-by: Golla Nagendra Reviewed-by: Frank Li Link: https://patch.msgid.link/20260814045616.1661199-6-nagendra.golla@amd.com Signed-off-by: Vinod Koul --- drivers/dma/xilinx/zynqmp_dma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dma/xilinx/zynqmp_dma.c b/drivers/dma/xilinx/zynqmp_dma.c index 6c1fc2120186..9a37003c7bd5 100644 --- a/drivers/dma/xilinx/zynqmp_dma.c +++ b/drivers/dma/xilinx/zynqmp_dma.c @@ -959,6 +959,7 @@ static int zynqmp_dma_chan_probe(struct zynqmp_dma_device *zdev, dma_cookie_init(&chan->common); chan->common.device = &zdev->common; + zynqmp_dma_init(chan); ret = platform_get_irq(pdev, 0); if (ret < 0) From bff5f96e79333f129b9ce1e177eb89e9a738a7fc Mon Sep 17 00:00:00 2001 From: Golla Nagendra Date: Fri, 14 Aug 2026 10:26:14 +0530 Subject: [PATCH 019/149] dmaengine: zynqmp_dma: Use of_dma_is_coherent for dma-coherent Use of_dma_is_coherent() instead of parsing the common dma-coherent device-tree property directly. Signed-off-by: Golla Nagendra Reviewed-by: Frank Li Link: https://patch.msgid.link/20260814045616.1661199-7-nagendra.golla@amd.com Signed-off-by: Vinod Koul --- drivers/dma/xilinx/zynqmp_dma.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/dma/xilinx/zynqmp_dma.c b/drivers/dma/xilinx/zynqmp_dma.c index 9a37003c7bd5..80cc5020128d 100644 --- a/drivers/dma/xilinx/zynqmp_dma.c +++ b/drivers/dma/xilinx/zynqmp_dma.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -947,7 +948,7 @@ static int zynqmp_dma_chan_probe(struct zynqmp_dma_device *zdev, if (match_data) chan->irq_offset = match_data->offset; - chan->is_dmacoherent = of_property_read_bool(node, "dma-coherent"); + chan->is_dmacoherent = of_dma_is_coherent(node); zdev->chan = chan; tasklet_setup(&chan->tasklet, zynqmp_dma_do_tasklet); spin_lock_init(&chan->lock); From cc38c812cb819257d37bfc28de613ce8fced3ca7 Mon Sep 17 00:00:00 2001 From: Golla Nagendra Date: Fri, 14 Aug 2026 10:26:15 +0530 Subject: [PATCH 020/149] dmaengine: zynqmp_dma: Reject zero-length memcpy transfers Zero-length prep_memcpy() needlessly consumed a descriptor slot. Reject zero-length memcpy at prep time and document the behaviour. Signed-off-by: Golla Nagendra Reviewed-by: Frank Li Link: https://patch.msgid.link/20260814045616.1661199-8-nagendra.golla@amd.com Signed-off-by: Vinod Koul --- drivers/dma/xilinx/zynqmp_dma.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/dma/xilinx/zynqmp_dma.c b/drivers/dma/xilinx/zynqmp_dma.c index 80cc5020128d..2f7588a7ee39 100644 --- a/drivers/dma/xilinx/zynqmp_dma.c +++ b/drivers/dma/xilinx/zynqmp_dma.c @@ -837,7 +837,8 @@ static void zynqmp_dma_synchronize(struct dma_chan *dchan) * @len: Transfer length * @flags: transfer ack flags * - * Return: Async transaction descriptor on success and NULL on failure + * Return: Async transaction descriptor on success and NULL on failure or + * zero length transfer */ static struct dma_async_tx_descriptor *zynqmp_dma_prep_memcpy( struct dma_chan *dchan, dma_addr_t dma_dst, @@ -852,6 +853,9 @@ static struct dma_async_tx_descriptor *zynqmp_dma_prep_memcpy( chan = to_chan(dchan); + if (!len) + return NULL; + desc_cnt = DIV_ROUND_UP(len, ZYNQMP_DMA_MAX_TRANS_LEN); spin_lock_irqsave(&chan->lock, irqflags); From 9267063f03b95d2686760ec1b018cca061dae297 Mon Sep 17 00:00:00 2001 From: Golla Nagendra Date: Fri, 14 Aug 2026 10:26:16 +0530 Subject: [PATCH 021/149] dmaengine: zynqmp_dma: Remove unused define and duplicate IRQ bit Remove the unused ZYNQMP_DMA_SRC_ISSUE_RST_VAL define. ZYNQMP_DMA_DST_DSCR_DONE was also set twice in the default interrupt enable mask; remove the duplicate bit. Signed-off-by: Golla Nagendra Reviewed-by: Frank Li Link: https://patch.msgid.link/20260814045616.1661199-9-nagendra.golla@amd.com Signed-off-by: Vinod Koul --- drivers/dma/xilinx/zynqmp_dma.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/dma/xilinx/zynqmp_dma.c b/drivers/dma/xilinx/zynqmp_dma.c index 2f7588a7ee39..d1ee51dde3d1 100644 --- a/drivers/dma/xilinx/zynqmp_dma.c +++ b/drivers/dma/xilinx/zynqmp_dma.c @@ -113,8 +113,7 @@ #define ZYNQMP_DMA_INT_DONE (ZYNQMP_DMA_DONE | ZYNQMP_DMA_DST_DSCR_DONE) #define ZYNQMP_DMA_INT_EN_DEFAULT_MASK (ZYNQMP_DMA_INT_DONE | \ ZYNQMP_DMA_INT_ERR | \ - ZYNQMP_DMA_INT_OVRFL | \ - ZYNQMP_DMA_DST_DSCR_DONE) + ZYNQMP_DMA_INT_OVRFL) /* Max number of descriptors per channel */ #define ZYNQMP_DMA_NUM_DESCS 32 @@ -129,8 +128,6 @@ /* Reset values for data attributes */ #define ZYNQMP_DMA_AXCACHE_VAL 0xF -#define ZYNQMP_DMA_SRC_ISSUE_RST_VAL 0x1F - #define ZYNQMP_DMA_IDS_DEFAULT_MASK 0xFFF /* Bus width in bits */ From d246fbf92ee22b84f13a339e629ad1dd7ad12f59 Mon Sep 17 00:00:00 2001 From: Sasha Finkelstein Date: Sat, 15 Aug 2026 12:41:38 +0200 Subject: [PATCH 022/149] dt-bindings: dma: apple,admac: Add M3 generation ADMACs The admacs seen in M3-generation SoCs (t603x, t8122) need additional configuration writes and so are getting a new compatible chain. Acked-by: Rob Herring (Arm) Reviewed-by: Joshua Peisach Reviewed-by: Janne Grunau Signed-off-by: Sasha Finkelstein Reviewed-by: Frank Li Link: https://patch.msgid.link/20260815-t603x-admac-v4-1-1149e342dcb0@chaosmail.tech Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/apple,admac.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/apple,admac.yaml b/Documentation/devicetree/bindings/dma/apple,admac.yaml index 6a200cbd7d02..5b4fd8348f99 100644 --- a/Documentation/devicetree/bindings/dma/apple,admac.yaml +++ b/Documentation/devicetree/bindings/dma/apple,admac.yaml @@ -10,7 +10,7 @@ description: | Apple's Audio DMA Controller (ADMAC) is used to fetch and store audio samples on SoCs from the "Apple Silicon" family. - The controller has been seen with up to 24 channels. Even-numbered channels + The controller has been seen with up to 32 channels. Even-numbered channels are TX-only, odd-numbered are RX-only. Individual channels are coupled to fixed device endpoints. @@ -33,6 +33,12 @@ properties: - apple,t8103-admac - apple,t8112-admac - const: apple,admac + - items: + - enum: + - apple,t6030-admac + - apple,t6031-admac + - const: apple,t8122-admac + - const: apple,t8122-admac reg: maxItems: 1 @@ -43,7 +49,7 @@ properties: Clients specify a single cell with channel number. dma-channels: - maximum: 24 + maximum: 32 interrupts: minItems: 4 From a1e078d3fca512fd77a531a1dfbcf5bf783e1ea5 Mon Sep 17 00:00:00 2001 From: Sasha Finkelstein Date: Sat, 15 Aug 2026 12:41:39 +0200 Subject: [PATCH 023/149] dmaengine: apple-admac: Add M3 generation ADMACs The admacs present on t8122 and t603x SoCs need additional writes in order to operate correctly. The exact purpose of this register is unknown Signed-off-by: Sasha Finkelstein Reviewed-by: Frank Li Link: https://patch.msgid.link/20260815-t603x-admac-v4-2-1149e342dcb0@chaosmail.tech Signed-off-by: Vinod Koul --- drivers/dma/apple-admac.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/dma/apple-admac.c b/drivers/dma/apple-admac.c index 14a5ee14a481..9a1c79c12268 100644 --- a/drivers/dma/apple-admac.c +++ b/drivers/dma/apple-admac.c @@ -39,10 +39,14 @@ #define FLAG_DESC_NOTIFY BIT(16) +#define T8122_UNK_28_VAL 0x200000 + #define REG_TX_START 0x0000 #define REG_TX_STOP 0x0004 #define REG_RX_START 0x0008 #define REG_RX_STOP 0x000c +#define REG_UNK_28 0x0028 +#define REG_UNK_2C 0x002c #define REG_IMPRINT 0x0090 #define REG_TX_SRAM_SIZE 0x0094 #define REG_RX_SRAM_SIZE 0x0098 @@ -85,6 +89,10 @@ struct admac_data; struct admac_tx; +struct admac_hw { + bool set_unk28; +}; + struct admac_chan { unsigned int no; struct admac_data *host; @@ -127,6 +135,7 @@ struct admac_data { struct mutex cache_alloc_lock; struct admac_sram txcache, rxcache; + const struct admac_hw *hw; int irq; int irq_index; int nchannels; @@ -747,6 +756,11 @@ static int admac_device_config(struct dma_chan *chan, u32 bus_width = readl_relaxed(ad->base + REG_BUS_WIDTH(adchan->no)) & ~(BUS_WIDTH_WORD_SIZE | BUS_WIDTH_FRAME_SIZE); + if (ad->hw->set_unk28) { + writel_relaxed(T8122_UNK_28_VAL, ad->base + REG_UNK_28); + writel_relaxed(T8122_UNK_28_VAL, ad->base + REG_UNK_2C); + } + switch (is_tx ? config->dst_addr_width : config->src_addr_width) { case DMA_SLAVE_BUSWIDTH_1_BYTE: wordsize = 1; @@ -800,11 +814,18 @@ static int admac_device_config(struct dma_chan *chan, return 0; } +static const struct admac_hw admac_base_hw = {}; + +static const struct admac_hw admac_t8122_hw = { + .set_unk28 = true, +}; + static int admac_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct admac_data *ad; struct dma_device *dma; + const struct admac_hw *hw; int nchannels; int err, irq, i; @@ -822,6 +843,8 @@ static int admac_probe(struct platform_device *pdev) ad->dev = &pdev->dev; ad->nchannels = nchannels; mutex_init(&ad->cache_alloc_lock); + hw = of_device_get_match_data(&pdev->dev); + ad->hw = hw ? hw : &admac_base_hw; /* * The controller has 4 IRQ outputs. Try them all until @@ -936,6 +959,7 @@ static void admac_remove(struct platform_device *pdev) } static const struct of_device_id admac_of_match[] = { + { .compatible = "apple,t8122-admac", .data = &admac_t8122_hw }, { .compatible = "apple,t8103-admac", }, { .compatible = "apple,admac", }, { } From c843417e6d6b55e24318e2edf405566e70786d3b Mon Sep 17 00:00:00 2001 From: Chaithanya Lagisetty Date: Sun, 16 Aug 2026 05:48:58 +0000 Subject: [PATCH 024/149] dmaengine: dw-axi-dmac: convert clock handling to clk_bulk API The driver managed its two mandatory clocks (core-clk and cfgr-clk) individually. This was error prone: axi_dma_resume() enabled cfgr_clk and then core_clk, and if enabling core_clk failed it returned the error without disabling cfgr_clk, leaving the clock refcount unbalanced. Convert the driver to the clk_bulk API. The two clocks are always acquired, enabled and disabled together, so a clk_bulk_data array expresses this naturally and shrinks the get/enable/disable paths. clk_bulk_prepare_enable() also unwinds any clock it already enabled when a later one fails, which fixes the resume imbalance. Fixes: 1fe20f1b8454 ("dmaengine: Introduce DW AXI DMAC driver") Signed-off-by: Chaithanya Lagisetty Link: https://lore.kernel.org/all/20260813105432.2577322-1-nagachaithanya9911@gmail.com/ Reviewed-by: Frank Li Link: https://patch.msgid.link/20260816054858.2667380-1-nagachaithanya9911@gmail.com Signed-off-by: Vinod Koul --- .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 28 ++++++++----------- drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 3 +- 2 files changed, 13 insertions(+), 18 deletions(-) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c index eebed2474210..9c21a5479437 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -1320,8 +1320,7 @@ static int axi_dma_suspend(struct axi_dma_chip *chip) axi_dma_irq_disable(chip); axi_dma_disable(chip); - clk_disable_unprepare(chip->core_clk); - clk_disable_unprepare(chip->cfgr_clk); + clk_bulk_disable_unprepare(ARRAY_SIZE(chip->clks), chip->clks); return 0; } @@ -1330,11 +1329,7 @@ static int axi_dma_resume(struct axi_dma_chip *chip) { int ret; - ret = clk_prepare_enable(chip->cfgr_clk); - if (ret < 0) - return ret; - - ret = clk_prepare_enable(chip->core_clk); + ret = clk_bulk_prepare_enable(ARRAY_SIZE(chip->clks), chip->clks); if (ret < 0) return ret; @@ -1524,13 +1519,11 @@ static int dw_probe(struct platform_device *pdev) chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2); - chip->core_clk = devm_clk_get(chip->dev, "core-clk"); - if (IS_ERR(chip->core_clk)) - return PTR_ERR(chip->core_clk); - - chip->cfgr_clk = devm_clk_get(chip->dev, "cfgr-clk"); - if (IS_ERR(chip->cfgr_clk)) - return PTR_ERR(chip->cfgr_clk); + chip->clks[0].id = "core-clk"; + chip->clks[1].id = "cfgr-clk"; + ret = devm_clk_bulk_get(chip->dev, ARRAY_SIZE(chip->clks), chip->clks); + if (ret) + return dev_err_probe(chip->dev, ret, "failed to get clocks\n"); ret = parse_device_properties(chip); if (ret) @@ -1640,10 +1633,13 @@ static void dw_remove(struct platform_device *pdev) struct dw_axi_dma *dw = chip->dw; struct axi_dma_chan *chan, *_chan; u32 i; + int ret; /* Enable clk before accessing to registers */ - clk_prepare_enable(chip->cfgr_clk); - clk_prepare_enable(chip->core_clk); + ret = clk_bulk_prepare_enable(ARRAY_SIZE(chip->clks), chip->clks); + if (ret) + dev_warn(chip->dev, "failed to enable clocks before remove: %d\n", + ret); axi_dma_irq_disable(chip); for (i = 0; i < dw->hdata->nr_channels; i++) { axi_chan_disable(&chip->dw->chan[i]); diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h index 67cc199e24d1..039316c42f05 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h @@ -69,8 +69,7 @@ struct axi_dma_chip { int irq[DMAC_MAX_CHANNELS]; void __iomem *regs; void __iomem *apb_regs; - struct clk *core_clk; - struct clk *cfgr_clk; + struct clk_bulk_data clks[2]; struct dw_axi_dma *dw; }; From b70ab341088b2114dcbc7be868588f3e97893e6a Mon Sep 17 00:00:00 2001 From: Srinivas Neeli Date: Tue, 18 Aug 2026 23:11:48 +0530 Subject: [PATCH 025/149] dmaengine: xilinx_dma: Fix MCDMA descriptor fields based on DMA direction The MCDMA BD format differs between memory-to-device (MM2S) and device-to-memory (S2MM) directions, but the driver was using generic 'status' and 'sideband_status' fields for both. This led to incorrect residue calculations when the hardware updates direction-specific fields. Refactor the descriptor structure to use unions with direction-specific field mappings, and update the residue calculation logic to select the correct status field based on DMA direction. This matches the hardware descriptor layout and fixes incorrect residue reporting. Fixes: 6ccd692bfb7f ("dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support") Reviewed-by: Radhey Shyam Pandey Signed-off-by: Srinivas Neeli Reviewed-by: Frank Li Link: https://patch.msgid.link/20260818174151.1608971-2-srinivas.neeli@amd.com Signed-off-by: Vinod Koul --- drivers/dma/xilinx/xilinx_dma.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index bef2b031dba1..2319101be778 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -223,6 +223,7 @@ #define XILINX_MCDMA_IRQ_ERR_MASK BIT(7) #define XILINX_MCDMA_BD_EOP BIT(30) #define XILINX_MCDMA_BD_SOP BIT(31) +#define XILINX_MCDMA_BD_HW_SIZE 64 /** * struct xilinx_vdma_desc_hw - Hardware Descriptor @@ -277,8 +278,10 @@ struct xilinx_axidma_desc_hw { * @buf_addr_msb: MSB of Buffer address @0x0C * @rsvd: Reserved field @0x10 * @control: Control Information field @0x14 - * @status: Status field @0x18 - * @sideband_status: Status of sideband signals @0x1C + * @mm2s_ctrl_sideband: Sideband control info for mm2s @0x18 + * @s2mm_status: Status field for s2mm @0x18 + * @mm2s_status: Status field for mm2s @0x1C + * @s2mm_sideband_status: Sideband status for s2mm @0x1C * @app: APP Fields @0x20 - 0x30 */ struct xilinx_aximcdma_desc_hw { @@ -288,10 +291,17 @@ struct xilinx_aximcdma_desc_hw { u32 buf_addr_msb; u32 rsvd; u32 control; - u32 status; - u32 sideband_status; + union { + u32 mm2s_ctrl_sideband; + u32 s2mm_status; + }; + union { + u32 mm2s_status; + u32 s2mm_sideband_status; + }; u32 app[XILINX_DMA_NUM_APP_WORDS]; } __aligned(64); +static_assert(sizeof(struct xilinx_aximcdma_desc_hw) == XILINX_MCDMA_BD_HW_SIZE); /** * struct xilinx_cdma_desc_hw - Hardware Descriptor @@ -1015,9 +1025,11 @@ static u32 xilinx_dma_get_residue(struct xilinx_dma_chan *chan, struct xilinx_aximcdma_tx_segment, node); aximcdma_hw = &aximcdma_seg->hw; - residue += - (aximcdma_hw->control & chan->xdev->max_buffer_len) - - (aximcdma_hw->status & chan->xdev->max_buffer_len); + residue += aximcdma_hw->control & chan->xdev->max_buffer_len; + if (chan->direction == DMA_DEV_TO_MEM) + residue -= aximcdma_hw->s2mm_status & chan->xdev->max_buffer_len; + else + residue -= aximcdma_hw->mm2s_status & chan->xdev->max_buffer_len; } } From 5b585cc8778185ae7a7c9903f8cd70d562b91282 Mon Sep 17 00:00:00 2001 From: Srinivas Neeli Date: Tue, 18 Aug 2026 23:11:49 +0530 Subject: [PATCH 026/149] dmaengine: xilinx_dma: Move descriptors to done list based on completion bit In AXI MCDMA, xilinx_dma_complete_descriptor() walks the channel's active_list and unconditionally moves every entry to the done_list. The MCDMA IOC interrupt handler invokes this function on every interrupt-on-completion, but with interrupt coalescing (IRQThreshold > 1) an IOC interrupt may fire after only a subset of the queued descriptors have actually been processed by the hardware. As a result, descriptors whose completion bit is not yet set in the BD status were being reported as completed to client drivers. Add a check for the descriptor completion bit before moving entries from the active list to the done list, using the appropriate direction- specific status field (s2mm_status for DMA_DEV_TO_MEM, mm2s_status for DMA_MEM_TO_DEV). This mirrors the AXIDMA fix in commit 7bcdaa658102 ("dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit"). Fixes: 6ccd692bfb7f ("dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support") Reviewed-by: Radhey Shyam Pandey Signed-off-by: Srinivas Neeli Reviewed-by: Frank Li Link: https://patch.msgid.link/20260818174151.1608971-3-srinivas.neeli@amd.com Signed-off-by: Vinod Koul --- drivers/dma/xilinx/xilinx_dma.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 2319101be778..506ce1ec29bc 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1784,6 +1784,17 @@ static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan) struct xilinx_axidma_tx_segment, node); if (!(seg->hw.status & XILINX_DMA_BD_COMP_MASK) && chan->has_sg) break; + } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { + struct xilinx_aximcdma_tx_segment *seg; + u32 status; + + seg = list_last_entry(&desc->segments, + struct xilinx_aximcdma_tx_segment, + node); + status = (chan->direction == DMA_DEV_TO_MEM) ? + seg->hw.s2mm_status : seg->hw.mm2s_status; + if (!(status & XILINX_DMA_BD_COMP_MASK)) + break; } if (chan->has_sg && chan->xdev->dma_config->dmatype != XDMA_TYPE_VDMA) From 5f677afc9567f311f34517560d0115cd956b2942 Mon Sep 17 00:00:00 2001 From: Suraj Gupta Date: Tue, 18 Aug 2026 23:11:51 +0530 Subject: [PATCH 027/149] dmaengine: xilinx_dma: Extend metadata handling for AXI DMA and MCDMA xilinx_dma_get_metadata_ptr() returns the AXI DMA APP words from the SOP descriptor in both directions. This is wrong for RX, where the hardware writes the APP words into the EOF descriptor. It also leaves AXI MCDMA without metadata support. Return the metadata from the SOP descriptor for TX and from the EOF descriptor for RX, matching where the hardware reads and writes the fields. For AXI DMA, expose the APP words (20 bytes). For AXI MCDMA, expose the control sideband, status, and APP fields (28 bytes). On TX the control sideband holds TID and TUSER configuration for the outgoing stream. On RX the sideband status holds the received TID, TDEST and TUSER from the incoming stream. The field layout differs between MM2S and S2MM, and the wider payload lets a consumer distinguish the two controllers. No in-tree consumer is affected. Read xlnx,axistream-connected for AXI MCDMA. Attach metadata_ops in xilinx_mcdma_prep_slave_sg() when an AXI4-Stream interface is present, so MCDMA clients use the metadata API the same way as AXI DMA clients. Signed-off-by: Suraj Gupta Co-developed-by: Srinivas Neeli Reviewed-by: Radhey Shyam Pandey Signed-off-by: Srinivas Neeli Reviewed-by: Frank Li Link: https://patch.msgid.link/20260818174151.1608971-5-srinivas.neeli@amd.com Signed-off-by: Vinod Koul --- drivers/dma/xilinx/xilinx_dma.c | 48 +++++++++++++++++++++++++++++---- 1 file changed, 43 insertions(+), 5 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 506ce1ec29bc..6ba3c172a006 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -651,17 +651,51 @@ static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan, * @tx: async transaction descriptor * @payload_len: metadata payload length * @max_len: metadata max length - * Return: The app field pointer. + * + * The metadata lives in the SOP descriptor for TX and the EOF descriptor for RX. + * Field order depends on dmatype and direction: + * + * AXI DMA: [0..] app + * AXI MCDMA (TX): [0] ctrl_sideband, [1] status, [2..] app + * AXI MCDMA (RX): [0] status, [1] sideband, [2..] app + * + * Return: Pointer to the first metadata word. */ static void *xilinx_dma_get_metadata_ptr(struct dma_async_tx_descriptor *tx, size_t *payload_len, size_t *max_len) { struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx); + struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan); + + if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { + struct xilinx_aximcdma_tx_segment *seg; + + if (chan->direction == DMA_DEV_TO_MEM) { + seg = list_last_entry(&desc->segments, + struct xilinx_aximcdma_tx_segment, node); + *max_len = *payload_len = sizeof(seg->hw.s2mm_status) + + sizeof(seg->hw.s2mm_sideband_status) + + sizeof(seg->hw.app); + return &seg->hw.s2mm_status; + } + seg = list_first_entry(&desc->segments, + struct xilinx_aximcdma_tx_segment, node); + *max_len = *payload_len = sizeof(seg->hw.mm2s_ctrl_sideband) + + sizeof(seg->hw.mm2s_status) + + sizeof(seg->hw.app); + return &seg->hw.mm2s_ctrl_sideband; + } + struct xilinx_axidma_tx_segment *seg; - *max_len = *payload_len = sizeof(u32) * XILINX_DMA_NUM_APP_WORDS; - seg = list_first_entry(&desc->segments, - struct xilinx_axidma_tx_segment, node); + if (chan->direction == DMA_DEV_TO_MEM) + seg = list_last_entry(&desc->segments, + struct xilinx_axidma_tx_segment, node); + else + seg = list_first_entry(&desc->segments, + struct xilinx_axidma_tx_segment, node); + + *max_len = *payload_len = sizeof(seg->hw.app); return seg->hw.app; } @@ -2639,6 +2673,9 @@ xilinx_mcdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, segment->hw.control |= XILINX_MCDMA_BD_EOP; } + if (chan->xdev->has_axistream_connected) + desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops; + return &desc->async_tx; error: @@ -3287,7 +3324,8 @@ static int xilinx_dma_probe(struct platform_device *pdev) dma_set_max_seg_size(xdev->dev, xdev->max_buffer_len); - if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { + if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA || + xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { xdev->has_axistream_connected = of_property_read_bool(node, "xlnx,axistream-connected"); } From bde5395c8f3f030c9b257355a022f30b5f464d6d Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 21 Aug 2026 02:34:30 +0900 Subject: [PATCH 028/149] dmaengine: dw-edma: Add dw_edma_core_ll_cur_idx() to get current LL entry index Add dw_edma_core_ll_cur_idx() to get the current LL entry index and prepare for dynamic addition of DMA requests while the DMA engine is running. Signed-off-by: Frank Li Reviewed-by: Frank Li Co-developed-by: Koichiro Den Signed-off-by: Koichiro Den Link: https://patch.msgid.link/20260820173439.2004068-2-den@valinux.co.jp Signed-off-by: Vinod Koul --- drivers/dma/dw-edma/dw-edma-core.h | 10 ++++++++++ drivers/dma/dw-edma/dw-edma-v0-core.c | 20 ++++++++++++++++++++ drivers/dma/dw-edma/dw-hdma-v0-core.c | 20 ++++++++++++++++++++ include/linux/dma/edma.h | 2 +- 4 files changed, 51 insertions(+), 1 deletion(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-edma-core.h index f6a5ad317567..e50fa7965778 100644 --- a/drivers/dma/dw-edma/dw-edma-core.h +++ b/drivers/dma/dw-edma/dw-edma-core.h @@ -138,6 +138,7 @@ struct dw_edma_core_ops { void (*ll_data)(struct dw_edma_chan *chan, struct dw_edma_burst *burst, u32 idx, bool cb, bool irq); void (*ll_link)(struct dw_edma_chan *chan, u32 idx, bool cb, u64 addr); + int (*ll_cur_idx)(struct dw_edma_chan *chan); void (*ch_doorbell)(struct dw_edma_chan *chan); void (*ch_enable)(struct dw_edma_chan *chan); void (*ch_config)(struct dw_edma_chan *chan); @@ -181,6 +182,15 @@ struct dw_edma_chan *dchan2dw_edma_chan(struct dma_chan *dchan) return vc2dw_edma_chan(to_virt_chan(dchan)); } +/* + * Return the current LL entry index. A negative value means that the channel + * context is not initialized or was lost after a link reset. + */ +static inline int dw_edma_core_ll_cur_idx(struct dw_edma_chan *chan) +{ + return chan->dw->core->ll_cur_idx(chan); +} + static inline u64 dw_edma_core_get_ll_paddr(struct dw_edma_chan *chan) { if (chan->dir == EDMA_DIR_WRITE) diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c index abc1bd4c0be2..cc8059182940 100644 --- a/drivers/dma/dw-edma/dw-edma-v0-core.c +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c @@ -616,6 +616,25 @@ static void dw_edma_v0_core_ch_doorbell(struct dw_edma_chan *chan) FIELD_PREP(EDMA_V0_DOORBELL_CH_MASK, chan->id)); } +static int dw_edma_v0_core_ll_cur_idx(struct dw_edma_chan *chan) +{ + u32 base, val; + + val = GET_CH_32(chan->dw, chan->dir, chan->id, llp.lsb); + base = lower_32_bits(dw_edma_core_get_ll_paddr(chan)); + + /* + * LL regions stay within one 4 GiB address window. Reject an all-ones + * MMIO value. If the low word is zero, use the high word to distinguish + * a nonzero boundary address from an unprogrammed all-zero context. + */ + if (val == U32_MAX || + (!val && !GET_CH_32(chan->dw, chan->dir, chan->id, llp.msb))) + return -EINVAL; + + return (val - base) / EDMA_LL_SZ; +} + /* eDMA debugfs callbacks */ static void dw_edma_v0_core_debugfs_on(struct dw_edma *dw) { @@ -650,6 +669,7 @@ static const struct dw_edma_core_ops dw_edma_v0_core = { .handle_int = dw_edma_v0_core_handle_int, .ll_data = dw_edma_v0_core_ll_data, .ll_link = dw_edma_v0_core_ll_link, + .ll_cur_idx = dw_edma_v0_core_ll_cur_idx, .ch_doorbell = dw_edma_v0_core_ch_doorbell, .ch_enable = dw_edma_v0_core_ch_enable, .ch_config = dw_edma_v0_core_ch_config, diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c index 36ee72efcd31..19da1c8fd615 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -384,6 +384,25 @@ static void dw_hdma_v0_core_ch_doorbell(struct dw_edma_chan *chan) SET_CH_32(dw, chan->dir, chan->id, doorbell, HDMA_V0_DOORBELL_START); } +static int dw_hdma_v0_core_ll_cur_idx(struct dw_edma_chan *chan) +{ + u32 base, val; + + val = GET_CH_32(chan->dw, chan->dir, chan->id, llp.lsb); + base = lower_32_bits(dw_edma_core_get_ll_paddr(chan)); + + /* + * LL regions stay within one 4 GiB address window. Reject an all-ones + * MMIO value. If the low word is zero, use the high word to distinguish + * a nonzero boundary address from an unprogrammed all-zero context. + */ + if (val == U32_MAX || + (!val && !GET_CH_32(chan->dw, chan->dir, chan->id, llp.msb))) + return -EINVAL; + + return (val - base) / EDMA_LL_SZ; +} + /* HDMA debugfs callbacks */ static void dw_hdma_v0_core_debugfs_on(struct dw_edma *dw) { @@ -406,6 +425,7 @@ static const struct dw_edma_core_ops dw_hdma_v0_core = { .non_ll_start = dw_hdma_v0_core_non_ll_start, .ll_data = dw_hdma_v0_core_ll_data, .ll_link = dw_hdma_v0_core_ll_link, + .ll_cur_idx = dw_hdma_v0_core_ll_cur_idx, .ch_doorbell = dw_hdma_v0_core_ch_doorbell, .ch_enable = dw_hdma_v0_core_ch_enable, .ch_config = dw_hdma_v0_core_ch_config, diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 3c8e2ef9dee0..a4e5aab8fddc 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -130,7 +130,7 @@ struct dw_edma_chip { u16 ll_wr_cnt; u16 ll_rd_cnt; - /* link list address */ + /* Linked-list regions must not cross a 4 GiB address boundary. */ struct dw_edma_region ll_region_wr[HDMA_MAX_WR_CH]; struct dw_edma_region ll_region_rd[HDMA_MAX_RD_CH]; From 3d50c87cead7c0181a6c766c1434036715d87efa Mon Sep 17 00:00:00 2001 From: Koichiro Den Date: Fri, 21 Aug 2026 02:34:31 +0900 Subject: [PATCH 029/149] dmaengine: dw-edma: Add dw_edma_core_ll_clear() to clear LL control-word Add a core operation for clearing the control word of one linked-list entry. A later patch uses the operation to invalidate stale CB when resetting a circular LL ring. No functional change. Reviewed-by: Frank Li Signed-off-by: Koichiro Den Link: https://patch.msgid.link/20260820173439.2004068-3-den@valinux.co.jp Signed-off-by: Vinod Koul --- drivers/dma/dw-edma/dw-edma-core.h | 6 ++++++ drivers/dma/dw-edma/dw-edma-v0-core.c | 16 ++++++++++++++++ drivers/dma/dw-edma/dw-hdma-v0-core.c | 16 ++++++++++++++++ 3 files changed, 38 insertions(+) diff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-edma-core.h index e50fa7965778..089f913fd247 100644 --- a/drivers/dma/dw-edma/dw-edma-core.h +++ b/drivers/dma/dw-edma/dw-edma-core.h @@ -138,6 +138,7 @@ struct dw_edma_core_ops { void (*ll_data)(struct dw_edma_chan *chan, struct dw_edma_burst *burst, u32 idx, bool cb, bool irq); void (*ll_link)(struct dw_edma_chan *chan, u32 idx, bool cb, u64 addr); + void (*ll_clear)(struct dw_edma_chan *chan, u32 idx); int (*ll_cur_idx)(struct dw_edma_chan *chan); void (*ch_doorbell)(struct dw_edma_chan *chan); void (*ch_enable)(struct dw_edma_chan *chan); @@ -255,6 +256,11 @@ dw_edma_core_ll_link(struct dw_edma_chan *chan, u32 idx, bool cb, u64 addr) chan->dw->core->ll_link(chan, idx, cb, addr); } +static inline void dw_edma_core_ll_clear(struct dw_edma_chan *chan, u32 idx) +{ + chan->dw->core->ll_clear(chan, idx); +} + static inline void dw_edma_core_ch_doorbell(struct dw_edma_chan *chan) { chan->dw->core->ch_doorbell(chan); diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c index cc8059182940..bb86d2f60ab5 100644 --- a/drivers/dma/dw-edma/dw-edma-v0-core.c +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c @@ -605,6 +605,21 @@ dw_edma_v0_core_ll_link(struct dw_edma_chan *chan, u32 idx, bool cb, u64 addr) dw_edma_v0_write_ll_link(chan, idx, control, addr); } +static void dw_edma_v0_core_ll_clear(struct dw_edma_chan *chan, u32 idx) +{ + ptrdiff_t ofs = idx * sizeof(struct dw_edma_v0_lli); + + if (chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) { + struct dw_edma_v0_lli *lli = chan->ll_region.vaddr.mem + ofs; + + lli->control = 0; + } else { + struct dw_edma_v0_lli __iomem *lli = chan->ll_region.vaddr.io + ofs; + + writel(0, &lli->control); + } +} + static void dw_edma_v0_core_ch_doorbell(struct dw_edma_chan *chan) { struct dw_edma *dw = chan->dw; @@ -669,6 +684,7 @@ static const struct dw_edma_core_ops dw_edma_v0_core = { .handle_int = dw_edma_v0_core_handle_int, .ll_data = dw_edma_v0_core_ll_data, .ll_link = dw_edma_v0_core_ll_link, + .ll_clear = dw_edma_v0_core_ll_clear, .ll_cur_idx = dw_edma_v0_core_ll_cur_idx, .ch_doorbell = dw_edma_v0_core_ch_doorbell, .ch_enable = dw_edma_v0_core_ch_enable, diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c index 19da1c8fd615..47d7a01658eb 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -374,6 +374,21 @@ dw_hdma_v0_core_ll_link(struct dw_edma_chan *chan, u32 idx, bool cb, u64 addr) dw_hdma_v0_write_ll_link(chan, idx, control, addr); } +static void dw_hdma_v0_core_ll_clear(struct dw_edma_chan *chan, u32 idx) +{ + ptrdiff_t ofs = idx * sizeof(struct dw_hdma_v0_lli); + + if (chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) { + struct dw_hdma_v0_lli *lli = chan->ll_region.vaddr.mem + ofs; + + lli->control = 0; + } else { + struct dw_hdma_v0_lli __iomem *lli = chan->ll_region.vaddr.io + ofs; + + writel(0, &lli->control); + } +} + static void dw_hdma_v0_core_ch_doorbell(struct dw_edma_chan *chan) { struct dw_edma *dw = chan->dw; @@ -425,6 +440,7 @@ static const struct dw_edma_core_ops dw_hdma_v0_core = { .non_ll_start = dw_hdma_v0_core_non_ll_start, .ll_data = dw_hdma_v0_core_ll_data, .ll_link = dw_hdma_v0_core_ll_link, + .ll_clear = dw_hdma_v0_core_ll_clear, .ll_cur_idx = dw_hdma_v0_core_ll_cur_idx, .ch_doorbell = dw_hdma_v0_core_ch_doorbell, .ch_enable = dw_hdma_v0_core_ch_enable, From 770792d7b8ef767a389fc386d7f0103828b34be4 Mon Sep 17 00:00:00 2001 From: Koichiro Den Date: Fri, 21 Aug 2026 02:34:32 +0900 Subject: [PATCH 030/149] dmaengine: dw-edma: Factor out linked-list transfer start Move linked-list programming into dw_edma_core_ll_start(). It can derive the first-batch state from desc->start_burst, so dw_edma_core_start() no longer needs a pass-through argument. No functional change. Reviewed-by: Frank Li Signed-off-by: Koichiro Den Link: https://patch.msgid.link/20260820173439.2004068-4-den@valinux.co.jp Signed-off-by: Vinod Koul --- drivers/dma/dw-edma/dw-edma-core.c | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c index 03b2c2188351..a6bb68ffdfe2 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -67,17 +67,11 @@ static void vchan_free_desc(struct virt_dma_desc *vdesc) kfree(vd2dw_edma_desc(vdesc)); } -static void dw_edma_core_start(struct dw_edma_desc *desc, bool first) +static void dw_edma_core_ll_start(struct dw_edma_desc *desc) { struct dw_edma_chan *chan = desc->chan; - size_t i = 0; - - if (chan->non_ll) { - chan->dw->core->non_ll_start(chan, &desc->burst[desc->start_burst]); - desc->done_burst = desc->start_burst; - desc->start_burst += 1; - return; - } + size_t i; + bool first = !desc->start_burst; for (i = 0; i + desc->start_burst < desc->nburst; i++) { u32 idx = i + desc->start_burst; @@ -101,6 +95,21 @@ static void dw_edma_core_start(struct dw_edma_desc *desc, bool first) dw_edma_core_ch_doorbell(chan); } +static void dw_edma_core_start(struct dw_edma_desc *desc) +{ + struct dw_edma_chan *chan = desc->chan; + + if (chan->non_ll) { + chan->dw->core->non_ll_start(chan, + &desc->burst[desc->start_burst]); + desc->done_burst = desc->start_burst; + desc->start_burst += 1; + return; + } + + dw_edma_core_ll_start(desc); +} + static int dw_edma_start_transfer(struct dw_edma_chan *chan) { struct dw_edma_desc *desc; @@ -114,7 +123,7 @@ static int dw_edma_start_transfer(struct dw_edma_chan *chan) if (!desc) return 0; - dw_edma_core_start(desc, !desc->start_burst); + dw_edma_core_start(desc); desc->cb = !desc->cb; From db79c4e264ef03beb5bd74a506d414fe11384643 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 21 Aug 2026 02:34:33 +0900 Subject: [PATCH 031/149] dmaengine: dw-edma: Make DMA link list work as a circular buffer The driver currently rebuilds the whole linked list for every transfer. Use it as a circular ring instead. Append entries at ll_head with the current cycle bit, and reserve the final entry for the link back to the start. Clear control words before first use so stale cycle bits cannot become valid entries. Reject rings without usable data slots and, until reclaim support lands, descriptors that exceed the usable ring capacity. Termination and abort can discard descriptors while ll_done still trails ll_head. Reset the ring after the channel has stopped so the next transfer does not inherit occupied slots. This prepares the driver for appending requests while the engine runs. Signed-off-by: Frank Li Reviewed-by: Frank Li Co-developed-by: Koichiro Den Signed-off-by: Koichiro Den Link: https://patch.msgid.link/20260820173439.2004068-5-den@valinux.co.jp Signed-off-by: Vinod Koul --- drivers/dma/dw-edma/dw-edma-core.c | 125 +++++++++++++++++++++++------ drivers/dma/dw-edma/dw-edma-core.h | 27 ++++++- 2 files changed, 125 insertions(+), 27 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c index a6bb68ffdfe2..1af262b6e881 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -51,13 +51,19 @@ dw_edma_alloc_desc(struct dw_edma_chan *chan, size_t nburst) { struct dw_edma_desc *desc; + /* + * For now, a descriptor that does not fit would stall the channel + * forever: reject it up front. + */ + if (!chan->non_ll && nburst > chan->ll_max - 1) + return NULL; + desc = kzalloc_flex(*desc, burst, nburst, GFP_NOWAIT); if (unlikely(!desc)) return NULL; desc->chan = chan; desc->nburst = nburst; - desc->cb = true; return desc; } @@ -67,30 +73,75 @@ static void vchan_free_desc(struct virt_dma_desc *vdesc) kfree(vd2dw_edma_desc(vdesc)); } +static void dw_edma_core_reset_ll(struct dw_edma_chan *chan) +{ + u32 i; + + chan->ll_head = 0; + chan->ll_done = 0; + /* Drop stale CB bits before reusing the circular LL ring. */ + for (i = 0; i < chan->ll_max; i++) + dw_edma_core_ll_clear(chan, i); + chan->cb = true; + + dw_edma_core_ll_link(chan, chan->ll_max, chan->cb, + chan->ll_region.paddr); + + dw_edma_core_ch_enable(chan); + chan->ll_valid = true; +} + +static u32 dw_edma_core_get_ll_dist(struct dw_edma_chan *chan, u32 from, u32 to) +{ + return (to + chan->ll_max - from) % chan->ll_max; +} + +static u32 dw_edma_core_get_used_num(struct dw_edma_chan *chan) +{ + return dw_edma_core_get_ll_dist(chan, chan->ll_done, chan->ll_head); +} + +static u32 dw_edma_core_get_free_num(struct dw_edma_chan *chan) +{ + /* Keep one data entry free so equal indices mean an empty ring. */ + return chan->ll_max - 1 - dw_edma_core_get_used_num(chan); +} + +static bool dw_edma_ll_pending(struct dw_edma_chan *chan) +{ + return chan->ll_head != chan->ll_done; +} + static void dw_edma_core_ll_start(struct dw_edma_desc *desc) { struct dw_edma_chan *chan = desc->chan; size_t i; - bool first = !desc->start_burst; + u32 free; - for (i = 0; i + desc->start_burst < desc->nburst; i++) { - u32 idx = i + desc->start_burst; + free = dw_edma_core_get_free_num(chan); + for (i = desc->start_burst; i < desc->nburst && free; i++, free--) { + /* + * Refresh the link element before filling the last data slot so + * the next lap has the updated CB value. + */ + if (chan->ll_head == chan->ll_max - 1) + dw_edma_core_ll_link(chan, chan->ll_max, chan->cb, + chan->ll_region.paddr); - if (i == chan->ll_max) - break; + dw_edma_core_ll_data(chan, &desc->burst[i], + chan->ll_head, chan->cb, + i == desc->nburst - 1 || free == 1); - dw_edma_core_ll_data(chan, &desc->burst[idx], - i, desc->cb, - idx == desc->nburst - 1 || i == chan->ll_max - 1); + chan->ll_head++; + + if (chan->ll_head == chan->ll_max) { + chan->cb = !chan->cb; + chan->ll_head = 0; + } } desc->done_burst = desc->start_burst; - desc->start_burst += i; - - dw_edma_core_ll_link(chan, i, desc->cb, chan->ll_region.paddr); - - if (first) - dw_edma_core_ch_enable(chan); + desc->start_burst = i; dw_edma_core_ch_doorbell(chan); } @@ -123,9 +174,10 @@ static int dw_edma_start_transfer(struct dw_edma_chan *chan) if (!desc) return 0; - dw_edma_core_start(desc); + if (!chan->non_ll && !chan->ll_valid) + dw_edma_core_reset_ll(chan); - desc->cb = !desc->cb; + dw_edma_core_start(desc); return 1; } @@ -159,6 +211,19 @@ static void dw_edma_terminate_all_descs(struct dw_edma_chan *chan) dw_edma_terminate_vdesc_list(&chan->vc.desc_submitted); } +/* Must be called with vc.lock held after the channel has stopped. */ +static void dw_edma_finish_termination(struct dw_edma_chan *chan) +{ + dw_edma_terminate_all_descs(chan); + + /* Preserve a clean ring; resync only if entries remain published. */ + if (!chan->non_ll && dw_edma_ll_pending(chan)) + dw_edma_core_reset_ll(chan); + + chan->request = EDMA_REQ_NONE; + chan->status = EDMA_ST_IDLE; +} + static void dw_edma_device_caps(struct dma_chan *dchan, struct dma_slave_caps *caps) { @@ -299,17 +364,15 @@ static int dw_edma_device_terminate_all(struct dma_chan *dchan) if (!chan->configured) { dw_edma_terminate_all_descs(chan); } else if (chan->status == EDMA_ST_PAUSE) { - dw_edma_terminate_all_descs(chan); - chan->status = EDMA_ST_IDLE; + dw_edma_finish_termination(chan); } else if (chan->status == EDMA_ST_IDLE) { - dw_edma_terminate_all_descs(chan); + dw_edma_finish_termination(chan); } else if (dw_edma_core_ch_status(chan) == DMA_COMPLETE) { /* * The channel is in a false BUSY state, probably didn't * receive or lost an interrupt */ - dw_edma_terminate_all_descs(chan); - chan->status = EDMA_ST_IDLE; + dw_edma_finish_termination(chan); } else if (chan->request > EDMA_REQ_PAUSE) { err = -EPERM; } else { @@ -645,6 +708,8 @@ static void dw_edma_done_interrupt(struct dw_edma_chan *chan) DMA_TRANS_NOERROR); list_del(&vd->node); vchan_cookie_complete(vd); + if (!chan->non_ll) + chan->ll_done = chan->ll_head; } if (chan->request == EDMA_REQ_PAUSE) { @@ -659,9 +724,7 @@ static void dw_edma_done_interrupt(struct dw_edma_chan *chan) break; case EDMA_REQ_STOP: - dw_edma_terminate_all_descs(chan); - chan->request = EDMA_REQ_NONE; - chan->status = EDMA_ST_IDLE; + dw_edma_finish_termination(chan); break; default: @@ -685,6 +748,8 @@ static void dw_edma_abort_interrupt(struct dw_edma_chan *chan) list_del(&vd->node); vchan_cookie_complete(vd); } + if (!chan->non_ll) + dw_edma_core_reset_ll(chan); chan->request = EDMA_REQ_NONE; chan->status = EDMA_ST_IDLE; spin_unlock_irqrestore(&chan->vc.lock, flags); @@ -872,6 +937,9 @@ static int dw_edma_alloc_chan_resources(struct dma_chan *dchan) if (chan->status != EDMA_ST_IDLE) return -EBUSY; + /* The hardware context may have been invalidated while unowned. */ + chan->ll_valid = false; + return 0; } @@ -963,6 +1031,13 @@ static int dw_edma_channel_setup(struct dw_edma *dw, u32 wr_alloc, u32 rd_alloc) else chan->ll_region = chip->ll_region_rd[chan->id]; + if (!chip->cfg_non_ll && chan->ll_region.sz < 3 * EDMA_LL_SZ) { + dev_err(dev, + "channel %s[%u]: LL region has fewer than 2 data entries\n", + str_write_read(chan->dir == EDMA_DIR_WRITE), + chan->id); + return -EINVAL; + } chan->ll_max = chan->ll_region.sz / EDMA_LL_SZ - 1; dev_vdbg(dev, "L. List:\tChannel %s[%u] max_cnt=%u\n", diff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-edma-core.h index 089f913fd247..761a5ab4bbb5 100644 --- a/drivers/dma/dw-edma/dw-edma-core.h +++ b/drivers/dma/dw-edma/dw-edma-core.h @@ -60,7 +60,6 @@ struct dw_edma_desc { size_t done_burst; size_t start_burst; - u8 cb; size_t nburst; struct dw_edma_burst burst[] __counted_by(nburst); }; @@ -72,8 +71,32 @@ struct dw_edma_chan { enum dw_edma_dir dir; u8 func_no; - u32 ll_max; + /* + * New LL entries are appended at ll_head. Entries between ll_done + * and ll_head, modulo the LL ring, are owned by DMA; the rest are + * owned by software. + * + * software-owned DMA-owned software-owned + * +---------------+-------------------+---------------+ + * ^ ^ ^ + * 0 ll_done ll_head + * + * The link entry points back to the region start. ll_head == ll_done + * means all entries are software-owned and previous DMA work is + * done. + * + * Software always keeps at least one free entry, so the ring is + * never completely DMA-owned. That keeps a hardware-reported physical + * LL index unique within the current ll_done..ll_head producer window. + */ + u32 ll_head; + u32 ll_done; + + u32 ll_max; /* Data entries */ struct dw_edma_region ll_region; /* Linked list */ + bool ll_valid; /* LL context programmed */ + + bool cb; struct msi_msg msi; From 9a8d4965cd9f4fe736cdf1f2c35f802ef36125f5 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 21 Aug 2026 02:34:34 +0900 Subject: [PATCH 032/149] dmaengine: dw-edma: Move callback result helper before LL helpers Move dw_hdma_set_callback_result() next to the descriptor helpers so linked-list completion and reset code can use it without a forward declaration. No functional change. Signed-off-by: Frank Li Reviewed-by: Frank Li Signed-off-by: Koichiro Den Link: https://patch.msgid.link/20260820173439.2004068-6-den@valinux.co.jp Signed-off-by: Vinod Koul --- drivers/dma/dw-edma/dw-edma-core.c | 50 +++++++++++++++--------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c index 1af262b6e881..ab8e343f0196 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -73,6 +73,31 @@ static void vchan_free_desc(struct virt_dma_desc *vdesc) kfree(vd2dw_edma_desc(vdesc)); } +static void dw_hdma_set_callback_result(struct virt_dma_desc *vd, + enum dmaengine_tx_result result) +{ + u32 residue = 0; + struct dw_edma_desc *desc; + struct dmaengine_result *res; + + if (!vd->tx.callback_result) + return; + + desc = vd2dw_edma_desc(vd); + if (desc) { + residue = desc->alloc_sz; + + if (result == DMA_TRANS_NOERROR) + residue -= desc->burst[desc->start_burst - 1].xfer_sz; + else if (desc->done_burst) + residue -= desc->burst[desc->done_burst - 1].xfer_sz; + } + + res = &vd->tx_result; + res->result = result; + res->residue = residue; +} + static void dw_edma_core_reset_ll(struct dw_edma_chan *chan) { u32 i; @@ -660,31 +685,6 @@ dw_edma_device_prep_interleaved_dma(struct dma_chan *dchan, return dw_edma_device_transfer(&xfer, dw_edma_device_get_config(dchan, NULL)); } -static void dw_hdma_set_callback_result(struct virt_dma_desc *vd, - enum dmaengine_tx_result result) -{ - u32 residue = 0; - struct dw_edma_desc *desc; - struct dmaengine_result *res; - - if (!vd->tx.callback_result) - return; - - desc = vd2dw_edma_desc(vd); - if (desc) { - residue = desc->alloc_sz; - - if (result == DMA_TRANS_NOERROR) - residue -= desc->burst[desc->start_burst - 1].xfer_sz; - else if (desc->done_burst) - residue -= desc->burst[desc->done_burst - 1].xfer_sz; - } - - res = &vd->tx_result; - res->result = result; - res->residue = residue; -} - static void dw_edma_done_interrupt(struct dw_edma_chan *chan) { struct dw_edma_desc *desc; From 8d249a120ce615804edab065ef4d157dbc92125f Mon Sep 17 00:00:00 2001 From: Koichiro Den Date: Fri, 21 Aug 2026 02:34:35 +0900 Subject: [PATCH 033/149] dmaengine: dw-edma: Dispatch DONE interrupts by channel request Prepare for a later patch that reclaims LL progress before request handling and can remove the last issued descriptor. Move the request switch outside the common descriptor check. Keep the existing per-request descriptor checks for now. That later patch removes them when STOP/PAUSE handling becomes independent of the descriptor list. No functional change. Reviewed-by: Frank Li Signed-off-by: Koichiro Den Link: https://patch.msgid.link/20260820173439.2004068-7-den@valinux.co.jp Signed-off-by: Vinod Koul --- drivers/dma/dw-edma/dw-edma-core.c | 58 +++++++++++++++--------------- 1 file changed, 30 insertions(+), 28 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c index ab8e343f0196..3c1f3f728875 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -697,39 +697,41 @@ static void dw_edma_done_interrupt(struct dw_edma_chan *chan) return; } - vd = vchan_next_desc(&chan->vc); - if (vd) { - switch (chan->request) { - case EDMA_REQ_NONE: - case EDMA_REQ_PAUSE: - desc = vd2dw_edma_desc(vd); - if (desc->start_burst >= desc->nburst) { - dw_hdma_set_callback_result(vd, - DMA_TRANS_NOERROR); - list_del(&vd->node); - vchan_cookie_complete(vd); - if (!chan->non_ll) - chan->ll_done = chan->ll_head; - } - - if (chan->request == EDMA_REQ_PAUSE) { - chan->request = EDMA_REQ_NONE; - chan->status = EDMA_ST_PAUSE; - break; - } - - /* Continue transferring if there are remaining chunks or issued requests. - */ - chan->status = dw_edma_start_transfer(chan) ? EDMA_ST_BUSY : EDMA_ST_IDLE; + switch (chan->request) { + case EDMA_REQ_NONE: + case EDMA_REQ_PAUSE: + vd = vchan_next_desc(&chan->vc); + if (!vd) break; - case EDMA_REQ_STOP: - dw_edma_finish_termination(chan); - break; + desc = vd2dw_edma_desc(vd); + if (desc->start_burst >= desc->nburst) { + dw_hdma_set_callback_result(vd, DMA_TRANS_NOERROR); + list_del(&vd->node); + vchan_cookie_complete(vd); + if (!chan->non_ll) + chan->ll_done = chan->ll_head; + } - default: + if (chan->request == EDMA_REQ_PAUSE) { + chan->request = EDMA_REQ_NONE; + chan->status = EDMA_ST_PAUSE; break; } + + chan->status = dw_edma_start_transfer(chan) ? EDMA_ST_BUSY : EDMA_ST_IDLE; + break; + + case EDMA_REQ_STOP: + vd = vchan_next_desc(&chan->vc); + if (!vd) + break; + + dw_edma_finish_termination(chan); + break; + + default: + break; } spin_unlock_irqrestore(&chan->vc.lock, flags); } From 080b8cfa01bc86e5c601ff625a34bec30cf08156 Mon Sep 17 00:00:00 2001 From: Koichiro Den Date: Fri, 21 Aug 2026 02:34:36 +0900 Subject: [PATCH 034/149] dmaengine: dw-edma: Centralize LL doorbell decisions LL fill currently rings the doorbell every time. A running eDMA or HDMA channel follows entries whose CB matches CCS without another kick. A channel stopped at a CB mismatch needs one. Move that decision to dw_edma_core_ch_maybe_doorbell(). It rings only for a BUSY LL channel with pending entries, no EDMA_REQ_STOP or EDMA_REQ_PAUSE. The BUSY check prevents EDMA_REQ_STOP completion from restarting terminated work. issue_pending() still publishes LL entries only from IDLE. A later patch allows live appends. Non-LL channels are unchanged. Reviewed-by: Frank Li Signed-off-by: Koichiro Den Link: https://patch.msgid.link/20260820173439.2004068-8-den@valinux.co.jp Signed-off-by: Vinod Koul --- drivers/dma/dw-edma/dw-edma-core.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c index 3c1f3f728875..5a8407ca68a2 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -167,8 +167,6 @@ static void dw_edma_core_ll_start(struct dw_edma_desc *desc) desc->done_burst = desc->start_burst; desc->start_burst = i; - - dw_edma_core_ch_doorbell(chan); } static void dw_edma_core_start(struct dw_edma_desc *desc) @@ -249,6 +247,16 @@ static void dw_edma_finish_termination(struct dw_edma_chan *chan) chan->status = EDMA_ST_IDLE; } +/* Must be called with vc.lock held. */ +static void dw_edma_core_ch_maybe_doorbell(struct dw_edma_chan *chan) +{ + if (chan->non_ll || chan->request != EDMA_REQ_NONE || + chan->status != EDMA_ST_BUSY || !dw_edma_ll_pending(chan)) + return; + + dw_edma_core_ch_doorbell(chan); +} + static void dw_edma_device_caps(struct dma_chan *dchan, struct dma_slave_caps *caps) { @@ -374,6 +382,7 @@ static int dw_edma_device_resume(struct dma_chan *dchan) chan->status = EDMA_ST_BUSY; if (!dw_edma_start_transfer(chan)) chan->status = EDMA_ST_IDLE; + dw_edma_core_ch_maybe_doorbell(chan); } return err; @@ -420,6 +429,7 @@ static void dw_edma_device_issue_pending(struct dma_chan *dchan) chan->status == EDMA_ST_IDLE) { chan->status = EDMA_ST_BUSY; dw_edma_start_transfer(chan); + dw_edma_core_ch_maybe_doorbell(chan); } spin_unlock_irqrestore(&chan->vc.lock, flags); } @@ -733,6 +743,8 @@ static void dw_edma_done_interrupt(struct dw_edma_chan *chan) default: break; } + dw_edma_core_ch_maybe_doorbell(chan); + spin_unlock_irqrestore(&chan->vc.lock, flags); } From 33ea2d4e681f31c736d272eaab0695afc8664b4b Mon Sep 17 00:00:00 2001 From: Koichiro Den Date: Fri, 21 Aug 2026 02:34:37 +0900 Subject: [PATCH 035/149] dmaengine: dw-edma: Prepare LL progress event handling A later patch records each observed LL event (STOP or PROGRESS) together with the LLP sample taken in the same interrupt-handler pass. It needs a provider operation to clear stale LL interrupt status before a channel restart. Add it. Centralize runtime request updates in dw_edma_set_request(). A later patch uses it to cancel a pending LL recheck when STOP or PAUSE changes the channel policy. Rename the existing workqueue event bits to distinguish them from provider IRQ events. No functional change. Reviewed-by: Frank Li Signed-off-by: Koichiro Den Link: https://patch.msgid.link/20260820173439.2004068-9-den@valinux.co.jp Signed-off-by: Vinod Koul --- drivers/dma/dw-edma/dw-edma-core.c | 35 ++++++++++++++++----------- drivers/dma/dw-edma/dw-edma-core.h | 6 +++++ drivers/dma/dw-edma/dw-edma-v0-core.c | 1 + drivers/dma/dw-edma/dw-hdma-v0-core.c | 1 + 4 files changed, 29 insertions(+), 14 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c index 5a8407ca68a2..bbfd82b12ab5 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -30,9 +30,9 @@ struct dw_edma_desc *vd2dw_edma_desc(struct virt_dma_desc *vd) return container_of(vd, struct dw_edma_desc, vd); } -enum dw_edma_irq_event { - DW_EDMA_IRQ_DONE = BIT(0), - DW_EDMA_IRQ_ABORT = BIT(1), +enum dw_edma_deferred_event { + DW_EDMA_DEFERRED_DONE = BIT(0), + DW_EDMA_DEFERRED_ABORT = BIT(1), }; static inline @@ -73,6 +73,13 @@ static void vchan_free_desc(struct virt_dma_desc *vdesc) kfree(vd2dw_edma_desc(vdesc)); } +/* Must be called with vc.lock held. */ +static void +dw_edma_set_request(struct dw_edma_chan *chan, enum dw_edma_request request) +{ + chan->request = request; +} + static void dw_hdma_set_callback_result(struct virt_dma_desc *vd, enum dmaengine_tx_result result) { @@ -243,7 +250,7 @@ static void dw_edma_finish_termination(struct dw_edma_chan *chan) if (!chan->non_ll && dw_edma_ll_pending(chan)) dw_edma_core_reset_ll(chan); - chan->request = EDMA_REQ_NONE; + dw_edma_set_request(chan, EDMA_REQ_NONE); chan->status = EDMA_ST_IDLE; } @@ -360,7 +367,7 @@ static int dw_edma_device_pause(struct dma_chan *dchan) else if (chan->request != EDMA_REQ_NONE) err = -EPERM; else - chan->request = EDMA_REQ_PAUSE; + dw_edma_set_request(chan, EDMA_REQ_PAUSE); return err; } @@ -410,10 +417,10 @@ static int dw_edma_device_terminate_all(struct dma_chan *dchan) } else if (chan->request > EDMA_REQ_PAUSE) { err = -EPERM; } else { - chan->request = EDMA_REQ_STOP; + dw_edma_set_request(chan, EDMA_REQ_STOP); } if (chan->status == EDMA_ST_IDLE) - chan->request = EDMA_REQ_NONE; + dw_edma_set_request(chan, EDMA_REQ_NONE); return err; } @@ -724,7 +731,7 @@ static void dw_edma_done_interrupt(struct dw_edma_chan *chan) } if (chan->request == EDMA_REQ_PAUSE) { - chan->request = EDMA_REQ_NONE; + dw_edma_set_request(chan, EDMA_REQ_NONE); chan->status = EDMA_ST_PAUSE; break; } @@ -764,7 +771,7 @@ static void dw_edma_abort_interrupt(struct dw_edma_chan *chan) } if (!chan->non_ll) dw_edma_core_reset_ll(chan); - chan->request = EDMA_REQ_NONE; + dw_edma_set_request(chan, EDMA_REQ_NONE); chan->status = EDMA_ST_IDLE; spin_unlock_irqrestore(&chan->vc.lock, flags); } @@ -778,15 +785,15 @@ static void dw_edma_irq_work(struct work_struct *work) do { events = atomic_xchg(&chan->irq_pending, 0); - if (events & DW_EDMA_IRQ_DONE) + if (events & DW_EDMA_DEFERRED_DONE) dw_edma_done_interrupt(chan); - if (events & DW_EDMA_IRQ_ABORT) + if (events & DW_EDMA_DEFERRED_ABORT) dw_edma_abort_interrupt(chan); } while (atomic_read(&chan->irq_pending)); } static void dw_edma_queue_irq_work(struct dw_edma_chan *chan, - enum dw_edma_irq_event event) + enum dw_edma_deferred_event event) { atomic_or(event, &chan->irq_pending); queue_work(chan->dw->wq, &chan->irq_work); @@ -794,12 +801,12 @@ static void dw_edma_queue_irq_work(struct dw_edma_chan *chan, static void dw_edma_done_interrupt_deferred(struct dw_edma_chan *chan) { - dw_edma_queue_irq_work(chan, DW_EDMA_IRQ_DONE); + dw_edma_queue_irq_work(chan, DW_EDMA_DEFERRED_DONE); } static void dw_edma_abort_interrupt_deferred(struct dw_edma_chan *chan) { - dw_edma_queue_irq_work(chan, DW_EDMA_IRQ_ABORT); + dw_edma_queue_irq_work(chan, DW_EDMA_DEFERRED_ABORT); } static void dw_edma_emul_irq_ack(struct irq_data *d) diff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-edma-core.h index 761a5ab4bbb5..8d993e8cccbb 100644 --- a/drivers/dma/dw-edma/dw-edma-core.h +++ b/drivers/dma/dw-edma/dw-edma-core.h @@ -163,6 +163,7 @@ struct dw_edma_core_ops { void (*ll_link)(struct dw_edma_chan *chan, u32 idx, bool cb, u64 addr); void (*ll_clear)(struct dw_edma_chan *chan, u32 idx); int (*ll_cur_idx)(struct dw_edma_chan *chan); + void (*ll_irq_clear)(struct dw_edma_chan *chan); void (*ch_doorbell)(struct dw_edma_chan *chan); void (*ch_enable)(struct dw_edma_chan *chan); void (*ch_config)(struct dw_edma_chan *chan); @@ -284,6 +285,11 @@ static inline void dw_edma_core_ll_clear(struct dw_edma_chan *chan, u32 idx) chan->dw->core->ll_clear(chan, idx); } +static inline void dw_edma_core_ll_irq_clear(struct dw_edma_chan *chan) +{ + chan->dw->core->ll_irq_clear(chan); +} + static inline void dw_edma_core_ch_doorbell(struct dw_edma_chan *chan) { chan->dw->core->ch_doorbell(chan); diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c index bb86d2f60ab5..9053354eda67 100644 --- a/drivers/dma/dw-edma/dw-edma-v0-core.c +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c @@ -686,6 +686,7 @@ static const struct dw_edma_core_ops dw_edma_v0_core = { .ll_link = dw_edma_v0_core_ll_link, .ll_clear = dw_edma_v0_core_ll_clear, .ll_cur_idx = dw_edma_v0_core_ll_cur_idx, + .ll_irq_clear = dw_edma_v0_core_clear_done_int, .ch_doorbell = dw_edma_v0_core_ch_doorbell, .ch_enable = dw_edma_v0_core_ch_enable, .ch_config = dw_edma_v0_core_ch_config, diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c index 47d7a01658eb..4acbace43519 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -442,6 +442,7 @@ static const struct dw_edma_core_ops dw_hdma_v0_core = { .ll_link = dw_hdma_v0_core_ll_link, .ll_clear = dw_hdma_v0_core_ll_clear, .ll_cur_idx = dw_hdma_v0_core_ll_cur_idx, + .ll_irq_clear = dw_hdma_v0_core_clear_done_int, .ch_doorbell = dw_hdma_v0_core_ch_doorbell, .ch_enable = dw_hdma_v0_core_ch_enable, .ch_config = dw_hdma_v0_core_ch_config, From 1f59dfa4c3344a9707115cf63bca647549c83dfd Mon Sep 17 00:00:00 2001 From: Koichiro Den Date: Fri, 21 Aug 2026 02:34:38 +0900 Subject: [PATCH 036/149] dmaengine: dw-edma: Prepare deferred IRQ reporting for LL events A later change serializes status capture, interrupt clear, and event recording against channel restart. It must also publish all causes observed for a channel in that critical section through one callback. Otherwise, the deferred worker can consume one cause before another from the same status pass is recorded. Replace the DONE and ABORT callback pair with one callback carrying an event bitmap. For now, map the bitmap back to the existing deferred DONE and ABORT work, so behavior remains unchanged. Also split DONE handling into a lock-taking wrapper and a vc.lock-held body. The later LL event path needs to validate its recorded event under vc.lock before running the existing DONE state machine. No functional change. Reviewed-by: Frank Li Signed-off-by: Koichiro Den Link: https://patch.msgid.link/20260820173439.2004068-10-den@valinux.co.jp Signed-off-by: Vinod Koul --- drivers/dma/dw-edma/dw-edma-core.c | 44 ++++++++++++++++----------- drivers/dma/dw-edma/dw-edma-core.h | 16 +++++++--- drivers/dma/dw-edma/dw-edma-v0-core.c | 6 ++-- drivers/dma/dw-edma/dw-hdma-v0-core.c | 6 ++-- 4 files changed, 44 insertions(+), 28 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c index bbfd82b12ab5..97de0ad4489a 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -702,17 +702,16 @@ dw_edma_device_prep_interleaved_dma(struct dma_chan *dchan, return dw_edma_device_transfer(&xfer, dw_edma_device_get_config(dchan, NULL)); } -static void dw_edma_done_interrupt(struct dw_edma_chan *chan) +/* Must be called with vc.lock held. */ +static void dw_edma_done_interrupt_locked(struct dw_edma_chan *chan) { struct dw_edma_desc *desc; struct virt_dma_desc *vd; - unsigned long flags; - spin_lock_irqsave(&chan->vc.lock, flags); - if (chan->status == EDMA_ST_PAUSE) { - spin_unlock_irqrestore(&chan->vc.lock, flags); + lockdep_assert_held(&chan->vc.lock); + + if (chan->status == EDMA_ST_PAUSE) return; - } switch (chan->request) { case EDMA_REQ_NONE: @@ -751,7 +750,14 @@ static void dw_edma_done_interrupt(struct dw_edma_chan *chan) break; } dw_edma_core_ch_maybe_doorbell(chan); +} +static void dw_edma_done_interrupt(struct dw_edma_chan *chan) +{ + unsigned long flags; + + spin_lock_irqsave(&chan->vc.lock, flags); + dw_edma_done_interrupt_locked(chan); spin_unlock_irqrestore(&chan->vc.lock, flags); } @@ -793,20 +799,24 @@ static void dw_edma_irq_work(struct work_struct *work) } static void dw_edma_queue_irq_work(struct dw_edma_chan *chan, - enum dw_edma_deferred_event event) + unsigned int events) { - atomic_or(event, &chan->irq_pending); + atomic_or(events, &chan->irq_pending); queue_work(chan->dw->wq, &chan->irq_work); } -static void dw_edma_done_interrupt_deferred(struct dw_edma_chan *chan) +static void dw_edma_record_irq(struct dw_edma_chan *chan, unsigned int events) { - dw_edma_queue_irq_work(chan, DW_EDMA_DEFERRED_DONE); -} + unsigned int pending = 0; -static void dw_edma_abort_interrupt_deferred(struct dw_edma_chan *chan) -{ - dw_edma_queue_irq_work(chan, DW_EDMA_DEFERRED_ABORT); + if (events & (DW_EDMA_IRQ_DONE | DW_EDMA_IRQ_PROGRESS | + DW_EDMA_IRQ_STOP)) + pending |= DW_EDMA_DEFERRED_DONE; + if (events & DW_EDMA_IRQ_ABORT) + pending |= DW_EDMA_DEFERRED_ABORT; + + if (pending) + dw_edma_queue_irq_work(chan, pending); } static void dw_edma_emul_irq_ack(struct irq_data *d) @@ -907,8 +917,7 @@ static inline irqreturn_t dw_edma_interrupt_write_inner(int irq, void *data) struct dw_edma_irq *dw_irq = data; return dw_edma_core_handle_int(dw_irq, EDMA_DIR_WRITE, - dw_edma_done_interrupt_deferred, - dw_edma_abort_interrupt_deferred); + dw_edma_record_irq); } static inline irqreturn_t dw_edma_interrupt_read_inner(int irq, void *data) @@ -916,8 +925,7 @@ static inline irqreturn_t dw_edma_interrupt_read_inner(int irq, void *data) struct dw_edma_irq *dw_irq = data; return dw_edma_core_handle_int(dw_irq, EDMA_DIR_READ, - dw_edma_done_interrupt_deferred, - dw_edma_abort_interrupt_deferred); + dw_edma_record_irq); } static inline irqreturn_t dw_edma_interrupt_write(int irq, void *data) diff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-edma-core.h index 8d993e8cccbb..30b508eb3e3d 100644 --- a/drivers/dma/dw-edma/dw-edma-core.h +++ b/drivers/dma/dw-edma/dw-edma-core.h @@ -41,6 +41,13 @@ enum dw_edma_xfer_type { EDMA_XFER_INTERLEAVED }; +enum dw_edma_irq_event { + DW_EDMA_IRQ_DONE = BIT(0), + DW_EDMA_IRQ_PROGRESS = BIT(1), + DW_EDMA_IRQ_STOP = BIT(2), + DW_EDMA_IRQ_ABORT = BIT(3), +}; + struct dw_edma_chan; struct dw_edma_chunk; @@ -147,7 +154,8 @@ struct dw_edma { const struct dw_edma_core_ops *core; }; -typedef void (*dw_edma_handler_t)(struct dw_edma_chan *); +typedef void (*dw_edma_handler_t)(struct dw_edma_chan *chan, + unsigned int events); struct dw_edma_core_ops { void (*off)(struct dw_edma *dw); @@ -156,7 +164,7 @@ struct dw_edma_core_ops { u16 (*ch_count)(struct dw_edma *dw, enum dw_edma_dir dir); enum dma_status (*ch_status)(struct dw_edma_chan *chan); irqreturn_t (*handle_int)(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir, - dw_edma_handler_t done, dw_edma_handler_t abort); + dw_edma_handler_t handler); void (*non_ll_start)(struct dw_edma_chan *chan, struct dw_edma_burst *child); void (*ll_data)(struct dw_edma_chan *chan, struct dw_edma_burst *burst, u32 idx, bool cb, bool irq); @@ -256,9 +264,9 @@ enum dma_status dw_edma_core_ch_status(struct dw_edma_chan *chan) static inline irqreturn_t dw_edma_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir, - dw_edma_handler_t done, dw_edma_handler_t abort) + dw_edma_handler_t handler) { - return dw_irq->dw->core->handle_int(dw_irq, dir, done, abort); + return dw_irq->dw->core->handle_int(dw_irq, dir, handler); } static inline diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c index 9053354eda67..4a1bb128fa00 100644 --- a/drivers/dma/dw-edma/dw-edma-v0-core.c +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c @@ -336,7 +336,7 @@ static void dw_edma_v0_core_clear_abort_int(struct dw_edma_chan *chan) static irqreturn_t dw_edma_v0_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir, - dw_edma_handler_t done, dw_edma_handler_t abort) + dw_edma_handler_t handler) { struct dw_edma *dw = dw_irq->dw; unsigned long total, pos, val; @@ -375,7 +375,7 @@ dw_edma_v0_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir, continue; dw_edma_v0_core_clear_done_int(chan); - done(chan); + handler(chan, DW_EDMA_IRQ_DONE); ret = IRQ_HANDLED; } @@ -389,7 +389,7 @@ dw_edma_v0_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir, continue; dw_edma_v0_core_clear_abort_int(chan); - abort(chan); + handler(chan, DW_EDMA_IRQ_ABORT); ret = IRQ_HANDLED; } diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c index 4acbace43519..c6d7f9885aa8 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -174,7 +174,7 @@ static u32 dw_hdma_v0_core_status_int(struct dw_edma_chan *chan) static irqreturn_t dw_hdma_v0_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir, - dw_edma_handler_t done, dw_edma_handler_t abort) + dw_edma_handler_t handler) { struct dw_edma *dw = dw_irq->dw; unsigned long total, pos, val; @@ -200,14 +200,14 @@ dw_hdma_v0_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir, val = dw_hdma_v0_core_status_int(chan); if (FIELD_GET(HDMA_V0_STOP_INT_MASK, val)) { dw_hdma_v0_core_clear_done_int(chan); - done(chan); + handler(chan, DW_EDMA_IRQ_STOP); ret = IRQ_HANDLED; } if (FIELD_GET(HDMA_V0_ABORT_INT_MASK, val)) { dw_hdma_v0_core_clear_abort_int(chan); - abort(chan); + handler(chan, DW_EDMA_IRQ_ABORT); ret = IRQ_HANDLED; } From 65d40a9edef128d35006b5167fc26f99689b19ed Mon Sep 17 00:00:00 2001 From: Koichiro Den Date: Fri, 21 Aug 2026 02:34:39 +0900 Subject: [PATCH 037/149] dmaengine: dw-edma: Prepare LL kicks for event serialization Both eDMA and HDMA perform the same remote LL read-back immediately before writing the doorbell register. A later patch serializes each raw doorbell write against IRQ event capture. Keeping the read-back in the provider callback would hold event_lock across a remote read. Move the common read-back into the high-level dw_edma_core_ch_doorbell(), where it can run before the serialized section. Name the provider write wrapper dw_edma_core_do_ch_doorbell() to distinguish the raw write, and leave dw_edma_core_ch_maybe_doorbell() to decide whether a kick is needed. No functional change. Suggested-by: Frank Li Reviewed-by: Frank Li Signed-off-by: Koichiro Den Link: https://patch.msgid.link/20260820173439.2004068-11-den@valinux.co.jp Signed-off-by: Vinod Koul --- drivers/dma/dw-edma/dw-edma-core.c | 18 ++++++++++++++++++ drivers/dma/dw-edma/dw-edma-core.h | 2 +- drivers/dma/dw-edma/dw-edma-v0-core.c | 16 ---------------- drivers/dma/dw-edma/dw-hdma-v0-core.c | 16 ---------------- 4 files changed, 19 insertions(+), 33 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c index 97de0ad4489a..e2eba6d72b53 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -254,6 +255,23 @@ static void dw_edma_finish_termination(struct dw_edma_chan *chan) chan->status = EDMA_ST_IDLE; } +static void dw_edma_core_ll_sync(struct dw_edma_chan *chan) +{ + /* + * Remote controller registers and LL memory may be reached through + * different paths. Complete posted LL writes before the doorbell. + */ + if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL)) + readl(chan->ll_region.vaddr.io); +} + +/* Must be called with vc.lock held for an LL channel. */ +static void dw_edma_core_ch_doorbell(struct dw_edma_chan *chan) +{ + dw_edma_core_ll_sync(chan); + dw_edma_core_do_ch_doorbell(chan); +} + /* Must be called with vc.lock held. */ static void dw_edma_core_ch_maybe_doorbell(struct dw_edma_chan *chan) { diff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-edma-core.h index 30b508eb3e3d..76fd5a41a707 100644 --- a/drivers/dma/dw-edma/dw-edma-core.h +++ b/drivers/dma/dw-edma/dw-edma-core.h @@ -298,7 +298,7 @@ static inline void dw_edma_core_ll_irq_clear(struct dw_edma_chan *chan) chan->dw->core->ll_irq_clear(chan); } -static inline void dw_edma_core_ch_doorbell(struct dw_edma_chan *chan) +static inline void dw_edma_core_do_ch_doorbell(struct dw_edma_chan *chan) { chan->dw->core->ch_doorbell(chan); } diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c index 4a1bb128fa00..c053cb4c2844 100644 --- a/drivers/dma/dw-edma/dw-edma-v0-core.c +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c @@ -480,20 +480,6 @@ static void dw_edma_v0_core_ch_enable(struct dw_edma_chan *chan) upper_32_bits(chan->ll_region.paddr)); } -static void dw_edma_v0_sync_ll_data(struct dw_edma_chan *chan) -{ - /* - * In case of remote eDMA engine setup, the DW PCIe RP/EP internal - * configuration registers and application memory are normally accessed - * over different buses. Ensure LL-data reaches the memory before the - * doorbell register is toggled by issuing the dummy-read from the remote - * LL memory in a hope that the MRd TLP will return only after the - * last MWr TLP is completed - */ - if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL)) - readl(chan->ll_region.vaddr.io); -} - static void dw_edma_v0_core_ch_config(struct dw_edma_chan *chan) { struct dw_edma *dw = chan->dw; @@ -624,8 +610,6 @@ static void dw_edma_v0_core_ch_doorbell(struct dw_edma_chan *chan) { struct dw_edma *dw = chan->dw; - dw_edma_v0_sync_ll_data(chan); - /* Doorbell */ SET_RW_32(dw, chan->dir, doorbell, FIELD_PREP(EDMA_V0_DOORBELL_CH_MASK, chan->id)); diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c index c6d7f9885aa8..0b3c8496b0ad 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -282,20 +282,6 @@ static void dw_hdma_v0_core_ch_enable(struct dw_edma_chan *chan) HDMA_V0_CONSUMER_CYCLE_STAT | HDMA_V0_CONSUMER_CYCLE_BIT); } -static void dw_hdma_v0_sync_ll_data(struct dw_edma_chan *chan) -{ - /* - * In case of remote HDMA engine setup, the DW PCIe RP/EP internal - * configuration registers and application memory are normally accessed - * over different buses. Ensure LL-data reaches the memory before the - * doorbell register is toggled by issuing the dummy-read from the remote - * LL memory in a hope that the MRd TLP will return only after the - * last MWr TLP is completed - */ - if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL)) - readl(chan->ll_region.vaddr.io); -} - static void dw_hdma_v0_core_non_ll_start(struct dw_edma_chan *chan, struct dw_edma_burst *child) { @@ -393,8 +379,6 @@ static void dw_hdma_v0_core_ch_doorbell(struct dw_edma_chan *chan) { struct dw_edma *dw = chan->dw; - dw_hdma_v0_sync_ll_data(chan); - /* Doorbell */ SET_CH_32(dw, chan->dir, chan->id, doorbell, HDMA_V0_DOORBELL_START); } From 08f04d5ab868bc28d3115f7406499e8e5d1d1765 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 3 Sep 2026 22:33:57 +0530 Subject: [PATCH 038/149] dmaengine: zynqmp_dma: drop redundant label MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 3f30db282c28 ("dmaengine: zynqmp_dma: Fix chan probe/remove error handling") dropped the use of err_disable_pm label causing warning: drivers/dma/xilinx/zynqmp_dma.c: In function ‘zynqmp_dma_probe’: drivers/dma/xilinx/zynqmp_dma.c:1171:1: error: label ‘err_disable_pm’ defined but not used [-Werror=unused-label] 1171 | err_disable_pm: Drop it Fixes: 3f30db282c28 ("dmaengine: zynqmp_dma: Fix chan probe/remove error handling") Reviewed-by: Radhey Shyam Pandey Reviewed-by: Frank Li Link: https://patch.msgid.link/20260903170357.1711462-1-vkoul@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/xilinx/zynqmp_dma.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/dma/xilinx/zynqmp_dma.c b/drivers/dma/xilinx/zynqmp_dma.c index d1ee51dde3d1..3b7dfa53f972 100644 --- a/drivers/dma/xilinx/zynqmp_dma.c +++ b/drivers/dma/xilinx/zynqmp_dma.c @@ -1168,7 +1168,6 @@ static int zynqmp_dma_probe(struct platform_device *pdev) free_chan_resources: zynqmp_dma_chan_remove(zdev->chan); -err_disable_pm: if (!pm_runtime_enabled(zdev->dev)) zynqmp_dma_runtime_suspend(zdev->dev); pm_runtime_disable(zdev->dev); From 58a66a560aa1937ac7bd415d86acba42bf1eb4a0 Mon Sep 17 00:00:00 2001 From: Jia Wang Date: Mon, 7 Sep 2026 17:54:46 +0800 Subject: [PATCH 039/149] dt-bindings: dma: snps,dw-axi-dmac: Add UltraRISC DP1000 compatible The DP1000 integrates a DMA controller. Add its SoC-specific compatible with the generic fallback. Signed-off-by: Jia Wang Acked-by: Conor Dooley Link: https://patch.msgid.link/20260907-ultrarisc-dts-v2-7-5eb4c97477c5@ultrarisc.com Signed-off-by: Vinod Koul --- .../bindings/dma/snps,dw-axi-dmac.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml index 0a30a455b0ee..bfd6d67a98e6 100644 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml @@ -14,6 +14,27 @@ description: allOf: - $ref: dma-controller.yaml# + - if: + properties: + compatible: + contains: + const: ultrarisc,dp1000-axi-dma + then: + properties: + reg: + maxItems: 1 + interrupts: + minItems: 8 + dma-channels: + const: 8 + snps,dma-masters: + const: 1 + snps,data-width: + const: 4 + snps,priority: + minItems: 8 + snps,block-size: + minItems: 8 properties: compatible: @@ -27,6 +48,7 @@ properties: - enum: - altr,agilex5-axi-dma - sophgo,cv1800b-axi-dma + - ultrarisc,dp1000-axi-dma - const: snps,axi-dma-1.01a reg: From 6ba190e3b24c5f1b2ae31e7b9db3c7f2e8aacb3a Mon Sep 17 00:00:00 2001 From: Bhargav Joshi Date: Tue, 25 Aug 2026 16:55:22 +0530 Subject: [PATCH 040/149] dt-bindings: dma: ti,dma-crossbar: Convert to DT schema Convert Texas Instruments DMA Crossbar from text to DT schema. Modify MAINTAINERS file to correctly point to new yaml file. Reviewed-by: Rob Herring (Arm) Signed-off-by: Bhargav Joshi Link: https://patch.msgid.link/20260825-ti-dma-crossbar-v4-1-b0bc78cf071e@gmail.com Signed-off-by: Vinod Koul --- .../bindings/dma/ti,dra7-dma-crossbar.yaml | 94 +++++++++++++++++++ .../bindings/dma/ti-dma-crossbar.txt | 68 -------------- MAINTAINERS | 2 +- 3 files changed, 95 insertions(+), 69 deletions(-) create mode 100644 Documentation/devicetree/bindings/dma/ti,dra7-dma-crossbar.yaml delete mode 100644 Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt diff --git a/Documentation/devicetree/bindings/dma/ti,dra7-dma-crossbar.yaml b/Documentation/devicetree/bindings/dma/ti,dra7-dma-crossbar.yaml new file mode 100644 index 000000000000..873cedd1427d --- /dev/null +++ b/Documentation/devicetree/bindings/dma/ti,dra7-dma-crossbar.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/ti,dra7-dma-crossbar.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments DMA Crossbar (DMA request router) + +maintainers: + - Vignesh Raghavendra + - Bhargav Joshi + +description: + When requesting channel via ti,dra7-dma-crossbar, the DMA client must request + the DMA event number as crossbar ID (input to the DMA crossbar). For + ti,am335x-edma-crossbar the meaning of parameters of dmas for clients dmas = + <&edma_xbar 12 0 1>; where <12> is the DMA request number, <0> is the TC the + event should be assigned and <1> is the mux selection for in the crossbar. + When mux 0 is used the DMA channel can be requested directly from edma node. + +properties: + compatible: + enum: + - ti,dra7-dma-crossbar + - ti,am335x-edma-crossbar + + reg: + maxItems: 1 + + "#dma-cells": + minimum: 1 + maximum: 3 + + dma-requests: + minimum: 1 + maximum: 256 + + dma-masters: + maxItems: 1 + + ti,dma-safe-map: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Safe routing value for unused request lines + + ti,reserved-dma-request-ranges: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + DMA request ranges which should not be used when mapping xbar input to + DMA request, they are either allocated to be used by for example the DSP + or they are used as memcpy channels in eDMA. + items: + items: + - description: starting DMA request line number + - description: number of consecutive lines to reserve + +required: + - compatible + - reg + - "#dma-cells" + - dma-requests + - dma-masters + +allOf: + - $ref: dma-router.yaml# + + - if: + properties: + compatible: + contains: + const: ti,am335x-edma-crossbar + then: + properties: + "#dma-cells": + const: 3 + + else: + properties: + "#dma-cells": + enum: [1, 2] + +unevaluatedProperties: false + +examples: + - | + dma-router@4a002b78 { + compatible = "ti,dra7-dma-crossbar"; + reg = <0x4a002b78 0xfc>; + #dma-cells = <1>; + dma-requests = <205>; + ti,dma-safe-map = <0>; + /* Protect the sDMA request ranges: 10-14 and 100-126 */ + ti,reserved-dma-request-ranges = <10 5>, <100 27>; + dma-masters = <&sdma>; + }; diff --git a/Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt b/Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt deleted file mode 100644 index 1f9831540c97..000000000000 --- a/Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt +++ /dev/null @@ -1,68 +0,0 @@ -Texas Instruments DMA Crossbar (DMA request router) - -Required properties: -- compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar - "ti,am335x-edma-crossbar" for AM335x and AM437x -- reg: Memory map for accessing module -- #dma-cells: Should be set to match with the DMA controller's dma-cells - for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar. -- dma-requests: Number of DMA requests the crossbar can receive -- dma-masters: phandle pointing to the DMA controller - -The DMA controller node need to have the following poroperties: -- dma-requests: Number of DMA requests the controller can handle - -Optional properties: -- ti,dma-safe-map: Safe routing value for unused request lines -- ti,reserved-dma-request-ranges: DMA request ranges which should not be used - when mapping xbar input to DMA request, they are either - allocated to be used by for example the DSP or they are used as - memcpy channels in eDMA. - -Notes: -When requesting channel via ti,dra7-dma-crossbar, the DMA client must request -the DMA event number as crossbar ID (input to the DMA crossbar). - -For ti,am335x-edma-crossbar: the meaning of parameters of dmas for clients: -dmas = <&edma_xbar 12 0 1>; where <12> is the DMA request number, <0> is the TC -the event should be assigned and <1> is the mux selection for in the crossbar. -When mux 0 is used the DMA channel can be requested directly from edma node. - -Example: - -/* DMA controller */ -sdma: dma-controller@4a056000 { - compatible = "ti,omap4430-sdma"; - reg = <0x4a056000 0x1000>; - interrupts = , - , - , - ; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <127>; -}; - -/* DMA crossbar */ -sdma_xbar: dma-router@4a002b78 { - compatible = "ti,dra7-dma-crossbar"; - reg = <0x4a002b78 0xfc>; - #dma-cells = <1>; - dma-requests = <205>; - ti,dma-safe-map = <0>; - /* Protect the sDMA request ranges: 10-14 and 100-126 */ - ti,reserved-dma-request-ranges = <10 5>, <100 27>; - dma-masters = <&sdma>; -}; - -/* DMA client */ -uart1: serial@4806a000 { - compatible = "ti,omap4-uart"; - reg = <0x4806a000 0x100>; - interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "uart1"; - clock-frequency = <48000000>; - /* Requesting crossbar input 49 and 50 */ - dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; - dma-names = "tx", "rx"; -}; diff --git a/MAINTAINERS b/MAINTAINERS index 3a19da74d00c..c31b81eb42d7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -27019,7 +27019,7 @@ TEXAS INSTRUMENTS DMA DRIVERS M: Vignesh Raghavendra L: dmaengine@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt +F: Documentation/devicetree/bindings/dma/ti,dra7-dma-crossbar.yaml F: Documentation/devicetree/bindings/dma/ti-edma.txt F: Documentation/devicetree/bindings/dma/ti/ F: drivers/dma/ti/ From c64189e9772d74e90ae95b293f32c8d50dea1a91 Mon Sep 17 00:00:00 2001 From: Bhargav Joshi Date: Tue, 1 Sep 2026 04:53:05 +0530 Subject: [PATCH 041/149] dt-bindings: dma: ti,cppi41: Convert to DT schema Convert TI CPPI 4.1 DMA controller text bindings to DT schema. Add ti,am3359-cppi41 and ti,da830-cppi41 into single schema since they share the same hardware IP block and driver. Add undocumented #dma-requests and power-domains properties to match existing DTS usage. Reviewed-by: Rob Herring (Arm) Signed-off-by: Bhargav Joshi Link: https://patch.msgid.link/20260901-ti-am33-usb-v3-1-5e15c617d2e9@gmail.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/ti/ti,cppi41.yaml | 109 ++++++++++++++++++ .../devicetree/bindings/usb/am33xx-usb.txt | 14 --- .../devicetree/bindings/usb/da8xx-usb.txt | 12 -- 3 files changed, 109 insertions(+), 26 deletions(-) create mode 100644 Documentation/devicetree/bindings/dma/ti/ti,cppi41.yaml diff --git a/Documentation/devicetree/bindings/dma/ti/ti,cppi41.yaml b/Documentation/devicetree/bindings/dma/ti/ti,cppi41.yaml new file mode 100644 index 000000000000..a8c28e8ada07 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/ti/ti,cppi41.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/ti/ti,cppi41.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI CPPI41 DMA Controller + +maintainers: + - Sebastian Andrzej Siewior + +properties: + compatible: + enum: + - ti,am3359-cppi41 + - ti,da830-cppi41 + + reg: + minItems: 3 + maxItems: 4 + + reg-names: + minItems: 3 + maxItems: 4 + + interrupts: + maxItems: 1 + + interrupt-names: + const: glue + + "#dma-cells": + const: 2 + + dma-channels: + description: Number of DMA channels supported. + $ref: /schemas/types.yaml#/definitions/uint32 + + dma-requests: + description: Number of DMA requests supported. + $ref: /schemas/types.yaml#/definitions/uint32 + + power-domains: + maxItems: 1 + + "#dma-channels": + description: Deprecated, use dma-channels instead. + deprecated: true + + "#dma-requests": + description: Deprecated, use dma-requests instead. + deprecated: true + +required: + - compatible + - reg + - reg-names + - "#dma-cells" + - dma-channels + +allOf: + - $ref: /schemas/dma/dma-controller.yaml# + - if: + properties: + compatible: + contains: + const: ti,am3359-cppi41 + then: + properties: + reg: + minItems: 4 + reg-names: + items: + - const: glue + - const: controller + - const: scheduler + - const: queuemgr + power-domains: false + required: + - interrupt-names + - interrupts + - dma-requests + else: + properties: + reg: + maxItems: 3 + reg-names: + items: + - const: controller + - const: scheduler + - const: queuemgr + +unevaluatedProperties: false + +examples: + - | + dma-controller@7402000 { + compatible = "ti,am3359-cppi41"; + reg = <0x47400000 0x1000>, + <0x47402000 0x1000>, + <0x47403000 0x1000>, + <0x47404000 0x4000>; + reg-names = "glue", "controller", "scheduler", "queuemgr"; + interrupts = <17>; + interrupt-names = "glue"; + #dma-cells = <2>; + dma-channels = <30>; + dma-requests = <256>; + }; diff --git a/Documentation/devicetree/bindings/usb/am33xx-usb.txt b/Documentation/devicetree/bindings/usb/am33xx-usb.txt index 654ffc62d013..8431de346129 100644 --- a/Documentation/devicetree/bindings/usb/am33xx-usb.txt +++ b/Documentation/devicetree/bindings/usb/am33xx-usb.txt @@ -51,20 +51,6 @@ USB The controller should have an "usb" alias numbered properly in the alias node. -DMA -~~~ -- compatible: ti,am3359-cppi41 -- reg: offset and length of the following register spaces: USBSS, USB - CPPI DMA Controller, USB CPPI DMA Scheduler, USB Queue Manager -- reg-names: glue, controller, scheduler, queuemgr -- #dma-cells: should be set to 2. The first number represents the - endpoint number (0 … 14 for endpoints 1 … 15 on instance 0 and 15 … 29 - for endpoints 1 … 15 on instance 1). The second number is 0 for RX and - 1 for TX transfers. -- dma-channels: should be set to 30 representing the 15 endpoints for - each USB instance. -- #dma-channels: deprecated - Example: ~~~~~~~~ The following example contains all the nodes as used on am335x-evm: diff --git a/Documentation/devicetree/bindings/usb/da8xx-usb.txt b/Documentation/devicetree/bindings/usb/da8xx-usb.txt index fb2027a7d80d..00320d92d3bb 100644 --- a/Documentation/devicetree/bindings/usb/da8xx-usb.txt +++ b/Documentation/devicetree/bindings/usb/da8xx-usb.txt @@ -27,18 +27,6 @@ Optional properties: ~~~~~~~~~~~~~~~~~~~~ - vbus-supply: Phandle to a regulator providing the USB bus power. -DMA -~~~ -- compatible: ti,da830-cppi41 -- reg: offset and length of the following register spaces: CPPI DMA Controller, - CPPI DMA Scheduler, Queue Manager -- reg-names: "controller", "scheduler", "queuemgr" -- #dma-cells: should be set to 2. The first number represents the - channel number (0 … 3 for endpoints 1 … 4). - The second number is 0 for RX and 1 for TX transfers. -- dma-channels: should be set to 4 representing the 4 endpoints. -- #dma-channels: deprecated - Example: usb_phy: usb-phy { compatible = "ti,da830-usb-phy"; From a5f8e3471fc20567df888267885dec3eb340eb37 Mon Sep 17 00:00:00 2001 From: Runyu Xiao Date: Sun, 30 Aug 2026 13:33:08 +0800 Subject: [PATCH 042/149] dmaengine: altera-msgdma: initialize state before requesting IRQ msgdma_probe() registers the IRQ before initializing the tasklet, lock, and descriptor lists used by the interrupt handler. A pending interrupt can access incomplete state during probe. Initialize the handler state before requesting the IRQ so the interrupt path observes ready software state. Fixes: a85c6f1b2921 ("dmaengine: Add driver for Altera / Intel mSGDMA IP core") Cc: stable@vger.kernel.org Assisted-by: Codex:GPT-5 Signed-off-by: Runyu Xiao Acked-by: Adrian Ng Ho Yin Reviewed-by: Frank Li Link: https://patch.msgid.link/20260830053308.2190597-1-runyu.xiao@seu.edu.cn Signed-off-by: Vinod Koul --- drivers/dma/altera-msgdma.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/dma/altera-msgdma.c b/drivers/dma/altera-msgdma.c index e23e5b441a24..412f4bce1d4a 100644 --- a/drivers/dma/altera-msgdma.c +++ b/drivers/dma/altera-msgdma.c @@ -847,11 +847,6 @@ static int msgdma_probe(struct platform_device *pdev) if (mdev->irq < 0) return -ENXIO; - ret = devm_request_irq(&pdev->dev, mdev->irq, msgdma_irq_handler, - 0, dev_name(&pdev->dev), mdev); - if (ret) - return ret; - tasklet_setup(&mdev->irq_tasklet, msgdma_tasklet); dma_cookie_init(&mdev->dmachan); @@ -863,6 +858,11 @@ static int msgdma_probe(struct platform_device *pdev) INIT_LIST_HEAD(&mdev->done_list); INIT_LIST_HEAD(&mdev->free_list); + ret = devm_request_irq(&pdev->dev, mdev->irq, msgdma_irq_handler, + 0, dev_name(&pdev->dev), mdev); + if (ret) + return ret; + dma_dev = &mdev->dmadev; /* Set DMA capabilities */ From 140ebb6d10559a7d2d0c597926f1bfacf03c9f29 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sun, 16 Aug 2026 18:54:42 -0700 Subject: [PATCH 043/149] dmaengine: bestcomm: set bcom_eng to NULL on probe failure Functions like bcom_task_alloc() use if (!bcom_eng) as a safety readiness check. If the probe fails and hits this error path, subsequent or concurrent API calls will bypass the check and dereference the freed memory. Fixes: 9560aea4e9d1 ("[POWERPC] mpc5200: Fix null dereference if bestcomm fails to initialize") Signed-off-by: Rosen Penev Reviewed-by: Frank Li Link: https://patch.msgid.link/20260817015442.136038-1-rosenp@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/bestcomm/bestcomm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dma/bestcomm/bestcomm.c b/drivers/dma/bestcomm/bestcomm.c index 432b43520ddc..ec58d2c6573f 100644 --- a/drivers/dma/bestcomm/bestcomm.c +++ b/drivers/dma/bestcomm/bestcomm.c @@ -445,6 +445,7 @@ static int mpc52xx_bcom_probe(struct platform_device *op) release_mem_region(res_bcom.start, sizeof(struct mpc52xx_sdma)); error_sramclean: kfree(bcom_eng); + bcom_eng = NULL; bcom_sram_cleanup(); error_ofput: of_node_put(op->dev.of_node); From 152fd3f4a2456221abb5b07e1682ca8a0b7798bb Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sun, 16 Aug 2026 18:59:03 -0700 Subject: [PATCH 044/149] dmaengine: bestcomm: gen_bd: split struct bcom_psc_params from array definition The combined struct-definition-with-initializer pattern confuses the kernel-doc parser. Split into separate struct definition and array declaration. Also now that it's fixed, it warns on missing members. Add those as well. Since this is just a lookup table and not modified, make it const so that it can be moved to read only memory. Assisted-by: Opencode:Big-pickle Signed-off-by: Rosen Penev Reviewed-by: Frank Li Link: https://patch.msgid.link/20260817015903.137062-1-rosenp@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/bestcomm/gen_bd.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/dma/bestcomm/gen_bd.c b/drivers/dma/bestcomm/gen_bd.c index 8a24a5cbc263..61b5746e1a97 100644 --- a/drivers/dma/bestcomm/gen_bd.c +++ b/drivers/dma/bestcomm/gen_bd.c @@ -254,17 +254,23 @@ EXPORT_SYMBOL_GPL(bcom_gen_bd_tx_release); */ /** - * bcom_psc_parameters - Bestcomm initialization value table for PSC devices + * struct bcom_psc_params - Bestcomm initialization value table for PSC devices + * @rx_initiator: RX initiator ID + * @rx_ipr: RX interrupt priority register value + * @tx_initiator: TX initiator ID + * @tx_ipr: TX interrupt priority register value * * This structure is only used internally. It is a lookup table for PSC * specific parameters to bestcomm tasks. */ -static struct bcom_psc_params { +struct bcom_psc_params { int rx_initiator; int rx_ipr; int tx_initiator; int tx_ipr; -} bcom_psc_params[] = { +}; + +static const struct bcom_psc_params bcom_psc_params[] = { [0] = { .rx_initiator = BCOM_INITIATOR_PSC1_RX, .rx_ipr = BCOM_IPR_PSC1_RX, From bf27ec04a888d4f1301a8da040719f2c332da681 Mon Sep 17 00:00:00 2001 From: Binbin Zhou Date: Tue, 18 Aug 2026 17:34:48 +0800 Subject: [PATCH 045/149] dmaengine: loongson: loongson2-apb-cmc: Fix signedness bug in irq handling Storing that negative value into an unsigned variable makes the check `if (lchan->irq < 0)` always false, so probe errors are not correctly detected and propagated. Fix this by changing the type of `irq` to `int`, which allows proper signed comparison and error handling. Fixes: 1c0028e725f1 ("dmaengine: loongson: New driver for the Loongson Multi-Channel DMA controller") Reported-by: Julia Lawall Reported-by: kernel test robot Closes: https://lore.kernel.org/r/202608152230.p20WPlS0-lkp@intel.com/ Signed-off-by: Binbin Zhou Reviewed-by: Frank Li Reviewed-by: Huacai Chen Link: https://patch.msgid.link/20260818093448.3597016-1-zhoubinbin@loongson.cn Signed-off-by: Vinod Koul --- drivers/dma/loongson/loongson2-apb-cmc-dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/loongson/loongson2-apb-cmc-dma.c b/drivers/dma/loongson/loongson2-apb-cmc-dma.c index 1c9a542edc85..969dbc5dabe7 100644 --- a/drivers/dma/loongson/loongson2-apb-cmc-dma.c +++ b/drivers/dma/loongson/loongson2-apb-cmc-dma.c @@ -90,7 +90,7 @@ struct loongson2_cmc_dma_chan { struct dma_slave_config dma_sconfig; struct loongson2_cmc_dma_desc *desc; u32 id; - u32 irq; + int irq; u32 next_sg; struct loongson2_cmc_dma_chan_reg chan_reg; }; From d09cd5e8bbc98969b5333015b45c525078ac0f6f Mon Sep 17 00:00:00 2001 From: Chaithanya Lagisetty Date: Wed, 19 Aug 2026 05:35:18 +0000 Subject: [PATCH 046/149] dmaengine: sprd: use clk_bulk API to fix clock imbalance sprd_dma_enable() enabled sdev->clk and then the optional ashb_clk. If enabling ashb_clk failed, sdev->clk was left enabled: both callers (probe and resume) treat a non-zero return as "nothing was enabled" and bail out, leaking sdev->clk. Convert the driver to the clk_bulk API. clk_bulk_prepare_enable() enables all clocks and unwinds them on failure, and clk_bulk_disable_unprepare() disables them, which fixes the imbalance and simplifies the enable/disable paths. Both clocks are fetched with devm_clk_bulk_get_optional(); the optional ashb_eb clock simply becomes a NULL entry that the bulk helpers treat as a no-op, while the mandatory enable clock is still checked explicitly. Fixes: 9b3b8171f7f4 ("dmaengine: sprd: Add Spreadtrum DMA driver") Signed-off-by: Chaithanya Lagisetty Reviewed-by: Frank Li Link: https://patch.msgid.link/20260819053518.2825514-1-nagachaithanya9911@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/sprd-dma.c | 45 ++++++++++++------------------------------ 1 file changed, 13 insertions(+), 32 deletions(-) diff --git a/drivers/dma/sprd-dma.c b/drivers/dma/sprd-dma.c index 087fea3af2e4..749cabd984eb 100644 --- a/drivers/dma/sprd-dma.c +++ b/drivers/dma/sprd-dma.c @@ -208,8 +208,7 @@ struct sprd_dma_chn { struct sprd_dma_dev { struct dma_device dma_dev; void __iomem *glb_base; - struct clk *clk; - struct clk *ashb_clk; + struct clk_bulk_data clks[2]; int irq; u32 total_chns; struct sprd_dma_chn channels[] __counted_by(total_chns); @@ -260,31 +259,12 @@ static void sprd_dma_chn_update(struct sprd_dma_chn *schan, u32 reg, static int sprd_dma_enable(struct sprd_dma_dev *sdev) { - int ret; - - ret = clk_prepare_enable(sdev->clk); - if (ret) - return ret; - - /* - * The ashb_clk is optional and only for AGCP DMA controller, so we - * need add one condition to check if the ashb_clk need enable. - */ - if (!IS_ERR(sdev->ashb_clk)) - ret = clk_prepare_enable(sdev->ashb_clk); - - return ret; + return clk_bulk_prepare_enable(ARRAY_SIZE(sdev->clks), sdev->clks); } static void sprd_dma_disable(struct sprd_dma_dev *sdev) { - clk_disable_unprepare(sdev->clk); - - /* - * Need to check if we need disable the optional ashb_clk for AGCP DMA. - */ - if (!IS_ERR(sdev->ashb_clk)) - clk_disable_unprepare(sdev->ashb_clk); + clk_bulk_disable_unprepare(ARRAY_SIZE(sdev->clks), sdev->clks); } static void sprd_dma_set_uid(struct sprd_dma_chn *schan) @@ -1140,16 +1120,17 @@ static int sprd_dma_probe(struct platform_device *pdev) if (!sdev) return -ENOMEM; - sdev->clk = devm_clk_get(&pdev->dev, "enable"); - if (IS_ERR(sdev->clk)) { - dev_err(&pdev->dev, "get enable clock failed\n"); - return PTR_ERR(sdev->clk); - } + /* The ashb_eb clock is optional and only present for AGCP DMA */ + sdev->clks[0].id = "enable"; + sdev->clks[1].id = "ashb_eb"; + ret = devm_clk_bulk_get_optional(&pdev->dev, ARRAY_SIZE(sdev->clks), + sdev->clks); + if (ret) + return dev_err_probe(&pdev->dev, ret, "get clocks failed\n"); - /* ashb clock is optional for AGCP DMA */ - sdev->ashb_clk = devm_clk_get(&pdev->dev, "ashb_eb"); - if (IS_ERR(sdev->ashb_clk)) - dev_warn(&pdev->dev, "no optional ashb eb clock\n"); + if (!sdev->clks[0].clk) + return dev_err_probe(&pdev->dev, -ENOENT, + "get enable clock failed\n"); /* * We have three DMA controllers: AP DMA, AON DMA and AGCP DMA. For AGCP From dd27c3f4d6108556b74b5f3f4d1d885269e7ffa3 Mon Sep 17 00:00:00 2001 From: Aniket Randive Date: Wed, 19 Aug 2026 17:09:31 +0530 Subject: [PATCH 047/149] dmaengine: qcom: gpi: Fix resource leaks as part of channel clean up The gpi_ch_init() error handling paths do not fully clean up resources when channel initialization fails. The unwind paths iterate over the original channel pointer instead of the channels stored in gpii->gchan[], preventing previously initialized sibling channels from being properly reset and deallocated. In addition, gpi_alloc_chan_resources() allocates ch_ring before calling gpi_ch_init(), but does not release it when initialization fails, resulting in a memory leak. The event ring cleanup path also leaves the PM state unchanged after freeing the ring. As a result, subsequent cleanup may incorrectly assume that the ring is still allocated, leading to a redundant EV_CMD_DEALLOC command and an attempt to deallocate an already released ring. Fix the unwind paths to operate on the correct channels, release ch_ring when channel initialization fails, and restore the event ring PM state after freeing the ring. Signed-off-by: Aniket Randive Reviewed-by: Frank Li Reviewed-by: Mukesh Kumar Savaliya Reviewed-by: Praveen Talari Link: https://patch.msgid.link/20260810-gpi_bug_fix-v2-1-60555394cbf9@oss.qualcomm.com Link: https://patch.msgid.link/20260819-gpi_bug_fix-v3-1-4c97333e6f5b@oss.qualcomm.com Signed-off-by: Vinod Koul --- drivers/dma/qcom/gpi.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c index a5055a6273af..c41bfac65ddf 100644 --- a/drivers/dma/qcom/gpi.c +++ b/drivers/dma/qcom/gpi.c @@ -1965,16 +1965,19 @@ static int gpi_ch_init(struct gchan *gchan) error_start_chan: for (i = i - 1; i >= 0; i--) { gpi_stop_chan(&gpii->gchan[i]); - gpi_send_cmd(gpii, gchan, GPI_CH_CMD_RESET); + gpi_send_cmd(gpii, &gpii->gchan[i], GPI_CH_CMD_RESET); } i = 2; error_alloc_chan: for (i = i - 1; i >= 0; i--) - gpi_reset_chan(gchan, GPI_CH_CMD_DE_ALLOC); + gpi_reset_chan(&gpii->gchan[i], GPI_CH_CMD_DE_ALLOC); error_alloc_ev_ring: gpi_disable_interrupts(gpii); error_config_int: gpi_free_ring(&gpii->ev_ring, gpii); + write_lock_irq(&gpii->pm_lock); + gpii->pm_state = DISABLE_STATE; + write_unlock_irq(&gpii->pm_lock); exit_gpi_init: return ret; } @@ -2065,6 +2068,8 @@ static int gpi_alloc_chan_resources(struct dma_chan *chan) goto xfer_alloc_err; ret = gpi_ch_init(gchan); + if (ret) + gpi_free_ring(&gchan->ch_ring, gpii); mutex_unlock(&gpii->ctrl_lock); From 26d48e9fb6997f4026dd86daecf8d2c12258f698 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Wed, 19 Aug 2026 20:16:54 -0700 Subject: [PATCH 048/149] dmaengine: fsl_raid: zero CF descriptor pool allocations The compound frame descriptors and embedded CDBs are allocated from the cf_desc_pool with dma_pool_alloc(), which does not zero the memory. Only cdb32, the gfm coefficients and the frame address/length fields are programmed; the dpi_dest_spec/dpi_src_spec fields in the CDBs and the rbro32 field of each frame are left uninitialized. The hardware reads the whole block (frame 0 length is sizeof(struct fsl_re_xor_cdb) or sizeof(struct fsl_re_pq_cdb)), so uninitialized heap contents are exposed to the device on each new descriptor. Use dma_pool_zalloc() in both fsl_re_chan_alloc_desc() and fsl_re_alloc_chan_resources() so the descriptor and CDB memory is zeroed before it is handed to the RAID engine. Fixes: ad80da658bbc ("dmaengine: Driver support for FSL RaidEngine device.") Assisted-by: opencode:deepseek-v4-flash-free Signed-off-by: Rosen Penev Reviewed-by: Frank Li Link: https://patch.msgid.link/20260820031654.28450-1-rosenp@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/fsl_raid.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/dma/fsl_raid.c b/drivers/dma/fsl_raid.c index e698c40b2ebc..befb4bb69d54 100644 --- a/drivers/dma/fsl_raid.c +++ b/drivers/dma/fsl_raid.c @@ -306,8 +306,8 @@ static struct fsl_re_desc *fsl_re_chan_alloc_desc(struct fsl_re_chan *re_chan, if (!desc) return NULL; - cf = dma_pool_alloc(re_chan->re_dev->cf_desc_pool, GFP_NOWAIT, - &paddr); + cf = dma_pool_zalloc(re_chan->re_dev->cf_desc_pool, GFP_NOWAIT, + &paddr); if (!cf) { kfree(desc); return NULL; @@ -595,8 +595,8 @@ static int fsl_re_alloc_chan_resources(struct dma_chan *chan) if (!desc) break; - cf = dma_pool_alloc(re_chan->re_dev->cf_desc_pool, GFP_KERNEL, - &paddr); + cf = dma_pool_zalloc(re_chan->re_dev->cf_desc_pool, GFP_KERNEL, + &paddr); if (!cf) { kfree(desc); break; From 0d59891c42e11c3840276d8a632dbc355d6ddc4f Mon Sep 17 00:00:00 2001 From: Jia Wang Date: Wed, 2 Sep 2026 17:26:11 +0800 Subject: [PATCH 049/149] dmaengine: dw-axi-dmac: Fix AXI burst length encoding The snps,axi-max-burst-len property describes the number of beats in an AXI burst, while the ARLEN and AWLEN fields encode that value minus one. The driver keeps axi_rw_burst_len as the actual burst length so that dma_device.max_burst reports the correct value. However, it also programs that unencoded value directly into the hardware fields. A value of 256 therefore overflows the 8-bit fields and can cause AXI decode errors. Subtract one only when constructing hardware descriptors, while keeping the actual value for dma_device.max_burst. Fixes: c454d16a7d5a ("dmaengine: dw-axi-dmac: Burst length settings") Signed-off-by: Jia Wang Reviewed-by: Frank Li Link: https://patch.msgid.link/20260902-dma-fix-v3-1-414c6449fbcc@ultrarisc.com Signed-off-by: Vinod Koul --- drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c index 9c21a5479437..ea26ebc328bc 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -706,7 +706,7 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan, ctlhi = CH_CTL_H_LLI_VALID; if (chan->chip->dw->hdata->restrict_axi_burst_len) { - burst_len = chan->chip->dw->hdata->axi_rw_burst_len; + burst_len = chan->chip->dw->hdata->axi_rw_burst_len - 1; ctlhi |= CH_CTL_H_ARLEN_EN | CH_CTL_H_AWLEN_EN | burst_len << CH_CTL_H_ARLEN_POS | burst_len << CH_CTL_H_AWLEN_POS; @@ -975,7 +975,7 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr, reg = CH_CTL_H_LLI_VALID; if (chan->chip->dw->hdata->restrict_axi_burst_len) { - u32 burst_len = chan->chip->dw->hdata->axi_rw_burst_len; + u32 burst_len = chan->chip->dw->hdata->axi_rw_burst_len - 1; reg |= (CH_CTL_H_ARLEN_EN | burst_len << CH_CTL_H_ARLEN_POS | From e6b49f8016ee8b642e8e495d1704342ee0b35d72 Mon Sep 17 00:00:00 2001 From: Jia Wang Date: Wed, 2 Sep 2026 17:26:12 +0800 Subject: [PATCH 050/149] dmaengine: dw-axi-dmac: Fix LLI dump out-of-bounds access axi_chan_list_dump_lli() uses the channel-wide descs_allocated count to walk the hw_desc[] array of a single transaction. If multiple transactions have allocated LLIs, the channel count can exceed the transaction-local nr_hw_descs and make the DMA error path read past the end of hw_desc[]. Use the descriptor-local nr_hw_descs count when dumping LLIs. Fixes: ef6fb2d6f1ab ("dmaengine: dw-axi-dmac: simplify descriptor management") Signed-off-by: Jia Wang Reviewed-by: Frank Li Link: https://patch.msgid.link/20260902-dma-fix-v3-2-414c6449fbcc@ultrarisc.com Signed-off-by: Vinod Koul --- drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c index ea26ebc328bc..2d7d49017002 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -1052,10 +1052,7 @@ static void axi_chan_dump_lli(struct axi_dma_chan *chan, static void axi_chan_list_dump_lli(struct axi_dma_chan *chan, struct axi_dma_desc *desc_head) { - int count = atomic_read(&chan->descs_allocated); - int i; - - for (i = 0; i < count; i++) + for (unsigned int i = 0; i < desc_head->nr_hw_descs; i++) axi_chan_dump_lli(chan, &desc_head->hw_desc[i]); } From 2a9013c20c46216b92ff09e2283b5244a91c59da Mon Sep 17 00:00:00 2001 From: Jia Wang Date: Wed, 2 Sep 2026 17:26:13 +0800 Subject: [PATCH 051/149] dmaengine: dw-axi-dmac: Fix CH_CFG2 channel priority position The CH_CFG2 channel priority field occupies bits 51:47 of the 64-bit channel configuration register, corresponding to bits 19:15 of CH_CFG2_H. The driver currently shifts the priority value by 20, programming the wrong bits. Use bit 15 as the field position. Fixes: 824351668a41 ("dmaengine: dw-axi-dmac: support DMAX_NUM_CHANNELS > 8") Signed-off-by: Jia Wang Reviewed-by: Frank Li Link: https://patch.msgid.link/20260902-dma-fix-v3-3-414c6449fbcc@ultrarisc.com Signed-off-by: Vinod Koul --- drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h index 039316c42f05..da706bff3f12 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h @@ -326,7 +326,7 @@ enum { #define CH_CFG2_H_TT_FC_POS 0 #define CH_CFG2_H_HS_SEL_SRC_POS 3 #define CH_CFG2_H_HS_SEL_DST_POS 4 -#define CH_CFG2_H_PRIORITY_POS 20 +#define CH_CFG2_H_PRIORITY_POS 15 /** * DW AXI DMA channel interrupts From a72f75e1f5552df8765920b678a9037b7f31a91c Mon Sep 17 00:00:00 2001 From: Jia Wang Date: Wed, 2 Sep 2026 17:26:14 +0800 Subject: [PATCH 052/149] dmaengine: dw-axi-dmac: Use bitfield helpers for registers The driver open-codes several channel configuration and descriptor control bitfield writes with left shifts. Define masks for those fields and use FIELD_PREP() when programming the registers. Valid field values keep the same encoding. FIELD_PREP() confines values to their respective fields, but does not validate handshake numbers supplied through DMA specifiers. Suggested-by: Frank Li Signed-off-by: Jia Wang Reviewed-by: Frank Li Link: https://patch.msgid.link/20260902-dma-fix-v3-4-414c6449fbcc@ultrarisc.com Signed-off-by: Vinod Koul --- .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 75 ++++++++++--------- drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 44 +++++------ 2 files changed, 61 insertions(+), 58 deletions(-) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c index 2d7d49017002..8baf303a314d 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -7,6 +7,7 @@ * Author: Eugeniy Paltsev */ +#include #include #include #include @@ -101,23 +102,25 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan, { u32 cfg_lo, cfg_hi; - cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS | - config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS); if (chan->chip->dw->hdata->reg_map_8_channels && !chan->chip->dw->hdata->use_cfg2) { - cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS | - config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS | - config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS | - config->src_per << CH_CFG_H_SRC_PER_POS | - config->dst_per << CH_CFG_H_DST_PER_POS | - config->prior << CH_CFG_H_PRIORITY_POS; + cfg_lo = FIELD_PREP(CH_CFG_L_DST_MULTBLK_TYPE, config->dst_multblk_type) | + FIELD_PREP(CH_CFG_L_SRC_MULTBLK_TYPE, config->src_multblk_type); + cfg_hi = FIELD_PREP(CH_CFG_H_TT_FC, config->tt_fc) | + FIELD_PREP(CH_CFG_H_HS_SEL_SRC, config->hs_sel_src) | + FIELD_PREP(CH_CFG_H_HS_SEL_DST, config->hs_sel_dst) | + FIELD_PREP(CH_CFG_H_SRC_PER, config->src_per) | + FIELD_PREP(CH_CFG_H_DST_PER, config->dst_per) | + FIELD_PREP(CH_CFG_H_PRIORITY, config->prior); } else { - cfg_lo |= config->src_per << CH_CFG2_L_SRC_PER_POS | - config->dst_per << CH_CFG2_L_DST_PER_POS; - cfg_hi = config->tt_fc << CH_CFG2_H_TT_FC_POS | - config->hs_sel_src << CH_CFG2_H_HS_SEL_SRC_POS | - config->hs_sel_dst << CH_CFG2_H_HS_SEL_DST_POS | - config->prior << CH_CFG2_H_PRIORITY_POS; + cfg_lo = FIELD_PREP(CH_CFG_L_DST_MULTBLK_TYPE, config->dst_multblk_type) | + FIELD_PREP(CH_CFG_L_SRC_MULTBLK_TYPE, config->src_multblk_type) | + FIELD_PREP(CH_CFG2_L_SRC_PER, config->src_per) | + FIELD_PREP(CH_CFG2_L_DST_PER, config->dst_per); + cfg_hi = FIELD_PREP(CH_CFG2_H_TT_FC, config->tt_fc) | + FIELD_PREP(CH_CFG2_H_HS_SEL_SRC, config->hs_sel_src) | + FIELD_PREP(CH_CFG2_H_HS_SEL_DST, config->hs_sel_dst) | + FIELD_PREP(CH_CFG2_H_PRIORITY, config->prior); } axi_chan_iowrite32(chan, CH_CFG_L, cfg_lo); axi_chan_iowrite32(chan, CH_CFG_H, cfg_hi); @@ -677,19 +680,19 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan, case DMA_MEM_TO_DEV: reg_width = __ffs(chan->config.dst_addr_width); device_addr = chan->config.dst_addr; - ctllo = reg_width << CH_CTL_L_DST_WIDTH_POS | - mem_width << CH_CTL_L_SRC_WIDTH_POS | - DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS | - DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS; + ctllo = FIELD_PREP(CH_CTL_L_DST_WIDTH, reg_width) | + FIELD_PREP(CH_CTL_L_SRC_WIDTH, mem_width) | + FIELD_PREP(CH_CTL_L_DST_INC, DWAXIDMAC_CH_CTL_L_NOINC) | + FIELD_PREP(CH_CTL_L_SRC_INC, DWAXIDMAC_CH_CTL_L_INC); block_ts = len >> mem_width; break; case DMA_DEV_TO_MEM: reg_width = __ffs(chan->config.src_addr_width); device_addr = chan->config.src_addr; - ctllo = reg_width << CH_CTL_L_SRC_WIDTH_POS | - mem_width << CH_CTL_L_DST_WIDTH_POS | - DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS | - DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS; + ctllo = FIELD_PREP(CH_CTL_L_SRC_WIDTH, reg_width) | + FIELD_PREP(CH_CTL_L_DST_WIDTH, mem_width) | + FIELD_PREP(CH_CTL_L_DST_INC, DWAXIDMAC_CH_CTL_L_INC) | + FIELD_PREP(CH_CTL_L_SRC_INC, DWAXIDMAC_CH_CTL_L_NOINC); block_ts = len >> reg_width; break; default: @@ -708,8 +711,8 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan, if (chan->chip->dw->hdata->restrict_axi_burst_len) { burst_len = chan->chip->dw->hdata->axi_rw_burst_len - 1; ctlhi |= CH_CTL_H_ARLEN_EN | CH_CTL_H_AWLEN_EN | - burst_len << CH_CTL_H_ARLEN_POS | - burst_len << CH_CTL_H_AWLEN_POS; + FIELD_PREP(CH_CTL_H_ARLEN, burst_len) | + FIELD_PREP(CH_CTL_H_AWLEN, burst_len); } hw_desc->lli->ctl_hi = cpu_to_le32(ctlhi); @@ -724,8 +727,8 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan, hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1); - ctllo |= DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS | - DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS; + ctllo |= FIELD_PREP(CH_CTL_L_DST_MSIZE, DWAXIDMAC_BURST_TRANS_LEN_4) | + FIELD_PREP(CH_CTL_L_SRC_MSIZE, DWAXIDMAC_BURST_TRANS_LEN_4); hw_desc->lli->ctl_lo = cpu_to_le32(ctllo); set_desc_src_master(hw_desc); @@ -977,19 +980,19 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr, if (chan->chip->dw->hdata->restrict_axi_burst_len) { u32 burst_len = chan->chip->dw->hdata->axi_rw_burst_len - 1; - reg |= (CH_CTL_H_ARLEN_EN | - burst_len << CH_CTL_H_ARLEN_POS | - CH_CTL_H_AWLEN_EN | - burst_len << CH_CTL_H_AWLEN_POS); + reg |= CH_CTL_H_ARLEN_EN | + FIELD_PREP(CH_CTL_H_ARLEN, burst_len) | + CH_CTL_H_AWLEN_EN | + FIELD_PREP(CH_CTL_H_AWLEN, burst_len); } hw_desc->lli->ctl_hi = cpu_to_le32(reg); - reg = (DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS | - DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS | - xfer_width << CH_CTL_L_DST_WIDTH_POS | - xfer_width << CH_CTL_L_SRC_WIDTH_POS | - DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS | - DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS); + reg = FIELD_PREP(CH_CTL_L_DST_MSIZE, DWAXIDMAC_BURST_TRANS_LEN_4) | + FIELD_PREP(CH_CTL_L_SRC_MSIZE, DWAXIDMAC_BURST_TRANS_LEN_4) | + FIELD_PREP(CH_CTL_L_DST_WIDTH, xfer_width) | + FIELD_PREP(CH_CTL_L_SRC_WIDTH, xfer_width) | + FIELD_PREP(CH_CTL_L_DST_INC, DWAXIDMAC_CH_CTL_L_INC) | + FIELD_PREP(CH_CTL_L_SRC_INC, DWAXIDMAC_CH_CTL_L_INC); hw_desc->lli->ctl_lo = cpu_to_le32(reg); set_desc_src_master(hw_desc); diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h index da706bff3f12..ec83acd12a9b 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h @@ -233,9 +233,9 @@ static inline struct axi_dma_chan *dchan_to_axi_dma_chan(struct dma_chan *dchan) /* CH_CTL_H */ #define CH_CTL_H_ARLEN_EN BIT(6) -#define CH_CTL_H_ARLEN_POS 7 +#define CH_CTL_H_ARLEN GENMASK(14, 7) #define CH_CTL_H_AWLEN_EN BIT(15) -#define CH_CTL_H_AWLEN_POS 16 +#define CH_CTL_H_AWLEN GENMASK(23, 16) enum { DWAXIDMAC_ARWLEN_1 = 0, @@ -257,8 +257,8 @@ enum { /* CH_CTL_L */ #define CH_CTL_L_LAST_WRITE_EN BIT(30) -#define CH_CTL_L_DST_MSIZE_POS 18 -#define CH_CTL_L_SRC_MSIZE_POS 14 +#define CH_CTL_L_DST_MSIZE GENMASK(21, 18) +#define CH_CTL_L_SRC_MSIZE GENMASK(17, 14) enum { DWAXIDMAC_BURST_TRANS_LEN_1 = 0, @@ -273,11 +273,11 @@ enum { DWAXIDMAC_BURST_TRANS_LEN_1024 }; -#define CH_CTL_L_DST_WIDTH_POS 11 -#define CH_CTL_L_SRC_WIDTH_POS 8 +#define CH_CTL_L_DST_WIDTH GENMASK(13, 11) +#define CH_CTL_L_SRC_WIDTH GENMASK(10, 8) -#define CH_CTL_L_DST_INC_POS 6 -#define CH_CTL_L_SRC_INC_POS 4 +#define CH_CTL_L_DST_INC BIT(6) +#define CH_CTL_L_SRC_INC BIT(4) enum { DWAXIDMAC_CH_CTL_L_INC = 0, DWAXIDMAC_CH_CTL_L_NOINC @@ -287,17 +287,17 @@ enum { #define CH_CTL_L_SRC_MAST BIT(0) /* CH_CFG_H */ -#define CH_CFG_H_PRIORITY_POS 17 -#define CH_CFG_H_DST_PER_POS 12 -#define CH_CFG_H_SRC_PER_POS 7 -#define CH_CFG_H_HS_SEL_DST_POS 4 -#define CH_CFG_H_HS_SEL_SRC_POS 3 +#define CH_CFG_H_PRIORITY GENMASK(19, 17) +#define CH_CFG_H_DST_PER GENMASK(15, 12) +#define CH_CFG_H_SRC_PER GENMASK(10, 7) +#define CH_CFG_H_HS_SEL_DST BIT(4) +#define CH_CFG_H_HS_SEL_SRC BIT(3) enum { DWAXIDMAC_HS_SEL_HW = 0, DWAXIDMAC_HS_SEL_SW }; -#define CH_CFG_H_TT_FC_POS 0 +#define CH_CFG_H_TT_FC GENMASK(2, 0) enum { DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC = 0, DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC, @@ -310,8 +310,8 @@ enum { }; /* CH_CFG_L */ -#define CH_CFG_L_DST_MULTBLK_TYPE_POS 2 -#define CH_CFG_L_SRC_MULTBLK_TYPE_POS 0 +#define CH_CFG_L_DST_MULTBLK_TYPE GENMASK(3, 2) +#define CH_CFG_L_SRC_MULTBLK_TYPE GENMASK(1, 0) enum { DWAXIDMAC_MBLK_TYPE_CONTIGUOUS = 0, DWAXIDMAC_MBLK_TYPE_RELOAD, @@ -320,13 +320,13 @@ enum { }; /* CH_CFG2 */ -#define CH_CFG2_L_SRC_PER_POS 4 -#define CH_CFG2_L_DST_PER_POS 11 +#define CH_CFG2_L_SRC_PER GENMASK(9, 4) +#define CH_CFG2_L_DST_PER GENMASK(16, 11) -#define CH_CFG2_H_TT_FC_POS 0 -#define CH_CFG2_H_HS_SEL_SRC_POS 3 -#define CH_CFG2_H_HS_SEL_DST_POS 4 -#define CH_CFG2_H_PRIORITY_POS 15 +#define CH_CFG2_H_TT_FC GENMASK(2, 0) +#define CH_CFG2_H_HS_SEL_SRC BIT(3) +#define CH_CFG2_H_HS_SEL_DST BIT(4) +#define CH_CFG2_H_PRIORITY GENMASK(19, 15) /** * DW AXI DMA channel interrupts From d882935a2ca4457f6f446b02d7d08134cd9d4582 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Tue, 8 Sep 2026 14:26:07 -0700 Subject: [PATCH 053/149] dmaengine: at_hdmac: use devm_clk_get_enabled() Replace the devm_clk_get() + clk_prepare_enable() pair with devm_clk_get_enabled(), which handles enable/disable and the unprepare on driver detach automatically. This lets us drop the err_irq cleanup label and the clk_disable_unprepare() calls in probe error paths and at_dma_remove(). Assisted-by: opencode:big-pickle Signed-off-by: Rosen Penev Reviewed-by: Frank Li Link: https://patch.msgid.link/20260908212607.590224-1-rosenp@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/at_hdmac.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c index f4d0c72787d1..cae26ea890fa 100644 --- a/drivers/dma/at_hdmac.c +++ b/drivers/dma/at_hdmac.c @@ -1994,20 +1994,16 @@ static int __init at_dma_probe(struct platform_device *pdev) atdma->dma_device.cap_mask = plat_dat->cap_mask; atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1; - atdma->clk = devm_clk_get(&pdev->dev, "dma_clk"); + atdma->clk = devm_clk_get_enabled(&pdev->dev, "dma_clk"); if (IS_ERR(atdma->clk)) return PTR_ERR(atdma->clk); - err = clk_prepare_enable(atdma->clk); - if (err) - return err; - /* force dma off, just in case */ at_dma_off(atdma); err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma); if (err) - goto err_irq; + return err; platform_set_drvdata(pdev, atdma); @@ -2126,8 +2122,6 @@ static int __init at_dma_probe(struct platform_device *pdev) dma_pool_destroy(atdma->lli_pool); err_desc_pool_create: free_irq(irq, atdma); -err_irq: - clk_disable_unprepare(atdma->clk); return err; } @@ -2145,8 +2139,6 @@ static void at_dma_remove(struct platform_device *pdev) at_dma_cleanup_channels(atdma); dma_pool_destroy(atdma->memset_pool); dma_pool_destroy(atdma->lli_pool); - - clk_disable_unprepare(atdma->clk); } static void at_dma_shutdown(struct platform_device *pdev) From db1a748a3509da959c547689af40e8a064a19c6b Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Tue, 8 Sep 2026 14:33:34 -0700 Subject: [PATCH 054/149] dmaengine: bestcomm: ata: drop unused local variable 'inc' bcom_ata_init() declared and assigned a struct bcom_ata_inc *inc that was never read, tripping clang -Wunused-but-set-variable: drivers/dma/bestcomm/ata.c:58:23: error: variable 'inc' set but not used [-Werror,-Wunused-but-set-variable] 58 | struct bcom_ata_inc *inc; | ^ Drop the declaration and the bcom_task_inc() call that fed it. Signed-off-by: Rosen Penev Reviewed-by: Frank Li Link: https://patch.msgid.link/20260908213334.593584-1-rosenp@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/bestcomm/ata.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/dma/bestcomm/ata.c b/drivers/dma/bestcomm/ata.c index 502a45d76adc..40126f3f189e 100644 --- a/drivers/dma/bestcomm/ata.c +++ b/drivers/dma/bestcomm/ata.c @@ -55,7 +55,6 @@ bcom_ata_init(int queue_len, int maxbufsize) { struct bcom_task *tsk; struct bcom_ata_var *var; - struct bcom_ata_inc *inc; /* Prefetch breaks ATA DMA. Turn it off for ATA DMA */ bcom_disable_prefetch(); @@ -69,7 +68,6 @@ bcom_ata_init(int queue_len, int maxbufsize) bcom_ata_reset_bd(tsk); var = (struct bcom_ata_var *) bcom_task_var(tsk->tasknum); - inc = (struct bcom_ata_inc *) bcom_task_inc(tsk->tasknum); if (bcom_load_image(tsk->tasknum, bcom_ata_task)) { bcom_task_free(tsk); From 5d5f4b3407d6ec86e76d094c332301135f493636 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Wed, 9 Sep 2026 16:49:24 -0700 Subject: [PATCH 055/149] dmaengine: mv_xor: return descriptor to free pool on io_win failure When mv_xor_prep_dma_xor() allocates a descriptor slot and then mv_xor_add_io_win() fails in the source-address loop, the slot stays on the allocated list and is never reclaimed, leaking a descriptor resource. Return the slot to the free pool under the channel lock before returning NULL on failure. Assisted-by: opencode:big-pickle Signed-off-by: Rosen Penev Reviewed-by: Frank Li Link: https://patch.msgid.link/20260909234924.103418-1-rosenp@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/mv_xor.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c index 25ed61f1b089..dd4f150d5fb1 100644 --- a/drivers/dma/mv_xor.c +++ b/drivers/dma/mv_xor.c @@ -583,8 +583,13 @@ mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, while (src_cnt--) { /* Check if a new window needs to get added for 'src' */ ret = mv_xor_add_io_win(mv_chan, src[src_cnt]); - if (ret) + if (ret) { + spin_lock_bh(&mv_chan->lock); + list_move_tail(&sw_desc->node, + &mv_chan->free_slots); + spin_unlock_bh(&mv_chan->lock); return NULL; + } mv_desc_set_src_addr(sw_desc, src_cnt, src[src_cnt]); } } From 62fb4a3a59223abb4d7baa3e088169767a28d551 Mon Sep 17 00:00:00 2001 From: Devendra K Verma Date: Mon, 7 Sep 2026 15:42:12 +0530 Subject: [PATCH 056/149] dmaengine: dw-edma: Enable Chan Separation via VSEC As per, 'Designware Cores PCI Express DM Controller - Reference Manual', section 3.2.34.3, VSEC for DEVICE INFORMATION supports the channel separation mechanisms. Basically, the HDMA IP allows the user to configure the separation between DMA channel registers and retrieve it via the VSEC capability mentioned above. HDMA IP supports the channel register space separation from 256B to 32KB. Default supported size is 256B. Signed-off-by: Devendra K Verma Reviewed-by: Frank Li Link: https://patch.msgid.link/20260907101213.1917064-2-devverma@amd.com Signed-off-by: Vinod Koul --- drivers/dma/dw-edma/dw-edma-pcie.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c index 9f237ba916de..07931b181785 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -33,6 +33,8 @@ #define DW_PCIE_XILINX_MDB_VSEC_ID 0x20 #define DW_PCIE_XILINX_MDB_VSEC_DMA_BAR GENMASK(10, 8) #define DW_PCIE_XILINX_MDB_VSEC_DMA_MAP GENMASK(2, 0) +/* AMD CPM6 (Xilinx) supported cap */ +#define DW_PCIE_XILINX_CPM6_VSEC_CH_SEP GENMASK(18, 16) #define DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH GENMASK(9, 0) #define DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH GENMASK(25, 16) @@ -76,6 +78,7 @@ struct dw_edma_pcie_data { u16 rd_ch_cnt; u64 devmem_phys_off; bool cfg_non_ll; + u32 ch_space_sz; }; struct dw_edma_pcie_match_data { @@ -208,6 +211,13 @@ static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr) return pci_irq_vector(to_pci_dev(dev), nr); } +static u32 dw_edma_get_ch_space_sz(u32 val) +{ + if (val > 0 && val <= 7) + return 256 << val; + return 256; +} + static u64 dw_edma_pcie_address(struct device *dev, phys_addr_t cpu_addr) { struct pci_dev *pdev = to_pci_dev(dev); @@ -298,6 +308,10 @@ static void dw_edma_pcie_get_xilinx_dma_data(struct pci_dev *pdev, pdata->mf = map; pdata->rg.bar = FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_BAR, val); + if (pdev->device == PCI_DEVICE_ID_XILINX_B00F) + pdata->ch_space_sz = dw_edma_get_ch_space_sz + (FIELD_GET(DW_PCIE_XILINX_CPM6_VSEC_CH_SEP, val)); + pci_read_config_dword(pdev, vsec + 0xc, &val); pdata->wr_ch_cnt = min(pdata->wr_ch_cnt, FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH, val)); From ff4dc66e80d2c31138a9ca31f1a4340dc4919d50 Mon Sep 17 00:00:00 2001 From: Devendra K Verma Date: Mon, 7 Sep 2026 15:42:13 +0530 Subject: [PATCH 057/149] dmaengine: dw-edma: Add changes to support Channel Separation HDMA supports configurable DMA channel register space separation which ranges from 256B to 32KB. Current implementation supports 256B as default for DMA channel register space. CPM6 supports the selection of channel register space via VSEC. The default value for channel register space for CPM6 is 512B. Updated the functions and methods to calculate the DMA channel registers base address as per the selected channel separation available as part of 'ch_space_sz'. Removed the unused function __dw_regs() and structs, namely dw_hdma_v0_ch and dw_hdma_v0_regs. Signed-off-by: Devendra K Verma Reviewed-by: Frank Li Link: https://patch.msgid.link/20260907101213.1917064-3-devverma@amd.com Signed-off-by: Vinod Koul --- drivers/dma/dw-edma/dw-edma-pcie.c | 4 ++++ drivers/dma/dw-edma/dw-hdma-v0-core.c | 23 ++++++++++++-------- drivers/dma/dw-edma/dw-hdma-v0-debugfs.c | 17 +++++---------- drivers/dma/dw-edma/dw-hdma-v0-regs.h | 10 --------- drivers/pci/controller/dwc/pcie-designware.c | 1 + include/linux/dma/edma.h | 1 + 6 files changed, 26 insertions(+), 30 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c index 07931b181785..fab4faf68b77 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -133,6 +133,7 @@ static const struct dw_edma_pcie_data snps_edda_data = { .irqs = 1, .wr_ch_cnt = 2, .rd_ch_cnt = 2, + .ch_space_sz = 256, }; static const struct dw_edma_pcie_data xilinx_mdb_data = { @@ -146,6 +147,7 @@ static const struct dw_edma_pcie_data xilinx_mdb_data = { .irqs = 1, .wr_ch_cnt = 8, .rd_ch_cnt = 8, + .ch_space_sz = 256, }; static const struct dw_edma_pcie_data xilinx_cpm6_dma_data = { @@ -159,6 +161,7 @@ static const struct dw_edma_pcie_data xilinx_cpm6_dma_data = { .irqs = 1, .wr_ch_cnt = 8, .rd_ch_cnt = 8, + .ch_space_sz = 512, }; static void dw_edma_set_chan_region_offset(struct dw_edma_pcie_data *pdata, @@ -491,6 +494,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, chip->nr_irqs = nr_irqs; chip->ops = match->plat_ops; chip->cfg_non_ll = dma_data->cfg_non_ll; + chip->ch_space_sz = dma_data->ch_space_sz; chip->ll_wr_cnt = dma_data->wr_ch_cnt; chip->ll_rd_cnt = dma_data->rd_ch_cnt; diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c index 0b3c8496b0ad..d42cb4ad49a2 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -23,18 +23,23 @@ enum dw_hdma_control { DW_HDMA_V0_LLE = BIT(9), }; -static inline struct dw_hdma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) -{ - return dw->chip->reg_base; -} - static inline struct dw_hdma_v0_ch_regs __iomem * __dw_ch_regs(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch) { - if (dir == EDMA_DIR_WRITE) - return &(__dw_regs(dw)->ch[ch].wr); - else - return &(__dw_regs(dw)->ch[ch].rd); + u32 ch_base; + + /* + * For Write, the channel register index starts at + * wr_base(ch_idx) = (2 * ch_idx) * ch_space_sz + * + * For Read channel, + * rd_base(ch_idx) = (2 * ch_idx + 1) * ch_space_sz + */ + ch_base = 2 * ch; + if (dir == EDMA_DIR_READ) + ch_base += 1; + + return dw->chip->reg_base + (ch_base * dw->chip->ch_space_sz); } #define SET_CH_32(dw, dir, ch, name, value) \ diff --git a/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c b/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c index dcdc57fe976c..3fa16e045a58 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c @@ -13,22 +13,17 @@ #include "dw-hdma-v0-regs.h" #include "dw-edma-core.h" -#define REGS_ADDR(dw, name) \ - ({ \ - struct dw_hdma_v0_regs __iomem *__regs = (dw)->chip->reg_base; \ - \ - (void __iomem *)&__regs->name; \ - }) - #define REGS_CH_ADDR(dw, name, _dir, _ch) \ ({ \ - struct dw_hdma_v0_ch_regs __iomem *__ch_regs; \ + struct dw_hdma_v0_ch_regs __iomem *__ch_regs; \ + off_t __off = (dw)->chip->ch_space_sz; \ \ - if (_dir == EDMA_DIR_READ) \ - __ch_regs = REGS_ADDR(dw, ch[_ch].rd); \ + if ((_dir) == EDMA_DIR_READ) \ + __off *= (2 * (_ch) + 1); \ else \ - __ch_regs = REGS_ADDR(dw, ch[_ch].wr); \ + __off *= (2 * (_ch)); \ \ + __ch_regs = ((dw)->chip->reg_base + __off); \ (void __iomem *)&__ch_regs->name; \ }) diff --git a/drivers/dma/dw-edma/dw-hdma-v0-regs.h b/drivers/dma/dw-edma/dw-hdma-v0-regs.h index 2124c162a62f..b88226cdd791 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-regs.h +++ b/drivers/dma/dw-edma/dw-hdma-v0-regs.h @@ -85,16 +85,6 @@ struct dw_hdma_v0_ch_regs { }; } msi_abort; u32 msi_msgdata; /* 0x00a8 */ - u32 padding_2[21]; /* 0x00ac..0x00fc */ -} __packed; - -struct dw_hdma_v0_ch { - struct dw_hdma_v0_ch_regs wr; /* 0x0000 */ - struct dw_hdma_v0_ch_regs rd; /* 0x0100 */ -} __packed; - -struct dw_hdma_v0_regs { - struct dw_hdma_v0_ch ch[HDMA_V0_MAX_NR_CH]; /* 0x0000..0x0fa8 */ } __packed; struct dw_hdma_v0_lli { diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 593388f29bdd..ea29c9833491 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -1039,6 +1039,7 @@ static void dw_pcie_edma_init_data(struct dw_pcie *pci) pci->edma.ops = &dw_pcie_edma_ops; pci->edma.flags |= DW_EDMA_CHIP_LOCAL; + pci->edma.ch_space_sz = 256; } static int dw_pcie_edma_find_mf(struct dw_pcie *pci) diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index a4e5aab8fddc..affd896563a1 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -147,6 +147,7 @@ struct dw_edma_chip { struct dw_edma *dw; bool cfg_non_ll; + u32 ch_space_sz; }; /* Export to the platform drivers */ From 75d8640d7f5f89d1a1c39ccb72166ada95fb38d2 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 9 Sep 2026 12:22:28 -0400 Subject: [PATCH 058/149] dmaengine: vchan: add vchan_chan_name() to get channel device name Introduce vchan_chan_name() to obtain the DMA channel device name. Use a dedicated helper instead of directly accessing dma_chan::dev so callers remain unaffected by an upcoming rename of the struct member. Reviewed-by: Logan Gunthorpe Reviewed-by: Amelie Delaunay # For STM32 Reviewed-by: Andy Shevchenko Signed-off-by: Frank Li Link: https://patch.msgid.link/20260909-dma-chan_dev-rename-v4-1-d8fb6892a70f@nxp.com Signed-off-by: Vinod Koul --- drivers/dma/arm-dma350.c | 2 +- drivers/dma/loongson/loongson2-apb-cmc-dma.c | 2 +- drivers/dma/stm32/stm32-dma.c | 2 +- drivers/dma/stm32/stm32-dma3.c | 4 ++-- drivers/dma/virt-dma.h | 11 +++++++++++ 5 files changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c index 09403aca8bb0..52f5242ea332 100644 --- a/drivers/dma/arm-dma350.c +++ b/drivers/dma/arm-dma350.c @@ -512,7 +512,7 @@ static int d350_alloc_chan_resources(struct dma_chan *chan) { struct d350_chan *dch = to_d350_chan(chan); int ret = request_irq(dch->irq, d350_irq, IRQF_SHARED, - dev_name(&dch->vc.chan.dev->device), dch); + vchan_chan_name(&dch->vc), dch); if (!ret) writel_relaxed(CH_INTREN_DONE | CH_INTREN_ERR, dch->base + CH_INTREN); diff --git a/drivers/dma/loongson/loongson2-apb-cmc-dma.c b/drivers/dma/loongson/loongson2-apb-cmc-dma.c index 969dbc5dabe7..ed69688c8c05 100644 --- a/drivers/dma/loongson/loongson2-apb-cmc-dma.c +++ b/drivers/dma/loongson/loongson2-apb-cmc-dma.c @@ -678,7 +678,7 @@ static int loongson2_cmc_dma_probe(struct platform_device *pdev) return lchan->irq; ret = devm_request_irq(dev, lchan->irq, loongson2_cmc_dma_chan_irq, IRQF_SHARED, - dev_name(chan2dev(lchan)), lchan); + vchan_chan_name(&lchan->vchan), lchan); if (ret) return ret; } diff --git a/drivers/dma/stm32/stm32-dma.c b/drivers/dma/stm32/stm32-dma.c index d3ad78562a14..3e8151e2ad75 100644 --- a/drivers/dma/stm32/stm32-dma.c +++ b/drivers/dma/stm32/stm32-dma.c @@ -1668,7 +1668,7 @@ static int stm32_dma_probe(struct platform_device *pdev) ret = devm_request_irq(&pdev->dev, chan->irq, stm32_dma_chan_irq, 0, - dev_name(chan2dev(chan)), chan); + vchan_chan_name(&chan->vchan), chan); if (ret) { dev_err(&pdev->dev, "request_irq failed with err %d channel %d\n", diff --git a/drivers/dma/stm32/stm32-dma3.c b/drivers/dma/stm32/stm32-dma3.c index 4724e7fa0008..1ee1bd22703f 100644 --- a/drivers/dma/stm32/stm32-dma3.c +++ b/drivers/dma/stm32/stm32-dma3.c @@ -1892,10 +1892,10 @@ static int stm32_dma3_probe(struct platform_device *pdev) chan->irq = ret; ret = devm_request_irq(&pdev->dev, chan->irq, stm32_dma3_chan_irq, 0, - dev_name(chan2dev(chan)), chan); + vchan_chan_name(&chan->vchan), chan); if (ret) { dev_err_probe(&pdev->dev, ret, "Failed to request channel %s IRQ\n", - dev_name(chan2dev(chan))); + vchan_chan_name(&chan->vchan)); goto err_clk_disable; } } diff --git a/drivers/dma/virt-dma.h b/drivers/dma/virt-dma.h index 59d9eabc8b67..dd023a383120 100644 --- a/drivers/dma/virt-dma.h +++ b/drivers/dma/virt-dma.h @@ -209,6 +209,17 @@ static inline void vchan_free_chan_resources(struct virt_dma_chan *vc) vchan_dma_desc_free_list(vc, &head); } +/** + * vchan_chan_name - Return vchan DMA channel device name + * @vc: virtual channel + * + * Return: The name of the DMA channel device + */ +static inline const char *vchan_chan_name(struct virt_dma_chan *vc) +{ + return dma_chan_name(&vc->chan); +} + /** * vchan_synchronize() - synchronize callback execution to the current context * @vc: virtual channel to synchronize From 76574306c1ac38137683c69407f0e7810f407e4d Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 9 Sep 2026 12:22:29 -0400 Subject: [PATCH 059/149] dmaengine: use dma_chan_name() helper to get per-channel device name Use the existing dma_chan_name() helper to obtain the per-channel device name instead of open-coding: dev_name(chan->dev->device) / dev_name(chan2dev()). Simplify the code, improve consistency and reduce line wrapping where possible. No functional change intended. Reviewed-by: Logan Gunthorpe Reviewed-by: Amelie Delaunay # For STM32 Reviewed-by: Andy Shevchenko Signed-off-by: Frank Li Link: https://patch.msgid.link/20260909-dma-chan_dev-rename-v4-2-d8fb6892a70f@nxp.com Signed-off-by: Vinod Koul --- drivers/dma/dma-jz4780.c | 2 +- drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 3 +-- drivers/dma/idma64.c | 3 +-- drivers/dma/loongson/loongson2-apb-dma.c | 2 +- drivers/dma/mmp_pdma.c | 3 +-- drivers/dma/st_fdma.c | 2 +- drivers/dma/stm32/stm32-dma3.c | 2 +- drivers/dma/stm32/stm32-mdma.c | 3 +-- include/trace/events/tegra_apb_dma.h | 6 +++--- 9 files changed, 11 insertions(+), 15 deletions(-) diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c index 6070dfdb7114..194649811d02 100644 --- a/drivers/dma/dma-jz4780.c +++ b/drivers/dma/dma-jz4780.c @@ -760,7 +760,7 @@ static int jz4780_dma_alloc_chan_resources(struct dma_chan *chan) { struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); - jzchan->desc_pool = dma_pool_create(dev_name(&chan->dev->device), + jzchan->desc_pool = dma_pool_create(dma_chan_name(chan), chan->device->dev, JZ_DMA_DESC_BLOCK_SIZE, PAGE_SIZE, 0); diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c index 8baf303a314d..6e63dfe9d641 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -534,8 +534,7 @@ static int dma_chan_alloc_chan_resources(struct dma_chan *dchan) } /* LLI address must be aligned to a 64-byte boundary */ - chan->desc_pool = dma_pool_create(dev_name(chan2dev(chan)), - chan->chip->dev, + chan->desc_pool = dma_pool_create(dma_chan_name(dchan), chan->chip->dev, sizeof(struct axi_dma_lli), 64, 0); if (!chan->desc_pool) { diff --git a/drivers/dma/idma64.c b/drivers/dma/idma64.c index 5fcd1befc92d..e1fcce07d1c1 100644 --- a/drivers/dma/idma64.c +++ b/drivers/dma/idma64.c @@ -507,8 +507,7 @@ static int idma64_alloc_chan_resources(struct dma_chan *chan) struct idma64_chan *idma64c = to_idma64_chan(chan); /* Create a pool of consistent memory blocks for hardware descriptors */ - idma64c->pool = dma_pool_create(dev_name(chan2dev(chan)), - chan->device->dev, + idma64c->pool = dma_pool_create(dma_chan_name(chan), chan->device->dev, sizeof(struct idma64_lli), 8, 0); if (!idma64c->pool) { dev_err(chan2dev(chan), "No memory for descriptors\n"); diff --git a/drivers/dma/loongson/loongson2-apb-dma.c b/drivers/dma/loongson/loongson2-apb-dma.c index aceb069e71fc..7c3d7c327395 100644 --- a/drivers/dma/loongson/loongson2-apb-dma.c +++ b/drivers/dma/loongson/loongson2-apb-dma.c @@ -282,7 +282,7 @@ static int ls2x_dma_alloc_chan_resources(struct dma_chan *chan) struct ls2x_dma_chan *lchan = to_ldma_chan(chan); /* Create a pool of consistent memory blocks for hardware descriptors */ - lchan->pool = dma_pool_create(dev_name(chan2dev(chan)), + lchan->pool = dma_pool_create(dma_chan_name(chan), chan->device->dev, PAGE_SIZE, __alignof__(struct ls2x_dma_hw_desc), 0); if (!lchan->pool) { diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c index 386e85cd4882..863160de3b7d 100644 --- a/drivers/dma/mmp_pdma.c +++ b/drivers/dma/mmp_pdma.c @@ -565,8 +565,7 @@ static int mmp_pdma_alloc_chan_resources(struct dma_chan *dchan) if (chan->desc_pool) return 1; - chan->desc_pool = dma_pool_create(dev_name(&dchan->dev->device), - chan->dev, + chan->desc_pool = dma_pool_create(dma_chan_name(dchan), chan->dev, sizeof(struct mmp_pdma_desc_sw), __alignof__(struct mmp_pdma_desc_sw), 0); diff --git a/drivers/dma/st_fdma.c b/drivers/dma/st_fdma.c index d9547017f3bd..35dbff5f9f1a 100644 --- a/drivers/dma/st_fdma.c +++ b/drivers/dma/st_fdma.c @@ -268,7 +268,7 @@ static int st_fdma_alloc_chan_res(struct dma_chan *chan) struct st_fdma_chan *fchan = to_st_fdma_chan(chan); /* Create the dma pool for descriptor allocation */ - fchan->node_pool = dma_pool_create(dev_name(&chan->dev->device), + fchan->node_pool = dma_pool_create(dma_chan_name(chan), fchan->fdev->dev, sizeof(struct st_fdma_hw_node), __alignof__(struct st_fdma_hw_node), diff --git a/drivers/dma/stm32/stm32-dma3.c b/drivers/dma/stm32/stm32-dma3.c index 1ee1bd22703f..6ee7a1435efb 100644 --- a/drivers/dma/stm32/stm32-dma3.c +++ b/drivers/dma/stm32/stm32-dma3.c @@ -1126,7 +1126,7 @@ static int stm32_dma3_alloc_chan_resources(struct dma_chan *c) goto err_put_sync; } - chan->lli_pool = dmam_pool_create(dev_name(&c->dev->device), c->device->dev, + chan->lli_pool = dmam_pool_create(dma_chan_name(c), c->device->dev, sizeof(struct stm32_dma3_hwdesc), __alignof__(struct stm32_dma3_hwdesc), SZ_64K); if (!chan->lli_pool) { diff --git a/drivers/dma/stm32/stm32-mdma.c b/drivers/dma/stm32/stm32-mdma.c index e3bbdc9ee36e..c6dc8a9a7a28 100644 --- a/drivers/dma/stm32/stm32-mdma.c +++ b/drivers/dma/stm32/stm32-mdma.c @@ -1484,8 +1484,7 @@ static int stm32_mdma_alloc_chan_resources(struct dma_chan *c) struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan); int ret; - chan->desc_pool = dmam_pool_create(dev_name(&c->dev->device), - c->device->dev, + chan->desc_pool = dmam_pool_create(dma_chan_name(c), c->device->dev, sizeof(struct stm32_mdma_hwdesc), __alignof__(struct stm32_mdma_hwdesc), 0); diff --git a/include/trace/events/tegra_apb_dma.h b/include/trace/events/tegra_apb_dma.h index 6d9f5075baa3..c38117c127ef 100644 --- a/include/trace/events/tegra_apb_dma.h +++ b/include/trace/events/tegra_apb_dma.h @@ -11,7 +11,7 @@ TRACE_EVENT(tegra_dma_tx_status, TP_PROTO(struct dma_chan *dc, dma_cookie_t cookie, struct dma_tx_state *state), TP_ARGS(dc, cookie, state), TP_STRUCT__entry( - __string(chan, dev_name(&dc->dev->device)) + __string(chan, dma_chan_name(dc)) __field(dma_cookie_t, cookie) __field(__u32, residue) ), @@ -28,7 +28,7 @@ TRACE_EVENT(tegra_dma_complete_cb, TP_PROTO(struct dma_chan *dc, int count, void *ptr), TP_ARGS(dc, count, ptr), TP_STRUCT__entry( - __string(chan, dev_name(&dc->dev->device)) + __string(chan, dma_chan_name(dc)) __field(int, count) __field(void *, ptr) ), @@ -45,7 +45,7 @@ TRACE_EVENT(tegra_dma_isr, TP_PROTO(struct dma_chan *dc, int irq), TP_ARGS(dc, irq), TP_STRUCT__entry( - __string(chan, dev_name(&dc->dev->device)) + __string(chan, dma_chan_name(dc)) __field(int, irq) ), TP_fast_assign( From 3b97a3ec420542591c10db8600cf481f1038a011 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 9 Sep 2026 12:22:30 -0400 Subject: [PATCH 060/149] dmaengine: add (dmaengine|vchan)_chan_dev() helper Add a new helper function (dmaengine|vchan)_chan_dev() to access the DMA channel device embedded in struct dma_chan_dev (chan->dev->device). This provides a cleaner API instead of open-coding &chan->dev->device throughout the drivers. Replay private chan2dev() and dchan2dev() with this new common APIs in indivial DMA engine drivers. Prepare rename dma_chan::dev field. Reviewed-by: Andy Shevchenko Signed-off-by: Frank Li Link: https://patch.msgid.link/20260909-dma-chan_dev-rename-v4-3-d8fb6892a70f@nxp.com Signed-off-by: Vinod Koul --- drivers/dma/at_hdmac.c | 81 +++++---- drivers/dma/at_xdmac.c | 159 +++++++++--------- drivers/dma/dma-jz4780.c | 8 +- drivers/dma/dmaengine.c | 20 +-- .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 36 ++-- drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 10 -- drivers/dma/dw/core.c | 47 +++--- drivers/dma/ep93xx_dma.c | 37 ++-- drivers/dma/idma64.c | 7 +- drivers/dma/loongson/loongson1-apb-dma.c | 23 +-- drivers/dma/loongson/loongson2-apb-cmc-dma.c | 15 +- drivers/dma/loongson/loongson2-apb-dma.c | 7 +- drivers/dma/moxart-dma.c | 23 +-- drivers/dma/nbpfaxi.c | 2 +- drivers/dma/owl-dma.c | 21 +-- drivers/dma/pch_dma.c | 41 ++--- drivers/dma/pxa_dma.c | 52 +++--- drivers/dma/ste_dma40.c | 15 +- drivers/dma/stm32/stm32-dma.c | 67 ++++---- drivers/dma/stm32/stm32-dma3.c | 93 +++++----- drivers/dma/stm32/stm32-mdma.c | 93 +++++----- drivers/dma/sun4i-dma.c | 17 +- drivers/dma/sun6i-dma.c | 31 ++-- drivers/dma/switchtec_dma.c | 14 +- drivers/dma/tegra186-gpc-dma.c | 2 +- drivers/dma/tegra20-apb-dma.c | 2 +- drivers/dma/ti/k3-udma.c | 2 +- drivers/dma/timb_dma.c | 63 ++++--- drivers/dma/txx9dmac.c | 73 ++++---- drivers/dma/virt-dma.h | 5 + include/linux/dmaengine.h | 7 +- 31 files changed, 489 insertions(+), 584 deletions(-) diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c index cae26ea890fa..3fedc907db63 100644 --- a/drivers/dma/at_hdmac.c +++ b/drivers/dma/at_hdmac.c @@ -381,23 +381,18 @@ static inline struct at_dma *to_at_dma(struct dma_device *ddev) /*-- Helper functions ------------------------------------------------*/ -static struct device *chan2dev(struct dma_chan *chan) -{ - return &chan->dev->device; -} - #if defined(VERBOSE_DEBUG) static void vdbg_dump_regs(struct at_dma_chan *atchan) { struct at_dma *atdma = to_at_dma(atchan->vc.chan.device); - dev_err(chan2dev(&atchan->vc.chan), + dev_err(vchan_chan_dev(&atchan->vc), " channel %d : imr = 0x%x, chsr = 0x%x\n", atchan->vc.chan.chan_id, dma_readl(atdma, EBCIMR), dma_readl(atdma, CHSR)); - dev_err(chan2dev(&atchan->vc.chan), + dev_err(vchan_chan_dev(&atchan->vc), " channel: s0x%x d0x%x ctrl0x%x:0x%x cfg0x%x l0x%x\n", channel_readl(atchan, SADDR), channel_readl(atchan, DADDR), @@ -412,7 +407,7 @@ static void vdbg_dump_regs(struct at_dma_chan *atchan) {} static void atc_dump_lli(struct at_dma_chan *atchan, struct at_lli *lli) { - dev_crit(chan2dev(&atchan->vc.chan), + dev_crit(vchan_chan_dev(&atchan->vc), "desc: s%pad d%pad ctrl0x%x:0x%x l%pad\n", &lli->saddr, &lli->daddr, lli->ctrla, lli->ctrlb, &lli->dscr); @@ -790,8 +785,8 @@ static void atc_handle_error(struct at_dma_chan *atchan, unsigned int i) * controller flagged an error instead of scribbling over * random memory locations. */ - dev_crit(chan2dev(&atchan->vc.chan), "Bad descriptor submitted for DMA!\n"); - dev_crit(chan2dev(&atchan->vc.chan), "cookie: %d\n", + dev_crit(vchan_chan_dev(&atchan->vc), "Bad descriptor submitted for DMA!\n"); + dev_crit(vchan_chan_dev(&atchan->vc), "cookie: %d\n", desc->vd.tx.cookie); for (i = 0; i < desc->sglen; i++) atc_dump_lli(atchan, desc->sg[i].lli); @@ -886,7 +881,7 @@ atc_prep_dma_interleaved(struct dma_chan *chan, first = xt->sgl; - dev_info(chan2dev(chan), + dev_info(dmaengine_chan_dev(chan), "%s: src=%pad, dest=%pad, numf=%zu, frame_size=%zu, flags=0x%lx\n", __func__, &xt->src_start, &xt->dst_start, xt->numf, xt->frame_size, flags); @@ -903,7 +898,7 @@ atc_prep_dma_interleaved(struct dma_chan *chan, if ((chunk->size != xt->sgl->size) || (dmaengine_get_dst_icg(xt, chunk) != dmaengine_get_dst_icg(xt, first)) || (dmaengine_get_src_icg(xt, chunk) != dmaengine_get_src_icg(xt, first))) { - dev_err(chan2dev(chan), + dev_err(dmaengine_chan_dev(chan), "%s: the controller can transfer only identical chunks\n", __func__); return NULL; @@ -916,7 +911,7 @@ atc_prep_dma_interleaved(struct dma_chan *chan, xfer_count = len >> dwidth; if (xfer_count > ATC_BTSIZE_MAX) { - dev_err(chan2dev(chan), "%s: buffer is too big\n", __func__); + dev_err(dmaengine_chan_dev(chan), "%s: buffer is too big\n", __func__); return NULL; } @@ -983,11 +978,11 @@ atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, u32 ctrla; u32 ctrlb; - dev_dbg(chan2dev(chan), "prep_dma_memcpy: d%pad s%pad l0x%zx f0x%lx\n", + dev_dbg(dmaengine_chan_dev(chan), "prep_dma_memcpy: d%pad s%pad l0x%zx f0x%lx\n", &dest, &src, len, flags); if (unlikely(!len)) { - dev_err(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); + dev_err(dmaengine_chan_dev(chan), "prep_dma_memcpy: length is zero!\n"); return NULL; } @@ -1062,7 +1057,7 @@ static int atdma_create_memset_lli(struct dma_chan *chan, xfer_count = len >> 2; if (xfer_count > ATC_BTSIZE_MAX) { - dev_err(chan2dev(chan), "%s: buffer is too big\n", __func__); + dev_err(dmaengine_chan_dev(chan), "%s: buffer is too big\n", __func__); return -EINVAL; } @@ -1102,23 +1097,23 @@ atc_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value, char fill_pattern; int ret; - dev_vdbg(chan2dev(chan), "%s: d%pad v0x%x l0x%zx f0x%lx\n", __func__, + dev_vdbg(dmaengine_chan_dev(chan), "%s: d%pad v0x%x l0x%zx f0x%lx\n", __func__, &dest, value, len, flags); if (unlikely(!len)) { - dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); + dev_dbg(dmaengine_chan_dev(chan), "%s: length is zero!\n", __func__); return NULL; } if (!is_dma_fill_aligned(chan->device, dest, 0, len)) { - dev_dbg(chan2dev(chan), "%s: buffer is not aligned\n", + dev_dbg(dmaengine_chan_dev(chan), "%s: buffer is not aligned\n", __func__); return NULL; } vaddr = dma_pool_alloc(atdma->memset_pool, GFP_NOWAIT, &paddr); if (!vaddr) { - dev_err(chan2dev(chan), "%s: couldn't allocate buffer\n", + dev_err(dmaengine_chan_dev(chan), "%s: couldn't allocate buffer\n", __func__); return NULL; } @@ -1174,18 +1169,18 @@ atc_prep_dma_memset_sg(struct dma_chan *chan, int i; int ret; - dev_vdbg(chan2dev(chan), "%s: v0x%x l0x%x f0x%lx\n", __func__, + dev_vdbg(dmaengine_chan_dev(chan), "%s: v0x%x l0x%x f0x%lx\n", __func__, value, sg_len, flags); if (unlikely(!sgl || !sg_len)) { - dev_dbg(chan2dev(chan), "%s: scatterlist is empty!\n", + dev_dbg(dmaengine_chan_dev(chan), "%s: scatterlist is empty!\n", __func__); return NULL; } vaddr = dma_pool_alloc(atdma->memset_pool, GFP_NOWAIT, &paddr); if (!vaddr) { - dev_err(chan2dev(chan), "%s: couldn't allocate buffer\n", + dev_err(dmaengine_chan_dev(chan), "%s: couldn't allocate buffer\n", __func__); return NULL; } @@ -1200,11 +1195,11 @@ atc_prep_dma_memset_sg(struct dma_chan *chan, dma_addr_t dest = sg_dma_address(sg); size_t len = sg_dma_len(sg); - dev_vdbg(chan2dev(chan), "%s: d%pad, l0x%zx\n", + dev_vdbg(dmaengine_chan_dev(chan), "%s: d%pad, l0x%zx\n", __func__, &dest, len); if (!is_dma_fill_aligned(chan->device, dest, 0, len)) { - dev_err(chan2dev(chan), "%s: buffer is not aligned\n", + dev_err(dmaengine_chan_dev(chan), "%s: buffer is not aligned\n", __func__); goto err_free_desc; } @@ -1264,13 +1259,13 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, struct scatterlist *sg; size_t total_len = 0; - dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n", + dev_vdbg(dmaengine_chan_dev(chan), "prep_slave_sg (%d): %s f0x%lx\n", sg_len, direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", flags); if (unlikely(!atslave || !sg_len)) { - dev_dbg(chan2dev(chan), "prep_slave_sg: sg length is zero!\n"); + dev_dbg(dmaengine_chan_dev(chan), "prep_slave_sg: sg length is zero!\n"); return NULL; } @@ -1310,7 +1305,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, mem = sg_dma_address(sg); len = sg_dma_len(sg); if (unlikely(!len)) { - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "prep_slave_sg: sg(%d) data length is zero\n", i); goto err; } @@ -1359,7 +1354,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, mem = sg_dma_address(sg); len = sg_dma_len(sg); if (unlikely(!len)) { - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "prep_slave_sg: sg(%d) data length is zero\n", i); goto err; } @@ -1392,7 +1387,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, return vchan_tx_prep(&atchan->vc, &desc->vd, flags); err_desc_get: - dev_err(chan2dev(chan), "not enough descriptors available\n"); + dev_err(dmaengine_chan_dev(chan), "not enough descriptors available\n"); err: atdma_desc_free(&desc->vd); return NULL; @@ -1503,19 +1498,19 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, unsigned int periods = buf_len / period_len; unsigned int i; - dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@%pad - %d (%zu/%zu)\n", + dev_vdbg(dmaengine_chan_dev(chan), "prep_dma_cyclic: %s buf@%pad - %d (%zu/%zu)\n", direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", &buf_addr, periods, buf_len, period_len); if (unlikely(!atslave || !buf_len || !period_len)) { - dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n"); + dev_dbg(dmaengine_chan_dev(chan), "prep_dma_cyclic: length is zero!\n"); return NULL; } was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status); if (was_cyclic) { - dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n"); + dev_dbg(dmaengine_chan_dev(chan), "prep_dma_cyclic: channel in use!\n"); return NULL; } @@ -1561,7 +1556,7 @@ static int atc_config(struct dma_chan *chan, { struct at_dma_chan *atchan = to_at_dma_chan(chan); - dev_vdbg(chan2dev(chan), "%s\n", __func__); + dev_vdbg(dmaengine_chan_dev(chan), "%s\n", __func__); /* Check if it is chan is configured for slave transfers */ if (!chan->private) @@ -1582,7 +1577,7 @@ static int atc_pause(struct dma_chan *chan) int chan_id = atchan->vc.chan.chan_id; unsigned long flags; - dev_vdbg(chan2dev(chan), "%s\n", __func__); + dev_vdbg(dmaengine_chan_dev(chan), "%s\n", __func__); spin_lock_irqsave(&atchan->vc.lock, flags); @@ -1601,7 +1596,7 @@ static int atc_resume(struct dma_chan *chan) int chan_id = atchan->vc.chan.chan_id; unsigned long flags; - dev_vdbg(chan2dev(chan), "%s\n", __func__); + dev_vdbg(dmaengine_chan_dev(chan), "%s\n", __func__); if (!atc_chan_is_paused(atchan)) return 0; @@ -1625,7 +1620,7 @@ static int atc_terminate_all(struct dma_chan *chan) LIST_HEAD(list); - dev_vdbg(chan2dev(chan), "%s\n", __func__); + dev_vdbg(dmaengine_chan_dev(chan), "%s\n", __func__); /* * This is only called when something went wrong elsewhere, so @@ -1691,13 +1686,13 @@ atc_tx_status(struct dma_chan *chan, spin_unlock_irqrestore(&atchan->vc.lock, flags); if (unlikely(ret < 0)) { - dev_vdbg(chan2dev(chan), "get residual bytes error\n"); + dev_vdbg(dmaengine_chan_dev(chan), "get residual bytes error\n"); return DMA_ERROR; } else { dma_set_residue(txstate, residue); } - dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d residue = %u\n", + dev_vdbg(dmaengine_chan_dev(chan), "tx_status %d: cookie = %d residue = %u\n", dma_status, cookie, residue); return dma_status; @@ -1729,11 +1724,11 @@ static int atc_alloc_chan_resources(struct dma_chan *chan) struct at_dma_slave *atslave; u32 cfg; - dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); + dev_vdbg(dmaengine_chan_dev(chan), "alloc_chan_resources\n"); /* ASSERT: channel is idle */ if (atc_chan_is_enabled(atchan)) { - dev_dbg(chan2dev(chan), "DMA channel not idle ?\n"); + dev_dbg(dmaengine_chan_dev(chan), "DMA channel not idle ?\n"); return -EIO; } @@ -1782,7 +1777,7 @@ static void atc_free_chan_resources(struct dma_chan *chan) chan->private = NULL; } - dev_vdbg(chan2dev(chan), "free_chan_resources: done\n"); + dev_vdbg(dmaengine_chan_dev(chan), "free_chan_resources: done\n"); } #ifdef CONFIG_OF @@ -2171,7 +2166,7 @@ static void atc_suspend_cyclic(struct at_dma_chan *atchan) /* Channel should be paused by user * do it anyway even if it is not done already */ if (!atc_chan_is_paused(atchan)) { - dev_warn(chan2dev(chan), + dev_warn(dmaengine_chan_dev(chan), "cyclic channel not paused, should be done by channel user\n"); atc_pause(chan); } diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c index 901971e8bae6..d40a8b40dddc 100644 --- a/drivers/dma/at_xdmac.c +++ b/drivers/dma/at_xdmac.c @@ -324,11 +324,6 @@ static inline struct at_xdmac_chan *to_at_xdmac_chan(struct dma_chan *dchan) return container_of(dchan, struct at_xdmac_chan, chan); } -static struct device *chan2dev(struct dma_chan *chan) -{ - return &chan->dev->device; -} - static inline struct at_xdmac *to_at_xdmac(struct dma_device *ddev) { return container_of(ddev, struct at_xdmac, dma); @@ -459,7 +454,7 @@ static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan, if (ret < 0) return; - dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, first); + dev_vdbg(dmaengine_chan_dev(&atchan->chan), "%s: desc 0x%p\n", __func__, first); /* Set transfer as active to not try to start it again. */ first->active_xfer = true; @@ -496,7 +491,7 @@ static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan, | AT_XDMAC_CNDC_NDE; at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, reg); - dev_vdbg(chan2dev(&atchan->chan), + dev_vdbg(dmaengine_chan_dev(&atchan->chan), "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n", __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC), at_xdmac_chan_read(atchan, AT_XDMAC_CNDA), @@ -524,12 +519,12 @@ static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan, at_xdmac_chan_write(atchan, AT_XDMAC_CIE, reg | AT_XDMAC_CIE_LIE); at_xdmac_write(atxdmac, AT_XDMAC_GIE, atchan->mask); - dev_vdbg(chan2dev(&atchan->chan), + dev_vdbg(dmaengine_chan_dev(&atchan->chan), "%s: enable channel (0x%08x)\n", __func__, atchan->mask); wmb(); at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask); - dev_vdbg(chan2dev(&atchan->chan), + dev_vdbg(dmaengine_chan_dev(&atchan->chan), "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n", __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC), at_xdmac_chan_read(atchan, AT_XDMAC_CNDA), @@ -552,7 +547,7 @@ static dma_cookie_t at_xdmac_tx_submit(struct dma_async_tx_descriptor *tx) list_add_tail(&desc->xfer_node, &atchan->xfers_list); spin_unlock_irqrestore(&atchan->lock, irqflags); - dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n", + dev_vdbg(dmaengine_chan_dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n", __func__, atchan, desc); return cookie; @@ -612,7 +607,7 @@ static void at_xdmac_queue_desc(struct dma_chan *chan, prev->lld.mbr_nda = desc->tx_dma_desc.phys; prev->lld.mbr_ubc |= AT_XDMAC_MBR_UBC_NDE; - dev_dbg(chan2dev(chan), "%s: chain lld: prev=0x%p, mbr_nda=%pad\n", + dev_dbg(dmaengine_chan_dev(chan), "%s: chain lld: prev=0x%p, mbr_nda=%pad\n", __func__, prev, &prev->lld.mbr_nda); } @@ -624,7 +619,7 @@ static inline void at_xdmac_increment_block_count(struct dma_chan *chan, desc->lld.mbr_bc++; - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "%s: incrementing the block count of the desc 0x%p\n", __func__, desc); } @@ -680,13 +675,13 @@ static int at_xdmac_compute_chan_conf(struct dma_chan *chan, csize = ffs(atchan->sconfig.src_maxburst) - 1; if (csize < 0) { - dev_err(chan2dev(chan), "invalid src maxburst value\n"); + dev_err(dmaengine_chan_dev(chan), "invalid src maxburst value\n"); return -EINVAL; } atchan->cfg |= AT_XDMAC_CC_CSIZE(csize); dwidth = ffs(atchan->sconfig.src_addr_width) - 1; if (dwidth < 0) { - dev_err(chan2dev(chan), "invalid src addr width value\n"); + dev_err(dmaengine_chan_dev(chan), "invalid src addr width value\n"); return -EINVAL; } atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth); @@ -705,19 +700,19 @@ static int at_xdmac_compute_chan_conf(struct dma_chan *chan, csize = ffs(atchan->sconfig.dst_maxburst) - 1; if (csize < 0) { - dev_err(chan2dev(chan), "invalid src maxburst value\n"); + dev_err(dmaengine_chan_dev(chan), "invalid src maxburst value\n"); return -EINVAL; } atchan->cfg |= AT_XDMAC_CC_CSIZE(csize); dwidth = ffs(atchan->sconfig.dst_addr_width) - 1; if (dwidth < 0) { - dev_err(chan2dev(chan), "invalid dst addr width value\n"); + dev_err(dmaengine_chan_dev(chan), "invalid dst addr width value\n"); return -EINVAL; } atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth); } - dev_dbg(chan2dev(chan), "%s: cfg=0x%08x\n", __func__, atchan->cfg); + dev_dbg(dmaengine_chan_dev(chan), "%s: cfg=0x%08x\n", __func__, atchan->cfg); return 0; } @@ -746,7 +741,7 @@ static int at_xdmac_set_slave_config(struct dma_chan *chan, struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); if (at_xdmac_check_slave_config(sconfig)) { - dev_err(chan2dev(chan), "invalid slave configuration\n"); + dev_err(dmaengine_chan_dev(chan), "invalid slave configuration\n"); return -EINVAL; } @@ -772,11 +767,11 @@ at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, return NULL; if (!is_slave_direction(direction)) { - dev_err(chan2dev(chan), "invalid DMA direction\n"); + dev_err(dmaengine_chan_dev(chan), "invalid DMA direction\n"); return NULL; } - dev_dbg(chan2dev(chan), "%s: sg_len=%d, dir=%s, flags=0x%lx\n", + dev_dbg(dmaengine_chan_dev(chan), "%s: sg_len=%d, dir=%s, flags=0x%lx\n", __func__, sg_len, direction == DMA_MEM_TO_DEV ? "to device" : "from device", flags); @@ -795,15 +790,15 @@ at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, len = sg_dma_len(sg); mem = sg_dma_address(sg); if (unlikely(!len)) { - dev_err(chan2dev(chan), "sg data length is zero\n"); + dev_err(dmaengine_chan_dev(chan), "sg data length is zero\n"); goto spin_unlock; } - dev_dbg(chan2dev(chan), "%s: * sg%d len=%u, mem=0x%08x\n", + dev_dbg(dmaengine_chan_dev(chan), "%s: * sg%d len=%u, mem=0x%08x\n", __func__, i, len, mem); desc = at_xdmac_get_desc(atchan); if (!desc) { - dev_err(chan2dev(chan), "can't get descriptor\n"); + dev_err(dmaengine_chan_dev(chan), "can't get descriptor\n"); if (first) list_splice_tail_init(&first->descs_list, &atchan->free_descs_list); @@ -828,7 +823,7 @@ at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | (len >> fixed_dwidth); /* microblock length */ desc->lld.mbr_cfg = (atchan->cfg & ~AT_XDMAC_CC_DWIDTH_MASK) | AT_XDMAC_CC_DWIDTH(fixed_dwidth); - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n", __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc); @@ -840,7 +835,7 @@ at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, if (!first) first = desc; - dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", + dev_dbg(dmaengine_chan_dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", __func__, desc, first); list_add_tail(&desc->desc_node, &first->descs_list); xfer_size += len; @@ -869,17 +864,17 @@ at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, int i; unsigned long irqflags; - dev_dbg(chan2dev(chan), "%s: buf_addr=%pad, buf_len=%zd, period_len=%zd, dir=%s, flags=0x%lx\n", + dev_dbg(dmaengine_chan_dev(chan), "%s: buf_addr=%pad, buf_len=%zd, period_len=%zd, dir=%s, flags=0x%lx\n", __func__, &buf_addr, buf_len, period_len, direction == DMA_MEM_TO_DEV ? "mem2per" : "per2mem", flags); if (!is_slave_direction(direction)) { - dev_err(chan2dev(chan), "invalid DMA direction\n"); + dev_err(dmaengine_chan_dev(chan), "invalid DMA direction\n"); return NULL; } if (test_and_set_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status)) { - dev_err(chan2dev(chan), "channel currently used\n"); + dev_err(dmaengine_chan_dev(chan), "channel currently used\n"); return NULL; } @@ -892,7 +887,7 @@ at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, spin_lock_irqsave(&atchan->lock, irqflags); desc = at_xdmac_get_desc(atchan); if (!desc) { - dev_err(chan2dev(chan), "can't get descriptor\n"); + dev_err(dmaengine_chan_dev(chan), "can't get descriptor\n"); if (first) list_splice_tail_init(&first->descs_list, &atchan->free_descs_list); @@ -900,7 +895,7 @@ at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, return NULL; } spin_unlock_irqrestore(&atchan->lock, irqflags); - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "%s: desc=0x%p, tx_dma_desc.phys=%pad\n", __func__, desc, &desc->tx_dma_desc.phys); @@ -917,7 +912,7 @@ at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, | AT_XDMAC_MBR_UBC_NSEN | period_len >> at_xdmac_get_dwidth(desc->lld.mbr_cfg); - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n", __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc); @@ -929,7 +924,7 @@ at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, if (!first) first = desc; - dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", + dev_dbg(dmaengine_chan_dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", __func__, desc, first); list_add_tail(&desc->desc_node, &first->descs_list); } @@ -956,16 +951,16 @@ static inline u32 at_xdmac_align_width(struct dma_chan *chan, dma_addr_t addr) */ if (!(addr & 7)) { width = AT_XDMAC_CC_DWIDTH_DWORD; - dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__); + dev_dbg(dmaengine_chan_dev(chan), "%s: dwidth: double word\n", __func__); } else if (!(addr & 3)) { width = AT_XDMAC_CC_DWIDTH_WORD; - dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__); + dev_dbg(dmaengine_chan_dev(chan), "%s: dwidth: word\n", __func__); } else if (!(addr & 1)) { width = AT_XDMAC_CC_DWIDTH_HALFWORD; - dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__); + dev_dbg(dmaengine_chan_dev(chan), "%s: dwidth: half word\n", __func__); } else { width = AT_XDMAC_CC_DWIDTH_BYTE; - dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__); + dev_dbg(dmaengine_chan_dev(chan), "%s: dwidth: byte\n", __func__); } return width; @@ -1005,7 +1000,7 @@ at_xdmac_interleaved_queue_desc(struct dma_chan *chan, dwidth = at_xdmac_align_width(chan, src | dst | chunk->size); if (chunk->size >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) { - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "%s: chunk too big (%zu, max size %lu)...\n", __func__, chunk->size, AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth); @@ -1013,7 +1008,7 @@ at_xdmac_interleaved_queue_desc(struct dma_chan *chan, } if (prev) - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "Adding items at the end of desc 0x%p\n", prev); if (xt->src_inc) { @@ -1034,7 +1029,7 @@ at_xdmac_interleaved_queue_desc(struct dma_chan *chan, desc = at_xdmac_get_desc(atchan); spin_unlock_irqrestore(&atchan->lock, flags); if (!desc) { - dev_err(chan2dev(chan), "can't get descriptor\n"); + dev_err(dmaengine_chan_dev(chan), "can't get descriptor\n"); return NULL; } @@ -1053,7 +1048,7 @@ at_xdmac_interleaved_queue_desc(struct dma_chan *chan, | ublen; desc->lld.mbr_cfg = chan_cc; - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n", __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg); @@ -1087,7 +1082,7 @@ at_xdmac_prep_interleaved(struct dma_chan *chan, if ((xt->numf > 1) && (xt->frame_size > 1)) return NULL; - dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, numf=%zu, frame_size=%zu, flags=0x%lx\n", + dev_dbg(dmaengine_chan_dev(chan), "%s: src=%pad, dest=%pad, numf=%zu, frame_size=%zu, flags=0x%lx\n", __func__, &xt->src_start, &xt->dst_start, xt->numf, xt->frame_size, flags); @@ -1106,7 +1101,7 @@ at_xdmac_prep_interleaved(struct dma_chan *chan, for (i = 0; i < xt->numf - 1; i++) at_xdmac_increment_block_count(chan, first); - dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", + dev_dbg(dmaengine_chan_dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", __func__, first, first); list_add_tail(&first->desc_node, &first->descs_list); } else { @@ -1122,7 +1117,7 @@ at_xdmac_prep_interleaved(struct dma_chan *chan, src_skip = chunk->size + src_icg; dst_skip = chunk->size + dst_icg; - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "%s: chunk size=%zu, src icg=%zu, dst icg=%zu\n", __func__, chunk->size, src_icg, dst_icg); @@ -1140,7 +1135,7 @@ at_xdmac_prep_interleaved(struct dma_chan *chan, if (!first) first = desc; - dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", + dev_dbg(dmaengine_chan_dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", __func__, desc, first); list_add_tail(&desc->desc_node, &first->descs_list); @@ -1193,7 +1188,7 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | AT_XDMAC_CC_TYPE_MEM_TRAN; unsigned long irqflags; - dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, len=%zd, flags=0x%lx\n", + dev_dbg(dmaengine_chan_dev(chan), "%s: src=%pad, dest=%pad, len=%zd, flags=0x%lx\n", __func__, &src, &dest, len, flags); if (unlikely(!len)) @@ -1205,13 +1200,13 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, while (remaining_size) { struct at_xdmac_desc *desc = NULL; - dev_dbg(chan2dev(chan), "%s: remaining_size=%zu\n", __func__, remaining_size); + dev_dbg(dmaengine_chan_dev(chan), "%s: remaining_size=%zu\n", __func__, remaining_size); spin_lock_irqsave(&atchan->lock, irqflags); desc = at_xdmac_get_desc(atchan); spin_unlock_irqrestore(&atchan->lock, irqflags); if (!desc) { - dev_err(chan2dev(chan), "can't get descriptor\n"); + dev_err(dmaengine_chan_dev(chan), "can't get descriptor\n"); if (first) list_splice_tail_init(&first->descs_list, &atchan->free_descs_list); @@ -1227,7 +1222,7 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, else xfer_size = remaining_size; - dev_dbg(chan2dev(chan), "%s: xfer_size=%zu\n", __func__, xfer_size); + dev_dbg(dmaengine_chan_dev(chan), "%s: xfer_size=%zu\n", __func__, xfer_size); /* Check remaining length and change data width if needed. */ dwidth = at_xdmac_align_width(chan, @@ -1246,7 +1241,7 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | ublen; desc->lld.mbr_cfg = chan_cc; - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n", __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg); @@ -1258,7 +1253,7 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, if (!first) first = desc; - dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", + dev_dbg(dmaengine_chan_dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", __func__, desc, first); list_add_tail(&desc->desc_node, &first->descs_list); } @@ -1306,7 +1301,7 @@ static struct at_xdmac_desc *at_xdmac_memset_create_desc(struct dma_chan *chan, dwidth = at_xdmac_align_width(chan, dst_addr); if (len >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) { - dev_err(chan2dev(chan), + dev_err(dmaengine_chan_dev(chan), "%s: Transfer too large, aborting...\n", __func__); return NULL; @@ -1316,7 +1311,7 @@ static struct at_xdmac_desc *at_xdmac_memset_create_desc(struct dma_chan *chan, desc = at_xdmac_get_desc(atchan); spin_unlock_irqrestore(&atchan->lock, flags); if (!desc) { - dev_err(chan2dev(chan), "can't get descriptor\n"); + dev_err(dmaengine_chan_dev(chan), "can't get descriptor\n"); return NULL; } @@ -1338,7 +1333,7 @@ static struct at_xdmac_desc *at_xdmac_memset_create_desc(struct dma_chan *chan, | ublen; desc->lld.mbr_cfg = chan_cc; - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "%s: lld: mbr_da=%pad, mbr_ds=0x%08x, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n", __func__, &desc->lld.mbr_da, desc->lld.mbr_ds, desc->lld.mbr_ubc, desc->lld.mbr_cfg); @@ -1353,7 +1348,7 @@ at_xdmac_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value, struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); struct at_xdmac_desc *desc; - dev_dbg(chan2dev(chan), "%s: dest=%pad, len=%zu, pattern=0x%x, flags=0x%lx\n", + dev_dbg(dmaengine_chan_dev(chan), "%s: dest=%pad, len=%zu, pattern=0x%x, flags=0x%lx\n", __func__, &dest, len, value, flags); if (unlikely(!len)) @@ -1386,12 +1381,12 @@ at_xdmac_prep_dma_memset_sg(struct dma_chan *chan, struct scatterlist *sgl, if (!sgl) return NULL; - dev_dbg(chan2dev(chan), "%s: sg_len=%d, value=0x%x, flags=0x%lx\n", + dev_dbg(dmaengine_chan_dev(chan), "%s: sg_len=%d, value=0x%x, flags=0x%lx\n", __func__, sg_len, value, flags); /* Prepare descriptors. */ for_each_sg(sgl, sg, sg_len, i) { - dev_dbg(chan2dev(chan), "%s: dest=%pad, len=%d, pattern=0x%x, flags=0x%lx\n", + dev_dbg(dmaengine_chan_dev(chan), "%s: dest=%pad, len=%d, pattern=0x%x, flags=0x%lx\n", __func__, &sg_dma_address(sg), sg_dma_len(sg), value, flags); desc = at_xdmac_memset_create_desc(chan, atchan, @@ -1433,7 +1428,7 @@ at_xdmac_prep_dma_memset_sg(struct dma_chan *chan, struct scatterlist *sgl, if (ppdesc && pdesc) { if ((stride == pstride) && (sg_dma_len(ppsg) == sg_dma_len(psg))) { - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "%s: desc 0x%p can be merged with desc 0x%p\n", __func__, pdesc, ppdesc); @@ -1481,7 +1476,7 @@ at_xdmac_prep_dma_memset_sg(struct dma_chan *chan, struct scatterlist *sgl, */ list_add_tail(&desc->desc_node, &first->descs_list); - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", __func__, desc, first); } @@ -1496,7 +1491,7 @@ at_xdmac_prep_dma_memset_sg(struct dma_chan *chan, struct scatterlist *sgl, */ if ((i == (sg_len - 1)) && sg_dma_len(psg) == sg_dma_len(sg)) { - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "%s: desc 0x%p can be merged with desc 0x%p\n", __func__, desc, pdesc); @@ -1667,7 +1662,7 @@ at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie, dma_set_residue(txstate, residue); - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "%s: desc=0x%p, tx_dma_desc.phys=%pad, tx_status=%d, cookie=%d, residue=%d\n", __func__, desc, &desc->tx_dma_desc.phys, ret, cookie, residue); @@ -1690,7 +1685,7 @@ static void at_xdmac_advance_work(struct at_xdmac_chan *atchan) desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node); - dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); + dev_vdbg(dmaengine_chan_dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); if (!desc->active_xfer) at_xdmac_start_xfer(atchan, desc); } @@ -1701,7 +1696,7 @@ static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan) struct dma_async_tx_descriptor *txd; spin_lock_irq(&atchan->lock); - dev_dbg(chan2dev(&atchan->chan), "%s: status=0x%08x\n", + dev_dbg(dmaengine_chan_dev(&atchan->chan), "%s: status=0x%08x\n", __func__, atchan->irq_status); if (list_empty(&atchan->xfers_list)) { spin_unlock_irq(&atchan->lock); @@ -1733,11 +1728,11 @@ static void at_xdmac_handle_error(struct at_xdmac_chan *atchan) * descriptors queued (if any). */ if (atchan->irq_status & AT_XDMAC_CIS_RBEIS) - dev_err(chan2dev(&atchan->chan), "read bus error!!!"); + dev_err(dmaengine_chan_dev(&atchan->chan), "read bus error!!!"); if (atchan->irq_status & AT_XDMAC_CIS_WBEIS) - dev_err(chan2dev(&atchan->chan), "write bus error!!!"); + dev_err(dmaengine_chan_dev(&atchan->chan), "write bus error!!!"); if (atchan->irq_status & AT_XDMAC_CIS_ROIS) - dev_err(chan2dev(&atchan->chan), "request overflow error!!!"); + dev_err(dmaengine_chan_dev(&atchan->chan), "request overflow error!!!"); /* Channel must be disabled first as it's not done automatically */ at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask); @@ -1749,7 +1744,7 @@ static void at_xdmac_handle_error(struct at_xdmac_chan *atchan) xfer_node); /* Print bad descriptor's details if needed */ - dev_dbg(chan2dev(&atchan->chan), + dev_dbg(dmaengine_chan_dev(&atchan->chan), "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n", __func__, &bad_desc->lld.mbr_sa, &bad_desc->lld.mbr_da, bad_desc->lld.mbr_ubc); @@ -1775,7 +1770,7 @@ static void at_xdmac_tasklet(struct tasklet_struct *t) spin_lock_irq(&atchan->lock); - dev_dbg(chan2dev(&atchan->chan), "%s: status=0x%08x\n", + dev_dbg(dmaengine_chan_dev(&atchan->chan), "%s: status=0x%08x\n", __func__, atchan->irq_status); if (!(atchan->irq_status & AT_XDMAC_CIS_LIS) && @@ -1789,9 +1784,9 @@ static void at_xdmac_tasklet(struct tasklet_struct *t) desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node); - dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); + dev_vdbg(dmaengine_chan_dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); if (!desc->active_xfer) { - dev_err(chan2dev(&atchan->chan), "Xfer not active: exiting"); + dev_err(dmaengine_chan_dev(&atchan->chan), "Xfer not active: exiting"); spin_unlock_irq(&atchan->lock); return; } @@ -1852,7 +1847,7 @@ static irqreturn_t at_xdmac_interrupt(int irq, void *dev_id) dev_vdbg(atxdmac->dma.dev, "%s: chan%d: imr=0x%x, status=0x%x\n", __func__, i, chan_imr, chan_status); - dev_vdbg(chan2dev(&atchan->chan), + dev_vdbg(dmaengine_chan_dev(&atchan->chan), "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n", __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC), @@ -1879,7 +1874,7 @@ static void at_xdmac_issue_pending(struct dma_chan *chan) struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); unsigned long flags; - dev_dbg(chan2dev(&atchan->chan), "%s\n", __func__); + dev_dbg(dmaengine_chan_dev(&atchan->chan), "%s\n", __func__); spin_lock_irqsave(&atchan->lock, flags); at_xdmac_advance_work(atchan); @@ -1895,7 +1890,7 @@ static int at_xdmac_device_config(struct dma_chan *chan, int ret; unsigned long flags; - dev_dbg(chan2dev(chan), "%s\n", __func__); + dev_dbg(dmaengine_chan_dev(chan), "%s\n", __func__); spin_lock_irqsave(&atchan->lock, flags); ret = at_xdmac_set_slave_config(chan, config); @@ -1931,7 +1926,7 @@ static int at_xdmac_device_pause(struct dma_chan *chan) unsigned long flags; int ret; - dev_dbg(chan2dev(chan), "%s\n", __func__); + dev_dbg(dmaengine_chan_dev(chan), "%s\n", __func__); if (test_and_set_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status)) return 0; @@ -1971,7 +1966,7 @@ static int at_xdmac_device_resume(struct dma_chan *chan) unsigned long flags; int ret; - dev_dbg(chan2dev(chan), "%s\n", __func__); + dev_dbg(dmaengine_chan_dev(chan), "%s\n", __func__); ret = pm_runtime_resume_and_get(atxdmac->dev); if (ret < 0) @@ -2004,7 +1999,7 @@ static int at_xdmac_device_terminate_all(struct dma_chan *chan) unsigned long flags; int ret; - dev_dbg(chan2dev(chan), "%s\n", __func__); + dev_dbg(dmaengine_chan_dev(chan), "%s\n", __func__); ret = pm_runtime_resume_and_get(atxdmac->dev); if (ret < 0) @@ -2045,13 +2040,13 @@ static int at_xdmac_alloc_chan_resources(struct dma_chan *chan) int i; if (at_xdmac_chan_is_enabled(atchan)) { - dev_err(chan2dev(chan), + dev_err(dmaengine_chan_dev(chan), "can't allocate channel resources (channel enabled)\n"); return -EIO; } if (!list_empty(&atchan->free_descs_list)) { - dev_err(chan2dev(chan), + dev_err(dmaengine_chan_dev(chan), "can't allocate channel resources (channel not free from a previous use)\n"); return -EIO; } @@ -2060,11 +2055,11 @@ static int at_xdmac_alloc_chan_resources(struct dma_chan *chan) desc = at_xdmac_alloc_desc(chan, GFP_KERNEL); if (!desc) { if (i == 0) { - dev_warn(chan2dev(chan), + dev_warn(dmaengine_chan_dev(chan), "can't allocate any descriptors\n"); return -EIO; } - dev_warn(chan2dev(chan), + dev_warn(dmaengine_chan_dev(chan), "only %d descriptors have been allocated\n", i); break; } @@ -2073,7 +2068,7 @@ static int at_xdmac_alloc_chan_resources(struct dma_chan *chan) dma_cookie_init(chan); - dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); + dev_dbg(dmaengine_chan_dev(chan), "%s: allocated %d descriptors\n", __func__, i); return i; } @@ -2085,7 +2080,7 @@ static void at_xdmac_free_chan_resources(struct dma_chan *chan) struct at_xdmac_desc *desc, *_desc; list_for_each_entry_safe(desc, _desc, &atchan->free_descs_list, desc_node) { - dev_dbg(chan2dev(chan), "%s: freeing descriptor %p\n", __func__, desc); + dev_dbg(dmaengine_chan_dev(chan), "%s: freeing descriptor %p\n", __func__, desc); list_del(&desc->desc_node); dma_pool_free(atxdmac->at_xdmac_desc_pool, desc, desc->tx_dma_desc.phys); } @@ -2148,7 +2143,7 @@ static int __maybe_unused atmel_xdmac_suspend(struct device *dev) atchan->save_cc = at_xdmac_chan_read(atchan, AT_XDMAC_CC); if (at_xdmac_chan_is_cyclic(atchan)) { if (!at_xdmac_chan_is_paused(atchan)) { - dev_warn(chan2dev(chan), "%s: channel %d not paused\n", + dev_warn(dmaengine_chan_dev(chan), "%s: channel %d not paused\n", __func__, chan->chan_id); at_xdmac_device_pause_internal(atchan); at_xdmac_runtime_suspend_descriptors(atchan); diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c index 194649811d02..ac2094e65ecf 100644 --- a/drivers/dma/dma-jz4780.c +++ b/drivers/dma/dma-jz4780.c @@ -687,12 +687,12 @@ static bool jz4780_dma_chan_irq(struct jz4780_dma_dev *jzdma, jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0); if (dcs & JZ_DMA_DCS_AR) { - dev_warn(&jzchan->vchan.chan.dev->device, + dev_warn(vchan_chan_dev(&jzchan->vchan), "address error (DCS=0x%x)\n", dcs); } if (dcs & JZ_DMA_DCS_HLT) { - dev_warn(&jzchan->vchan.chan.dev->device, + dev_warn(vchan_chan_dev(&jzchan->vchan), "channel halt (DCS=0x%x)\n", dcs); } @@ -721,7 +721,7 @@ static bool jz4780_dma_chan_irq(struct jz4780_dma_dev *jzdma, } } } else { - dev_err(&jzchan->vchan.chan.dev->device, + dev_err(vchan_chan_dev(&jzchan->vchan), "channel IRQ with no active transfer\n"); } @@ -765,7 +765,7 @@ static int jz4780_dma_alloc_chan_resources(struct dma_chan *chan) JZ_DMA_DESC_BLOCK_SIZE, PAGE_SIZE, 0); if (!jzchan->desc_pool) { - dev_err(&chan->dev->device, + dev_err(dmaengine_chan_dev(chan), "failed to allocate descriptor pool\n"); return -ENOMEM; } diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c index 6ffd8bd82154..a7ac2729e4d9 100644 --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c @@ -868,10 +868,10 @@ struct dma_chan *dma_request_chan(struct device *dev, const char *name) return chan; chan->slave = dev; - if (sysfs_create_link(&chan->dev->device.kobj, &dev->kobj, + if (sysfs_create_link(&dmaengine_chan_dev(chan)->kobj, &dev->kobj, DMA_SLAVE_NAME)) dev_warn(dev, "Cannot create DMA %s symlink\n", DMA_SLAVE_NAME); - if (sysfs_create_link(&dev->kobj, &chan->dev->device.kobj, chan->name)) + if (sysfs_create_link(&dev->kobj, &dmaengine_chan_dev(chan)->kobj, chan->name)) dev_warn(dev, "Cannot create DMA %s symlink\n", chan->name); return chan; @@ -917,7 +917,7 @@ void dma_release_channel(struct dma_chan *chan) dma_chan_put(chan); if (chan->slave) { - sysfs_remove_link(&chan->dev->device.kobj, DMA_SLAVE_NAME); + sysfs_remove_link(&dmaengine_chan_dev(chan)->kobj, DMA_SLAVE_NAME); sysfs_remove_link(&chan->slave->kobj, chan->name); kfree(chan->name); chan->name = NULL; @@ -1101,17 +1101,17 @@ static int __dma_async_device_channel_register(struct dma_device *device, goto err_free_dev; } - chan->dev->device.class = &dma_devclass; - chan->dev->device.parent = device->dev; + dmaengine_chan_dev(chan)->class = &dma_devclass; + dmaengine_chan_dev(chan)->parent = device->dev; chan->dev->chan = chan; chan->dev->dev_id = device->dev_id; spin_lock_init(&chan->lock); if (!name) - dev_set_name(&chan->dev->device, "dma%dchan%d", device->dev_id, chan->chan_id); + dev_set_name(dmaengine_chan_dev(chan), "dma%dchan%d", device->dev_id, chan->chan_id); else - dev_set_name(&chan->dev->device, "%s", name); - rc = device_register(&chan->dev->device); + dev_set_name(dmaengine_chan_dev(chan), "%s", name); + rc = device_register(dmaengine_chan_dev(chan)); if (rc) goto err_out_ida; chan->client_count = 0; @@ -1158,7 +1158,7 @@ static void __dma_async_device_channel_unregister(struct dma_device *device, chan->dev->chan = NULL; mutex_unlock(&dma_list_mutex); ida_free(&device->chan_ida, chan->chan_id); - device_unregister(&chan->dev->device); + device_unregister(dmaengine_chan_dev(chan)); free_percpu(chan->local); } @@ -1292,7 +1292,7 @@ int dma_async_device_register(struct dma_device *device) mutex_lock(&dma_list_mutex); chan->dev->chan = NULL; mutex_unlock(&dma_list_mutex); - device_unregister(&chan->dev->device); + device_unregister(dmaengine_chan_dev(chan)); free_percpu(chan->local); } return rc; diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c index 6e63dfe9d641..7520c78f55cc 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -319,7 +319,7 @@ static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan, lli = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, &phys); if (unlikely(!lli)) { - dev_err(chan2dev(chan), "%s: not enough descriptors available\n", + dev_err(vchan_chan_dev(&chan->vc), "%s: not enough descriptors available\n", axi_chan_name(chan)); return NULL; } @@ -345,7 +345,7 @@ static void axi_desc_put(struct axi_dma_desc *desc) kfree(desc->hw_desc); kfree(desc); atomic_sub(descs_put, &chan->descs_allocated); - dev_vdbg(chan2dev(chan), "%s: %d descs put, %d still allocated\n", + dev_vdbg(vchan_chan_dev(&chan->vc), "%s: %d descs put, %d still allocated\n", axi_chan_name(chan), descs_put, atomic_read(&chan->descs_allocated)); } @@ -434,7 +434,7 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan *chan, u8 lms = 0; /* Select AXI0 master for LLI fetching */ if (unlikely(axi_chan_is_hw_enable(chan))) { - dev_err(chan2dev(chan), "%s is non-idle!\n", + dev_err(vchan_chan_dev(&chan->vc), "%s is non-idle!\n", axi_chan_name(chan)); return; @@ -493,7 +493,7 @@ static void axi_chan_start_first_queued(struct axi_dma_chan *chan) return; desc = vd_to_axi_desc(vd); - dev_vdbg(chan2dev(chan), "%s: started %u\n", axi_chan_name(chan), + dev_vdbg(vchan_chan_dev(&chan->vc), "%s: started %u\n", axi_chan_name(chan), vd->tx.cookie); axi_chan_block_xfer_start(chan, desc); } @@ -527,7 +527,7 @@ static int dma_chan_alloc_chan_resources(struct dma_chan *dchan) /* ASSERT: channel is idle */ if (axi_chan_is_hw_enable(chan)) { - dev_err(chan2dev(chan), "%s is non-idle!\n", + dev_err(vchan_chan_dev(&chan->vc), "%s is non-idle!\n", axi_chan_name(chan)); pm_runtime_put(chan->chip->dev); return -EBUSY; @@ -538,11 +538,11 @@ static int dma_chan_alloc_chan_resources(struct dma_chan *dchan) sizeof(struct axi_dma_lli), 64, 0); if (!chan->desc_pool) { - dev_err(chan2dev(chan), "No memory for descriptors\n"); + dev_err(vchan_chan_dev(&chan->vc), "No memory for descriptors\n"); pm_runtime_put(chan->chip->dev); return -ENOMEM; } - dev_vdbg(dchan2dev(dchan), "%s: allocating\n", axi_chan_name(chan)); + dev_vdbg(dmaengine_chan_dev(dchan), "%s: allocating\n", axi_chan_name(chan)); return 0; } @@ -553,7 +553,7 @@ static void dma_chan_free_chan_resources(struct dma_chan *dchan) /* ASSERT: channel is idle */ if (axi_chan_is_hw_enable(chan)) - dev_err(dchan2dev(dchan), "%s is non-idle!\n", + dev_err(dmaengine_chan_dev(dchan), "%s is non-idle!\n", axi_chan_name(chan)); axi_chan_disable(chan); @@ -563,7 +563,7 @@ static void dma_chan_free_chan_resources(struct dma_chan *dchan) dma_pool_destroy(chan->desc_pool); chan->desc_pool = NULL; - dev_vdbg(dchan2dev(dchan), + dev_vdbg(dmaengine_chan_dev(dchan), "%s: free resources, descriptor still allocated: %u\n", axi_chan_name(chan), atomic_read(&chan->descs_allocated)); @@ -932,7 +932,7 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr, u64 llp = 0; u8 lms = 0; /* Select AXI0 master for LLI fetching */ - dev_dbg(chan2dev(chan), "%s: memcpy: src: %pad dst: %pad length: %zd flags: %#lx", + dev_dbg(vchan_chan_dev(&chan->vc), "%s: memcpy: src: %pad dst: %pad length: %zd flags: %#lx", axi_chan_name(chan), &src_adr, &dst_adr, len, flags); max_block_ts = chan->chip->dw->hdata->block_size[chan->id]; @@ -1037,11 +1037,11 @@ static void axi_chan_dump_lli(struct axi_dma_chan *chan, struct axi_dma_hw_desc *desc) { if (!desc->lli) { - dev_err(dchan2dev(&chan->vc.chan), "NULL LLI\n"); + dev_err(vchan_chan_dev(&chan->vc), "NULL LLI\n"); return; } - dev_err(dchan2dev(&chan->vc.chan), + dev_err(vchan_chan_dev(&chan->vc), "SAR: 0x%llx DAR: 0x%llx LLP: 0x%llx BTS 0x%x CTL: 0x%x:%08x", le64_to_cpu(desc->lli->sar), le64_to_cpu(desc->lli->dar), @@ -1070,7 +1070,7 @@ static noinline void axi_chan_handle_err(struct axi_dma_chan *chan, u32 status) /* The bad descriptor currently is in the head of vc list */ vd = vchan_next_desc(&chan->vc); if (!vd) { - dev_err(chan2dev(chan), "BUG: %s, IRQ with no descriptors\n", + dev_err(vchan_chan_dev(&chan->vc), "BUG: %s, IRQ with no descriptors\n", axi_chan_name(chan)); goto out; } @@ -1078,7 +1078,7 @@ static noinline void axi_chan_handle_err(struct axi_dma_chan *chan, u32 status) list_del(&vd->node); /* WARN about bad descriptor */ - dev_err(chan2dev(chan), + dev_err(vchan_chan_dev(&chan->vc), "Bad descriptor submitted for %s, cookie: %d, irq: 0x%08x\n", axi_chan_name(chan), vd->tx.cookie, status); axi_chan_list_dump_lli(chan, vd_to_axi_desc(vd)); @@ -1104,7 +1104,7 @@ static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan) spin_lock_irqsave(&chan->vc.lock, flags); if (unlikely(axi_chan_is_hw_enable(chan))) { - dev_err(chan2dev(chan), "BUG: %s caught DWAXIDMAC_IRQ_DMA_TRF, but channel not idle!\n", + dev_err(vchan_chan_dev(&chan->vc), "BUG: %s caught DWAXIDMAC_IRQ_DMA_TRF, but channel not idle!\n", axi_chan_name(chan)); axi_chan_disable(chan); } @@ -1112,7 +1112,7 @@ static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan) /* The completed descriptor currently is in the head of vc list */ vd = vchan_next_desc(&chan->vc); if (!vd) { - dev_err(chan2dev(chan), "BUG: %s, IRQ with no descriptors\n", + dev_err(vchan_chan_dev(&chan->vc), "BUG: %s, IRQ with no descriptors\n", axi_chan_name(chan)); goto out; } @@ -1192,7 +1192,7 @@ static int dma_chan_terminate_all(struct dma_chan *dchan) ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val, !(val & chan_active), 1000, 50000); if (ret == -ETIMEDOUT) - dev_warn(dchan2dev(dchan), + dev_warn(dmaengine_chan_dev(dchan), "%s failed to stop\n", axi_chan_name(chan)); if (chan->direction != DMA_MEM_TO_MEM) @@ -1209,7 +1209,7 @@ static int dma_chan_terminate_all(struct dma_chan *dchan) vchan_dma_desc_free_list(&chan->vc, &head); - dev_vdbg(dchan2dev(dchan), "terminated: %s\n", axi_chan_name(chan)); + dev_vdbg(dmaengine_chan_dev(dchan), "terminated: %s\n", axi_chan_name(chan)); return 0; } diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h index ec83acd12a9b..d8dd07efe60f 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h @@ -118,16 +118,6 @@ struct axi_dma_chan_config { u8 hs_sel_src; }; -static inline struct device *dchan2dev(struct dma_chan *dchan) -{ - return &dchan->dev->device; -} - -static inline struct device *chan2dev(struct axi_dma_chan *chan) -{ - return &chan->vc.chan.dev->device; -} - static inline struct axi_dma_desc *vd_to_axi_desc(struct virt_dma_desc *vd) { return container_of(vd, struct axi_dma_desc, vd); diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c index dd75f97a33b3..575b7bb6af9a 100644 --- a/drivers/dma/dw/core.c +++ b/drivers/dma/dw/core.c @@ -41,11 +41,6 @@ /*----------------------------------------------------------------------*/ -static struct device *chan2dev(struct dma_chan *chan) -{ - return &chan->dev->device; -} - static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) { return to_dw_desc(dwc->active_list.next); @@ -69,7 +64,7 @@ static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) list_add_tail(&desc->desc_node, &dwc->queue); spin_unlock_irqrestore(&dwc->lock, flags); - dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", + dev_vdbg(dmaengine_chan_dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie); return cookie; @@ -127,7 +122,7 @@ static void dwc_initialize(struct dw_dma_chan *dwc) static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) { - dev_err(chan2dev(&dwc->chan), + dev_err(dmaengine_chan_dev(&dwc->chan), " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", channel_readl(dwc, SAR), channel_readl(dwc, DAR), @@ -177,7 +172,7 @@ static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) /* ASSERT: channel is idle */ if (dma_readl(dw, CH_EN) & dwc->mask) { - dev_err(chan2dev(&dwc->chan), + dev_err(dmaengine_chan_dev(&dwc->chan), "%s: BUG: Attempted to start non-idle channel\n", __func__); dwc_dump_chan_regs(dwc); @@ -190,7 +185,7 @@ static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); if (was_soft_llp) { - dev_err(chan2dev(&dwc->chan), + dev_err(dmaengine_chan_dev(&dwc->chan), "BUG: Attempted to start new LLP transfer inside ongoing one\n"); return; } @@ -223,7 +218,7 @@ static void dwc_dostart_first_queued(struct dw_dma_chan *dwc) list_move(dwc->queue.next, &dwc->active_list); desc = dwc_first_active(dwc); - dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie); + dev_vdbg(dmaengine_chan_dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie); dwc_dostart(dwc, desc); } @@ -238,7 +233,7 @@ dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, unsigned long flags; struct dmaengine_desc_callback cb; - dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); + dev_vdbg(dmaengine_chan_dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); spin_lock_irqsave(&dwc->lock, flags); dma_cookie_complete(txd); @@ -265,7 +260,7 @@ static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) spin_lock_irqsave(&dwc->lock, flags); if (dma_readl(dw, CH_EN) & dwc->mask) { - dev_err(chan2dev(&dwc->chan), + dev_err(dmaengine_chan_dev(&dwc->chan), "BUG: XFER bit set, but channel not idle!\n"); /* Try to continue after resetting the channel... */ @@ -353,12 +348,12 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) } if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { - dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); + dev_vdbg(dmaengine_chan_dev(&dwc->chan), "%s: soft LLP mode\n", __func__); spin_unlock_irqrestore(&dwc->lock, flags); return; } - dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); + dev_vdbg(dmaengine_chan_dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { /* Initial residue value */ @@ -398,7 +393,7 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) spin_lock_irqsave(&dwc->lock, flags); } - dev_err(chan2dev(&dwc->chan), + dev_err(dmaengine_chan_dev(&dwc->chan), "BUG: All descriptors done, but channel not idle!\n"); /* Try to continue after resetting the channel... */ @@ -410,7 +405,7 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_desc *desc) { - dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", + dev_crit(dmaengine_chan_dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", lli_read(desc, sar), lli_read(desc, dar), lli_read(desc, llp), @@ -449,7 +444,7 @@ static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) * controller flagged an error instead of scribbling over * random memory locations. */ - dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" + dev_WARN(dmaengine_chan_dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" " cookie: %d\n", bad_desc->txd.cookie); dwc_dump_lli(dwc, bad_desc); list_for_each_entry(child, &bad_desc->tx_list, desc_node) @@ -552,12 +547,12 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, u32 ctllo, ctlhi; u8 lms = DWC_LLP_LMS(m_master); - dev_vdbg(chan2dev(chan), + dev_vdbg(dmaengine_chan_dev(chan), "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__, &dest, &src, len, flags); if (unlikely(!len)) { - dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); + dev_dbg(dmaengine_chan_dev(chan), "%s: length is zero!\n", __func__); return NULL; } @@ -630,7 +625,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, struct scatterlist *sg; size_t total_len = 0; - dev_vdbg(chan2dev(chan), "%s\n", __func__); + dev_vdbg(dmaengine_chan_dev(chan), "%s\n", __func__); if (unlikely(!is_slave_direction(direction) || !sg_len)) return NULL; @@ -754,7 +749,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, return &first->txd; err_desc_get: - dev_err(chan2dev(chan), + dev_err(dmaengine_chan_dev(chan), "not enough descriptors available. Direction %d\n", direction); dwc_desc_put(dwc, first); return NULL; @@ -1063,11 +1058,11 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan) struct dw_dma_chan *dwc = to_dw_dma_chan(chan); struct dw_dma *dw = to_dw_dma(chan->device); - dev_vdbg(chan2dev(chan), "%s\n", __func__); + dev_vdbg(dmaengine_chan_dev(chan), "%s\n", __func__); /* ASSERT: channel is idle */ if (dma_readl(dw, CH_EN) & dwc->mask) { - dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); + dev_dbg(dmaengine_chan_dev(chan), "DMA channel not idle?\n"); return -EIO; } @@ -1083,7 +1078,7 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan) * We need controller-specific data to set up slave transfers. */ if (chan->private && !dw_dma_filter(chan, chan->private)) { - dev_warn(chan2dev(chan), "Wrong controller-specific data\n"); + dev_warn(dmaengine_chan_dev(chan), "Wrong controller-specific data\n"); return -EINVAL; } @@ -1101,7 +1096,7 @@ static void dwc_free_chan_resources(struct dma_chan *chan) struct dw_dma *dw = to_dw_dma(chan->device); unsigned long flags; - dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, + dev_dbg(dmaengine_chan_dev(chan), "%s: descs allocated=%u\n", __func__, dwc->descs_allocated); /* ASSERT: channel is idle */ @@ -1126,7 +1121,7 @@ static void dwc_free_chan_resources(struct dma_chan *chan) if (!dw->in_use) do_dw_dma_off(dw); - dev_vdbg(chan2dev(chan), "%s: done\n", __func__); + dev_vdbg(dmaengine_chan_dev(chan), "%s: done\n", __func__); } static void dwc_caps(struct dma_chan *chan, struct dma_slave_caps *caps) diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c index 311e55a97ba9..cbfe74fc8d71 100644 --- a/drivers/dma/ep93xx_dma.c +++ b/drivers/dma/ep93xx_dma.c @@ -250,11 +250,6 @@ struct ep93xx_edma_data { size_t num_channels; }; -static inline struct device *chan2dev(struct ep93xx_dma_chan *edmac) -{ - return &edmac->chan.dev->device; -} - static struct ep93xx_dma_chan *to_ep93xx_dma_chan(struct dma_chan *chan) { return container_of(chan, struct ep93xx_dma_chan, chan); @@ -415,7 +410,7 @@ static void m2p_hw_shutdown(struct ep93xx_dma_chan *edmac) m2p_set_control(edmac, 0); while (m2p_channel_state(edmac) != M2P_STATE_IDLE) - dev_warn(chan2dev(edmac), "M2P: Not yet IDLE\n"); + dev_warn(dmaengine_chan_dev(&edmac->chan), "M2P: Not yet IDLE\n"); } static void m2p_fill_desc(struct ep93xx_dma_chan *edmac) @@ -425,7 +420,7 @@ static void m2p_fill_desc(struct ep93xx_dma_chan *edmac) desc = ep93xx_dma_get_active(edmac); if (!desc) { - dev_warn(chan2dev(edmac), "M2P: empty descriptor list\n"); + dev_warn(dmaengine_chan_dev(&edmac->chan), "M2P: empty descriptor list\n"); return; } @@ -479,7 +474,7 @@ static int m2p_hw_interrupt(struct ep93xx_dma_chan *edmac) * Revisit this when there is a mechanism to report back the * errors. */ - dev_err(chan2dev(edmac), + dev_err(dmaengine_chan_dev(&edmac->chan), "DMA transfer failed! Details:\n" "\tcookie : %d\n" "\tsrc_addr : 0x%08x\n" @@ -586,7 +581,7 @@ static void m2m_fill_desc(struct ep93xx_dma_chan *edmac) desc = ep93xx_dma_get_active(edmac); if (!desc) { - dev_warn(chan2dev(edmac), "M2M: empty descriptor list\n"); + dev_warn(dmaengine_chan_dev(&edmac->chan), "M2M: empty descriptor list\n"); return; } @@ -849,7 +844,7 @@ static irqreturn_t ep93xx_dma_interrupt(int irq, void *dev_id) desc = ep93xx_dma_get_active(edmac); if (!desc) { - dev_warn(chan2dev(edmac), + dev_warn(dmaengine_chan_dev(&edmac->chan), "got interrupt while active list is empty\n"); spin_unlock(&edmac->lock); return IRQ_NONE; @@ -867,7 +862,7 @@ static irqreturn_t ep93xx_dma_interrupt(int irq, void *dev_id) break; default: - dev_warn(chan2dev(edmac), "unknown interrupt!\n"); + dev_warn(dmaengine_chan_dev(&edmac->chan), "unknown interrupt!\n"); ret = IRQ_NONE; break; } @@ -967,7 +962,7 @@ static int ep93xx_dma_alloc_chan_resources(struct dma_chan *chan) desc = kzalloc_obj(*desc); if (!desc) { - dev_warn(chan2dev(edmac), "not enough descriptors\n"); + dev_warn(dmaengine_chan_dev(&edmac->chan), "not enough descriptors\n"); break; } @@ -1044,7 +1039,7 @@ ep93xx_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, for (offset = 0; offset < len; offset += bytes) { desc = ep93xx_dma_desc_get(edmac); if (!desc) { - dev_warn(chan2dev(edmac), "couldn't get descriptor\n"); + dev_warn(dmaengine_chan_dev(&edmac->chan), "couldn't get descriptor\n"); goto fail; } @@ -1091,13 +1086,13 @@ ep93xx_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, int i; if (!edmac->edma->m2m && dir != ep93xx_dma_chan_direction(chan)) { - dev_warn(chan2dev(edmac), + dev_warn(dmaengine_chan_dev(&edmac->chan), "channel was configured with different direction\n"); return NULL; } if (test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags)) { - dev_warn(chan2dev(edmac), + dev_warn(dmaengine_chan_dev(&edmac->chan), "channel is already used for cyclic transfers\n"); return NULL; } @@ -1109,14 +1104,14 @@ ep93xx_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, size_t len = sg_dma_len(sg); if (len > DMA_MAX_CHAN_BYTES) { - dev_warn(chan2dev(edmac), "too big transfer size %zu\n", + dev_warn(dmaengine_chan_dev(&edmac->chan), "too big transfer size %zu\n", len); goto fail; } desc = ep93xx_dma_desc_get(edmac); if (!desc) { - dev_warn(chan2dev(edmac), "couldn't get descriptor\n"); + dev_warn(dmaengine_chan_dev(&edmac->chan), "couldn't get descriptor\n"); goto fail; } @@ -1172,19 +1167,19 @@ ep93xx_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr, size_t offset = 0; if (!edmac->edma->m2m && dir != ep93xx_dma_chan_direction(chan)) { - dev_warn(chan2dev(edmac), + dev_warn(dmaengine_chan_dev(&edmac->chan), "channel was configured with different direction\n"); return NULL; } if (test_and_set_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags)) { - dev_warn(chan2dev(edmac), + dev_warn(dmaengine_chan_dev(&edmac->chan), "channel is already used for cyclic transfers\n"); return NULL; } if (period_len > DMA_MAX_CHAN_BYTES) { - dev_warn(chan2dev(edmac), "too big period length %zu\n", + dev_warn(dmaengine_chan_dev(&edmac->chan), "too big period length %zu\n", period_len); return NULL; } @@ -1196,7 +1191,7 @@ ep93xx_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr, for (offset = 0; offset < buf_len; offset += period_len) { desc = ep93xx_dma_desc_get(edmac); if (!desc) { - dev_warn(chan2dev(edmac), "couldn't get descriptor\n"); + dev_warn(dmaengine_chan_dev(&edmac->chan), "couldn't get descriptor\n"); goto fail; } diff --git a/drivers/dma/idma64.c b/drivers/dma/idma64.c index e1fcce07d1c1..657629b100fa 100644 --- a/drivers/dma/idma64.c +++ b/drivers/dma/idma64.c @@ -25,11 +25,6 @@ /* ---------------------------------------------------------------------- */ -static struct device *chan2dev(struct dma_chan *chan) -{ - return &chan->dev->device; -} - /* ---------------------------------------------------------------------- */ static void idma64_off(struct idma64 *idma64) @@ -510,7 +505,7 @@ static int idma64_alloc_chan_resources(struct dma_chan *chan) idma64c->pool = dma_pool_create(dma_chan_name(chan), chan->device->dev, sizeof(struct idma64_lli), 8, 0); if (!idma64c->pool) { - dev_err(chan2dev(chan), "No memory for descriptors\n"); + dev_err(dmaengine_chan_dev(chan), "No memory for descriptors\n"); return -ENOMEM; } diff --git a/drivers/dma/loongson/loongson1-apb-dma.c b/drivers/dma/loongson/loongson1-apb-dma.c index 89786cbd20ab..46b4bfef45e2 100644 --- a/drivers/dma/loongson/loongson1-apb-dma.c +++ b/drivers/dma/loongson/loongson1-apb-dma.c @@ -89,11 +89,6 @@ static irqreturn_t ls1x_dma_irq_handler(int irq, void *data); #define to_ls1x_dma_desc(d) \ container_of(d, struct ls1x_dma_desc, vd) -static inline struct device *chan2dev(struct dma_chan *chan) -{ - return &chan->dev->device; -} - static inline int ls1x_dma_query(struct ls1x_dma_chan *chan, dma_addr_t *lli_phys) { @@ -107,7 +102,7 @@ static inline int ls1x_dma_query(struct ls1x_dma_chan *chan, ret = readl_poll_timeout_atomic(chan->reg_base + LS1X_DMA_CTRL, val, !(val & LS1X_DMA_ASK_VALID), 0, 3000); if (ret) - dev_err(chan2dev(dchan), "failed to query DMA\n"); + dev_err(dmaengine_chan_dev(dchan), "failed to query DMA\n"); return ret; } @@ -116,7 +111,7 @@ static inline int ls1x_dma_start(struct ls1x_dma_chan *chan, dma_addr_t *lli_phys) { struct dma_chan *dchan = &chan->vc.chan; - struct device *dev = chan2dev(dchan); + struct device *dev = dmaengine_chan_dev(dchan); int val, ret; val = *lli_phys & LS1X_DMA_LLI_ADDR_MASK; @@ -143,7 +138,7 @@ static inline void ls1x_dma_stop(struct ls1x_dma_chan *chan) static void ls1x_dma_free_chan_resources(struct dma_chan *dchan) { struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan); - struct device *dev = chan2dev(dchan); + struct device *dev = dmaengine_chan_dev(dchan); dma_free_coherent(dev, sizeof(struct ls1x_dma_lli), chan->curr_lli, chan->curr_lli->phys); @@ -156,7 +151,7 @@ static void ls1x_dma_free_chan_resources(struct dma_chan *dchan) static int ls1x_dma_alloc_chan_resources(struct dma_chan *dchan) { struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan); - struct device *dev = chan2dev(dchan); + struct device *dev = dmaengine_chan_dev(dchan); dma_addr_t phys; int ret; @@ -219,7 +214,7 @@ static int ls1x_dma_prep_lli(struct dma_chan *dchan, struct ls1x_dma_desc *desc, { struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan); struct ls1x_dma_lli *lli, *prev = NULL, *first = NULL; - struct device *dev = chan2dev(dchan); + struct device *dev = dmaengine_chan_dev(dchan); struct list_head *pos = NULL; struct scatterlist *sg; unsigned int dev_addr, cmd, i; @@ -299,7 +294,7 @@ ls1x_dma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, { struct ls1x_dma_desc *desc; - dev_dbg(chan2dev(dchan), "sg_len=%u flags=0x%lx dir=%s\n", + dev_dbg(dmaengine_chan_dev(dchan), "sg_len=%u flags=0x%lx dir=%s\n", sg_len, flags, dmaengine_get_direction_text(dir)); desc = ls1x_dma_alloc_desc(); @@ -325,7 +320,7 @@ ls1x_dma_prep_dma_cyclic(struct dma_chan *dchan, dma_addr_t buf_addr, unsigned int i; int ret; - dev_dbg(chan2dev(dchan), + dev_dbg(dmaengine_chan_dev(dchan), "buf_len=%zu period_len=%zu flags=0x%lx dir=%s\n", buf_len, period_len, flags, dmaengine_get_direction_text(dir)); @@ -450,7 +445,7 @@ static enum dma_status ls1x_dma_tx_status(struct dma_chan *dchan, if (lli->hw[LS1X_DMADESC_NEXT] == next_phys) break; - dev_dbg(chan2dev(dchan), "current lli_phys=%pad", + dev_dbg(dmaengine_chan_dev(dchan), "current lli_phys=%pad", &lli->phys); /* count the residues */ @@ -489,7 +484,7 @@ static irqreturn_t ls1x_dma_irq_handler(int irq, void *data) { struct ls1x_dma_chan *chan = data; struct dma_chan *dchan = &chan->vc.chan; - struct device *dev = chan2dev(dchan); + struct device *dev = dmaengine_chan_dev(dchan); struct virt_dma_desc *vd; scoped_guard(spinlock, &chan->vc.lock) { diff --git a/drivers/dma/loongson/loongson2-apb-cmc-dma.c b/drivers/dma/loongson/loongson2-apb-cmc-dma.c index ed69688c8c05..bc336947e31a 100644 --- a/drivers/dma/loongson/loongson2-apb-cmc-dma.c +++ b/drivers/dma/loongson/loongson2-apb-cmc-dma.c @@ -134,11 +134,6 @@ static struct loongson2_cmc_dma_desc *to_lmdma_desc(struct virt_dma_desc *vdesc) return container_of(vdesc, struct loongson2_cmc_dma_desc, vdesc); } -static struct device *chan2dev(struct loongson2_cmc_dma_chan *lchan) -{ - return &lchan->vchan.chan.dev->device; -} - static u32 loongson2_cmc_dma_read(struct loongson2_cmc_dma_dev *lddev, u32 reg, u32 id) { return readl(lddev->base + (reg + lddev->chan_reg_offset * id)); @@ -302,7 +297,7 @@ static irqreturn_t loongson2_cmc_dma_chan_irq(int irq, void *devid) { struct loongson2_cmc_dma_chan *lchan = devid; struct loongson2_cmc_dma_dev *lddev = lmdma_get_dev(lchan); - struct device *dev = chan2dev(lchan); + struct device *dev = vchan_chan_dev(&lchan->vchan); u32 ists, status, ccr; scoped_guard(spinlock, &lchan->vchan.lock) { @@ -337,7 +332,7 @@ static void loongson2_cmc_dma_issue_pending(struct dma_chan *chan) guard(spinlock_irqsave)(&lchan->vchan.lock); if (vchan_issue_pending(&lchan->vchan) && !lchan->desc) { - dev_dbg(chan2dev(lchan), "vchan %pK: issued\n", &lchan->vchan); + dev_dbg(vchan_chan_dev(&lchan->vchan), "vchan %pK: issued\n", &lchan->vchan); loongson2_cmc_dma_start_transfer(lchan); } } @@ -347,7 +342,7 @@ static int loongson2_cmc_dma_set_xfer_param(struct loongson2_cmc_dma_chan *lchan enum dma_slave_buswidth *buswidth, u32 buf_len) { struct dma_slave_config sconfig = lchan->dma_sconfig; - struct device *dev = chan2dev(lchan); + struct device *dev = vchan_chan_dev(&lchan->vchan); int dev_width; u32 ccr; @@ -409,7 +404,7 @@ loongson2_cmc_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, num_items = DIV_ROUND_UP(sg_dma_len(sg), buswidth); if (num_items >= LOONSON2_CMCDMA_MAX_DATA_ITEMS) { - dev_err(chan2dev(lchan), "Number of items not supported\n"); + dev_err(vchan_chan_dev(&lchan->vchan), "Number of items not supported\n"); kfree(desc); return ERR_PTR(-EINVAL); } @@ -447,7 +442,7 @@ loongson2_cmc_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, si num_items = DIV_ROUND_UP(period_len, buswidth); if (num_items >= LOONSON2_CMCDMA_MAX_DATA_ITEMS) { - dev_err(chan2dev(lchan), "Number of items not supported\n"); + dev_err(vchan_chan_dev(&lchan->vchan), "Number of items not supported\n"); return ERR_PTR(-EINVAL); } diff --git a/drivers/dma/loongson/loongson2-apb-dma.c b/drivers/dma/loongson/loongson2-apb-dma.c index 7c3d7c327395..16a0c1c60d59 100644 --- a/drivers/dma/loongson/loongson2-apb-dma.c +++ b/drivers/dma/loongson/loongson2-apb-dma.c @@ -161,11 +161,6 @@ static inline struct ls2x_dma_priv *to_ldma_priv(struct dma_device *ddev) return container_of(ddev, struct ls2x_dma_priv, ddev); } -static struct device *chan2dev(struct dma_chan *chan) -{ - return &chan->dev->device; -} - static void ls2x_dma_desc_free(struct virt_dma_desc *vdesc) { struct ls2x_dma_chan *lchan = to_ldma_chan(vdesc->tx.chan); @@ -286,7 +281,7 @@ static int ls2x_dma_alloc_chan_resources(struct dma_chan *chan) chan->device->dev, PAGE_SIZE, __alignof__(struct ls2x_dma_hw_desc), 0); if (!lchan->pool) { - dev_err(chan2dev(chan), "No memory for descriptors\n"); + dev_err(dmaengine_chan_dev(chan), "No memory for descriptors\n"); return -ENOMEM; } diff --git a/drivers/dma/moxart-dma.c b/drivers/dma/moxart-dma.c index 442f5aa16031..28be93eed4cc 100644 --- a/drivers/dma/moxart-dma.c +++ b/drivers/dma/moxart-dma.c @@ -154,11 +154,6 @@ static const unsigned int es_bytes[] = { [MOXART_DMA_DATA_TYPE_S32] = 4, }; -static struct device *chan2dev(struct dma_chan *chan) -{ - return &chan->dev->device; -} - static inline struct moxart_chan *to_moxart_dma_chan(struct dma_chan *c) { return container_of(c, struct moxart_chan, vc.chan); @@ -182,7 +177,7 @@ static int moxart_terminate_all(struct dma_chan *chan) LIST_HEAD(head); u32 ctrl; - dev_dbg(chan2dev(chan), "%s: ch=%p\n", __func__, ch); + dev_dbg(dmaengine_chan_dev(chan), "%s: ch=%p\n", __func__, ch); spin_lock_irqsave(&ch->vc.lock, flags); @@ -272,7 +267,7 @@ static struct dma_async_tx_descriptor *moxart_prep_slave_sg( unsigned int i; if (!is_slave_direction(dir)) { - dev_err(chan2dev(chan), "%s: invalid DMA direction\n", + dev_err(dmaengine_chan_dev(chan), "%s: invalid DMA direction\n", __func__); return NULL; } @@ -296,7 +291,7 @@ static struct dma_async_tx_descriptor *moxart_prep_slave_sg( es = MOXART_DMA_DATA_TYPE_S32; break; default: - dev_err(chan2dev(chan), "%s: unsupported data width (%u)\n", + dev_err(dmaengine_chan_dev(chan), "%s: unsupported data width (%u)\n", __func__, dev_width); return NULL; } @@ -341,7 +336,7 @@ static int moxart_alloc_chan_resources(struct dma_chan *chan) { struct moxart_chan *ch = to_moxart_dma_chan(chan); - dev_dbg(chan2dev(chan), "%s: allocating channel #%u\n", + dev_dbg(dmaengine_chan_dev(chan), "%s: allocating channel #%u\n", __func__, ch->ch_num); ch->allocated = 1; @@ -354,7 +349,7 @@ static void moxart_free_chan_resources(struct dma_chan *chan) vchan_free_chan_resources(&ch->vc); - dev_dbg(chan2dev(chan), "%s: freeing channel #%u\n", + dev_dbg(dmaengine_chan_dev(chan), "%s: freeing channel #%u\n", __func__, ch->ch_num); ch->allocated = 0; } @@ -379,7 +374,7 @@ static void moxart_set_transfer_params(struct moxart_chan *ch, unsigned int len) */ writel(d->dma_cycles, ch->base + REG_OFF_CYCLES); - dev_dbg(chan2dev(&ch->vc.chan), "%s: set %u DMA cycles (len=%u)\n", + dev_dbg(vchan_chan_dev(&ch->vc), "%s: set %u DMA cycles (len=%u)\n", __func__, d->dma_cycles, len); } @@ -460,7 +455,7 @@ static size_t moxart_dma_desc_size_in_flight(struct moxart_chan *ch) completed_cycles = (ch->desc->dma_cycles - cycles); size -= completed_cycles << es_bytes[ch->desc->es]; - dev_dbg(chan2dev(&ch->vc.chan), "%s: size=%zu\n", __func__, size); + dev_dbg(vchan_chan_dev(&ch->vc), "%s: size=%zu\n", __func__, size); return size; } @@ -517,7 +512,7 @@ static irqreturn_t moxart_dma_interrupt(int irq, void *devid) unsigned int i; u32 ctrl; - dev_dbg(chan2dev(&ch->vc.chan), "%s\n", __func__); + dev_dbg(vchan_chan_dev(&ch->vc), "%s\n", __func__); for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) { if (!ch->allocated) @@ -525,7 +520,7 @@ static irqreturn_t moxart_dma_interrupt(int irq, void *devid) ctrl = readl(ch->base + REG_OFF_CTRL); - dev_dbg(chan2dev(&ch->vc.chan), "%s: ch=%p ch->base=%p ctrl=%x\n", + dev_dbg(vchan_chan_dev(&ch->vc), "%s: ch=%p ch->base=%p ctrl=%x\n", __func__, ch, ch->base, ctrl); if (ctrl & APB_DMA_FIN_INT_STS) { diff --git a/drivers/dma/nbpfaxi.c b/drivers/dma/nbpfaxi.c index 05d7321629cc..744cd14d7872 100644 --- a/drivers/dma/nbpfaxi.c +++ b/drivers/dma/nbpfaxi.c @@ -1202,7 +1202,7 @@ static irqreturn_t nbpf_chan_irq(int irq, void *dev) nbpf_status_ack(chan); - dev_dbg(&chan->dma_chan.dev->device, "%s()\n", __func__); + dev_dbg(dmaengine_chan_dev(&chan->dma_chan), "%s()\n", __func__); spin_lock(&chan->lock); desc = chan->running; diff --git a/drivers/dma/owl-dma.c b/drivers/dma/owl-dma.c index 7c80572fc71d..9dc88d804a2e 100644 --- a/drivers/dma/owl-dma.c +++ b/drivers/dma/owl-dma.c @@ -292,11 +292,6 @@ static inline struct owl_dma *to_owl_dma(struct dma_device *dd) return container_of(dd, struct owl_dma, dma); } -static struct device *chan2dev(struct dma_chan *chan) -{ - return &chan->dev->device; -} - static inline struct owl_dma_vchan *to_owl_vchan(struct dma_chan *chan) { return container_of(chan, struct owl_dma_vchan, vc.chan); @@ -573,7 +568,7 @@ static int owl_dma_start_next_txd(struct owl_dma_vchan *vchan) spin_unlock_irqrestore(&od->lock, flags); - dev_dbg(chan2dev(&vchan->vc.chan), "starting pchan %d\n", pchan->id); + dev_dbg(vchan_chan_dev(&vchan->vc), "starting pchan %d\n", pchan->id); /* Start DMA transfer for this pchan */ pchan_writel(pchan, OWL_DMAX_START, 0x1); @@ -757,7 +752,7 @@ static int owl_dma_resume(struct dma_chan *chan) if (!vchan->pchan && !vchan->txd) return 0; - dev_dbg(chan2dev(chan), "vchan %p: resume\n", &vchan->vc); + dev_dbg(dmaengine_chan_dev(chan), "vchan %p: resume\n", &vchan->vc); spin_lock_irqsave(&vchan->vc.lock, flags); @@ -888,7 +883,7 @@ static struct dma_async_tx_descriptor for (offset = 0; offset < len; offset += bytes) { lli = owl_dma_alloc_lli(od); if (!lli) { - dev_warn(chan2dev(chan), "failed to allocate lli\n"); + dev_warn(dmaengine_chan_dev(chan), "failed to allocate lli\n"); goto err_txd_free; } @@ -898,7 +893,7 @@ static struct dma_async_tx_descriptor bytes, DMA_MEM_TO_MEM, &vchan->cfg, txd->cyclic); if (ret) { - dev_warn(chan2dev(chan), "failed to config lli\n"); + dev_warn(dmaengine_chan_dev(chan), "failed to config lli\n"); goto err_txd_free; } @@ -947,7 +942,7 @@ static struct dma_async_tx_descriptor lli = owl_dma_alloc_lli(od); if (!lli) { - dev_err(chan2dev(chan), "failed to allocate lli"); + dev_err(dmaengine_chan_dev(chan), "failed to allocate lli"); goto err_txd_free; } @@ -962,7 +957,7 @@ static struct dma_async_tx_descriptor ret = owl_dma_cfg_lli(vchan, lli, src, dst, len, dir, sconfig, txd->cyclic); if (ret) { - dev_warn(chan2dev(chan), "failed to config lli"); + dev_warn(dmaengine_chan_dev(chan), "failed to config lli"); goto err_txd_free; } @@ -1003,7 +998,7 @@ static struct dma_async_tx_descriptor for (i = 0; i < periods; i++) { lli = owl_dma_alloc_lli(od); if (!lli) { - dev_warn(chan2dev(chan), "failed to allocate lli"); + dev_warn(dmaengine_chan_dev(chan), "failed to allocate lli"); goto err_txd_free; } @@ -1018,7 +1013,7 @@ static struct dma_async_tx_descriptor ret = owl_dma_cfg_lli(vchan, lli, src, dst, period_len, dir, sconfig, txd->cyclic); if (ret) { - dev_warn(chan2dev(chan), "failed to config lli"); + dev_warn(dmaengine_chan_dev(chan), "failed to config lli"); goto err_txd_free; } diff --git a/drivers/dma/pch_dma.c b/drivers/dma/pch_dma.c index bf805f1024f6..88baf7ffec37 100644 --- a/drivers/dma/pch_dma.c +++ b/drivers/dma/pch_dma.c @@ -150,11 +150,6 @@ static inline struct pch_dma *to_pd(struct dma_device *ddev) return container_of(ddev, struct pch_dma, dma); } -static inline struct device *chan2dev(struct dma_chan *chan) -{ - return &chan->dev->device; -} - static inline struct pch_dma_desc *pdc_first_active(struct pch_dma_chan *pd_chan) { @@ -189,7 +184,7 @@ static void pdc_enable_irq(struct dma_chan *chan, int enable) dma_writel(pd, CTL2, val); - dev_dbg(chan2dev(chan), "pdc_enable_irq: chan %d -> %x\n", + dev_dbg(dmaengine_chan_dev(chan), "pdc_enable_irq: chan %d -> %x\n", chan->chan_id, val); } @@ -237,7 +232,7 @@ static void pdc_set_dir(struct dma_chan *chan) dma_writel(pd, CTL3, val); } - dev_dbg(chan2dev(chan), "pdc_set_dir: chan %d -> %x\n", + dev_dbg(dmaengine_chan_dev(chan), "pdc_set_dir: chan %d -> %x\n", chan->chan_id, val); } @@ -271,7 +266,7 @@ static void pdc_set_mode(struct dma_chan *chan, u32 mode) dma_writel(pd, CTL3, val); } - dev_dbg(chan2dev(chan), "pdc_set_mode: chan %d -> %x\n", + dev_dbg(dmaengine_chan_dev(chan), "pdc_set_mode: chan %d -> %x\n", chan->chan_id, val); } @@ -314,18 +309,18 @@ static bool pdc_is_idle(struct pch_dma_chan *pd_chan) static void pdc_dostart(struct pch_dma_chan *pd_chan, struct pch_dma_desc* desc) { if (!pdc_is_idle(pd_chan)) { - dev_err(chan2dev(&pd_chan->chan), + dev_err(dmaengine_chan_dev(&pd_chan->chan), "BUG: Attempt to start non-idle channel\n"); return; } - dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> dev_addr: %x\n", + dev_dbg(dmaengine_chan_dev(&pd_chan->chan), "chan %d -> dev_addr: %x\n", pd_chan->chan.chan_id, desc->regs.dev_addr); - dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> mem_addr: %x\n", + dev_dbg(dmaengine_chan_dev(&pd_chan->chan), "chan %d -> mem_addr: %x\n", pd_chan->chan.chan_id, desc->regs.mem_addr); - dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> size: %x\n", + dev_dbg(dmaengine_chan_dev(&pd_chan->chan), "chan %d -> size: %x\n", pd_chan->chan.chan_id, desc->regs.size); - dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> next: %x\n", + dev_dbg(dmaengine_chan_dev(&pd_chan->chan), "chan %d -> next: %x\n", pd_chan->chan.chan_id, desc->regs.next); if (list_empty(&desc->tx_list)) { @@ -382,8 +377,8 @@ static void pdc_handle_error(struct pch_dma_chan *pd_chan) if (!list_empty(&pd_chan->active_list)) pdc_dostart(pd_chan, pdc_first_active(pd_chan)); - dev_crit(chan2dev(&pd_chan->chan), "Bad descriptor submitted\n"); - dev_crit(chan2dev(&pd_chan->chan), "descriptor cookie: %d\n", + dev_crit(dmaengine_chan_dev(&pd_chan->chan), "Bad descriptor submitted\n"); + dev_crit(dmaengine_chan_dev(&pd_chan->chan), "descriptor cookie: %d\n", bad_desc->txd.cookie); pdc_chain_complete(pd_chan, bad_desc); @@ -450,10 +445,10 @@ static struct pch_dma_desc *pdc_desc_get(struct pch_dma_chan *pd_chan) ret = desc; break; } - dev_dbg(chan2dev(&pd_chan->chan), "desc %p not ACKed\n", desc); + dev_dbg(dmaengine_chan_dev(&pd_chan->chan), "desc %p not ACKed\n", desc); } spin_unlock(&pd_chan->lock); - dev_dbg(chan2dev(&pd_chan->chan), "scanned %d descriptors\n", i); + dev_dbg(dmaengine_chan_dev(&pd_chan->chan), "scanned %d descriptors\n", i); if (!ret) { ret = pdc_alloc_desc(&pd_chan->chan, GFP_ATOMIC); @@ -462,7 +457,7 @@ static struct pch_dma_desc *pdc_desc_get(struct pch_dma_chan *pd_chan) pd_chan->descs_allocated++; spin_unlock(&pd_chan->lock); } else { - dev_err(chan2dev(&pd_chan->chan), + dev_err(dmaengine_chan_dev(&pd_chan->chan), "failed to alloc desc\n"); } } @@ -489,7 +484,7 @@ static int pd_alloc_chan_resources(struct dma_chan *chan) int i; if (!pdc_is_idle(pd_chan)) { - dev_dbg(chan2dev(chan), "DMA channel not idle ?\n"); + dev_dbg(dmaengine_chan_dev(chan), "DMA channel not idle ?\n"); return -EIO; } @@ -500,7 +495,7 @@ static int pd_alloc_chan_resources(struct dma_chan *chan) desc = pdc_alloc_desc(chan, GFP_KERNEL); if (!desc) { - dev_warn(chan2dev(chan), + dev_warn(dmaengine_chan_dev(chan), "Only allocated %d initial descriptors\n", i); break; } @@ -573,7 +568,7 @@ static struct dma_async_tx_descriptor *pd_prep_slave_sg(struct dma_chan *chan, int i; if (unlikely(!sg_len)) { - dev_info(chan2dev(chan), "prep_slave_sg: length is zero!\n"); + dev_info(dmaengine_chan_dev(chan), "prep_slave_sg: length is zero!\n"); return NULL; } @@ -639,7 +634,7 @@ static struct dma_async_tx_descriptor *pd_prep_slave_sg(struct dma_chan *chan, return &first->txd; err_desc_get: - dev_err(chan2dev(chan), "failed to get desc or wrong parameters\n"); + dev_err(dmaengine_chan_dev(chan), "failed to get desc or wrong parameters\n"); pdc_desc_put(pd_chan, first); return NULL; } @@ -671,7 +666,7 @@ static void pdc_tasklet(struct tasklet_struct *t) unsigned long flags; if (!pdc_is_idle(pd_chan)) { - dev_err(chan2dev(&pd_chan->chan), + dev_err(dmaengine_chan_dev(&pd_chan->chan), "BUG: handle non-idle channel in tasklet\n"); return; } diff --git a/drivers/dma/pxa_dma.c b/drivers/dma/pxa_dma.c index fa2ee0b3e09f..b552b34f2a67 100644 --- a/drivers/dma/pxa_dma.c +++ b/drivers/dma/pxa_dma.c @@ -149,7 +149,7 @@ struct pxad_device { ({ \ u32 _v; \ _v = readl_relaxed((phy)->base + _reg((phy)->idx)); \ - dev_vdbg(&phy->vchan->vc.chan.dev->device, \ + dev_vdbg(vchan_chan_dev(&phy->vchan->vc), \ "%s(): readl(%s): 0x%08x\n", __func__, #_reg, \ _v); \ _v; \ @@ -157,14 +157,14 @@ struct pxad_device { #define phy_writel(phy, val, _reg) \ do { \ writel((val), (phy)->base + _reg((phy)->idx)); \ - dev_vdbg(&phy->vchan->vc.chan.dev->device, \ + dev_vdbg(vchan_chan_dev(&phy->vchan->vc), \ "%s(): writel(0x%08x, %s)\n", \ __func__, (u32)(val), #_reg); \ } while (0) #define phy_writel_relaxed(phy, val, _reg) \ do { \ writel_relaxed((val), (phy)->base + _reg((phy)->idx)); \ - dev_vdbg(&phy->vchan->vc.chan.dev->device, \ + dev_vdbg(vchan_chan_dev(&phy->vchan->vc), \ "%s(): writel_relaxed(0x%08x, %s)\n", \ __func__, (u32)(val), #_reg); \ } while (0) @@ -396,7 +396,7 @@ static struct pxad_phy *lookup_phy(struct pxad_chan *pchan) out_unlock: spin_unlock_irqrestore(&pdev->phy_lock, flags); - dev_dbg(&pchan->vc.chan.dev->device, + dev_dbg(vchan_chan_dev(&pchan->vc), "%s(): phy=%p(%d)\n", __func__, found, found ? found->idx : -1); @@ -409,7 +409,7 @@ static void pxad_free_phy(struct pxad_chan *chan) unsigned long flags; u32 reg; - dev_dbg(&chan->vc.chan.dev->device, + dev_dbg(vchan_chan_dev(&chan->vc), "%s(): freeing\n", __func__); if (!chan->phy) return; @@ -454,7 +454,7 @@ static void phy_enable(struct pxad_phy *phy, bool misaligned) if (!phy->vchan) return; - dev_dbg(&phy->vchan->vc.chan.dev->device, + dev_dbg(vchan_chan_dev(&phy->vchan->vc), "%s(); phy=%p(%d) misaligned=%d\n", __func__, phy, phy->idx, misaligned); @@ -483,7 +483,7 @@ static void phy_disable(struct pxad_phy *phy) return; dcsr = phy_readl_relaxed(phy, DCSR); - dev_dbg(&phy->vchan->vc.chan.dev->device, + dev_dbg(vchan_chan_dev(&phy->vchan->vc), "%s(): phy=%p(%d)\n", __func__, phy, phy->idx); phy_writel(phy, dcsr & ~PXA_DCSR_RUN & ~PXA_DCSR_STOPIRQEN, DCSR); } @@ -491,12 +491,12 @@ static void phy_disable(struct pxad_phy *phy) static void pxad_launch_chan(struct pxad_chan *chan, struct pxad_desc_sw *desc) { - dev_dbg(&chan->vc.chan.dev->device, + dev_dbg(vchan_chan_dev(&chan->vc), "%s(): desc=%p\n", __func__, desc); if (!chan->phy) { chan->phy = lookup_phy(chan); if (!chan->phy) { - dev_dbg(&chan->vc.chan.dev->device, + dev_dbg(vchan_chan_dev(&chan->vc), "%s(): no free dma channel\n", __func__); return; } @@ -592,7 +592,7 @@ static unsigned int clear_chan_irq(struct pxad_phy *phy) dcsr = phy_readl_relaxed(phy, DCSR); phy_writel(phy, dcsr, DCSR); if ((dcsr & PXA_DCSR_BUSERR) && (phy->vchan)) - dev_warn(&phy->vchan->vc.chan.dev->device, + dev_warn(vchan_chan_dev(&phy->vchan->vc), "%s(chan=%p): PXA_DCSR_BUSERR\n", __func__, &phy->vchan); @@ -617,7 +617,7 @@ static irqreturn_t pxad_chan_handler(int irq, void *dev_id) spin_lock(&chan->vc.lock); list_for_each_entry_safe(vd, tmp, &chan->vc.desc_issued, node) { vd_completed = is_desc_completed(vd); - dev_dbg(&chan->vc.chan.dev->device, + dev_dbg(vchan_chan_dev(&chan->vc), "%s(): checking txd %p[%x]: completed=%d dcsr=0x%x\n", __func__, vd, vd->tx.cookie, vd_completed, dcsr); @@ -640,7 +640,7 @@ static irqreturn_t pxad_chan_handler(int irq, void *dev_id) } if (!chan->bus_error && dcsr & PXA_DCSR_STOPSTATE) { - dev_dbg(&chan->vc.chan.dev->device, + dev_dbg(vchan_chan_dev(&chan->vc), "%s(): channel stopped, submitted_empty=%d issued_empty=%d", __func__, list_empty(&chan->vc.desc_submitted), @@ -694,7 +694,7 @@ static int pxad_alloc_chan_resources(struct dma_chan *dchan) __alignof__(struct pxad_desc_hw), 0); if (!chan->desc_pool) { - dev_err(&chan->vc.chan.dev->device, + dev_err(vchan_chan_dev(&chan->vc), "%s(): unable to allocate descriptor pool\n", __func__); return -ENOMEM; @@ -749,7 +749,7 @@ pxad_alloc_desc(struct pxad_chan *chan, unsigned int nb_hw_desc) for (i = 0; i < nb_hw_desc; i++) { desc = dma_pool_alloc(sw_desc->desc_pool, GFP_NOWAIT, &dma); if (!desc) { - dev_err(&chan->vc.chan.dev->device, + dev_err(vchan_chan_dev(&chan->vc), "%s(): Couldn't allocate the %dth hw_desc from dma_pool %p\n", __func__, i, sw_desc->desc_pool); goto err; @@ -786,7 +786,7 @@ static dma_cookie_t pxad_tx_submit(struct dma_async_tx_descriptor *tx) if (list_empty(&vc->desc_submitted) && pxad_try_hotchain(vc, vd)) { list_move_tail(&vd->node, &vc->desc_issued); - dev_dbg(&chan->vc.chan.dev->device, + dev_dbg(vchan_chan_dev(&chan->vc), "%s(): txd %p[%x]: submitted (hot linked)\n", __func__, vd, cookie); goto out; @@ -809,7 +809,7 @@ static dma_cookie_t pxad_tx_submit(struct dma_async_tx_descriptor *tx) else vd_chained = NULL; } - dev_dbg(&chan->vc.chan.dev->device, + dev_dbg(vchan_chan_dev(&chan->vc), "%s(): txd %p[%x]: submitted (%s linked)\n", __func__, vd, cookie, vd_chained ? "cold" : "not"); list_move_tail(&vd->node, &vc->desc_submitted); @@ -832,7 +832,7 @@ static void pxad_issue_pending(struct dma_chan *dchan) vd_first = list_first_entry(&chan->vc.desc_submitted, struct virt_dma_desc, node); - dev_dbg(&chan->vc.chan.dev->device, + dev_dbg(vchan_chan_dev(&chan->vc), "%s(): txd %p[%x]", __func__, vd_first, vd_first->tx.cookie); vchan_issue_pending(&chan->vc); @@ -852,7 +852,7 @@ pxad_tx_prep(struct virt_dma_chan *vc, struct virt_dma_desc *vd, INIT_LIST_HEAD(&vd->node); tx = vchan_tx_prep(vc, vd, tx_flags); tx->tx_submit = pxad_tx_submit; - dev_dbg(&chan->vc.chan.dev->device, + dev_dbg(vchan_chan_dev(&chan->vc), "%s(): vc=%p txd=%p[%x] flags=0x%lx\n", __func__, vc, vd, vd->tx.cookie, tx_flags); @@ -891,7 +891,7 @@ static void pxad_get_config(struct pxad_chan *chan, *dcmd |= PXA_DCMD_BURST32 | PXA_DCMD_INCTRGADDR | PXA_DCMD_INCSRCADDR; - dev_dbg(&chan->vc.chan.dev->device, + dev_dbg(vchan_chan_dev(&chan->vc), "%s(): dev_addr=0x%x maxburst=%d width=%d dir=%d\n", __func__, dev_addr, maxburst, width, dir); @@ -925,7 +925,7 @@ pxad_prep_memcpy(struct dma_chan *dchan, if (!dchan || !len) return NULL; - dev_dbg(&chan->vc.chan.dev->device, + dev_dbg(vchan_chan_dev(&chan->vc), "%s(): dma_dst=0x%lx dma_src=0x%lx len=%zu flags=%lx\n", __func__, (unsigned long)dma_dst, (unsigned long)dma_src, len, flags); @@ -974,7 +974,7 @@ pxad_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, return NULL; pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr); - dev_dbg(&chan->vc.chan.dev->device, + dev_dbg(vchan_chan_dev(&chan->vc), "%s(): dir=%d flags=%lx\n", __func__, dir, flags); nb_desc = sg_nents_for_dma(sgl, sg_len, PDMA_MAX_DESC_BYTES); @@ -1021,7 +1021,7 @@ pxad_prep_dma_cyclic(struct dma_chan *dchan, if (!dchan || !len || !period_len) return NULL; if ((dir != DMA_DEV_TO_MEM) && (dir != DMA_MEM_TO_DEV)) { - dev_err(&chan->vc.chan.dev->device, + dev_err(vchan_chan_dev(&chan->vc), "Unsupported direction for cyclic DMA\n"); return NULL; } @@ -1032,7 +1032,7 @@ pxad_prep_dma_cyclic(struct dma_chan *dchan, pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr); dcmd |= PXA_DCMD_ENDIRQEN | (PXA_DCMD_LENGTH & period_len); - dev_dbg(&chan->vc.chan.dev->device, + dev_dbg(vchan_chan_dev(&chan->vc), "%s(): buf_addr=0x%lx len=%zu period=%zu dir=%d flags=%lx\n", __func__, (unsigned long)buf_addr, len, period_len, dir, flags); @@ -1080,14 +1080,14 @@ static int pxad_terminate_all(struct dma_chan *dchan) struct pxad_phy *phy; LIST_HEAD(head); - dev_dbg(&chan->vc.chan.dev->device, + dev_dbg(vchan_chan_dev(&chan->vc), "%s(): vchan %p: terminate all\n", __func__, &chan->vc); spin_lock_irqsave(&chan->vc.lock, flags); vchan_get_all_descriptors(&chan->vc, &head); list_for_each_entry(vd, &head, node) { - dev_dbg(&chan->vc.chan.dev->device, + dev_dbg(vchan_chan_dev(&chan->vc), "%s(): cancelling txd %p[%x] (completed=%d)", __func__, vd, vd->tx.cookie, is_desc_completed(vd)); } @@ -1177,7 +1177,7 @@ static unsigned int pxad_residue(struct pxad_chan *chan, out: spin_unlock_irqrestore(&chan->vc.lock, flags); - dev_dbg(&chan->vc.chan.dev->device, + dev_dbg(vchan_chan_dev(&chan->vc), "%s(): txd %p[%x] sw_desc=%p: %d\n", __func__, vd, cookie, sw_desc, residue); return residue; diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 0d9ffa3e2663..05e797496cae 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -623,11 +623,6 @@ struct d40_base { struct d40_chan phy_chans[]; }; -static struct device *chan2dev(struct d40_chan *d40c) -{ - return &d40c->chan.dev->device; -} - static bool chan_is_physical(struct d40_chan *chan) { return chan->log_num == D40_PHY_CHAN; @@ -648,7 +643,7 @@ static void __iomem *chan_base(struct d40_chan *chan) dev_err(dev, "[%s] " format, __func__, ## arg) #define chan_err(d40c, format, arg...) \ - d40_err(chan2dev(d40c), format, ## arg) + d40_err(dmaengine_chan_dev(&d40c->chan), format, ## arg) static int d40_set_runtime_config_write(struct dma_chan *chan, struct dma_slave_config *config, @@ -1243,7 +1238,7 @@ static void __d40_config_set_event(struct d40_chan *d40c, } if (tries != 99) - dev_dbg(chan2dev(d40c), + dev_dbg(dmaengine_chan_dev(&d40c->chan), "[%s] workaround enable S%cLNK (%d tries)\n", __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D', 100 - tries); @@ -1924,7 +1919,7 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user) i = d40c->dma_cfg.phy_channel; if ((i != phy_num) && (i != phy_num + 1)) { - dev_err(chan2dev(d40c), + dev_err(dmaengine_chan_dev(&d40c->chan), "invalid fixed phy channel %d\n", i); return -EINVAL; } @@ -1933,7 +1928,7 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user) is_log, first_phy_user)) goto found_log; - dev_err(chan2dev(d40c), + dev_err(dmaengine_chan_dev(&d40c->chan), "could not allocate fixed phy channel %d\n", i); return -EINVAL; } @@ -2446,7 +2441,7 @@ static int d40_alloc_chan_resources(struct dma_chan *chan) d40c->dst_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS); } - dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n", + dev_dbg(dmaengine_chan_dev(&d40c->chan), "allocated %s channel (phy %d%s)\n", chan_is_logical(d40c) ? "logical" : "physical", d40c->phy_chan->num, d40c->dma_cfg.use_fixed_channel ? ", fixed" : ""); diff --git a/drivers/dma/stm32/stm32-dma.c b/drivers/dma/stm32/stm32-dma.c index 3e8151e2ad75..4688cebaf7f7 100644 --- a/drivers/dma/stm32/stm32-dma.c +++ b/drivers/dma/stm32/stm32-dma.c @@ -248,11 +248,6 @@ static struct stm32_dma_desc *to_stm32_dma_desc(struct virt_dma_desc *vdesc) return container_of(vdesc, struct stm32_dma_desc, vdesc); } -static struct device *chan2dev(struct stm32_dma_chan *chan) -{ - return &chan->vchan.chan.dev->device; -} - static u32 stm32_dma_read(struct stm32_dma_device *dmadev, u32 reg) { return readl_relaxed(dmadev->base + reg); @@ -274,7 +269,7 @@ static int stm32_dma_get_width(struct stm32_dma_chan *chan, case DMA_SLAVE_BUSWIDTH_4_BYTES: return STM32_DMA_WORD; default: - dev_err(chan2dev(chan), "Dma bus width not supported\n"); + dev_err(vchan_chan_dev(&chan->vchan), "Dma bus width not supported\n"); return -EINVAL; } } @@ -374,7 +369,7 @@ static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst) case 16: return STM32_DMA_BURST_INCR16; default: - dev_err(chan2dev(chan), "Dma burst size not supported\n"); + dev_err(vchan_chan_dev(&chan->vchan), "Dma burst size not supported\n"); return -EINVAL; } } @@ -487,7 +482,7 @@ static void stm32_dma_stop(struct stm32_dma_chan *chan) /* Clear interrupt status if it is there */ status = stm32_dma_irq_status(chan); if (status) { - dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n", + dev_dbg(vchan_chan_dev(&chan->vchan), "%s(): clearing interrupt: 0x%08x\n", __func__, status); stm32_dma_irq_clear(chan, status); } @@ -536,12 +531,12 @@ static void stm32_dma_dump_reg(struct stm32_dma_chan *chan) u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id)); u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); - dev_dbg(chan2dev(chan), "SCR: 0x%08x\n", scr); - dev_dbg(chan2dev(chan), "NDTR: 0x%08x\n", ndtr); - dev_dbg(chan2dev(chan), "SPAR: 0x%08x\n", spar); - dev_dbg(chan2dev(chan), "SM0AR: 0x%08x\n", sm0ar); - dev_dbg(chan2dev(chan), "SM1AR: 0x%08x\n", sm1ar); - dev_dbg(chan2dev(chan), "SFCR: 0x%08x\n", sfcr); + dev_dbg(vchan_chan_dev(&chan->vchan), "SCR: 0x%08x\n", scr); + dev_dbg(vchan_chan_dev(&chan->vchan), "NDTR: 0x%08x\n", ndtr); + dev_dbg(vchan_chan_dev(&chan->vchan), "SPAR: 0x%08x\n", spar); + dev_dbg(vchan_chan_dev(&chan->vchan), "SM0AR: 0x%08x\n", sm0ar); + dev_dbg(vchan_chan_dev(&chan->vchan), "SM1AR: 0x%08x\n", sm1ar); + dev_dbg(vchan_chan_dev(&chan->vchan), "SFCR: 0x%08x\n", sfcr); } static void stm32_dma_sg_inc(struct stm32_dma_chan *chan) @@ -613,7 +608,7 @@ static void stm32_dma_start_transfer(struct stm32_dma_chan *chan) reg->dma_scr |= STM32_DMA_SCR_EN; stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); - dev_dbg(chan2dev(chan), "vchan %p: started\n", &chan->vchan); + dev_dbg(vchan_chan_dev(&chan->vchan), "vchan %p: started\n", &chan->vchan); } static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan) @@ -630,12 +625,12 @@ static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan) if (dma_scr & STM32_DMA_SCR_CT) { dma_sm0ar = sg_req->chan_reg.dma_sm0ar; stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar); - dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n", + dev_dbg(vchan_chan_dev(&chan->vchan), "CT=1 <=> SM0AR: 0x%08x\n", stm32_dma_read(dmadev, STM32_DMA_SM0AR(id))); } else { dma_sm1ar = sg_req->chan_reg.dma_sm1ar; stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar); - dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n", + dev_dbg(vchan_chan_dev(&chan->vchan), "CT=0 <=> SM1AR: 0x%08x\n", stm32_dma_read(dmadev, STM32_DMA_SM1AR(id))); } } @@ -676,7 +671,7 @@ static void stm32_dma_handle_chan_paused(struct stm32_dma_chan *chan) chan->status = DMA_PAUSED; - dev_dbg(chan2dev(chan), "vchan %p: paused\n", &chan->vchan); + dev_dbg(vchan_chan_dev(&chan->vchan), "vchan %p: paused\n", &chan->vchan); } static void stm32_dma_post_resume_reconfigure(struct stm32_dma_chan *chan) @@ -728,7 +723,7 @@ static void stm32_dma_post_resume_reconfigure(struct stm32_dma_chan *chan) dma_scr |= STM32_DMA_SCR_EN; stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); - dev_dbg(chan2dev(chan), "vchan %p: reconfigured after pause/resume\n", &chan->vchan); + dev_dbg(vchan_chan_dev(&chan->vchan), "vchan %p: reconfigured after pause/resume\n", &chan->vchan); } static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan, u32 scr) @@ -775,16 +770,16 @@ static irqreturn_t stm32_dma_chan_irq(int irq, void *devid) if (sfcr & STM32_DMA_SFCR_FEIE) { if (!(scr & STM32_DMA_SCR_EN) && !(status & STM32_DMA_TCI)) - dev_err(chan2dev(chan), "FIFO Error\n"); + dev_err(vchan_chan_dev(&chan->vchan), "FIFO Error\n"); else - dev_dbg(chan2dev(chan), "FIFO over/underrun\n"); + dev_dbg(vchan_chan_dev(&chan->vchan), "FIFO over/underrun\n"); } } if (status & STM32_DMA_DMEI) { stm32_dma_irq_clear(chan, STM32_DMA_DMEI); status &= ~STM32_DMA_DMEI; if (sfcr & STM32_DMA_SCR_DMEIE) - dev_dbg(chan2dev(chan), "Direct mode overrun\n"); + dev_dbg(vchan_chan_dev(&chan->vchan), "Direct mode overrun\n"); } if (status & STM32_DMA_TCI) { @@ -803,9 +798,9 @@ static irqreturn_t stm32_dma_chan_irq(int irq, void *devid) if (status) { stm32_dma_irq_clear(chan, status); - dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status); + dev_err(vchan_chan_dev(&chan->vchan), "DMA error: status=0x%08x\n", status); if (!(scr & STM32_DMA_SCR_EN)) - dev_err(chan2dev(chan), "chan disabled by HW\n"); + dev_err(vchan_chan_dev(&chan->vchan), "chan disabled by HW\n"); } spin_unlock(&chan->vchan.lock); @@ -820,7 +815,7 @@ static void stm32_dma_issue_pending(struct dma_chan *c) spin_lock_irqsave(&chan->vchan.lock, flags); if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) { - dev_dbg(chan2dev(chan), "vchan %p: issued\n", &chan->vchan); + dev_dbg(vchan_chan_dev(&chan->vchan), "vchan %p: issued\n", &chan->vchan); stm32_dma_start_transfer(chan); } @@ -922,7 +917,7 @@ static int stm32_dma_resume(struct dma_chan *c) spin_unlock_irqrestore(&chan->vchan.lock, flags); - dev_dbg(chan2dev(chan), "vchan %p: resumed\n", &chan->vchan); + dev_dbg(vchan_chan_dev(&chan->vchan), "vchan %p: resumed\n", &chan->vchan); return 0; } @@ -1059,7 +1054,7 @@ static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan, break; default: - dev_err(chan2dev(chan), "Dma direction is not supported\n"); + dev_err(vchan_chan_dev(&chan->vchan), "Dma direction is not supported\n"); return -EINVAL; } @@ -1092,12 +1087,12 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg( int i, ret; if (!chan->config_init) { - dev_err(chan2dev(chan), "dma channel is not configured\n"); + dev_err(vchan_chan_dev(&chan->vchan), "dma channel is not configured\n"); return NULL; } if (sg_len < 1) { - dev_err(chan2dev(chan), "Invalid segment length %d\n", sg_len); + dev_err(vchan_chan_dev(&chan->vchan), "Invalid segment length %d\n", sg_len); return NULL; } @@ -1129,7 +1124,7 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg( nb_data_items = desc->sg_req[i].len / buswidth; if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) { - dev_err(chan2dev(chan), "nb items not supported\n"); + dev_err(vchan_chan_dev(&chan->vchan), "nb items not supported\n"); goto err; } @@ -1164,17 +1159,17 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic( int i, ret; if (!buf_len || !period_len) { - dev_err(chan2dev(chan), "Invalid buffer/period len\n"); + dev_err(vchan_chan_dev(&chan->vchan), "Invalid buffer/period len\n"); return NULL; } if (!chan->config_init) { - dev_err(chan2dev(chan), "dma channel is not configured\n"); + dev_err(vchan_chan_dev(&chan->vchan), "dma channel is not configured\n"); return NULL; } if (buf_len % period_len) { - dev_err(chan2dev(chan), "buf_len not multiple of period_len\n"); + dev_err(vchan_chan_dev(&chan->vchan), "buf_len not multiple of period_len\n"); return NULL; } @@ -1185,7 +1180,7 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic( * terminating the DMA. */ if (chan->busy) { - dev_err(chan2dev(chan), "Request not allowed when dma busy\n"); + dev_err(vchan_chan_dev(&chan->vchan), "Request not allowed when dma busy\n"); return NULL; } @@ -1196,7 +1191,7 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic( nb_data_items = period_len / buswidth; if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) { - dev_err(chan2dev(chan), "number of items not supported\n"); + dev_err(vchan_chan_dev(&chan->vchan), "number of items not supported\n"); return NULL; } @@ -1478,7 +1473,7 @@ static void stm32_dma_free_chan_resources(struct dma_chan *c) struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); unsigned long flags; - dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id); + dev_dbg(vchan_chan_dev(&chan->vchan), "Freeing channel %d\n", chan->id); if (chan->busy) { spin_lock_irqsave(&chan->vchan.lock, flags); diff --git a/drivers/dma/stm32/stm32-dma3.c b/drivers/dma/stm32/stm32-dma3.c index 6ee7a1435efb..4fe226541efa 100644 --- a/drivers/dma/stm32/stm32-dma3.c +++ b/drivers/dma/stm32/stm32-dma3.c @@ -328,11 +328,6 @@ static inline struct stm32_dma3_swdesc *to_stm32_dma3_swdesc(struct virt_dma_des return container_of(vdesc, struct stm32_dma3_swdesc, vdesc); } -static struct device *chan2dev(struct stm32_dma3_chan *chan) -{ - return &chan->vchan.chan.dev->device; -} - static struct device *ddata2dev(struct stm32_dma3_ddata *ddata) { return ddata->dma_dev.dev; @@ -341,7 +336,7 @@ static struct device *ddata2dev(struct stm32_dma3_ddata *ddata) static void stm32_dma3_chan_dump_reg(struct stm32_dma3_chan *chan) { struct stm32_dma3_ddata *ddata = to_stm32_dma3_ddata(chan); - struct device *dev = chan2dev(chan); + struct device *dev = vchan_chan_dev(&chan->vchan); u32 id = chan->id, offset; offset = STM32_DMA3_SECCFGR; @@ -381,21 +376,21 @@ static void stm32_dma3_chan_dump_hwdesc(struct stm32_dma3_chan *chan, for (i = 0; i < swdesc->lli_size; i++) { hwdesc = swdesc->lli[i].hwdesc; if (i) - dev_dbg(chan2dev(chan), "V\n"); - dev_dbg(chan2dev(chan), "[%d]@%pad\n", i, &swdesc->lli[i].hwdesc_addr); - dev_dbg(chan2dev(chan), "| C%dTR1: %08x\n", chan->id, hwdesc->ctr1); - dev_dbg(chan2dev(chan), "| C%dTR2: %08x\n", chan->id, hwdesc->ctr2); - dev_dbg(chan2dev(chan), "| C%dBR1: %08x\n", chan->id, hwdesc->cbr1); - dev_dbg(chan2dev(chan), "| C%dSAR: %08x\n", chan->id, hwdesc->csar); - dev_dbg(chan2dev(chan), "| C%dDAR: %08x\n", chan->id, hwdesc->cdar); - dev_dbg(chan2dev(chan), "| C%dLLR: %08x\n", chan->id, hwdesc->cllr); + dev_dbg(vchan_chan_dev(&chan->vchan), "V\n"); + dev_dbg(vchan_chan_dev(&chan->vchan), "[%d]@%pad\n", i, &swdesc->lli[i].hwdesc_addr); + dev_dbg(vchan_chan_dev(&chan->vchan), "| C%dTR1: %08x\n", chan->id, hwdesc->ctr1); + dev_dbg(vchan_chan_dev(&chan->vchan), "| C%dTR2: %08x\n", chan->id, hwdesc->ctr2); + dev_dbg(vchan_chan_dev(&chan->vchan), "| C%dBR1: %08x\n", chan->id, hwdesc->cbr1); + dev_dbg(vchan_chan_dev(&chan->vchan), "| C%dSAR: %08x\n", chan->id, hwdesc->csar); + dev_dbg(vchan_chan_dev(&chan->vchan), "| C%dDAR: %08x\n", chan->id, hwdesc->cdar); + dev_dbg(vchan_chan_dev(&chan->vchan), "| C%dLLR: %08x\n", chan->id, hwdesc->cllr); } if (swdesc->cyclic) { - dev_dbg(chan2dev(chan), "|\n"); - dev_dbg(chan2dev(chan), "-->[0]@%pad\n", &swdesc->lli[0].hwdesc_addr); + dev_dbg(vchan_chan_dev(&chan->vchan), "|\n"); + dev_dbg(vchan_chan_dev(&chan->vchan), "-->[0]@%pad\n", &swdesc->lli[0].hwdesc_addr); } else { - dev_dbg(chan2dev(chan), "X\n"); + dev_dbg(vchan_chan_dev(&chan->vchan), "X\n"); } } @@ -411,7 +406,7 @@ static struct stm32_dma3_swdesc *stm32_dma3_chan_desc_alloc(struct stm32_dma3_ch * addressed, so abort the allocation. */ if ((count * 32) > CLLR_LA) { - dev_err(chan2dev(chan), "Transfer is too big (> %luB)\n", STM32_DMA3_MAX_SEG_SIZE); + dev_err(vchan_chan_dev(&chan->vchan), "Transfer is too big (> %luB)\n", STM32_DMA3_MAX_SEG_SIZE); return NULL; } @@ -438,7 +433,7 @@ static struct stm32_dma3_swdesc *stm32_dma3_chan_desc_alloc(struct stm32_dma3_ch return swdesc; err_pool_free: - dev_err(chan2dev(chan), "Failed to alloc descriptors\n"); + dev_err(vchan_chan_dev(&chan->vchan), "Failed to alloc descriptors\n"); while (--i >= 0) dma_pool_free(chan->lli_pool, swdesc->lli[i].hwdesc, swdesc->lli[i].hwdesc_addr); kfree(swdesc); @@ -468,7 +463,7 @@ static void stm32_dma3_chan_vdesc_free(struct virt_dma_desc *vdesc) static void stm32_dma3_check_user_setting(struct stm32_dma3_chan *chan) { struct stm32_dma3_ddata *ddata = to_stm32_dma3_ddata(chan); - struct device *dev = chan2dev(chan); + struct device *dev = vchan_chan_dev(&chan->vchan); u32 ctr1 = readl_relaxed(ddata->base + STM32_DMA3_CTR1(chan->id)); u32 cbr1 = readl_relaxed(ddata->base + STM32_DMA3_CBR1(chan->id)); u32 csar = readl_relaxed(ddata->base + STM32_DMA3_CSAR(chan->id)); @@ -579,7 +574,7 @@ static int stm32_dma3_chan_prep_hw(struct stm32_dma3_chan *chan, enum dma_transf u32 sap = FIELD_GET(STM32_DMA3_DT_SAP, tr_conf), sap_max_dw; u32 dap = FIELD_GET(STM32_DMA3_DT_DAP, tr_conf), dap_max_dw; - dev_dbg(chan2dev(chan), "%s from %pad to %pad\n", + dev_dbg(vchan_chan_dev(&chan->vchan), "%s from %pad to %pad\n", dmaengine_get_direction_text(dir), &src_addr, &dst_addr); sdw = chan->dma_config.src_addr_width ? : get_chan_max_dw(sap, chan->max_burst); @@ -589,12 +584,12 @@ static int stm32_dma3_chan_prep_hw(struct stm32_dma3_chan *chan, enum dma_transf /* Following conditions would raise User Setting Error interrupt */ if (!(dma_device.src_addr_widths & BIT(sdw)) || !(dma_device.dst_addr_widths & BIT(ddw))) { - dev_err(chan2dev(chan), "Bus width (src=%u, dst=%u) not supported\n", sdw, ddw); + dev_err(vchan_chan_dev(&chan->vchan), "Bus width (src=%u, dst=%u) not supported\n", sdw, ddw); return -EINVAL; } if (ddata->ports_max_dw[1] == DW_INVALID && (sap || dap)) { - dev_err(chan2dev(chan), "Only one master port, port 1 is not supported\n"); + dev_err(vchan_chan_dev(&chan->vchan), "Only one master port, port 1 is not supported\n"); return -EINVAL; } @@ -602,7 +597,7 @@ static int stm32_dma3_chan_prep_hw(struct stm32_dma3_chan *chan, enum dma_transf dap_max_dw = ddata->ports_max_dw[dap]; if ((port_is_ahb(sap_max_dw) && sdw == DMA_SLAVE_BUSWIDTH_8_BYTES) || (port_is_ahb(dap_max_dw) && ddw == DMA_SLAVE_BUSWIDTH_8_BYTES)) { - dev_err(chan2dev(chan), + dev_err(vchan_chan_dev(&chan->vchan), "8 bytes buswidth (src=%u, dst=%u) not supported on port (sap=%u, dap=%u\n", sdw, ddw, sap, dap); return -EINVAL; @@ -659,7 +654,7 @@ static int stm32_dma3_chan_prep_hw(struct stm32_dma3_chan *chan, enum dma_transf _ctr1 |= FIELD_PREP(CTR1_PAM, CTR1_PAM_PACK_UNPACK); /* Should never reach this case as ddw is clamped down */ if (len & (ddw - 1)) { - dev_err(chan2dev(chan), + dev_err(vchan_chan_dev(&chan->vchan), "Packing mode is enabled and len is not multiple of ddw"); return -EINVAL; } @@ -695,7 +690,7 @@ static int stm32_dma3_chan_prep_hw(struct stm32_dma3_chan *chan, enum dma_transf _ctr1 |= FIELD_PREP(CTR1_PAM, CTR1_PAM_PACK_UNPACK); /* Should never reach this case as ddw is clamped down */ if (len & (ddw - 1)) { - dev_err(chan2dev(chan), + dev_err(vchan_chan_dev(&chan->vchan), "Packing mode is enabled and len is not multiple of ddw\n"); return -EINVAL; } @@ -740,7 +735,7 @@ static int stm32_dma3_chan_prep_hw(struct stm32_dma3_chan *chan, enum dma_transf _ctr1 |= FIELD_PREP(CTR1_PAM, CTR1_PAM_PACK_UNPACK); /* Should never reach this case as ddw is clamped down */ if (len & (ddw - 1)) { - dev_err(chan2dev(chan), + dev_err(vchan_chan_dev(&chan->vchan), "Packing mode is enabled and len is not multiple of ddw"); return -EINVAL; } @@ -752,7 +747,7 @@ static int stm32_dma3_chan_prep_hw(struct stm32_dma3_chan *chan, enum dma_transf break; default: - dev_err(chan2dev(chan), "Direction %s not supported\n", + dev_err(vchan_chan_dev(&chan->vchan), "Direction %s not supported\n", dmaengine_get_direction_text(dir)); return -EINVAL; } @@ -761,7 +756,7 @@ static int stm32_dma3_chan_prep_hw(struct stm32_dma3_chan *chan, enum dma_transf *ctr1 = _ctr1; *ctr2 = _ctr2; - dev_dbg(chan2dev(chan), "%s: sdw=%u bytes sbl=%u beats ddw=%u bytes dbl=%u beats\n", + dev_dbg(vchan_chan_dev(&chan->vchan), "%s: sdw=%u bytes sbl=%u beats ddw=%u bytes dbl=%u beats\n", __func__, sdw, sbl_max, ddw, dbl_max); return 0; @@ -807,7 +802,7 @@ static void stm32_dma3_chan_start(struct stm32_dma3_chan *chan) chan->dma_status = DMA_IN_PROGRESS; - dev_dbg(chan2dev(chan), "vchan %p: started\n", &chan->vchan); + dev_dbg(vchan_chan_dev(&chan->vchan), "vchan %p: started\n", &chan->vchan); } static int stm32_dma3_chan_suspend(struct stm32_dma3_chan *chan, bool susp) @@ -871,7 +866,7 @@ static void stm32_dma3_chan_set_residue(struct stm32_dma3_chan *chan, struct dma_tx_state *txstate) { struct stm32_dma3_ddata *ddata = to_stm32_dma3_ddata(chan); - struct device *dev = chan2dev(chan); + struct device *dev = vchan_chan_dev(&chan->vchan); struct stm32_dma3_hwdesc *hwdesc; u32 residue, curr_lli, csr, cdar, cbr1, cllr, bndt, fifol; bool pack_unpack; @@ -921,7 +916,7 @@ static void stm32_dma3_chan_set_residue(struct stm32_dma3_chan *chan, /* Get current hwdesc and cumulate residue of pending hwdesc BNDT */ ret = stm32_dma3_chan_get_curr_hwdesc(swdesc, cllr, &residue); if (ret < 0) { - dev_err(chan2dev(chan), "Can't get residue: current hwdesc not found\n"); + dev_err(vchan_chan_dev(&chan->vchan), "Can't get residue: current hwdesc not found\n"); return; } curr_lli = ret; @@ -957,7 +952,7 @@ static void stm32_dma3_chan_set_residue(struct stm32_dma3_chan *chan, skip_fifol_update: if (fifol) { - dev_dbg(chan2dev(chan), "%u byte(s) in the FIFO\n", fifol); + dev_dbg(vchan_chan_dev(&chan->vchan), "%u byte(s) in the FIFO\n", fifol); dma_set_in_flight_bytes(txstate, fifol); /* * Residue is already accurate for DMA_MEM_TO_DEV as BNDT reflects data read from @@ -987,7 +982,7 @@ static int stm32_dma3_chan_stop(struct stm32_dma3_chan *chan) /* Suspend the channel */ ret = stm32_dma3_chan_suspend(chan, true); if (ret) - dev_warn(chan2dev(chan), "%s: timeout, data might be lost\n", __func__); + dev_warn(vchan_chan_dev(&chan->vchan), "%s: timeout, data might be lost\n", __func__); } /* @@ -1034,7 +1029,7 @@ static irqreturn_t stm32_dma3_chan_irq(int irq, void *devid) } if (csr & CSR_USEF && ccr & CCR_USEIE) { - dev_err(chan2dev(chan), "User setting error\n"); + dev_err(vchan_chan_dev(&chan->vchan), "User setting error\n"); chan->dma_status = DMA_ERROR; /* CCR.EN automatically cleared by HW */ stm32_dma3_check_user_setting(chan); @@ -1042,14 +1037,14 @@ static irqreturn_t stm32_dma3_chan_irq(int irq, void *devid) } if (csr & CSR_ULEF && ccr & CCR_ULEIE) { - dev_err(chan2dev(chan), "Update link transfer error\n"); + dev_err(vchan_chan_dev(&chan->vchan), "Update link transfer error\n"); chan->dma_status = DMA_ERROR; /* CCR.EN automatically cleared by HW */ stm32_dma3_chan_reset(chan); } if (csr & CSR_DTEF && ccr & CCR_DTEIE) { - dev_err(chan2dev(chan), "Data transfer error\n"); + dev_err(vchan_chan_dev(&chan->vchan), "Data transfer error\n"); chan->dma_status = DMA_ERROR; /* CCR.EN automatically cleared by HW */ stm32_dma3_chan_reset(chan); @@ -1087,13 +1082,13 @@ static int stm32_dma3_get_chan_sem(struct stm32_dma3_chan *chan) goto bad_cid; chan->semaphore_taken = true; - dev_dbg(chan2dev(chan), "under CID1 control (semcr=0x%08x)\n", csemcr); + dev_dbg(vchan_chan_dev(&chan->vchan), "under CID1 control (semcr=0x%08x)\n", csemcr); return 0; bad_cid: chan->semaphore_taken = false; - dev_err(chan2dev(chan), "not under CID1 control (in-use by CID%d)\n", ccid); + dev_err(vchan_chan_dev(&chan->vchan), "not under CID1 control (in-use by CID%d)\n", ccid); return -EACCES; } @@ -1105,7 +1100,7 @@ static void stm32_dma3_put_chan_sem(struct stm32_dma3_chan *chan) if (chan->semaphore_taken) { writel_relaxed(0, ddata->base + STM32_DMA3_CSEMCR(chan->id)); chan->semaphore_taken = false; - dev_dbg(chan2dev(chan), "no more under CID1 control\n"); + dev_dbg(vchan_chan_dev(&chan->vchan), "no more under CID1 control\n"); } } @@ -1130,7 +1125,7 @@ static int stm32_dma3_alloc_chan_resources(struct dma_chan *c) sizeof(struct stm32_dma3_hwdesc), __alignof__(struct stm32_dma3_hwdesc), SZ_64K); if (!chan->lli_pool) { - dev_err(chan2dev(chan), "Failed to create LLI pool\n"); + dev_err(vchan_chan_dev(&chan->vchan), "Failed to create LLI pool\n"); ret = -ENOMEM; goto err_put_sync; } @@ -1366,7 +1361,7 @@ static struct dma_async_tx_descriptor *stm32_dma3_prep_slave_sg(struct dma_chan } if (count != sg_len && chan->tcem != CTR2_TCEM_CHANNEL) - dev_warn(chan2dev(chan), "Linked-list refactored, %d items instead of %d\n", + dev_warn(vchan_chan_dev(&chan->vchan), "Linked-list refactored, %d items instead of %d\n", count, sg_len); /* Enable Error interrupts */ @@ -1401,12 +1396,12 @@ static struct dma_async_tx_descriptor *stm32_dma3_prep_dma_cyclic(struct dma_cha return NULL; if (!buf_len || !period_len || period_len > STM32_DMA3_MAX_BLOCK_SIZE) { - dev_err(chan2dev(chan), "Invalid buffer/period length\n"); + dev_err(vchan_chan_dev(&chan->vchan), "Invalid buffer/period length\n"); return NULL; } if (buf_len % period_len) { - dev_err(chan2dev(chan), "Buffer length not multiple of period length\n"); + dev_err(vchan_chan_dev(&chan->vchan), "Buffer length not multiple of period length\n"); return NULL; } @@ -1428,7 +1423,7 @@ static struct dma_async_tx_descriptor *stm32_dma3_prep_dma_cyclic(struct dma_cha ret = stm32_dma3_chan_prep_hw(chan, DMA_DEV_TO_MEM, &swdesc->ccr, &ctr1, &ctr2, src, dst, period_len); } else { - dev_err(chan2dev(chan), "Invalid direction\n"); + dev_err(vchan_chan_dev(&chan->vchan), "Invalid direction\n"); ret = -EINVAL; } @@ -1502,7 +1497,7 @@ static int stm32_dma3_pause(struct dma_chan *c) chan->dma_status = DMA_PAUSED; - dev_dbg(chan2dev(chan), "vchan %p: paused\n", &chan->vchan); + dev_dbg(vchan_chan_dev(&chan->vchan), "vchan %p: paused\n", &chan->vchan); return 0; } @@ -1515,7 +1510,7 @@ static int stm32_dma3_resume(struct dma_chan *c) chan->dma_status = DMA_IN_PROGRESS; - dev_dbg(chan2dev(chan), "vchan %p: resumed\n", &chan->vchan); + dev_dbg(vchan_chan_dev(&chan->vchan), "vchan %p: resumed\n", &chan->vchan); return 0; } @@ -1540,7 +1535,7 @@ static int stm32_dma3_terminate_all(struct dma_chan *c) spin_unlock_irqrestore(&chan->vchan.lock, flags); vchan_dma_desc_free_list(&chan->vchan, &head); - dev_dbg(chan2dev(chan), "vchan %p: terminated\n", &chan->vchan); + dev_dbg(vchan_chan_dev(&chan->vchan), "vchan %p: terminated\n", &chan->vchan); return 0; } @@ -1593,7 +1588,7 @@ static void stm32_dma3_issue_pending(struct dma_chan *c) spin_lock_irqsave(&chan->vchan.lock, flags); if (vchan_issue_pending(&chan->vchan) && !chan->swdesc) { - dev_dbg(chan2dev(chan), "vchan %p: issued\n", &chan->vchan); + dev_dbg(vchan_chan_dev(&chan->vchan), "vchan %p: issued\n", &chan->vchan); stm32_dma3_chan_start(chan); } diff --git a/drivers/dma/stm32/stm32-mdma.c b/drivers/dma/stm32/stm32-mdma.c index c6dc8a9a7a28..04639e4b554e 100644 --- a/drivers/dma/stm32/stm32-mdma.c +++ b/drivers/dma/stm32/stm32-mdma.c @@ -276,11 +276,6 @@ static struct stm32_mdma_desc *to_stm32_mdma_desc(struct virt_dma_desc *vdesc) return container_of(vdesc, struct stm32_mdma_desc, vdesc); } -static struct device *chan2dev(struct stm32_mdma_chan *chan) -{ - return &chan->vchan.chan.dev->device; -} - static struct device *mdma2dev(struct stm32_mdma_device *mdma_dev) { return mdma_dev->ddev.dev; @@ -334,7 +329,7 @@ static struct stm32_mdma_desc *stm32_mdma_alloc_desc( return desc; err: - dev_err(chan2dev(chan), "Failed to allocate descriptor\n"); + dev_err(vchan_chan_dev(&chan->vchan), "Failed to allocate descriptor\n"); while (--i >= 0) dma_pool_free(chan->desc_pool, desc->node[i].hwdesc, desc->node[i].hwdesc_phys); @@ -364,7 +359,7 @@ static int stm32_mdma_get_width(struct stm32_mdma_chan *chan, case DMA_SLAVE_BUSWIDTH_8_BYTES: return ffs(width) - 1; default: - dev_err(chan2dev(chan), "Dma bus width %i not supported\n", + dev_err(vchan_chan_dev(&chan->vchan), "Dma bus width %i not supported\n", width); return -EINVAL; } @@ -422,7 +417,7 @@ static int stm32_mdma_disable_chan(struct stm32_mdma_chan *chan) dmadev->base + STM32_MDMA_CISR(id), cisr, (cisr & STM32_MDMA_CISR_CTCIF), 10, 1000); if (ret) { - dev_err(chan2dev(chan), "%s: timeout!\n", __func__); + dev_err(vchan_chan_dev(&chan->vchan), "%s: timeout!\n", __func__); return -EBUSY; } } @@ -444,7 +439,7 @@ static void stm32_mdma_stop(struct stm32_mdma_chan *chan) /* Clear interrupt status if it is there */ status = stm32_mdma_read(dmadev, STM32_MDMA_CISR(chan->id)); if (status) { - dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n", + dev_dbg(vchan_chan_dev(&chan->vchan), "%s(): clearing interrupt: 0x%08x\n", __func__, status); stm32_mdma_set_bits(dmadev, STM32_MDMA_CIFCR(chan->id), status); } @@ -513,7 +508,7 @@ static int stm32_mdma_set_xfer_param(struct stm32_mdma_chan *chan, /* Check burst size constraints */ if (src_maxburst * src_addr_width > STM32_MDMA_MAX_BURST || dst_maxburst * dst_addr_width > STM32_MDMA_MAX_BURST) { - dev_err(chan2dev(chan), + dev_err(vchan_chan_dev(&chan->vchan), "burst size * bus width higher than %d bytes\n", STM32_MDMA_MAX_BURST); return -EINVAL; @@ -521,7 +516,7 @@ static int stm32_mdma_set_xfer_param(struct stm32_mdma_chan *chan, if ((!is_power_of_2(src_maxburst) && src_maxburst > 0) || (!is_power_of_2(dst_maxburst) && dst_maxburst > 0)) { - dev_err(chan2dev(chan), "burst size must be a power of 2\n"); + dev_err(vchan_chan_dev(&chan->vchan), "burst size must be a power of 2\n"); return -EINVAL; } @@ -658,7 +653,7 @@ static int stm32_mdma_set_xfer_param(struct stm32_mdma_chan *chan, break; default: - dev_err(chan2dev(chan), "Dma direction is not supported\n"); + dev_err(vchan_chan_dev(&chan->vchan), "Dma direction is not supported\n"); return -EINVAL; } @@ -672,16 +667,16 @@ static int stm32_mdma_set_xfer_param(struct stm32_mdma_chan *chan, static void stm32_mdma_dump_hwdesc(struct stm32_mdma_chan *chan, struct stm32_mdma_desc_node *node) { - dev_dbg(chan2dev(chan), "hwdesc: %pad\n", &node->hwdesc_phys); - dev_dbg(chan2dev(chan), "CTCR: 0x%08x\n", node->hwdesc->ctcr); - dev_dbg(chan2dev(chan), "CBNDTR: 0x%08x\n", node->hwdesc->cbndtr); - dev_dbg(chan2dev(chan), "CSAR: 0x%08x\n", node->hwdesc->csar); - dev_dbg(chan2dev(chan), "CDAR: 0x%08x\n", node->hwdesc->cdar); - dev_dbg(chan2dev(chan), "CBRUR: 0x%08x\n", node->hwdesc->cbrur); - dev_dbg(chan2dev(chan), "CLAR: 0x%08x\n", node->hwdesc->clar); - dev_dbg(chan2dev(chan), "CTBR: 0x%08x\n", node->hwdesc->ctbr); - dev_dbg(chan2dev(chan), "CMAR: 0x%08x\n", node->hwdesc->cmar); - dev_dbg(chan2dev(chan), "CMDR: 0x%08x\n\n", node->hwdesc->cmdr); + dev_dbg(vchan_chan_dev(&chan->vchan), "hwdesc: %pad\n", &node->hwdesc_phys); + dev_dbg(vchan_chan_dev(&chan->vchan), "CTCR: 0x%08x\n", node->hwdesc->ctcr); + dev_dbg(vchan_chan_dev(&chan->vchan), "CBNDTR: 0x%08x\n", node->hwdesc->cbndtr); + dev_dbg(vchan_chan_dev(&chan->vchan), "CSAR: 0x%08x\n", node->hwdesc->csar); + dev_dbg(vchan_chan_dev(&chan->vchan), "CDAR: 0x%08x\n", node->hwdesc->cdar); + dev_dbg(vchan_chan_dev(&chan->vchan), "CBRUR: 0x%08x\n", node->hwdesc->cbrur); + dev_dbg(vchan_chan_dev(&chan->vchan), "CLAR: 0x%08x\n", node->hwdesc->clar); + dev_dbg(vchan_chan_dev(&chan->vchan), "CTBR: 0x%08x\n", node->hwdesc->ctbr); + dev_dbg(vchan_chan_dev(&chan->vchan), "CMAR: 0x%08x\n", node->hwdesc->cmar); + dev_dbg(vchan_chan_dev(&chan->vchan), "CMDR: 0x%08x\n\n", node->hwdesc->cmdr); } static void stm32_mdma_setup_hwdesc(struct stm32_mdma_chan *chan, @@ -739,7 +734,7 @@ static int stm32_mdma_setup_xfer(struct stm32_mdma_chan *chan, for_each_sg(sgl, sg, sg_len, i) { if (sg_dma_len(sg) > STM32_MDMA_MAX_BLOCK_LEN) { - dev_err(chan2dev(chan), "Invalid block len\n"); + dev_err(vchan_chan_dev(&chan->vchan), "Invalid block len\n"); return -EINVAL; } @@ -797,7 +792,7 @@ stm32_mdma_prep_slave_sg(struct dma_chan *c, struct scatterlist *sgl, * for allowing another request. */ if (chan->desc && chan->desc->cyclic) { - dev_err(chan2dev(chan), + dev_err(vchan_chan_dev(&chan->vchan), "Request not allowed when dma in cyclic mode\n"); return NULL; } @@ -858,18 +853,18 @@ stm32_mdma_prep_dma_cyclic(struct dma_chan *c, dma_addr_t buf_addr, * for allowing another request. */ if (chan->desc && chan->desc->cyclic) { - dev_err(chan2dev(chan), + dev_err(vchan_chan_dev(&chan->vchan), "Request not allowed when dma in cyclic mode\n"); return NULL; } if (!buf_len || !period_len || period_len > STM32_MDMA_MAX_BLOCK_LEN) { - dev_err(chan2dev(chan), "Invalid buffer/period len\n"); + dev_err(vchan_chan_dev(&chan->vchan), "Invalid buffer/period len\n"); return NULL; } if (buf_len % period_len) { - dev_err(chan2dev(chan), "buf_len not multiple of period_len\n"); + dev_err(vchan_chan_dev(&chan->vchan), "buf_len not multiple of period_len\n"); return NULL; } @@ -954,7 +949,7 @@ stm32_mdma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dest, dma_addr_t src, * to allow another request */ if (chan->desc && chan->desc->cyclic) { - dev_err(chan2dev(chan), + dev_err(vchan_chan_dev(&chan->vchan), "Request not allowed when dma in cyclic mode\n"); return NULL; } @@ -1116,25 +1111,25 @@ static void stm32_mdma_dump_reg(struct stm32_mdma_chan *chan) { struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan); - dev_dbg(chan2dev(chan), "CCR: 0x%08x\n", + dev_dbg(vchan_chan_dev(&chan->vchan), "CCR: 0x%08x\n", stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id))); - dev_dbg(chan2dev(chan), "CTCR: 0x%08x\n", + dev_dbg(vchan_chan_dev(&chan->vchan), "CTCR: 0x%08x\n", stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id))); - dev_dbg(chan2dev(chan), "CBNDTR: 0x%08x\n", + dev_dbg(vchan_chan_dev(&chan->vchan), "CBNDTR: 0x%08x\n", stm32_mdma_read(dmadev, STM32_MDMA_CBNDTR(chan->id))); - dev_dbg(chan2dev(chan), "CSAR: 0x%08x\n", + dev_dbg(vchan_chan_dev(&chan->vchan), "CSAR: 0x%08x\n", stm32_mdma_read(dmadev, STM32_MDMA_CSAR(chan->id))); - dev_dbg(chan2dev(chan), "CDAR: 0x%08x\n", + dev_dbg(vchan_chan_dev(&chan->vchan), "CDAR: 0x%08x\n", stm32_mdma_read(dmadev, STM32_MDMA_CDAR(chan->id))); - dev_dbg(chan2dev(chan), "CBRUR: 0x%08x\n", + dev_dbg(vchan_chan_dev(&chan->vchan), "CBRUR: 0x%08x\n", stm32_mdma_read(dmadev, STM32_MDMA_CBRUR(chan->id))); - dev_dbg(chan2dev(chan), "CLAR: 0x%08x\n", + dev_dbg(vchan_chan_dev(&chan->vchan), "CLAR: 0x%08x\n", stm32_mdma_read(dmadev, STM32_MDMA_CLAR(chan->id))); - dev_dbg(chan2dev(chan), "CTBR: 0x%08x\n", + dev_dbg(vchan_chan_dev(&chan->vchan), "CTBR: 0x%08x\n", stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id))); - dev_dbg(chan2dev(chan), "CMAR: 0x%08x\n", + dev_dbg(vchan_chan_dev(&chan->vchan), "CMAR: 0x%08x\n", stm32_mdma_read(dmadev, STM32_MDMA_CMAR(chan->id))); - dev_dbg(chan2dev(chan), "CMDR: 0x%08x\n", + dev_dbg(vchan_chan_dev(&chan->vchan), "CMDR: 0x%08x\n", stm32_mdma_read(dmadev, STM32_MDMA_CMDR(chan->id))); } @@ -1187,7 +1182,7 @@ static void stm32_mdma_start_transfer(struct stm32_mdma_chan *chan) chan->busy = true; - dev_dbg(chan2dev(chan), "vchan %p: started\n", &chan->vchan); + dev_dbg(vchan_chan_dev(&chan->vchan), "vchan %p: started\n", &chan->vchan); } static void stm32_mdma_issue_pending(struct dma_chan *c) @@ -1200,7 +1195,7 @@ static void stm32_mdma_issue_pending(struct dma_chan *c) if (!vchan_issue_pending(&chan->vchan)) goto end; - dev_dbg(chan2dev(chan), "vchan %p: issued\n", &chan->vchan); + dev_dbg(vchan_chan_dev(&chan->vchan), "vchan %p: issued\n", &chan->vchan); if (!chan->desc && !chan->busy) stm32_mdma_start_transfer(chan); @@ -1220,7 +1215,7 @@ static int stm32_mdma_pause(struct dma_chan *c) spin_unlock_irqrestore(&chan->vchan.lock, flags); if (!ret) - dev_dbg(chan2dev(chan), "vchan %p: pause\n", &chan->vchan); + dev_dbg(vchan_chan_dev(&chan->vchan), "vchan %p: pause\n", &chan->vchan); return ret; } @@ -1261,7 +1256,7 @@ static int stm32_mdma_resume(struct dma_chan *c) spin_unlock_irqrestore(&chan->vchan.lock, flags); - dev_dbg(chan2dev(chan), "vchan %p: resume\n", &chan->vchan); + dev_dbg(vchan_chan_dev(&chan->vchan), "vchan %p: resume\n", &chan->vchan); return 0; } @@ -1422,10 +1417,10 @@ static irqreturn_t stm32_mdma_irq_handler(int irq, void *devid) if (!(status & ien)) { spin_unlock(&chan->vchan.lock); if (chan->busy) - dev_warn(chan2dev(chan), + dev_warn(vchan_chan_dev(&chan->vchan), "spurious it (status=0x%04x, ien=0x%04x)\n", status, ien); else - dev_dbg(chan2dev(chan), + dev_dbg(vchan_chan_dev(&chan->vchan), "spurious it (status=0x%04x, ien=0x%04x)\n", status, ien); return IRQ_NONE; } @@ -1433,7 +1428,7 @@ static irqreturn_t stm32_mdma_irq_handler(int irq, void *devid) reg = STM32_MDMA_CIFCR(id); if (status & STM32_MDMA_CISR_TEIF) { - dev_err(chan2dev(chan), "Transfer Err: stat=0x%08x\n", + dev_err(vchan_chan_dev(&chan->vchan), "Transfer Err: stat=0x%08x\n", readl_relaxed(dmadev->base + STM32_MDMA_CESR(id))); stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CTEIF); status &= ~STM32_MDMA_CISR_TEIF; @@ -1468,9 +1463,9 @@ static irqreturn_t stm32_mdma_irq_handler(int irq, void *devid) if (status) { stm32_mdma_set_bits(dmadev, reg, status); - dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status); + dev_err(vchan_chan_dev(&chan->vchan), "DMA error: status=0x%08x\n", status); if (!(ccr & STM32_MDMA_CCR_EN)) - dev_err(chan2dev(chan), "chan disabled by HW\n"); + dev_err(vchan_chan_dev(&chan->vchan), "chan disabled by HW\n"); } spin_unlock(&chan->vchan.lock); @@ -1489,7 +1484,7 @@ static int stm32_mdma_alloc_chan_resources(struct dma_chan *c) __alignof__(struct stm32_mdma_hwdesc), 0); if (!chan->desc_pool) { - dev_err(chan2dev(chan), "failed to allocate descriptor pool\n"); + dev_err(vchan_chan_dev(&chan->vchan), "failed to allocate descriptor pool\n"); return -ENOMEM; } @@ -1510,7 +1505,7 @@ static void stm32_mdma_free_chan_resources(struct dma_chan *c) struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan); unsigned long flags; - dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id); + dev_dbg(vchan_chan_dev(&chan->vchan), "Freeing channel %d\n", chan->id); if (chan->busy) { spin_lock_irqsave(&chan->vchan.lock, flags); diff --git a/drivers/dma/sun4i-dma.c b/drivers/dma/sun4i-dma.c index d2321f7287d2..225e4a53502b 100644 --- a/drivers/dma/sun4i-dma.c +++ b/drivers/dma/sun4i-dma.c @@ -246,11 +246,6 @@ static struct sun4i_dma_contract *to_sun4i_dma_contract(struct virt_dma_desc *vd return container_of(vd, struct sun4i_dma_contract, vd); } -static struct device *chan2dev(struct dma_chan *chan) -{ - return &chan->dev->device; -} - static void set_dst_data_width_a10(u32 *p_cfg, s8 data_width) { *p_cfg |= SUN4I_DMA_CFG_DST_DATA_WIDTH(data_width); @@ -428,7 +423,7 @@ static int __execute_vchan_pending(struct sun4i_dma_dev *priv, * has already submitted some work, we can't do anything else */ if (vchan->processing) { - dev_dbg(chan2dev(&vchan->vc.chan), + dev_dbg(vchan_chan_dev(&vchan->vc), "processing something to this endpoint already\n"); ret = -EBUSY; goto release_pchan; @@ -438,7 +433,7 @@ static int __execute_vchan_pending(struct sun4i_dma_dev *priv, /* Figure out which contract we're working with today */ vd = vchan_next_desc(&vchan->vc); if (!vd) { - dev_dbg(chan2dev(&vchan->vc.chan), + dev_dbg(vchan_chan_dev(&vchan->vc), "No pending contract found"); ret = 0; goto release_pchan; @@ -449,7 +444,7 @@ static int __execute_vchan_pending(struct sun4i_dma_dev *priv, /* The contract has been completed so mark it as such */ list_del(&contract->vd.node); vchan_cookie_complete(&contract->vd); - dev_dbg(chan2dev(&vchan->vc.chan), + dev_dbg(vchan_chan_dev(&vchan->vc), "Empty contract found and marked complete"); } } while (list_empty(&contract->demands)); @@ -542,7 +537,7 @@ generate_ndma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t dest, promise->cfg = SUN4I_DMA_CFG_LOADING | SUN4I_NDMA_CFG_BYTE_COUNT_MODE_REMAIN; - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "src burst %d, dst burst %d, src buswidth %d, dst buswidth %d", sconfig->src_maxburst, sconfig->dst_maxburst, sconfig->src_addr_width, sconfig->dst_addr_width); @@ -769,7 +764,7 @@ sun4i_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf, size_t len, u8 ram_type, io_mode, linear_mode; if (!is_slave_direction(dir)) { - dev_err(chan2dev(chan), "Invalid DMA direction\n"); + dev_err(dmaengine_chan_dev(chan), "Invalid DMA direction\n"); return NULL; } @@ -894,7 +889,7 @@ sun4i_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, return NULL; if (!is_slave_direction(dir)) { - dev_err(chan2dev(chan), "Invalid DMA direction\n"); + dev_err(dmaengine_chan_dev(chan), "Invalid DMA direction\n"); return NULL; } diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index c248c2dec956..5ad9d01cff3a 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -213,11 +213,6 @@ struct sun6i_dma_dev { u32 max_request; }; -static struct device *chan2dev(struct dma_chan *chan) -{ - return &chan->dev->device; -} - static inline struct sun6i_dma_dev *to_sun6i_dma_dev(struct dma_device *d) { return container_of(d, struct sun6i_dma_dev, slave); @@ -397,7 +392,7 @@ static inline void sun6i_dma_dump_lli(struct sun6i_vchan *vchan, struct sun6i_dma_lli *v_lli, dma_addr_t p_lli) { - dev_dbg(chan2dev(&vchan->vc.chan), + dev_dbg(vchan_chan_dev(&vchan->vc), "\n\tdesc:\tp - %pad v - 0x%p\n" "\t\tc - 0x%08x s - 0x%08x d - 0x%08x\n" "\t\tl - 0x%08x p - 0x%08x n - 0x%08x\n", @@ -678,7 +673,7 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy( dma_addr_t p_lli; s8 burst, width; - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "%s; chan: %d, dest: %pad, src: %pad, len: %zu. flags: 0x%08lx\n", __func__, vchan->vc.chan.chan_id, &dest, &src, len, flags); @@ -739,7 +734,7 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg( ret = set_config(sdev, sconfig, dir, &lli_cfg); if (ret) { - dev_err(chan2dev(chan), "Invalid DMA configuration\n"); + dev_err(dmaengine_chan_dev(chan), "Invalid DMA configuration\n"); return NULL; } @@ -763,7 +758,7 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg( sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port); sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE); - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", __func__, vchan->vc.chan.chan_id, &sconfig->dst_addr, &sg_dma_address(sg), @@ -777,7 +772,7 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg( sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM); sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE); - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", __func__, vchan->vc.chan.chan_id, &sg_dma_address(sg), &sconfig->src_addr, @@ -787,7 +782,7 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg( prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd); } - dev_dbg(chan2dev(chan), "First: %pad\n", &txd->p_lli); + dev_dbg(dmaengine_chan_dev(chan), "First: %pad\n", &txd->p_lli); for (p_lli = txd->p_lli, v_lli = txd->v_lli; v_lli; p_lli = v_lli->p_lli_next, v_lli = v_lli->v_lli_next) sun6i_dma_dump_lli(vchan, v_lli, p_lli); @@ -819,7 +814,7 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_cyclic( ret = set_config(sdev, sconfig, dir, &lli_cfg); if (ret) { - dev_err(chan2dev(chan), "Invalid DMA configuration\n"); + dev_err(dmaengine_chan_dev(chan), "Invalid DMA configuration\n"); return NULL; } @@ -844,7 +839,7 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_cyclic( v_lli->cfg = lli_cfg; sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port); sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE); - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "%s; chan: %d, dest: %pad, src: %pad, len: %zu. flags: 0x%08lx\n", __func__, vchan->vc.chan.chan_id, &sconfig->dst_addr, &buf_addr, @@ -856,7 +851,7 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_cyclic( v_lli->cfg = lli_cfg; sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM); sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE); - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "%s; chan: %d, dest: %pad, src: %pad, len: %zu. flags: 0x%08lx\n", __func__, vchan->vc.chan.chan_id, &buf_addr, &sconfig->src_addr, @@ -893,7 +888,7 @@ static int sun6i_dma_pause(struct dma_chan *chan) struct sun6i_vchan *vchan = to_sun6i_vchan(chan); struct sun6i_pchan *pchan = vchan->phy; - dev_dbg(chan2dev(chan), "vchan %p: pause\n", &vchan->vc); + dev_dbg(dmaengine_chan_dev(chan), "vchan %p: pause\n", &vchan->vc); if (pchan) { writel(DMA_CHAN_PAUSE_PAUSE, @@ -914,7 +909,7 @@ static int sun6i_dma_resume(struct dma_chan *chan) struct sun6i_pchan *pchan = vchan->phy; unsigned long flags; - dev_dbg(chan2dev(chan), "vchan %p: resume\n", &vchan->vc); + dev_dbg(dmaengine_chan_dev(chan), "vchan %p: resume\n", &vchan->vc); spin_lock_irqsave(&vchan->vc.lock, flags); @@ -1024,13 +1019,13 @@ static void sun6i_dma_issue_pending(struct dma_chan *chan) if (!vchan->phy && list_empty(&vchan->node)) { list_add_tail(&vchan->node, &sdev->pending); tasklet_schedule(&sdev->task); - dev_dbg(chan2dev(chan), "vchan %p: issued\n", + dev_dbg(dmaengine_chan_dev(chan), "vchan %p: issued\n", &vchan->vc); } spin_unlock(&sdev->lock); } else { - dev_dbg(chan2dev(chan), "vchan %p: nothing to issue\n", + dev_dbg(dmaengine_chan_dev(chan), "vchan %p: nothing to issue\n", &vchan->vc); } diff --git a/drivers/dma/switchtec_dma.c b/drivers/dma/switchtec_dma.c index c133535d3765..4cc80752f5b6 100644 --- a/drivers/dma/switchtec_dma.c +++ b/drivers/dma/switchtec_dma.c @@ -406,7 +406,7 @@ static int disable_channel(struct switchtec_dma_chan *swdma_chan) static void switchtec_dma_cleanup_completed(struct switchtec_dma_chan *swdma_chan) { - struct device *chan_dev = &swdma_chan->dma_chan.dev->device; + struct device *chan_dev = dmaengine_chan_dev(&swdma_chan->dma_chan); struct switchtec_dma_desc *desc; struct switchtec_dma_hw_ce *ce; struct dmaengine_result res; @@ -851,7 +851,7 @@ static irqreturn_t switchtec_dma_chan_status_isr(int irq, void *dma) list_for_each_entry(chan, &dma_dev->channels, device_node) { swdma_chan = container_of(chan, struct switchtec_dma_chan, dma_chan); - chan_dev = &swdma_chan->dma_chan.dev->device; + chan_dev = dmaengine_chan_dev(&swdma_chan->dma_chan); chan_hw = swdma_chan->mmio_chan_hw; rcu_read_lock(); @@ -1009,19 +1009,19 @@ static int switchtec_dma_alloc_chan_resources(struct dma_chan *chan) perf_cfg = readl(&swdma_chan->mmio_chan_fw->perf_cfg); rcu_read_unlock(); - dev_dbg(&chan->dev->device, "Burst Size: 0x%x\n", + dev_dbg(dmaengine_chan_dev(chan), "Burst Size: 0x%x\n", FIELD_GET(PERF_BURST_SIZE_MASK, perf_cfg)); - dev_dbg(&chan->dev->device, "Burst Scale: 0x%x\n", + dev_dbg(dmaengine_chan_dev(chan), "Burst Scale: 0x%x\n", FIELD_GET(PERF_BURST_SCALE_MASK, perf_cfg)); - dev_dbg(&chan->dev->device, "Interval: 0x%x\n", + dev_dbg(dmaengine_chan_dev(chan), "Interval: 0x%x\n", FIELD_GET(PERF_INTERVAL_MASK, perf_cfg)); - dev_dbg(&chan->dev->device, "Arb Weight: 0x%x\n", + dev_dbg(dmaengine_chan_dev(chan), "Arb Weight: 0x%x\n", FIELD_GET(PERF_ARB_WEIGHT_MASK, perf_cfg)); - dev_dbg(&chan->dev->device, "MRRS: 0x%x\n", + dev_dbg(dmaengine_chan_dev(chan), "MRRS: 0x%x\n", FIELD_GET(PERF_MRRS_MASK, perf_cfg)); return SWITCHTEC_DMA_SQ_SIZE; diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c index 64cedef1050a..b3327aa35de4 100644 --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -1537,7 +1537,7 @@ static int tegra_dma_probe(struct platform_device *pdev) * the channels available and registered for the DMA device are used. */ list_for_each_entry(chan, &tdma->dma_dev.channels, device_node) { - chdev = &chan->dev->device; + chdev = dmaengine_chan_dev(chan); tdc = to_tegra_dma_chan(chan); if (use_iommu_map) { diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c index 640b8a218c9a..7ff8c0241f61 100644 --- a/drivers/dma/tegra20-apb-dma.c +++ b/drivers/dma/tegra20-apb-dma.c @@ -256,7 +256,7 @@ txd_to_tegra_dma_desc(struct dma_async_tx_descriptor *td) static inline struct device *tdc2dev(struct tegra_dma_channel *tdc) { - return &tdc->dma_chan.dev->device; + return dmaengine_chan_dev(&tdc->dma_chan); } static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *tx); diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index fb21e0df5ab7..49e2d0014d5e 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -422,7 +422,7 @@ static int navss_psil_unpair(struct udma_dev *ud, u32 src_thread, static void k3_configure_chan_coherency(struct dma_chan *chan, u32 asel) { - struct device *chan_dev = &chan->dev->device; + struct device *chan_dev = dmaengine_chan_dev(chan); if (asel == 0) { /* No special handling for the channel */ diff --git a/drivers/dma/timb_dma.c b/drivers/dma/timb_dma.c index 4fc5119854ec..0acd7a36a3d0 100644 --- a/drivers/dma/timb_dma.c +++ b/drivers/dma/timb_dma.c @@ -90,14 +90,9 @@ struct timb_dma { struct tasklet_struct tasklet; struct timb_dma_chan channels[]; }; - -static struct device *chan2dev(struct dma_chan *chan) -{ - return &chan->dev->device; -} static struct device *chan2dmadev(struct dma_chan *chan) { - return chan2dev(chan)->parent->parent; + return dmaengine_chan_dev(chan)->parent->parent; } static struct timb_dma *tdchantotd(struct timb_dma_chan *td_chan) @@ -117,7 +112,7 @@ static void __td_enable_chan_irq(struct timb_dma_chan *td_chan) /* enable interrupt for this channel */ ier = ioread32(td->membase + TIMBDMA_IER); ier |= 1 << id; - dev_dbg(chan2dev(&td_chan->chan), "Enabling irq: %d, IER: 0x%x\n", id, + dev_dbg(dmaengine_chan_dev(&td_chan->chan), "Enabling irq: %d, IER: 0x%x\n", id, ier); iowrite32(ier, td->membase + TIMBDMA_IER); } @@ -131,7 +126,7 @@ static bool __td_dma_done_ack(struct timb_dma_chan *td_chan) u32 isr; bool done = false; - dev_dbg(chan2dev(&td_chan->chan), "Checking irq: %d, td: %p\n", id, td); + dev_dbg(dmaengine_chan_dev(&td_chan->chan), "Checking irq: %d, td: %p\n", id, td); isr = ioread32(td->membase + TIMBDMA_ISR) & (1 << id); if (isr) { @@ -146,18 +141,18 @@ static int td_fill_desc(struct timb_dma_chan *td_chan, u8 *dma_desc, struct scatterlist *sg, bool last) { if (sg_dma_len(sg) > USHRT_MAX) { - dev_err(chan2dev(&td_chan->chan), "Too big sg element\n"); + dev_err(dmaengine_chan_dev(&td_chan->chan), "Too big sg element\n"); return -EINVAL; } /* length must be word aligned */ if (sg_dma_len(sg) % sizeof(u32)) { - dev_err(chan2dev(&td_chan->chan), "Incorrect length: %d\n", + dev_err(dmaengine_chan_dev(&td_chan->chan), "Incorrect length: %d\n", sg_dma_len(sg)); return -EINVAL; } - dev_dbg(chan2dev(&td_chan->chan), "desc: %p, addr: 0x%llx\n", + dev_dbg(dmaengine_chan_dev(&td_chan->chan), "desc: %p, addr: 0x%llx\n", dma_desc, (unsigned long long)sg_dma_address(sg)); dma_desc[7] = (sg_dma_address(sg) >> 24) & 0xff; @@ -180,7 +175,7 @@ static void __td_start_dma(struct timb_dma_chan *td_chan) struct timb_dma_desc *td_desc; if (td_chan->ongoing) { - dev_err(chan2dev(&td_chan->chan), + dev_err(dmaengine_chan_dev(&td_chan->chan), "Transfer already ongoing\n"); return; } @@ -188,7 +183,7 @@ static void __td_start_dma(struct timb_dma_chan *td_chan) td_desc = list_entry(td_chan->active_list.next, struct timb_dma_desc, desc_node); - dev_dbg(chan2dev(&td_chan->chan), + dev_dbg(dmaengine_chan_dev(&td_chan->chan), "td_chan: %p, chan: %d, membase: %p\n", td_chan, td_chan->chan.chan_id, td_chan->membase); @@ -230,7 +225,7 @@ static void __td_finish(struct timb_dma_chan *td_chan) desc_node); txd = &td_desc->txd; - dev_dbg(chan2dev(&td_chan->chan), "descriptor %u complete\n", + dev_dbg(dmaengine_chan_dev(&td_chan->chan), "descriptor %u complete\n", txd->cookie); /* make sure to stop the transfer */ @@ -284,7 +279,7 @@ static void __td_start_next(struct timb_dma_chan *td_chan) td_desc = list_entry(td_chan->queue.next, struct timb_dma_desc, desc_node); - dev_dbg(chan2dev(&td_chan->chan), "%s: started %u\n", + dev_dbg(dmaengine_chan_dev(&td_chan->chan), "%s: started %u\n", __func__, td_desc->txd.cookie); list_move(&td_desc->desc_node, &td_chan->active_list); @@ -303,12 +298,12 @@ static dma_cookie_t td_tx_submit(struct dma_async_tx_descriptor *txd) cookie = dma_cookie_assign(txd); if (list_empty(&td_chan->active_list)) { - dev_dbg(chan2dev(txd->chan), "%s: started %u\n", __func__, + dev_dbg(dmaengine_chan_dev(txd->chan), "%s: started %u\n", __func__, txd->cookie); list_add_tail(&td_desc->desc_node, &td_chan->active_list); __td_start_dma(td_chan); } else { - dev_dbg(chan2dev(txd->chan), "tx_submit: queued %u\n", + dev_dbg(dmaengine_chan_dev(txd->chan), "tx_submit: queued %u\n", txd->cookie); list_add_tail(&td_desc->desc_node, &td_chan->queue); @@ -344,7 +339,7 @@ static struct timb_dma_desc *td_alloc_init_desc(struct timb_dma_chan *td_chan) err = dma_mapping_error(chan2dmadev(chan), td_desc->txd.phys); if (err) { - dev_err(chan2dev(chan), "DMA mapping error: %d\n", err); + dev_err(dmaengine_chan_dev(chan), "DMA mapping error: %d\n", err); goto err; } @@ -359,7 +354,7 @@ static struct timb_dma_desc *td_alloc_init_desc(struct timb_dma_chan *td_chan) static void td_free_desc(struct timb_dma_desc *td_desc) { - dev_dbg(chan2dev(td_desc->txd.chan), "Freeing desc: %p\n", td_desc); + dev_dbg(dmaengine_chan_dev(td_desc->txd.chan), "Freeing desc: %p\n", td_desc); dma_unmap_single(chan2dmadev(td_desc->txd.chan), td_desc->txd.phys, td_desc->desc_list_len, DMA_TO_DEVICE); @@ -370,7 +365,7 @@ static void td_free_desc(struct timb_dma_desc *td_desc) static void td_desc_put(struct timb_dma_chan *td_chan, struct timb_dma_desc *td_desc) { - dev_dbg(chan2dev(&td_chan->chan), "Putting desc: %p\n", td_desc); + dev_dbg(dmaengine_chan_dev(&td_chan->chan), "Putting desc: %p\n", td_desc); spin_lock_bh(&td_chan->lock); list_add(&td_desc->desc_node, &td_chan->free_list); @@ -390,7 +385,7 @@ static struct timb_dma_desc *td_desc_get(struct timb_dma_chan *td_chan) ret = td_desc; break; } - dev_dbg(chan2dev(&td_chan->chan), "desc %p not ACKed\n", + dev_dbg(dmaengine_chan_dev(&td_chan->chan), "desc %p not ACKed\n", td_desc); } spin_unlock_bh(&td_chan->lock); @@ -404,7 +399,7 @@ static int td_alloc_chan_resources(struct dma_chan *chan) container_of(chan, struct timb_dma_chan, chan); int i; - dev_dbg(chan2dev(chan), "%s: entry\n", __func__); + dev_dbg(dmaengine_chan_dev(chan), "%s: entry\n", __func__); BUG_ON(!list_empty(&td_chan->free_list)); for (i = 0; i < td_chan->descs; i++) { @@ -413,7 +408,7 @@ static int td_alloc_chan_resources(struct dma_chan *chan) if (i) break; else { - dev_err(chan2dev(chan), + dev_err(dmaengine_chan_dev(chan), "Couldn't allocate any descriptors\n"); return -ENOMEM; } @@ -436,7 +431,7 @@ static void td_free_chan_resources(struct dma_chan *chan) struct timb_dma_desc *td_desc, *_td_desc; LIST_HEAD(list); - dev_dbg(chan2dev(chan), "%s: Entry\n", __func__); + dev_dbg(dmaengine_chan_dev(chan), "%s: Entry\n", __func__); /* check that all descriptors are free */ BUG_ON(!list_empty(&td_chan->active_list)); @@ -447,7 +442,7 @@ static void td_free_chan_resources(struct dma_chan *chan) spin_unlock_bh(&td_chan->lock); list_for_each_entry_safe(td_desc, _td_desc, &list, desc_node) { - dev_dbg(chan2dev(chan), "%s: Freeing desc: %p\n", __func__, + dev_dbg(dmaengine_chan_dev(chan), "%s: Freeing desc: %p\n", __func__, td_desc); td_free_desc(td_desc); } @@ -458,11 +453,11 @@ static enum dma_status td_tx_status(struct dma_chan *chan, dma_cookie_t cookie, { enum dma_status ret; - dev_dbg(chan2dev(chan), "%s: Entry\n", __func__); + dev_dbg(dmaengine_chan_dev(chan), "%s: Entry\n", __func__); ret = dma_cookie_status(chan, cookie, txstate); - dev_dbg(chan2dev(chan), "%s: exit, ret: %d\n", __func__, ret); + dev_dbg(dmaengine_chan_dev(chan), "%s: exit, ret: %d\n", __func__, ret); return ret; } @@ -472,7 +467,7 @@ static void td_issue_pending(struct dma_chan *chan) struct timb_dma_chan *td_chan = container_of(chan, struct timb_dma_chan, chan); - dev_dbg(chan2dev(chan), "%s: Entry\n", __func__); + dev_dbg(dmaengine_chan_dev(chan), "%s: Entry\n", __func__); spin_lock_bh(&td_chan->lock); if (!list_empty(&td_chan->active_list)) @@ -499,20 +494,20 @@ static struct dma_async_tx_descriptor *td_prep_slave_sg(struct dma_chan *chan, unsigned int desc_usage = 0; if (!sgl || !sg_len) { - dev_err(chan2dev(chan), "%s: No SG list\n", __func__); + dev_err(dmaengine_chan_dev(chan), "%s: No SG list\n", __func__); return NULL; } /* even channels are for RX, odd for TX */ if (td_chan->direction != direction) { - dev_err(chan2dev(chan), + dev_err(dmaengine_chan_dev(chan), "Requesting channel in wrong direction\n"); return NULL; } td_desc = td_desc_get(td_chan); if (!td_desc) { - dev_err(chan2dev(chan), "Not enough descriptors available\n"); + dev_err(dmaengine_chan_dev(chan), "Not enough descriptors available\n"); return NULL; } @@ -521,14 +516,14 @@ static struct dma_async_tx_descriptor *td_prep_slave_sg(struct dma_chan *chan, for_each_sg(sgl, sg, sg_len, i) { int err; if (desc_usage > td_desc->desc_list_len) { - dev_err(chan2dev(chan), "No descriptor space\n"); + dev_err(dmaengine_chan_dev(chan), "No descriptor space\n"); return NULL; } err = td_fill_desc(td_chan, td_desc->desc_list + desc_usage, sg, i == (sg_len - 1)); if (err) { - dev_err(chan2dev(chan), "Failed to update desc: %d\n", + dev_err(dmaengine_chan_dev(chan), "Failed to update desc: %d\n", err); td_desc_put(td_chan, td_desc); return NULL; @@ -548,7 +543,7 @@ static int td_terminate_all(struct dma_chan *chan) container_of(chan, struct timb_dma_chan, chan); struct timb_dma_desc *td_desc, *_td_desc; - dev_dbg(chan2dev(chan), "%s: Entry\n", __func__); + dev_dbg(dmaengine_chan_dev(chan), "%s: Entry\n", __func__); /* first the easy part, put the queue into the free list */ spin_lock_bh(&td_chan->lock); diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c index 6595a54a4b97..ecfaa6a76516 100644 --- a/drivers/dma/txx9dmac.c +++ b/drivers/dma/txx9dmac.c @@ -125,14 +125,9 @@ static struct txx9dmac_regs32 __iomem *__txx9dmac_regs32( #define dma_writel(ddev, name, val) \ (__is_dmac64(ddev) ? \ dma64_writel(ddev, name, val) : dma32_writel(ddev, name, val)) - -static struct device *chan2dev(struct dma_chan *chan) -{ - return &chan->dev->device; -} static struct device *chan2parent(struct dma_chan *chan) { - return chan->dev->device.parent; + return dmaengine_chan_dev(chan)->parent; } static struct txx9dmac_desc * @@ -218,12 +213,12 @@ static struct txx9dmac_desc *txx9dmac_desc_get(struct txx9dmac_chan *dc) ret = desc; break; } - dev_dbg(chan2dev(&dc->chan), "desc %p not ACKed\n", desc); + dev_dbg(dmaengine_chan_dev(&dc->chan), "desc %p not ACKed\n", desc); i++; } spin_unlock_bh(&dc->lock); - dev_vdbg(chan2dev(&dc->chan), "scanned %u descriptors on freelist\n", + dev_vdbg(dmaengine_chan_dev(&dc->chan), "scanned %u descriptors on freelist\n", i); if (!ret) { ret = txx9dmac_desc_alloc(dc, GFP_ATOMIC); @@ -232,7 +227,7 @@ static struct txx9dmac_desc *txx9dmac_desc_get(struct txx9dmac_chan *dc) dc->descs_allocated++; spin_unlock_bh(&dc->lock); } else - dev_err(chan2dev(&dc->chan), + dev_err(dmaengine_chan_dev(&dc->chan), "not enough descriptors available\n"); } return ret; @@ -267,11 +262,11 @@ static void txx9dmac_desc_put(struct txx9dmac_chan *dc, spin_lock_bh(&dc->lock); list_for_each_entry(child, &desc->tx_list, desc_node) - dev_vdbg(chan2dev(&dc->chan), + dev_vdbg(dmaengine_chan_dev(&dc->chan), "moving child desc %p to freelist\n", child); list_splice_init(&desc->tx_list, &dc->free_list); - dev_vdbg(chan2dev(&dc->chan), "moving desc %p to freelist\n", + dev_vdbg(dmaengine_chan_dev(&dc->chan), "moving desc %p to freelist\n", desc); list_add(&desc->desc_node, &dc->free_list); spin_unlock_bh(&dc->lock); @@ -283,7 +278,7 @@ static void txx9dmac_desc_put(struct txx9dmac_chan *dc, static void txx9dmac_dump_regs(struct txx9dmac_chan *dc) { if (is_dmac64(dc)) - dev_err(chan2dev(&dc->chan), + dev_err(dmaengine_chan_dev(&dc->chan), " CHAR: %#llx SAR: %#llx DAR: %#llx CNTR: %#x" " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n", (u64)channel64_read_CHAR(dc), @@ -295,7 +290,7 @@ static void txx9dmac_dump_regs(struct txx9dmac_chan *dc) channel64_readl(dc, CCR), channel64_readl(dc, CSR)); else - dev_err(chan2dev(&dc->chan), + dev_err(dmaengine_chan_dev(&dc->chan), " CHAR: %#x SAR: %#x DAR: %#x CNTR: %#x" " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n", channel32_readl(dc, CHAR), @@ -333,11 +328,11 @@ static void txx9dmac_dostart(struct txx9dmac_chan *dc, struct txx9dmac_slave *ds = dc->chan.private; u32 sai, dai; - dev_vdbg(chan2dev(&dc->chan), "dostart %u %p\n", + dev_vdbg(dmaengine_chan_dev(&dc->chan), "dostart %u %p\n", first->txd.cookie, first); /* ASSERT: channel is idle */ if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) { - dev_err(chan2dev(&dc->chan), + dev_err(dmaengine_chan_dev(&dc->chan), "BUG: Attempted to start non-idle channel\n"); txx9dmac_dump_regs(dc); /* The tasklet will hopefully advance the queue... */ @@ -402,7 +397,7 @@ txx9dmac_descriptor_complete(struct txx9dmac_chan *dc, struct dmaengine_desc_callback cb; struct dma_async_tx_descriptor *txd = &desc->txd; - dev_vdbg(chan2dev(&dc->chan), "descriptor %u %p complete\n", + dev_vdbg(dmaengine_chan_dev(&dc->chan), "descriptor %u %p complete\n", txd->cookie, desc); dma_cookie_complete(txd); @@ -469,11 +464,11 @@ static void txx9dmac_dump_desc(struct txx9dmac_chan *dc, { if (is_dmac64(dc)) { #ifdef TXX9_DMA_USE_SIMPLE_CHAIN - dev_crit(chan2dev(&dc->chan), + dev_crit(dmaengine_chan_dev(&dc->chan), " desc: ch%#llx s%#llx d%#llx c%#x\n", (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR); #else - dev_crit(chan2dev(&dc->chan), + dev_crit(dmaengine_chan_dev(&dc->chan), " desc: ch%#llx s%#llx d%#llx c%#x" " si%#x di%#x cc%#x cs%#x\n", (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR, @@ -482,11 +477,11 @@ static void txx9dmac_dump_desc(struct txx9dmac_chan *dc, } else { struct txx9dmac_hwdesc32 *d = (struct txx9dmac_hwdesc32 *)desc; #ifdef TXX9_DMA_USE_SIMPLE_CHAIN - dev_crit(chan2dev(&dc->chan), + dev_crit(dmaengine_chan_dev(&dc->chan), " desc: ch%#x s%#x d%#x c%#x\n", d->CHAR, d->SAR, d->DAR, d->CNTR); #else - dev_crit(chan2dev(&dc->chan), + dev_crit(dmaengine_chan_dev(&dc->chan), " desc: ch%#x s%#x d%#x c%#x" " si%#x di%#x cc%#x cs%#x\n", d->CHAR, d->SAR, d->DAR, d->CNTR, @@ -506,7 +501,7 @@ static void txx9dmac_handle_error(struct txx9dmac_chan *dc, u32 csr) * borked. Since we don't have any way to report errors, we'll * just have to scream loudly and try to carry on. */ - dev_crit(chan2dev(&dc->chan), "Abnormal Chain Completion\n"); + dev_crit(dmaengine_chan_dev(&dc->chan), "Abnormal Chain Completion\n"); txx9dmac_dump_regs(dc); bad_desc = txx9dmac_first_active(dc); @@ -523,7 +518,7 @@ static void txx9dmac_handle_error(struct txx9dmac_chan *dc, u32 csr) if (!list_empty(&dc->active_list)) txx9dmac_dostart(dc, txx9dmac_first_active(dc)); - dev_crit(chan2dev(&dc->chan), + dev_crit(dmaengine_chan_dev(&dc->chan), "Bad descriptor submitted for DMA! (cookie: %d)\n", bad_desc->txd.cookie); txx9dmac_dump_desc(dc, &bad_desc->hwdesc); @@ -558,7 +553,7 @@ static void txx9dmac_scan_descriptors(struct txx9dmac_chan *dc) if (!(csr & TXX9_DMA_CSR_CHNEN)) chain = 0; /* last descriptor of this chain */ - dev_vdbg(chan2dev(&dc->chan), "scan_descriptors: char=%#llx\n", + dev_vdbg(dmaengine_chan_dev(&dc->chan), "scan_descriptors: char=%#llx\n", (u64)chain); list_for_each_entry_safe(desc, _desc, &dc->active_list, desc_node) { @@ -589,7 +584,7 @@ static void txx9dmac_scan_descriptors(struct txx9dmac_chan *dc) return; } - dev_err(chan2dev(&dc->chan), + dev_err(dmaengine_chan_dev(&dc->chan), "BUG: All descriptors done, but channel not idle!\n"); /* Try to continue after resetting the channel... */ @@ -609,7 +604,7 @@ static void txx9dmac_chan_tasklet(struct tasklet_struct *t) dc = from_tasklet(dc, t, tasklet); csr = channel_readl(dc, CSR); - dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n", csr); + dev_vdbg(dmaengine_chan_dev(&dc->chan), "tasklet: status=%x\n", csr); spin_lock(&dc->lock); if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC | @@ -625,7 +620,7 @@ static irqreturn_t txx9dmac_chan_interrupt(int irq, void *dev_id) { struct txx9dmac_chan *dc = dev_id; - dev_vdbg(chan2dev(&dc->chan), "interrupt: status=%#x\n", + dev_vdbg(dmaengine_chan_dev(&dc->chan), "interrupt: status=%#x\n", channel_readl(dc, CSR)); tasklet_schedule(&dc->tasklet); @@ -654,7 +649,7 @@ static void txx9dmac_tasklet(struct tasklet_struct *t) if ((mcr >> (24 + i)) & 0x11) { dc = ddev->chan[i]; csr = channel_readl(dc, CSR); - dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n", + dev_vdbg(dmaengine_chan_dev(&dc->chan), "tasklet: status=%x\n", csr); spin_lock(&dc->lock); if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC | @@ -696,7 +691,7 @@ static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx) spin_lock_bh(&dc->lock); cookie = dma_cookie_assign(tx); - dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u %p\n", + dev_vdbg(dmaengine_chan_dev(tx->chan), "tx_submit: queued %u %p\n", desc->txd.cookie, desc); list_add_tail(&desc->desc_node, &dc->queue); @@ -717,11 +712,11 @@ txx9dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, size_t xfer_count; size_t offset; - dev_vdbg(chan2dev(chan), "prep_dma_memcpy d%#llx s%#llx l%#zx f%#lx\n", + dev_vdbg(dmaengine_chan_dev(chan), "prep_dma_memcpy d%#llx s%#llx l%#zx f%#lx\n", (u64)dest, (u64)src, len, flags); if (unlikely(!len)) { - dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); + dev_dbg(dmaengine_chan_dev(chan), "prep_dma_memcpy: length is zero!\n"); return NULL; } @@ -812,7 +807,7 @@ txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, unsigned int i; struct scatterlist *sg; - dev_vdbg(chan2dev(chan), "prep_dma_slave\n"); + dev_vdbg(dmaengine_chan_dev(chan), "prep_dma_slave\n"); BUG_ON(!ds || !ds->reg_width); if (ds->tx_reg) @@ -900,7 +895,7 @@ static int txx9dmac_terminate_all(struct dma_chan *chan) struct txx9dmac_desc *desc, *_desc; LIST_HEAD(list); - dev_vdbg(chan2dev(chan), "terminate_all\n"); + dev_vdbg(dmaengine_chan_dev(chan), "terminate_all\n"); spin_lock_bh(&dc->lock); txx9dmac_reset_chan(dc); @@ -988,11 +983,11 @@ static int txx9dmac_alloc_chan_resources(struct dma_chan *chan) struct txx9dmac_desc *desc; int i; - dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); + dev_vdbg(dmaengine_chan_dev(chan), "alloc_chan_resources\n"); /* ASSERT: channel is idle */ if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) { - dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); + dev_dbg(dmaengine_chan_dev(chan), "DMA channel not idle?\n"); return -EIO; } @@ -1022,7 +1017,7 @@ static int txx9dmac_alloc_chan_resources(struct dma_chan *chan) desc = txx9dmac_desc_alloc(dc, GFP_KERNEL); if (!desc) { - dev_info(chan2dev(chan), + dev_info(dmaengine_chan_dev(chan), "only allocated %d descriptors\n", i); spin_lock_bh(&dc->lock); break; @@ -1034,7 +1029,7 @@ static int txx9dmac_alloc_chan_resources(struct dma_chan *chan) } spin_unlock_bh(&dc->lock); - dev_dbg(chan2dev(chan), + dev_dbg(dmaengine_chan_dev(chan), "alloc_chan_resources allocated %d descriptors\n", i); return i; @@ -1047,7 +1042,7 @@ static void txx9dmac_free_chan_resources(struct dma_chan *chan) struct txx9dmac_desc *desc, *_desc; LIST_HEAD(list); - dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n", + dev_dbg(dmaengine_chan_dev(chan), "free_chan_resources (descs allocated=%u)\n", dc->descs_allocated); /* ASSERT: channel is idle */ @@ -1061,13 +1056,13 @@ static void txx9dmac_free_chan_resources(struct dma_chan *chan) spin_unlock_bh(&dc->lock); list_for_each_entry_safe(desc, _desc, &list, desc_node) { - dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); + dev_vdbg(dmaengine_chan_dev(chan), " freeing descriptor %p\n", desc); dma_unmap_single(chan2parent(chan), desc->txd.phys, ddev->descsize, DMA_TO_DEVICE); kfree(desc); } - dev_vdbg(chan2dev(chan), "free_chan_resources done\n"); + dev_vdbg(dmaengine_chan_dev(chan), "free_chan_resources done\n"); } /*----------------------------------------------------------------------*/ diff --git a/drivers/dma/virt-dma.h b/drivers/dma/virt-dma.h index dd023a383120..abf2ae737c30 100644 --- a/drivers/dma/virt-dma.h +++ b/drivers/dma/virt-dma.h @@ -41,6 +41,11 @@ static inline struct virt_dma_chan *to_virt_chan(struct dma_chan *chan) return container_of(chan, struct virt_dma_chan, chan); } +static inline struct device *vchan_chan_dev(struct virt_dma_chan *vc) +{ + return dmaengine_chan_dev(&vc->chan); +} + void vchan_dma_desc_free_list(struct virt_dma_chan *vc, struct list_head *head); void vchan_init(struct virt_dma_chan *vc, struct dma_device *dmadev); struct virt_dma_desc *vchan_find_desc(struct virt_dma_chan *, dma_cookie_t); diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index fe33a20abc61..33aa1bfc8fb8 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -1803,10 +1803,15 @@ dmaengine_get_direction_text(enum dma_transfer_direction dir) } } +static inline struct device *dmaengine_chan_dev(struct dma_chan *chan) +{ + return &chan->dev->device; +} + static inline struct device *dmaengine_get_dma_device(struct dma_chan *chan) { if (chan->dev->chan_dma_dev) - return &chan->dev->device; + return dmaengine_chan_dev(chan); return chan->device->dev; } From 6ad1b49cc30dc9bc7c06dd44241e61fe6f82c0b8 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 9 Sep 2026 12:22:31 -0400 Subject: [PATCH 061/149] dmaengine: add union chan_dev for dma_chan::dev for clarity The current dma_chan structure contains both "device" and "dev". So chan->device->dev refers to the DMA engine device. chan->dev->device refers to the per-channel device instance. Their similar naming makes the distinction unclear and increases reader confusion. Add union dma_chan::chan_dev to make its purpose explicit and clearly identify it as the per-channel device. After all user switch to chan_dev, union and dma_chan::dev will be removed. Update the kernel-doc accordingly. Besides its sysfs usage, the per-channel device is also used by some DMA engine drivers for IOMMU mapping and therefore deserves a more accurate description. No functional change intended. Reviewed-by: Logan Gunthorpe Reviewed-by: Andy Shevchenko Signed-off-by: Frank Li Link: https://patch.msgid.link/20260909-dma-chan_dev-rename-v4-4-d8fb6892a70f@nxp.com Signed-off-by: Vinod Koul --- drivers/dma/dmaengine.c | 14 +++++++------- drivers/dma/tegra186-gpc-dma.c | 2 +- drivers/dma/ti/k3-udma.c | 4 ++-- include/linux/dmaengine.h | 18 +++++++++++++----- 4 files changed, 23 insertions(+), 15 deletions(-) diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c index a7ac2729e4d9..bb30a9aa54d3 100644 --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c @@ -1083,8 +1083,8 @@ static int __dma_async_device_channel_register(struct dma_device *device, chan->local = alloc_percpu(typeof(*chan->local)); if (!chan->local) return -ENOMEM; - chan->dev = kzalloc_obj(*chan->dev); - if (!chan->dev) { + chan->chan_dev = kzalloc_obj(*chan->chan_dev); + if (!chan->chan_dev) { rc = -ENOMEM; goto err_free_local; } @@ -1103,8 +1103,8 @@ static int __dma_async_device_channel_register(struct dma_device *device, dmaengine_chan_dev(chan)->class = &dma_devclass; dmaengine_chan_dev(chan)->parent = device->dev; - chan->dev->chan = chan; - chan->dev->dev_id = device->dev_id; + chan->chan_dev->chan = chan; + chan->chan_dev->dev_id = device->dev_id; spin_lock_init(&chan->lock); if (!name) @@ -1122,7 +1122,7 @@ static int __dma_async_device_channel_register(struct dma_device *device, err_out_ida: ida_free(&device->chan_ida, chan->chan_id); err_free_dev: - kfree(chan->dev); + kfree(chan->chan_dev); err_free_local: free_percpu(chan->local); chan->local = NULL; @@ -1155,7 +1155,7 @@ static void __dma_async_device_channel_unregister(struct dma_device *device, __func__, chan->client_count); mutex_lock(&dma_list_mutex); device->chancnt--; - chan->dev->chan = NULL; + chan->chan_dev->chan = NULL; mutex_unlock(&dma_list_mutex); ida_free(&device->chan_ida, chan->chan_id); device_unregister(dmaengine_chan_dev(chan)); @@ -1290,7 +1290,7 @@ int dma_async_device_register(struct dma_device *device) if (chan->local == NULL) continue; mutex_lock(&dma_list_mutex); - chan->dev->chan = NULL; + chan->chan_dev->chan = NULL; mutex_unlock(&dma_list_mutex); device_unregister(dmaengine_chan_dev(chan)); free_percpu(chan->local); diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c index b3327aa35de4..e76c58f213d8 100644 --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -1554,7 +1554,7 @@ static int tegra_dma_probe(struct platform_device *pdev) return dev_err_probe(chdev, -EINVAL, "Failed to get stream ID for channel %d\n", tdc->id); - chan->dev->chan_dma_dev = true; + chan->chan_dev->chan_dma_dev = true; } /* program stream-id for this channel */ diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 49e2d0014d5e..78a67cb9d6e0 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -426,12 +426,12 @@ static void k3_configure_chan_coherency(struct dma_chan *chan, u32 asel) if (asel == 0) { /* No special handling for the channel */ - chan->dev->chan_dma_dev = false; + chan->chan_dev->chan_dma_dev = false; dev_clear_dma_coherent(chan_dev); chan_dev->dma_parms = NULL; } else if (asel == 14 || asel == 15) { - chan->dev->chan_dma_dev = true; + chan->chan_dev->chan_dma_dev = true; dev_set_dma_coherent(chan_dev); dma_coerce_mask_and_coherent(chan_dev, DMA_BIT_MASK(48)); diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 33aa1bfc8fb8..c3a49a33307c 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -325,7 +325,8 @@ struct dma_router { * @lock: protect between config and prepare transfer when driver have not * implemented callback device_prep_config_sg(). * @chan_id: channel ID for sysfs - * @dev: class device for sysfs + * @chan_dev: class channel device for sysfs, some device use it for per-channel + * IOMMU mapping. * @name: backlink name for sysfs * @dbg_client_name: slave name for debugfs in format: * dev_name(requester's dev):channel name, for example: "2b00000.mcasp:tx" @@ -351,7 +352,14 @@ struct dma_chan { /* sysfs */ int chan_id; - struct dma_chan_dev *dev; + union { + struct dma_chan_dev *chan_dev; + /* + * Use chan_dev; dev will be removed once all users are + * converted. + */ + struct dma_chan_dev *dev; + }; const char *name; #ifdef CONFIG_DEBUG_FS char *dbg_client_name; @@ -532,7 +540,7 @@ struct dma_slave_caps { static inline const char *dma_chan_name(struct dma_chan *chan) { - return dev_name(&chan->dev->device); + return dev_name(&chan->chan_dev->device); } /** @@ -1805,12 +1813,12 @@ dmaengine_get_direction_text(enum dma_transfer_direction dir) static inline struct device *dmaengine_chan_dev(struct dma_chan *chan) { - return &chan->dev->device; + return &chan->chan_dev->device; } static inline struct device *dmaengine_get_dma_device(struct dma_chan *chan) { - if (chan->dev->chan_dma_dev) + if (chan->chan_dev->chan_dma_dev) return dmaengine_chan_dev(chan); return chan->device->dev; From bcb4d469b19d53dc21e4a1da12d4438e7489e150 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Wed, 9 Sep 2026 16:46:01 -0700 Subject: [PATCH 062/149] dmaengine: mv_xor: kill tasklet on channel add error path If request_irq() succeeds but a later step (self-test or device registration) fails, the error path at err_free_irq frees the IRQ but does not kill the tasklet. A previously scheduled tasklet can still run after the channel is freed, accessing freed memory. Add tasklet_kill() after free_irq() on the error path. Fixes: ff7b04796d98 ("dmaengine: DMA engine driver for Marvell XOR engine") Assisted-by: opencode:big-pickle Signed-off-by: Rosen Penev Reviewed-by: Frank Li Link: https://patch.msgid.link/20260909234601.101883-1-rosenp@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/mv_xor.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c index dd4f150d5fb1..c4e0dce3ca64 100644 --- a/drivers/dma/mv_xor.c +++ b/drivers/dma/mv_xor.c @@ -1167,6 +1167,7 @@ mv_xor_channel_add(struct mv_xor_device *xordev, err_free_irq: free_irq(mv_chan->irq, mv_chan); + tasklet_kill(&mv_chan->irq_tasklet); err_free_dma: dma_free_wc(&pdev->dev, MV_XOR_POOL_SIZE, mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); From 8b641810905cba4eb200d72adde386bca380c0df Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Thu, 10 Sep 2026 12:43:24 -0700 Subject: [PATCH 063/149] dmaengine: fsl_raid: byte-swap cdb32 when programming CDBs The three prep functions write the first word of the command descriptor block (cdb32) with a plain u32 assignment, while every other CDB/CF descriptor field is written with cpu_to_be32(). The RAID Engine expects big-endian descriptors, so the plain assignment produces a corrupted CDB on little-endian hosts. Use cpu_to_be32() for cdb32 to match the surrounding code. Assisted-by: opencode:big-pickle Signed-off-by: Rosen Penev Reviewed-by: Frank Li Link: https://patch.msgid.link/20260910194324.33697-1-rosenp@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/fsl_raid.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/dma/fsl_raid.c b/drivers/dma/fsl_raid.c index befb4bb69d54..9cc289f7129e 100644 --- a/drivers/dma/fsl_raid.c +++ b/drivers/dma/fsl_raid.c @@ -361,7 +361,7 @@ static struct dma_async_tx_descriptor *fsl_re_prep_dma_genq( cdb |= FSL_RE_INTR_ON_ERROR << FSL_RE_CDB_ERROR_SHIFT; cdb |= FSL_RE_DATA_DEP << FSL_RE_CDB_DEPEND_SHIFT; xor = desc->cdb_addr; - xor->cdb32 = cdb; + xor->cdb32 = cpu_to_be32(cdb); if (scf) { /* compute q = src0*coef0^src1*coef1^..., * is GF(8) mult */ @@ -481,7 +481,7 @@ static struct dma_async_tx_descriptor *fsl_re_prep_dma_pq( cdb |= FSL_RE_DATA_DEP << FSL_RE_CDB_DEPEND_SHIFT; pq = desc->cdb_addr; - pq->cdb32 = cdb; + pq->cdb32 = cpu_to_be32(cdb); p = pq->gfm_q1; /* Init gfm_q1[] */ @@ -564,7 +564,7 @@ static struct dma_async_tx_descriptor *fsl_re_prep_dma_memcpy( cdb |= FSL_RE_DATA_DEP << FSL_RE_CDB_DEPEND_SHIFT; move = desc->cdb_addr; - move->cdb32 = cdb; + move->cdb32 = cpu_to_be32(cdb); /* Filling frame 0 of CFD with move CDB */ cf = desc->cf_addr; From eb18901d481971c4ee938f59b0256ee8f02e0ce7 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Thu, 10 Sep 2026 13:24:53 -0700 Subject: [PATCH 064/149] dmaengine: fsldma: fix kernel-doc param names to match function signatures Fix kernel-doc warnings where the documented parameter names (@chan) no longer match the actual function signatures (@dchan), and add the missing @cookie and @txstate parameters to fsl_tx_status. Assisted-by: opencode:big-pickle Signed-off-by: Rosen Penev Reviewed-by: Frank Li Link: https://patch.msgid.link/20260910202453.47887-1-rosenp@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/fsldma.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index 22d62d958abd..6ce0e5668dc2 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -681,7 +681,7 @@ static void fsldma_cleanup_descriptors(struct fsldma_chan *chan) /** * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. - * @chan : Freescale DMA channel + * @dchan : Freescale DMA channel * * This function will create a dma pool for descriptor allocation. * @@ -738,7 +738,7 @@ static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan, /** * fsl_dma_free_chan_resources - Free all resources of the channel. - * @chan : Freescale DMA channel + * @dchan : Freescale DMA channel */ static void fsl_dma_free_chan_resources(struct dma_chan *dchan) { @@ -873,7 +873,7 @@ static int fsl_dma_device_config(struct dma_chan *dchan, /** * fsl_dma_memcpy_issue_pending - Issue the DMA start command - * @chan : Freescale DMA channel + * @dchan : Freescale DMA channel */ static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan) { @@ -886,7 +886,9 @@ static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan) /** * fsl_tx_status - Determine the DMA status - * @chan : Freescale DMA channel + * @dchan : Freescale DMA channel + * @cookie : DMA transaction identifier + * @txstate : DMA transaction state */ static enum dma_status fsl_tx_status(struct dma_chan *dchan, dma_cookie_t cookie, From 32ac4723e5526c44e5a1f3b1586578c17647f2ef Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Thu, 10 Sep 2026 13:28:46 -0700 Subject: [PATCH 065/149] dmaengine: fsldma: kill tasklet before removing channel Add tasklet_kill() in fsl_dma_chan_remove() to prevent a race where the tasklet is scheduled by the IRQ handler and runs after the channel has been freed. Assisted-by: opencode:big-pickle Signed-off-by: Rosen Penev Reviewed-by: Frank Li Link: https://patch.msgid.link/20260910202846.48941-1-rosenp@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/fsldma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index 6ce0e5668dc2..5eca8ab23564 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -1207,6 +1207,7 @@ static int fsl_dma_chan_probe(struct fsldma_device *fdev, static void fsl_dma_chan_remove(struct fsldma_chan *chan) { + tasklet_kill(&chan->tasklet); irq_dispose_mapping(chan->irq); list_del(&chan->common.device_node); iounmap(chan->regs); From bfd958664fccd794377a8adb74b492498c824643 Mon Sep 17 00:00:00 2001 From: Slavin Liu Date: Fri, 11 Sep 2026 14:09:02 +0800 Subject: [PATCH 066/149] dmaengine: fsl-edma: check channel acquisition before use dma_get_slave_channel() can return NULL when acquiring a channel fails, for example if fsl_edma_alloc_chan_resources() cannot request an IRQ. fsl_edma3_xlate() dereferences that return value to update privatecnt. Acquire and check the channel before publishing its source ID and request parameters. A NULL-only check after the existing source-ID assignment would leave the failed request marked as in use, causing fsl_edma_srcid_in_use() to reject a subsequent request for that source. The channel resource-allocation callback does not consume these request parameters, so set them only after acquisition succeeds. The existing scoped mutex release and successful-channel return are preserved. Detected by static analysis and reviewed with AI-assisted source auditing. Assisted-by: LLM Signed-off-by: Slavin Liu Reviewed-by: Frank Li Link: https://patch.msgid.link/20260911060902.94153-1-bolin.liu@seu.edu.cn Signed-off-by: Vinod Koul --- drivers/dma/fsl-edma-main.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index d9fb717b5b53..6934ac882697 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -326,13 +326,16 @@ static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec, if ((dma_spec->args[2] & FSL_EDMA_ODD_CH) && !(i & 0x1)) continue; + chan = dma_get_slave_channel(chan); + if (!chan) + return NULL; + fsl_chan->srcid = dma_spec->args[0]; fsl_chan->priority = dma_spec->args[1]; fsl_chan->is_rxchan = dma_spec->args[2] & FSL_EDMA_RX; fsl_chan->is_remote = dma_spec->args[2] & FSL_EDMA_REMOTE; fsl_chan->is_multi_fifo = dma_spec->args[2] & FSL_EDMA_MULTI_FIFO; - chan = dma_get_slave_channel(chan); chan->device->privatecnt++; return chan; } From 0838d7cfa42536d2cdeb90074417fae33a2585a6 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Fri, 11 Sep 2026 15:04:39 -0700 Subject: [PATCH 067/149] dmaengine: fsldma: convert to platform_get_irq_optional() Replace the per-controller irq_of_parse_and_map() call with platform_get_irq_optional(). The controller IRQ is optional when absent and the driver falls back to per-channel IRQs. The corresponding irq_dispose_mapping() calls in the probe error path and remove function are removed. Moved before anything else in order to handle -EPROBE_DEFER and to avoid doing extra work. Simplifies the if statements as well. Assisted-by: LLM Signed-off-by: Rosen Penev Reviewed-by: Frank Li Link: https://patch.msgid.link/20260911220439.177474-1-rosenp@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/fsldma.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index 5eca8ab23564..99a878ed1444 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -1219,8 +1219,13 @@ static int fsldma_of_probe(struct platform_device *op) struct fsldma_device *fdev; struct device_node *child; unsigned int i; + int irq; int err; + irq = platform_get_irq_optional(op, 0); + if (irq == -EPROBE_DEFER) + return irq; + fdev = kzalloc_obj(*fdev); if (!fdev) { err = -ENOMEM; @@ -1241,7 +1246,9 @@ static int fsldma_of_probe(struct platform_device *op) } /* map the channel IRQ if it exists, but don't hookup the handler yet */ - fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0); + fdev->irq = irq; + if (fdev->irq < 0) + fdev->irq = 0; dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); @@ -1303,7 +1310,6 @@ static int fsldma_of_probe(struct platform_device *op) if (fdev->chan[i]) fsl_dma_chan_remove(fdev->chan[i]); } - irq_dispose_mapping(fdev->irq); iounmap(fdev->regs); out_free: kfree(fdev); @@ -1325,7 +1331,6 @@ static void fsldma_of_remove(struct platform_device *op) if (fdev->chan[i]) fsl_dma_chan_remove(fdev->chan[i]); } - irq_dispose_mapping(fdev->irq); iounmap(fdev->regs); kfree(fdev); From 1ff9bed1b5547259f67e58b03a83eda934d78735 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sun, 13 Sep 2026 12:48:04 -0700 Subject: [PATCH 068/149] dmaengine: bestcomm: make gen_bd init helpers static bcom_gen_bd_rx_init() and bcom_gen_bd_tx_init() are only called from the PSC wrapper functions in gen_bd.c, so make them static, drop their now-unneeded exports, and remove the corresponding header declarations. These had use before commit 7d3ee229ea51 ("powerpc: Drop MPC5200 LocalPlus bus FIFO driver") Assisted-by: LLM Signed-off-by: Rosen Penev Reviewed-by: Frank Li Reviewed-by: Christophe Leroy (CS GROUP) Link: https://patch.msgid.link/20260913194804.39939-1-rosenp@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/bestcomm/gen_bd.c | 6 ++---- include/linux/fsl/bestcomm/gen_bd.h | 8 -------- 2 files changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/dma/bestcomm/gen_bd.c b/drivers/dma/bestcomm/gen_bd.c index 61b5746e1a97..b5093f7445cb 100644 --- a/drivers/dma/bestcomm/gen_bd.c +++ b/drivers/dma/bestcomm/gen_bd.c @@ -81,7 +81,7 @@ struct bcom_gen_bd_priv { /* Task support code */ /* ======================================================================== */ -struct bcom_task * +static struct bcom_task * bcom_gen_bd_rx_init(int queue_len, phys_addr_t fifo, int initiator, int ipr, int maxbufsize) { @@ -108,7 +108,6 @@ bcom_gen_bd_rx_init(int queue_len, phys_addr_t fifo, return tsk; } -EXPORT_SYMBOL_GPL(bcom_gen_bd_rx_init); int bcom_gen_bd_rx_reset(struct bcom_task *tsk) @@ -166,7 +165,7 @@ bcom_gen_bd_rx_release(struct bcom_task *tsk) EXPORT_SYMBOL_GPL(bcom_gen_bd_rx_release); -extern struct bcom_task * +static struct bcom_task * bcom_gen_bd_tx_init(int queue_len, phys_addr_t fifo, int initiator, int ipr) { @@ -192,7 +191,6 @@ bcom_gen_bd_tx_init(int queue_len, phys_addr_t fifo, return tsk; } -EXPORT_SYMBOL_GPL(bcom_gen_bd_tx_init); int bcom_gen_bd_tx_reset(struct bcom_task *tsk) diff --git a/include/linux/fsl/bestcomm/gen_bd.h b/include/linux/fsl/bestcomm/gen_bd.h index aeb312a1cd00..7253d308d77a 100644 --- a/include/linux/fsl/bestcomm/gen_bd.h +++ b/include/linux/fsl/bestcomm/gen_bd.h @@ -16,10 +16,6 @@ struct bcom_gen_bd { }; -extern struct bcom_task * -bcom_gen_bd_rx_init(int queue_len, phys_addr_t fifo, - int initiator, int ipr, int maxbufsize); - extern int bcom_gen_bd_rx_reset(struct bcom_task *tsk); @@ -27,10 +23,6 @@ extern void bcom_gen_bd_rx_release(struct bcom_task *tsk); -extern struct bcom_task * -bcom_gen_bd_tx_init(int queue_len, phys_addr_t fifo, - int initiator, int ipr); - extern int bcom_gen_bd_tx_reset(struct bcom_task *tsk); From a8d1f582fae8231bd0cf66164ef140cd410382d4 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Tue, 15 Sep 2026 00:26:08 -0700 Subject: [PATCH 069/149] dmaengine: bestcomm: gen_bd: fix out-of-bounds access in PSC parameter lookup The bcom_psc_params[] array has 6 entries (indices 0-5), but bcom_psc_gen_bd_rx_init() checked against MPC52xx_PSC_MAXNUM which can be 12 when CONFIG_PPC_MPC512x is set, allowing indices 6-11 to pass and read past the array. The tx init function had no bounds check at all. A malformed device tree with a large cell-index could therefore trigger an out-of-bounds read. The garbage initiator and ipr values would then be used for MMIO writes via out_8(&bcom_eng->regs->ipr[...], ...), potentially causing out-of-bounds MMIO accesses. Assisted-by: LLM Signed-off-by: Rosen Penev Reviewed-by: Frank Li Link: https://patch.msgid.link/20260915072608.57887-1-rosenp@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/bestcomm/gen_bd.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/dma/bestcomm/gen_bd.c b/drivers/dma/bestcomm/gen_bd.c index b5093f7445cb..3b4fabb4d12b 100644 --- a/drivers/dma/bestcomm/gen_bd.c +++ b/drivers/dma/bestcomm/gen_bd.c @@ -319,7 +319,7 @@ static const struct bcom_psc_params bcom_psc_params[] = { struct bcom_task * bcom_psc_gen_bd_rx_init(unsigned psc_num, int queue_len, phys_addr_t fifo, int maxbufsize) { - if (psc_num >= MPC52xx_PSC_MAXNUM) + if (psc_num >= ARRAY_SIZE(bcom_psc_params)) return NULL; return bcom_gen_bd_rx_init(queue_len, fifo, @@ -340,6 +340,9 @@ EXPORT_SYMBOL_GPL(bcom_psc_gen_bd_rx_init); struct bcom_task * bcom_psc_gen_bd_tx_init(unsigned psc_num, int queue_len, phys_addr_t fifo) { + if (psc_num >= ARRAY_SIZE(bcom_psc_params)) + return NULL; + struct psc; return bcom_gen_bd_tx_init(queue_len, fifo, bcom_psc_params[psc_num].tx_initiator, From 0a8dda0a15d3926422d286567f945a05328a4ac6 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Tue, 15 Sep 2026 00:28:53 -0700 Subject: [PATCH 070/149] dmaengine: bestcomm: use devm_platform_get_and_ioremap_resource() to simplify code Replace the open-coded resource lookup, request_mem_region, ioremap and the manual iounmap/release_mem_region cleanup in probe/remove with the managed devm_platform_get_and_ioremap_resource() helper. This removes the now-unused error-unmap/release paths and simplifies probing. Fix a resource size mismatch between allocating and freeing where request_mem_region() and release_mem_region() hopefully use the same size but is not guarenteed. Signed-off-by: Rosen Penev Reviewed-by: Frank Li Link: https://patch.msgid.link/20260915072853.58587-1-rosenp@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/bestcomm/bestcomm.c | 45 ++++++++------------------------- 1 file changed, 10 insertions(+), 35 deletions(-) diff --git a/drivers/dma/bestcomm/bestcomm.c b/drivers/dma/bestcomm/bestcomm.c index ec58d2c6573f..241a91936fe8 100644 --- a/drivers/dma/bestcomm/bestcomm.c +++ b/drivers/dma/bestcomm/bestcomm.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -365,13 +364,19 @@ bcom_engine_cleanup(void) static int mpc52xx_bcom_probe(struct platform_device *op) { struct device_node *ofn_sram; - struct resource res_bcom; + struct resource *res_bcom; + void __iomem *regs; int rv; /* Inform user we're ok so far */ printk(KERN_INFO "DMA: MPC52xx BestComm driver\n"); + /* Get, reserve & map io */ + regs = devm_platform_get_and_ioremap_resource(op, 0, &res_bcom); + if (IS_ERR(regs)) + return PTR_ERR(regs); + /* Get the bestcomm node */ of_node_get(op->dev.of_node); @@ -402,35 +407,13 @@ static int mpc52xx_bcom_probe(struct platform_device *op) /* Save the node */ bcom_eng->ofnode = op->dev.of_node; - /* Get, reserve & map io */ - if (of_address_to_resource(op->dev.of_node, 0, &res_bcom)) { - printk(KERN_ERR DRIVER_NAME ": " - "Can't get resource\n"); - rv = -EINVAL; - goto error_sramclean; - } - - if (!request_mem_region(res_bcom.start, resource_size(&res_bcom), - DRIVER_NAME)) { - printk(KERN_ERR DRIVER_NAME ": " - "Can't request registers region\n"); - rv = -EBUSY; - goto error_sramclean; - } - - bcom_eng->regs_base = res_bcom.start; - bcom_eng->regs = ioremap(res_bcom.start, sizeof(struct mpc52xx_sdma)); - if (!bcom_eng->regs) { - printk(KERN_ERR DRIVER_NAME ": " - "Can't map registers\n"); - rv = -ENOMEM; - goto error_release; - } + bcom_eng->regs = regs; + bcom_eng->regs_base = res_bcom->start; /* Now, do the real init */ rv = bcom_engine_init(); if (rv) - goto error_unmap; + goto error_sramclean; /* Done ! */ printk(KERN_INFO "DMA: MPC52xx BestComm engine @%08lx ok !\n", @@ -439,10 +422,6 @@ static int mpc52xx_bcom_probe(struct platform_device *op) return 0; /* Error path */ -error_unmap: - iounmap(bcom_eng->regs); -error_release: - release_mem_region(res_bcom.start, sizeof(struct mpc52xx_sdma)); error_sramclean: kfree(bcom_eng); bcom_eng = NULL; @@ -464,10 +443,6 @@ static void mpc52xx_bcom_remove(struct platform_device *op) /* Cleanup SRAM */ bcom_sram_cleanup(); - /* Release regs */ - iounmap(bcom_eng->regs); - release_mem_region(bcom_eng->regs_base, sizeof(struct mpc52xx_sdma)); - /* Release the node */ of_node_put(bcom_eng->ofnode); From 6c0a5a1fb1668b5fa9f9c9c302f5235d131f2ed5 Mon Sep 17 00:00:00 2001 From: Roman Vivchar Date: Mon, 14 Sep 2026 15:10:52 +0300 Subject: [PATCH 071/149] dt-bindings: dma: mediatek,uart-dma: add mt6572 Add a compatible string for the mt6572 APDMA, that is compatible with mt6577 IP. Signed-off-by: Roman Vivchar Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Link: https://patch.msgid.link/20260914-6572-dt-uartdma-v1-1-b26b429ab68c@protonmail.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml b/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml index bba20e88a6dc..bd5f5260613b 100644 --- a/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml +++ b/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml @@ -23,6 +23,7 @@ properties: - items: - enum: - mediatek,mt2712-uart-dma + - mediatek,mt6572-uart-dma - mediatek,mt6795-uart-dma - mediatek,mt8173-uart-dma - mediatek,mt8183-uart-dma From 3b18c8e460760a7993c54f9d591b1b758349b1b3 Mon Sep 17 00:00:00 2001 From: Yuanshen Cao Date: Wed, 26 Aug 2026 02:40:27 +0000 Subject: [PATCH 072/149] dmaengine: sun6i-dma: Refactor to support A733 interrupt and register handling The `sun6i-dma` driver currently uses hardcoded logic for interrupt handling (reading/writing interrupt enable and status registers) and register dumping. To support the Allwinner A733, which has a different register layout and interrupt handling logic, add `irq_stride`, `irq_en_offset`, and `irq_stat_offset` to `struct sun6i_dma_config`. Implement generic `sun6i_read/write_irq_*` functions using these new configuration fields to accommodate different hardware revisions. Signed-off-by: Yuanshen Cao Reviewed-by: Frank Li Link: https://patch.msgid.link/20260826-sun60i-a733-dma-v5-1-abc5229b441e@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/sun6i-dma.c | 87 +++++++++++++++++++++++++++++++---------- 1 file changed, 67 insertions(+), 20 deletions(-) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index 5ad9d01cff3a..f38a80f918fb 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -27,7 +27,6 @@ /* * Common registers */ -#define DMA_IRQ_EN(x) ((x) * 0x04) #define DMA_IRQ_HALF BIT(0) #define DMA_IRQ_PKG BIT(1) #define DMA_IRQ_QUEUE BIT(2) @@ -36,8 +35,6 @@ #define DMA_IRQ_CHAN_WIDTH 4 -#define DMA_IRQ_STAT(x) ((x) * 0x04 + 0x10) - #define DMA_STAT 0x30 /* Offset between DMA_IRQ_EN and DMA_IRQ_STAT limits number of channels */ @@ -52,6 +49,14 @@ #define SUNXI_H3_SECURE_REG 0x20 #define SUNXI_H3_DMA_GATE 0x28 #define SUNXI_H3_DMA_GATE_ENABLE 0x4 + +/* + * Interrupts specific registers + */ +#define DMA_IRQ_STRIDE_A31 0x04 +#define DMA_IRQ_EN_OFFSET_A31 0x00 +#define DMA_IRQ_STAT_OFFSET_A31 0x10 + /* * Channels specific registers */ @@ -144,6 +149,9 @@ struct sun6i_dma_config { u32 dst_addr_widths; bool has_high_addr; bool has_mbus_clk; + u32 irq_stride; + u32 irq_en_offset; + u32 irq_stat_offset; }; /* @@ -229,19 +237,43 @@ to_sun6i_desc(struct dma_async_tx_descriptor *tx) return container_of(tx, struct sun6i_desc, vd.tx); } +static u32 sun6i_read_irq_en(struct sun6i_dma_dev *sdev, u32 irq_reg) +{ + return readl(sdev->base + irq_reg * sdev->cfg->irq_stride + sdev->cfg->irq_en_offset); +} + +static void sun6i_write_irq_en(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 irq_val) +{ + writel(irq_val, sdev->base + irq_reg * sdev->cfg->irq_stride + sdev->cfg->irq_en_offset); +} + +static u32 sun6i_read_irq_stat(struct sun6i_dma_dev *sdev, u32 irq_reg) +{ + return readl(sdev->base + irq_reg * sdev->cfg->irq_stride + sdev->cfg->irq_stat_offset); +} + +static void sun6i_write_irq_stat(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 status) +{ + writel(status, sdev->base + irq_reg * sdev->cfg->irq_stride + sdev->cfg->irq_stat_offset); +} + static inline void sun6i_dma_dump_com_regs(struct sun6i_dma_dev *sdev) { - dev_dbg(sdev->slave.dev, "Common register:\n" - "\tmask0(%04x): 0x%08x\n" - "\tmask1(%04x): 0x%08x\n" - "\tpend0(%04x): 0x%08x\n" - "\tpend1(%04x): 0x%08x\n" - "\tstats(%04x): 0x%08x\n", - DMA_IRQ_EN(0), readl(sdev->base + DMA_IRQ_EN(0)), - DMA_IRQ_EN(1), readl(sdev->base + DMA_IRQ_EN(1)), - DMA_IRQ_STAT(0), readl(sdev->base + DMA_IRQ_STAT(0)), - DMA_IRQ_STAT(1), readl(sdev->base + DMA_IRQ_STAT(1)), - DMA_STAT, readl(sdev->base + DMA_STAT)); + int i; + + for (i = 0; i < 2; i++) { + dev_dbg(sdev->slave.dev, "Common register:\n" + "chan num %d\n" + "\tmask(%04x): 0x%08x\n" + "\tpend(%04x): 0x%08x\n" + "\tstats(%04x): 0x%08x\n", + i, + i * sdev->cfg->irq_stride + sdev->cfg->irq_en_offset, + sun6i_read_irq_en(sdev, i), + i * sdev->cfg->irq_stride + sdev->cfg->irq_stat_offset, + sun6i_read_irq_stat(sdev, i), + DMA_STAT, readl(sdev->base + DMA_STAT)); + } } static inline void sun6i_dma_dump_chan_regs(struct sun6i_dma_dev *sdev, @@ -462,11 +494,11 @@ static int sun6i_dma_start_desc(struct sun6i_vchan *vchan) vchan->irq_type = vchan->cyclic ? DMA_IRQ_PKG : DMA_IRQ_QUEUE; - irq_val = readl(sdev->base + DMA_IRQ_EN(irq_reg)); + irq_val = sun6i_read_irq_en(sdev, irq_reg); irq_val &= ~((DMA_IRQ_HALF | DMA_IRQ_PKG | DMA_IRQ_QUEUE) << (irq_offset * DMA_IRQ_CHAN_WIDTH)); irq_val |= vchan->irq_type << (irq_offset * DMA_IRQ_CHAN_WIDTH); - writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg)); + sun6i_write_irq_en(sdev, irq_reg, irq_val); writel(pchan->desc->p_lli, pchan->base + DMA_CHAN_LLI_ADDR); writel(DMA_CHAN_ENABLE_START, pchan->base + DMA_CHAN_ENABLE); @@ -551,14 +583,14 @@ static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id) u32 status; for (i = 0; i < sdev->num_pchans / DMA_IRQ_CHAN_NR; i++) { - status = readl(sdev->base + DMA_IRQ_STAT(i)); + status = sun6i_read_irq_stat(sdev, i); if (!status) continue; dev_dbg(sdev->slave.dev, "DMA irq status %s: 0x%x\n", str_high_low(i), status); - writel(status, sdev->base + DMA_IRQ_STAT(i)); + sun6i_write_irq_stat(sdev, i, status); for (j = 0; (j < DMA_IRQ_CHAN_NR) && status; j++) { pchan = sdev->pchans + j; @@ -1068,9 +1100,11 @@ static struct dma_chan *sun6i_dma_of_xlate(struct of_phandle_args *dma_spec, static inline void sun6i_kill_tasklet(struct sun6i_dma_dev *sdev) { + int i; + /* Disable all interrupts from DMA */ - writel(0, sdev->base + DMA_IRQ_EN(0)); - writel(0, sdev->base + DMA_IRQ_EN(1)); + for (i = 0; i < 2; i++) + sun6i_write_irq_en(sdev, i, 0); /* Prevent spurious interrupts from scheduling the tasklet */ atomic_inc(&sdev->tasklet_shutdown); @@ -1094,6 +1128,11 @@ static inline void sun6i_dma_free(struct sun6i_dma_dev *sdev) } } +#define SUN6I_DMA_IRQ_A31_COMMON_CFG \ + .irq_stride = DMA_IRQ_STRIDE_A31, \ + .irq_en_offset = DMA_IRQ_EN_OFFSET_A31, \ + .irq_stat_offset = DMA_IRQ_STAT_OFFSET_A31, + /* * For A31: * @@ -1125,6 +1164,7 @@ static struct sun6i_dma_config sun6i_a31_dma_cfg = { .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_CFG }; /* @@ -1148,6 +1188,7 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = { .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_CFG }; static struct sun6i_dma_config sun8i_a83t_dma_cfg = { @@ -1166,6 +1207,7 @@ static struct sun6i_dma_config sun8i_a83t_dma_cfg = { .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_CFG }; /* @@ -1193,6 +1235,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_CFG }; /* @@ -1214,6 +1257,7 @@ static struct sun6i_dma_config sun50i_a64_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_CFG }; /* @@ -1237,6 +1281,7 @@ static struct sun6i_dma_config sun50i_a100_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), .has_high_addr = true, .has_mbus_clk = true, + SUN6I_DMA_IRQ_A31_COMMON_CFG }; /* @@ -1259,6 +1304,7 @@ static struct sun6i_dma_config sun50i_h6_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), .has_mbus_clk = true, + SUN6I_DMA_IRQ_A31_COMMON_CFG }; /* @@ -1282,6 +1328,7 @@ static struct sun6i_dma_config sun8i_v3s_dma_cfg = { .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_CFG }; static const struct of_device_id sun6i_dma_match[] = { From 4ec2d7bbbf2c79a63469b4a027cd522abdbfb2f9 Mon Sep 17 00:00:00 2001 From: Yuanshen Cao Date: Wed, 26 Aug 2026 02:40:28 +0000 Subject: [PATCH 073/149] dmaengine: sun6i-dma: Support variable address widths using masks The Allwinner A733 DMA controller supports higher addresses (up to 32G) compared to previous generations. The existing `sun6i_dma_set_addr` function uses hardcoded logic for setting the high-address bits in the LLI parameters. Add `src_high_addr_mask` and `dst_high_addr_mask` to `struct sun6i_dma_config` to handle different high-address bitfield mappings. Update `sun6i_dma_set_addr` to use these masks via `field_prep()`, allowing the driver to support variable address widths. Signed-off-by: Yuanshen Cao Reviewed-by: Frank Li Link: https://patch.msgid.link/20260826-sun60i-a733-dma-v5-2-abc5229b441e@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/sun6i-dma.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index f38a80f918fb..eb0a6a349399 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -7,6 +7,7 @@ * Maxime Ripard */ +#include #include #include #include @@ -103,8 +104,8 @@ * The LLI link physical address is also mangled, but we avoid dealing * with that by allocating LLIs from the DMA32 zone. */ -#define SRC_HIGH_ADDR(x) (((x) & 0x3U) << 16) -#define DST_HIGH_ADDR(x) (((x) & 0x3U) << 18) +#define SRC_HIGH_ADDR_MASK GENMASK(17, 16) +#define DST_HIGH_ADDR_MASK GENMASK(19, 18) /* * Various hardware related defines @@ -147,7 +148,8 @@ struct sun6i_dma_config { u32 dst_burst_lengths; u32 src_addr_widths; u32 dst_addr_widths; - bool has_high_addr; + u32 src_high_addr_mask; + u32 dst_high_addr_mask; bool has_mbus_clk; u32 irq_stride; u32 irq_en_offset; @@ -689,9 +691,10 @@ static inline void sun6i_dma_set_addr(struct sun6i_dma_dev *sdev, v_lli->src = lower_32_bits(src); v_lli->dst = lower_32_bits(dst); - if (sdev->cfg->has_high_addr) - v_lli->para |= SRC_HIGH_ADDR(upper_32_bits(src)) | - DST_HIGH_ADDR(upper_32_bits(dst)); + if (sdev->cfg->src_high_addr_mask) + v_lli->para |= + field_prep(sdev->cfg->src_high_addr_mask, upper_32_bits(src)) | + field_prep(sdev->cfg->dst_high_addr_mask, upper_32_bits(dst)); } static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy( @@ -1279,7 +1282,8 @@ static struct sun6i_dma_config sun50i_a100_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), - .has_high_addr = true, + .src_high_addr_mask = SRC_HIGH_ADDR_MASK, + .dst_high_addr_mask = DST_HIGH_ADDR_MASK, .has_mbus_clk = true, SUN6I_DMA_IRQ_A31_COMMON_CFG }; From 9ab1198158a5e6b1d24677970cdd30aba2d39d37 Mon Sep 17 00:00:00 2001 From: Yuanshen Cao Date: Wed, 26 Aug 2026 02:40:29 +0000 Subject: [PATCH 074/149] dmaengine: sun6i-dma: Add num_channels_per_reg for flexible interrupt mapping The `sun6i-dma` driver previously assumed a fixed number of channels per interrupt register. For example, `sun6i_kill_tasklet` was hardcoded to disable interrupts only for registers 0 and 1. `DMA_MAX_CHANNELS` was also not in used previously, and the old SoCs never has more than 16 channels. The A733 has a different interrupt structure where the number of channels per register may differ. Add `num_channels_per_reg` to `struct sun6i_dma_config` to make the interrupt handling logic handware-agnostic Update `sun6i_dma_interrupt`, `sun6i_dma_start_desc`, and `sun6i_kill_tasklet` to use this value. Additionally, set `DMA_MAX_CHANNELS` to 16 to ensure loops over interrupts are correctly bounded, aligning with the hardware specifications. Signed-off-by: Yuanshen Cao Reviewed-by: Frank Li Link: https://patch.msgid.link/20260826-sun60i-a733-dma-v5-3-abc5229b441e@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/sun6i-dma.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index eb0a6a349399..c336ce29f0b3 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -32,14 +32,13 @@ #define DMA_IRQ_PKG BIT(1) #define DMA_IRQ_QUEUE BIT(2) -#define DMA_IRQ_CHAN_NR 8 #define DMA_IRQ_CHAN_WIDTH 4 #define DMA_STAT 0x30 /* Offset between DMA_IRQ_EN and DMA_IRQ_STAT limits number of channels */ -#define DMA_MAX_CHANNELS (DMA_IRQ_CHAN_NR * 0x10 / 4) +#define DMA_MAX_CHANNELS 16 /* * sun8i specific registers @@ -58,6 +57,8 @@ #define DMA_IRQ_EN_OFFSET_A31 0x00 #define DMA_IRQ_STAT_OFFSET_A31 0x10 +#define DMA_IRQ_CHAN_NR_A31 8 + /* * Channels specific registers */ @@ -154,6 +155,7 @@ struct sun6i_dma_config { u32 irq_stride; u32 irq_en_offset; u32 irq_stat_offset; + u32 num_channels_per_reg; }; /* @@ -263,7 +265,7 @@ static inline void sun6i_dma_dump_com_regs(struct sun6i_dma_dev *sdev) { int i; - for (i = 0; i < 2; i++) { + for (i = 0; i < DIV_ROUND_UP(sdev->num_pchans, sdev->cfg->num_channels_per_reg); i++) { dev_dbg(sdev->slave.dev, "Common register:\n" "chan num %d\n" "\tmask(%04x): 0x%08x\n" @@ -491,8 +493,8 @@ static int sun6i_dma_start_desc(struct sun6i_vchan *vchan) sun6i_dma_dump_lli(vchan, pchan->desc->v_lli, pchan->desc->p_lli); - irq_reg = pchan->idx / DMA_IRQ_CHAN_NR; - irq_offset = pchan->idx % DMA_IRQ_CHAN_NR; + irq_reg = pchan->idx / sdev->cfg->num_channels_per_reg; + irq_offset = pchan->idx % sdev->cfg->num_channels_per_reg; vchan->irq_type = vchan->cyclic ? DMA_IRQ_PKG : DMA_IRQ_QUEUE; @@ -584,7 +586,7 @@ static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id) int i, j, ret = IRQ_NONE; u32 status; - for (i = 0; i < sdev->num_pchans / DMA_IRQ_CHAN_NR; i++) { + for (i = 0; i < sdev->num_pchans / sdev->cfg->num_channels_per_reg; i++) { status = sun6i_read_irq_stat(sdev, i); if (!status) continue; @@ -594,7 +596,7 @@ static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id) sun6i_write_irq_stat(sdev, i, status); - for (j = 0; (j < DMA_IRQ_CHAN_NR) && status; j++) { + for (j = 0; (j < sdev->cfg->num_channels_per_reg) && status; j++) { pchan = sdev->pchans + j; vchan = pchan->vchan; if (vchan && (status & vchan->irq_type)) { @@ -1106,7 +1108,7 @@ static inline void sun6i_kill_tasklet(struct sun6i_dma_dev *sdev) int i; /* Disable all interrupts from DMA */ - for (i = 0; i < 2; i++) + for (i = 0; i < DMA_MAX_CHANNELS / sdev->cfg->num_channels_per_reg; i++) sun6i_write_irq_en(sdev, i, 0); /* Prevent spurious interrupts from scheduling the tasklet */ @@ -1134,7 +1136,8 @@ static inline void sun6i_dma_free(struct sun6i_dma_dev *sdev) #define SUN6I_DMA_IRQ_A31_COMMON_CFG \ .irq_stride = DMA_IRQ_STRIDE_A31, \ .irq_en_offset = DMA_IRQ_EN_OFFSET_A31, \ - .irq_stat_offset = DMA_IRQ_STAT_OFFSET_A31, + .irq_stat_offset = DMA_IRQ_STAT_OFFSET_A31, \ + .num_channels_per_reg = DMA_IRQ_CHAN_NR_A31, /* * For A31: From 714f0410eaf057b3fe19e4b9c9028406e38a29d0 Mon Sep 17 00:00:00 2001 From: Yuanshen Cao Date: Wed, 26 Aug 2026 02:40:30 +0000 Subject: [PATCH 075/149] dt-bindings: dmaengine: sun50i-a64-dma: Add allwinner,sun60i-a733-dma compatible string Add `allwinner,sun60i-a733-dma` to the list of compatible strings for the `sun50i-a64-dma` dtbinding documentation. While the A733 DMA controller shares many similarities with the sun50i-a64 DMA controller, it requires a specific configuration due to differences in: - Interrupt register layout and mapping. - Number of channels per interrupt register. - Support for higher (32G) address widths in LLI parameters. Reviewed-by: Frank Li Reviewed-by: Krzysztof Kozlowski Signed-off-by: Yuanshen Cao Link: https://patch.msgid.link/20260826-sun60i-a733-dma-v5-4-abc5229b441e@gmail.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml index c3e14eb6cfff..1cc3304b7414 100644 --- a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml +++ b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml @@ -25,6 +25,7 @@ properties: - allwinner,sun50i-a64-dma - allwinner,sun50i-a100-dma - allwinner,sun50i-h6-dma + - allwinner,sun60i-a733-dma - items: - const: allwinner,sun8i-r40-dma - const: allwinner,sun50i-a64-dma @@ -70,6 +71,7 @@ if: - allwinner,sun20i-d1-dma - allwinner,sun50i-a100-dma - allwinner,sun50i-h6-dma + - allwinner,sun60i-a733-dma then: properties: From 779867c3a5309561e056f9c3c55e5d1dcc7717c9 Mon Sep 17 00:00:00 2001 From: Yuanshen Cao Date: Wed, 26 Aug 2026 02:40:31 +0000 Subject: [PATCH 076/149] dmaengine: sun6i-dma: Implement support for Allwinner A733 DMA controller Implement support for the Allwinner A733 DMA controller by defining A733-specific register offsets, bitfield masks, and the `sun60i_a733_dma_cfg` configuration structure. This includes the IRQ stride, offsets, and channel counts specific to the A733, as well as the 32G mask for high-address fields in the LLI. Add `sun60i_a733_dma_cfg`, which ties all the refactored functionality together for A733. Signed-off-by: Yuanshen Cao Reviewed-by: Frank Li Link: https://patch.msgid.link/20260826-sun60i-a733-dma-v5-5-abc5229b441e@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/sun6i-dma.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index c336ce29f0b3..50e54cebc5c8 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -54,10 +54,14 @@ * Interrupts specific registers */ #define DMA_IRQ_STRIDE_A31 0x04 +#define DMA_IRQ_STRIDE_A733 0x40 #define DMA_IRQ_EN_OFFSET_A31 0x00 +#define DMA_IRQ_EN_OFFSET_A733 0x134 #define DMA_IRQ_STAT_OFFSET_A31 0x10 +#define DMA_IRQ_STAT_OFFSET_A733 0x138 #define DMA_IRQ_CHAN_NR_A31 8 +#define DMA_IRQ_CHAN_NR_A733 1 /* * Channels specific registers @@ -107,6 +111,8 @@ */ #define SRC_HIGH_ADDR_MASK GENMASK(17, 16) #define DST_HIGH_ADDR_MASK GENMASK(19, 18) +#define SRC_HIGH_ADDR_32G_MASK GENMASK(13, 11) +#define DST_HIGH_ADDR_32G_MASK GENMASK(17, 15) /* * Various hardware related defines @@ -1314,6 +1320,32 @@ static struct sun6i_dma_config sun50i_h6_dma_cfg = { SUN6I_DMA_IRQ_A31_COMMON_CFG }; +/* + * The A733 binding uses the number of dma channels from the + * device tree node. + */ +static struct sun6i_dma_config sun60i_a733_dma_cfg = { + .clock_autogate_enable = sun6i_enable_clock_autogate_h3, + .set_burst_length = sun6i_set_burst_length_h3, + .set_drq = sun6i_set_drq_h6, + .set_mode = sun6i_set_mode_h6, + .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), + .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), + .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + .src_high_addr_mask = SRC_HIGH_ADDR_32G_MASK, + .dst_high_addr_mask = DST_HIGH_ADDR_32G_MASK, + .has_mbus_clk = true, + .irq_stride = DMA_IRQ_STRIDE_A733, + .irq_en_offset = DMA_IRQ_EN_OFFSET_A733, + .irq_stat_offset = DMA_IRQ_STAT_OFFSET_A733, + .num_channels_per_reg = DMA_IRQ_CHAN_NR_A733, +}; + /* * The V3s have only 8 physical channels, a maximum DRQ port id of 23, * and a total of 24 usable source and destination endpoints. @@ -1348,6 +1380,7 @@ static const struct of_device_id sun6i_dma_match[] = { { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg }, { .compatible = "allwinner,sun50i-a100-dma", .data = &sun50i_a100_dma_cfg }, { .compatible = "allwinner,sun50i-h6-dma", .data = &sun50i_h6_dma_cfg }, + { .compatible = "allwinner,sun60i-a733-dma", .data = &sun60i_a733_dma_cfg }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sun6i_dma_match); From 3cee6f79553202d7d3954555560ac38d719344b8 Mon Sep 17 00:00:00 2001 From: Vishnu Santhosh Date: Fri, 17 Jul 2026 10:30:28 +0530 Subject: [PATCH 077/149] dmaengine: qcom: bam_dma: Defer IRQ trigger type to device tree The driver hardcodes IRQF_TRIGGER_HIGH when registering the BAM interrupt, which overrides the trigger type specified in the device tree. On Qualcomm Shikra SoC, the A2 BAM signals an edge interrupt to the apps processor; registering it as level-high causes the interrupt to not fire, resulting in missed DMA completions. Use IRQF_TRIGGER_NONE instead, which causes the kernel to use the trigger type already configured by platform_get_irq() when it parsed the device tree interrupts property. This makes the driver platform-agnostic. Fixes: e7c0fe2a5c84 ("dmaengine: add Qualcomm BAM dma driver") Co-developed-by: Deepak Kumar Singh Signed-off-by: Deepak Kumar Singh Signed-off-by: Vishnu Santhosh Reviewed-by: Frank Li Link: https://patch.msgid.link/20260717-qcom-bam-dma-irq-trigger-v1-1-6405eac86f00@oss.qualcomm.com Signed-off-by: Vinod Koul --- drivers/dma/qcom/bam_dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c index 05a3b1f9e0c2..94cb957d4b18 100644 --- a/drivers/dma/qcom/bam_dma.c +++ b/drivers/dma/qcom/bam_dma.c @@ -1333,7 +1333,7 @@ static int bam_dma_probe(struct platform_device *pdev) bam_channel_init(bdev, &bdev->channels[i], i); ret = devm_request_irq(bdev->dev, bdev->irq, bam_dma_irq, - IRQF_TRIGGER_HIGH, "bam_dma", bdev); + IRQF_TRIGGER_NONE, "bam_dma", bdev); if (ret) goto err_bam_channel_exit; From f9587f7906ffca0d6bbee01a887079274adf3269 Mon Sep 17 00:00:00 2001 From: Jyothi Kumar Seerapu Date: Tue, 1 Sep 2026 13:10:59 +0530 Subject: [PATCH 078/149] dt-bindings: dma: qcom,gpi: Document GPI DMA engine for Maili Document the GPI DMA engine on the Maili platform. Signed-off-by: Jyothi Kumar Seerapu Acked-by: Mukesh Kumar Savaliya Acked-by: Krzysztof Kozlowski Reviewed-by: Frank Li Link: https://patch.msgid.link/20260901-maili_gpi_binding-v2-1-c10dd2324a09@oss.qualcomm.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml index 54dca623223d..dfc4a3054b5d 100644 --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -28,6 +28,7 @@ properties: - qcom,glymur-gpi-dma - qcom,hawi-gpi-dma - qcom,kaanapali-gpi-dma + - qcom,maili-gpi-dma - qcom,milos-gpi-dma - qcom,qcm2290-gpi-dma - qcom,qcs8300-gpi-dma From bdfd76514bd11301f4e67d150485ab696c26d83d Mon Sep 17 00:00:00 2001 From: Logan Gunthorpe Date: Wed, 2 Sep 2026 00:21:43 -0600 Subject: [PATCH 079/149] dmaengine: switchtec-dma: fix double-free in switchtec_dma_free_desc() switchtec_dma_free_desc() frees swdma_chan->hw_sq, hw_cq, and every desc_ring[] entry without clearing the pointers afterward. If switchtec_dma_alloc_chan_resources() fails partway through and calls it during unwind, then a later retry of alloc_chan_resources() fails in switchtec_dma_alloc_desc() before reallocating one of those pointers, its own failure path calls switchtec_dma_free_desc() again and frees the same, already-freed pointers a second time. NULL out each pointer as it's freed so a subsequent call is a no-op for anything already released. Fixes: 30eba9df76ad ("dmaengine: switchtec-dma: Implement hardware initialization and cleanup") Reviewed-by: Frank Li Signed-off-by: Logan Gunthorpe Link: https://patch.msgid.link/20260902062153.31048-2-logang@deltatee.com Signed-off-by: Vinod Koul --- drivers/dma/switchtec_dma.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/dma/switchtec_dma.c b/drivers/dma/switchtec_dma.c index 4cc80752f5b6..c1c124f1da18 100644 --- a/drivers/dma/switchtec_dma.c +++ b/drivers/dma/switchtec_dma.c @@ -886,14 +886,18 @@ static void switchtec_dma_free_desc(struct switchtec_dma_chan *swdma_chan) if (swdma_chan->hw_sq) dma_free_coherent(swdma_dev->dma_dev.dev, size, swdma_chan->hw_sq, swdma_chan->dma_addr_sq); + swdma_chan->hw_sq = NULL; size = SWITCHTEC_DMA_CQ_SIZE * sizeof(*swdma_chan->hw_cq); if (swdma_chan->hw_cq) dma_free_coherent(swdma_dev->dma_dev.dev, size, swdma_chan->hw_cq, swdma_chan->dma_addr_cq); + swdma_chan->hw_cq = NULL; - for (i = 0; i < SWITCHTEC_DMA_RING_SIZE; i++) + for (i = 0; i < SWITCHTEC_DMA_RING_SIZE; i++) { kfree(swdma_chan->desc_ring[i]); + swdma_chan->desc_ring[i] = NULL; + } } static int switchtec_dma_alloc_desc(struct switchtec_dma_chan *swdma_chan) From 1188942d6160b9f799af297bdb5d7812cd7fde6d Mon Sep 17 00:00:00 2001 From: Logan Gunthorpe Date: Wed, 2 Sep 2026 00:21:44 -0600 Subject: [PATCH 080/149] dmaengine: switchtec-dma: fix resource leak in alloc_chan_resources switchtec_dma_alloc_chan_resources() returns directly on any later failure, without ever freeing the descriptor rings and coherent DMA memory it just allocated. The dmaengine core does not call device_free_chan_resources() when device_alloc_chan_resources() fails, so the driver has to unwind its own partial state. The device-removed check also runs after ring_active and comp_ring_active have already been set true, so a failure there left the channel marked active despite alloc_chan_resources() reporting failure. Add an error-unwind path that disables the channel and frees the descriptor rings on every failure after allocation. ring_active and comp_ring_active are cleared under the same locks switchtec_dma_free_chan_resources() already uses, since the completion tasklet checks comp_ring_active under complete_lock before touching the completion ring, and a stale IRQ can still be in flight when this unwind path runs. Reported-by: Sashiko Link: https://lore.kernel.org/dmaengine/20260707165555.350951F000E9@smtp.kernel.org Fixes: 30eba9df76ad ("dmaengine: switchtec-dma: Implement hardware initialization and cleanup") Reviewed-by: Frank Li Signed-off-by: Logan Gunthorpe Link: https://lore.kernel.org/dmaengine/20260707165555.350951F000E9@smtp.kernel.org/T/#u Link: https://patch.msgid.link/20260902062153.31048-3-logang@deltatee.com Signed-off-by: Vinod Koul --- drivers/dma/switchtec_dma.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/dma/switchtec_dma.c b/drivers/dma/switchtec_dma.c index c1c124f1da18..32972667f4d6 100644 --- a/drivers/dma/switchtec_dma.c +++ b/drivers/dma/switchtec_dma.c @@ -988,15 +988,15 @@ static int switchtec_dma_alloc_chan_resources(struct dma_chan *chan) rc = enable_channel(swdma_chan); if (rc) - return rc; + goto err_free_desc; rc = reset_channel(swdma_chan); if (rc) - return rc; + goto err_disable_channel; rc = unhalt_channel(swdma_chan); if (rc) - return rc; + goto err_disable_channel; swdma_chan->ring_active = true; swdma_chan->comp_ring_active = true; @@ -1007,7 +1007,8 @@ static int switchtec_dma_alloc_chan_resources(struct dma_chan *chan) rcu_read_lock(); if (!rcu_dereference(swdma_dev->pdev)) { rcu_read_unlock(); - return -ENODEV; + rc = -ENODEV; + goto err_ring_inactive; } perf_cfg = readl(&swdma_chan->mmio_chan_fw->perf_cfg); @@ -1029,6 +1030,20 @@ static int switchtec_dma_alloc_chan_resources(struct dma_chan *chan) FIELD_GET(PERF_MRRS_MASK, perf_cfg)); return SWITCHTEC_DMA_SQ_SIZE; + +err_ring_inactive: + spin_lock_bh(&swdma_chan->submit_lock); + swdma_chan->ring_active = false; + spin_unlock_bh(&swdma_chan->submit_lock); + + spin_lock_bh(&swdma_chan->complete_lock); + swdma_chan->comp_ring_active = false; + spin_unlock_bh(&swdma_chan->complete_lock); +err_disable_channel: + disable_channel(swdma_chan); +err_free_desc: + switchtec_dma_free_desc(swdma_chan); + return rc; } static void switchtec_dma_free_chan_resources(struct dma_chan *chan) From fd39726ab7096840cc9c9dea6dfba23834fc81f0 Mon Sep 17 00:00:00 2001 From: Logan Gunthorpe Date: Wed, 2 Sep 2026 00:21:45 -0600 Subject: [PATCH 081/149] dmaengine: switchtec-dma: fix channel leak on registration failure switchtec_dma_chans_release() is called in three places but the underlying memory is not freed in all of those places. In order to clean this up, introduce a switchtec_dma_chans_free() helper that will free the memory. Ensure each call to switchtec_dma_chans_release() has a corresponding switchtec_dma_chans_free() call. (The release in switchtec_dma_remove() pairs with the free in switchtec_dma_release()). swdma_dev->chan_cnt is now set to the number of channels that succeeded when one fails to initialise, so switchtec_dma_chans_free() can still be used if not all channels succeed in being allocated. switchtec_dma_chans_free() also removes each channel from dma_dev->channels before freeing it, since the channel status ISR walks that list and would otherwise dereference freed memory. Fixes: 30eba9df76ad ("dmaengine: switchtec-dma: Implement hardware initialization and cleanup") Reported-by: Sashiko Link: https://lore.kernel.org/dmaengine/20260717223024.9BB8A1F000E9@smtp.kernel.org Link: https://lore.kernel.org/dmaengine/20260727190604.397DB1F000E9@smtp.kernel.org Reviewed-by: Frank Li Signed-off-by: Logan Gunthorpe Link: https://patch.msgid.link/20260902062153.31048-4-logang@deltatee.com Signed-off-by: Vinod Koul --- drivers/dma/switchtec_dma.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/dma/switchtec_dma.c b/drivers/dma/switchtec_dma.c index 32972667f4d6..6c653265d786 100644 --- a/drivers/dma/switchtec_dma.c +++ b/drivers/dma/switchtec_dma.c @@ -1175,6 +1175,18 @@ static int switchtec_dma_chans_release(struct pci_dev *pdev, return 0; } +static void switchtec_dma_chans_free(struct switchtec_dma_dev *swdma_dev) +{ + int i; + + for (i = 0; i < swdma_dev->chan_cnt; i++) { + list_del(&swdma_dev->swdma_chans[i]->dma_chan.device_node); + kfree(swdma_dev->swdma_chans[i]); + } + + kfree(swdma_dev->swdma_chans); +} + static int switchtec_dma_chans_enumerate(struct switchtec_dma_dev *swdma_dev, struct pci_dev *pdev, int chan_cnt) { @@ -1200,7 +1212,7 @@ static int switchtec_dma_chans_enumerate(struct switchtec_dma_dev *swdma_dev, if (rc) { dev_err(&pdev->dev, "Channel %d: init channel failed\n", i); - chan_cnt = i; + swdma_dev->chan_cnt = i; goto err_exit; } } @@ -1208,10 +1220,8 @@ static int switchtec_dma_chans_enumerate(struct switchtec_dma_dev *swdma_dev, return chan_cnt; err_exit: - for (i = 0; i < chan_cnt; i++) - switchtec_dma_chan_free(pdev, swdma_dev->swdma_chans[i]); - - kfree(swdma_dev->swdma_chans); + switchtec_dma_chans_release(pdev, swdma_dev); + switchtec_dma_chans_free(swdma_dev); return rc; } @@ -1220,12 +1230,8 @@ static void switchtec_dma_release(struct dma_device *dma_dev) { struct switchtec_dma_dev *swdma_dev = container_of(dma_dev, struct switchtec_dma_dev, dma_dev); - int i; - for (i = 0; i < swdma_dev->chan_cnt; i++) - kfree(swdma_dev->swdma_chans[i]); - - kfree(swdma_dev->swdma_chans); + switchtec_dma_chans_free(swdma_dev); put_device(dma_dev->dev); kfree(swdma_dev); @@ -1316,6 +1322,7 @@ static int switchtec_dma_create(struct pci_dev *pdev) err_chans_release_exit: switchtec_dma_chans_release(pdev, swdma_dev); + switchtec_dma_chans_free(swdma_dev); err_exit: if (swdma_dev->chan_status_irq) From 50bf400915d308b80729bae8c6c85f001d7b7295 Mon Sep 17 00:00:00 2001 From: Logan Gunthorpe Date: Wed, 2 Sep 2026 00:21:46 -0600 Subject: [PATCH 082/149] dmaengine: switchtec-dma: make switchtec_dma_chans_release() void switchtec_dma_chans_release() always returned 0, and no caller checked it. Reviewed-by: Frank Li Signed-off-by: Logan Gunthorpe Link: https://patch.msgid.link/20260902062153.31048-5-logang@deltatee.com Signed-off-by: Vinod Koul --- drivers/dma/switchtec_dma.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/dma/switchtec_dma.c b/drivers/dma/switchtec_dma.c index 6c653265d786..89c8c20fed1f 100644 --- a/drivers/dma/switchtec_dma.c +++ b/drivers/dma/switchtec_dma.c @@ -1164,15 +1164,13 @@ static int switchtec_dma_chan_free(struct pci_dev *pdev, return 0; } -static int switchtec_dma_chans_release(struct pci_dev *pdev, - struct switchtec_dma_dev *swdma_dev) +static void switchtec_dma_chans_release(struct pci_dev *pdev, + struct switchtec_dma_dev *swdma_dev) { int i; for (i = 0; i < swdma_dev->chan_cnt; i++) switchtec_dma_chan_free(pdev, swdma_dev->swdma_chans[i]); - - return 0; } static void switchtec_dma_chans_free(struct switchtec_dma_dev *swdma_dev) From 268f9159ebf38a7ed134e5008e705d8ff99e1c20 Mon Sep 17 00:00:00 2001 From: Logan Gunthorpe Date: Wed, 2 Sep 2026 00:21:47 -0600 Subject: [PATCH 083/149] dmaengine: switchtec-dma: fix chan_status_irq cleanup on create() error chan_status_irq stores an MSI-X vector index, but err_exit freed it with plain free_irq() instead of pci_free_irq(), which would free the wrong Linux IRQ. The guard also treated a valid vector index of 0 as unset, skipping the free entirely in that case and leaving the handler registered against soon-to-be-freed swdma_dev. Initialize chan_status_irq to -1 and use the value being non-negative to signal when to free it with pci_free_irq(). Reported-by: Sashiko Link: https://lore.kernel.org/dmaengine/20260717223431.625EE1F000E9@smtp.kernel.org Reviewed-by: Frank Li Signed-off-by: Logan Gunthorpe Link: https://patch.msgid.link/20260902062153.31048-6-logang@deltatee.com Signed-off-by: Vinod Koul --- drivers/dma/switchtec_dma.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/dma/switchtec_dma.c b/drivers/dma/switchtec_dma.c index 89c8c20fed1f..fb0bb1301e2d 100644 --- a/drivers/dma/switchtec_dma.c +++ b/drivers/dma/switchtec_dma.c @@ -1249,6 +1249,8 @@ static int switchtec_dma_create(struct pci_dev *pdev) if (!swdma_dev) return -ENOMEM; + swdma_dev->chan_status_irq = -1; + swdma_dev->bar = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0)); @@ -1323,8 +1325,8 @@ static int switchtec_dma_create(struct pci_dev *pdev) switchtec_dma_chans_free(swdma_dev); err_exit: - if (swdma_dev->chan_status_irq) - free_irq(swdma_dev->chan_status_irq, swdma_dev); + if (swdma_dev->chan_status_irq >= 0) + pci_free_irq(pdev, swdma_dev->chan_status_irq, swdma_dev); iounmap(swdma_dev->bar); kfree(swdma_dev); From 5b4c561554b2f802a4e3db539ba2c586b72b7721 Mon Sep 17 00:00:00 2001 From: Logan Gunthorpe Date: Wed, 2 Sep 2026 00:21:48 -0600 Subject: [PATCH 084/149] dmaengine: switchtec-dma: disable channels before freeing on registration failure When switchtec_dma_create() fails after channels have been added to dma_dev->channels (either from switchtec_dma_chans_enumerate()'s own error path, or from dma_async_device_register() failing), the channel status IRQ is still live while the channels are released and freed, so it can fire mid-teardown against channels that are only partially torn down. Add switchtec_dma_chans_disable(), which frees the channel status IRQ before releasing and freeing channels in both error paths. Reported-by: Sashiko Link: https://lore.kernel.org/dmaengine/20260717223431.625EE1F000E9@smtp.kernel.org Link: https://lore.kernel.org/dmaengine/20260721162822.05CDD1F000E9@smtp.kernel.org Reviewed-by: Frank Li Signed-off-by: Logan Gunthorpe Link: https://patch.msgid.link/20260902062153.31048-7-logang@deltatee.com Signed-off-by: Vinod Koul --- drivers/dma/switchtec_dma.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/dma/switchtec_dma.c b/drivers/dma/switchtec_dma.c index fb0bb1301e2d..0ae930de47c8 100644 --- a/drivers/dma/switchtec_dma.c +++ b/drivers/dma/switchtec_dma.c @@ -1185,6 +1185,15 @@ static void switchtec_dma_chans_free(struct switchtec_dma_dev *swdma_dev) kfree(swdma_dev->swdma_chans); } +static void switchtec_dma_chans_disable(struct pci_dev *pdev, + struct switchtec_dma_dev *swdma_dev) +{ + if (swdma_dev->chan_status_irq >= 0) { + pci_free_irq(pdev, swdma_dev->chan_status_irq, swdma_dev); + swdma_dev->chan_status_irq = -1; + } +} + static int switchtec_dma_chans_enumerate(struct switchtec_dma_dev *swdma_dev, struct pci_dev *pdev, int chan_cnt) { @@ -1218,6 +1227,7 @@ static int switchtec_dma_chans_enumerate(struct switchtec_dma_dev *swdma_dev, return chan_cnt; err_exit: + switchtec_dma_chans_disable(pdev, swdma_dev); switchtec_dma_chans_release(pdev, swdma_dev); switchtec_dma_chans_free(swdma_dev); @@ -1321,6 +1331,7 @@ static int switchtec_dma_create(struct pci_dev *pdev) return 0; err_chans_release_exit: + switchtec_dma_chans_disable(pdev, swdma_dev); switchtec_dma_chans_release(pdev, swdma_dev); switchtec_dma_chans_free(swdma_dev); From 9f744689c49defa61238836829202d1473da2ea5 Mon Sep 17 00:00:00 2001 From: Logan Gunthorpe Date: Wed, 2 Sep 2026 00:21:49 -0600 Subject: [PATCH 085/149] dmaengine: switchtec-dma: fix use-after-free of swdma_dev in remove() dma_async_device_unregister() can drop the last reference on dma_dev and free swdma_dev synchronously via switchtec_dma_release(), but switchtec_dma_remove() then uses swdma_dev->bar for iounmap(). Cache bar in a local variable before the unregister call. Reported-by: Sashiko Link: https://lore.kernel.org/dmaengine/20260717223431.625EE1F000E9@smtp.kernel.org Reviewed-by: Frank Li Signed-off-by: Logan Gunthorpe Link: https://patch.msgid.link/20260902062153.31048-8-logang@deltatee.com Signed-off-by: Vinod Koul --- drivers/dma/switchtec_dma.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/dma/switchtec_dma.c b/drivers/dma/switchtec_dma.c index 0ae930de47c8..ddcb6d84bdc6 100644 --- a/drivers/dma/switchtec_dma.c +++ b/drivers/dma/switchtec_dma.c @@ -1380,6 +1380,7 @@ static int switchtec_dma_probe(struct pci_dev *pdev, static void switchtec_dma_remove(struct pci_dev *pdev) { struct switchtec_dma_dev *swdma_dev = pci_get_drvdata(pdev); + void __iomem *bar = swdma_dev->bar; switchtec_dma_chans_release(pdev, swdma_dev); @@ -1392,7 +1393,7 @@ static void switchtec_dma_remove(struct pci_dev *pdev) dma_async_device_unregister(&swdma_dev->dma_dev); - iounmap(swdma_dev->bar); + iounmap(bar); pci_release_mem_regions(pdev); pci_disable_device(pdev); } From 10d34fbca6e09a6a18d64fa3ebaa3db9f27fc1a6 Mon Sep 17 00:00:00 2001 From: Logan Gunthorpe Date: Wed, 2 Sep 2026 00:21:50 -0600 Subject: [PATCH 086/149] dmaengine: ioat: disable relaxed ordering before registering the device ioat3_dma_probe() disabled PCIe relaxed ordering after calling dma_async_device_register(), so if an error occurs and the code jumps to err_disable_interrupts, the function returns with the device still registered in the core's dma_device_list while the caller frees the ioatdma_device struct, leaving a dangling registration that anything walking the device list can dereference after it's been freed. Move the capability read/write ahead of dma_async_device_register() instead. Nothing after registration depends on relaxed ordering already being disabled, and nothing before it depends on the device being registered, so this is a plain reordering. It also means every remaining step after registration can't fail, so there's no need to ever have to unregister the device once registered. Fixes: 511deae0261c ("dmaengine: ioatdma: disable relaxed ordering for ioatdma") Reported-by: Sashiko Link: https://lore.kernel.org/dmaengine/20260707165906.249F41F000E9@smtp.kernel.org Acked-by: Dave Jiang Reviewed-by: Frank Li Signed-off-by: Logan Gunthorpe Link: https://lore.kernel.org/dmaengine/20260707165906.249F41F000E9@smtp.kernel.org/T/#u Link: https://patch.msgid.link/20260902062153.31048-9-logang@deltatee.com Signed-off-by: Vinod Koul --- drivers/dma/ioat/init.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/dma/ioat/init.c b/drivers/dma/ioat/init.c index 737496391109..a57024c4b066 100644 --- a/drivers/dma/ioat/init.c +++ b/drivers/dma/ioat/init.c @@ -1170,15 +1170,6 @@ static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca) ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); } - err = dma_async_device_register(&ioat_dma->dma_dev); - if (err) - goto err_disable_interrupts; - - ioat_kobject_add(ioat_dma, &ioat_ktype); - - if (dca) - ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base); - /* disable relaxed ordering */ err = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &val16); if (err) { @@ -1194,6 +1185,15 @@ static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca) goto err_disable_interrupts; } + err = dma_async_device_register(&ioat_dma->dma_dev); + if (err) + goto err_disable_interrupts; + + ioat_kobject_add(ioat_dma, &ioat_ktype); + + if (dca) + ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base); + if (ioat_dma->cap & IOAT_CAP_DPS) writeb(ioat_pending_level + 1, ioat_dma->reg_base + IOAT_PREFETCH_LIMIT_OFFSET); From c691357acf76037b8a58ee4eb0ae07cd708a8ba1 Mon Sep 17 00:00:00 2001 From: Logan Gunthorpe Date: Wed, 2 Sep 2026 00:21:51 -0600 Subject: [PATCH 087/149] dmaengine: ioat: use sysfs_emit() in per-channel sysfs show() Convert the sprintf() calls in the per-channel sysfs attribute show() functions to sysfs_emit(). Acked-by: Dave Jiang Reviewed-by: Frank Li Signed-off-by: Logan Gunthorpe Link: https://patch.msgid.link/20260902062153.31048-10-logang@deltatee.com Signed-off-by: Vinod Koul --- drivers/dma/ioat/sysfs.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/dma/ioat/sysfs.c b/drivers/dma/ioat/sysfs.c index e796ddb5383f..976134df8108 100644 --- a/drivers/dma/ioat/sysfs.c +++ b/drivers/dma/ioat/sysfs.c @@ -24,12 +24,12 @@ static ssize_t cap_show(struct dma_chan *c, char *page) { struct dma_device *dma = c->device; - return sprintf(page, "copy%s%s%s%s%s\n", - dma_has_cap(DMA_PQ, dma->cap_mask) ? " pq" : "", - dma_has_cap(DMA_PQ_VAL, dma->cap_mask) ? " pq_val" : "", - dma_has_cap(DMA_XOR, dma->cap_mask) ? " xor" : "", - dma_has_cap(DMA_XOR_VAL, dma->cap_mask) ? " xor_val" : "", - dma_has_cap(DMA_INTERRUPT, dma->cap_mask) ? " intr" : ""); + return sysfs_emit(page, "copy%s%s%s%s%s\n", + dma_has_cap(DMA_PQ, dma->cap_mask) ? " pq" : "", + dma_has_cap(DMA_PQ_VAL, dma->cap_mask) ? " pq_val" : "", + dma_has_cap(DMA_XOR, dma->cap_mask) ? " xor" : "", + dma_has_cap(DMA_XOR_VAL, dma->cap_mask) ? " xor_val" : "", + dma_has_cap(DMA_INTERRUPT, dma->cap_mask) ? " intr" : ""); } static const struct ioat_sysfs_entry ioat_cap_attr = __ATTR_RO(cap); @@ -39,8 +39,8 @@ static ssize_t version_show(struct dma_chan *c, char *page) struct dma_device *dma = c->device; struct ioatdma_device *ioat_dma = to_ioatdma_device(dma); - return sprintf(page, "%d.%d\n", - ioat_dma->version >> 4, ioat_dma->version & 0xf); + return sysfs_emit(page, "%d.%d\n", + ioat_dma->version >> 4, ioat_dma->version & 0xf); } static const struct ioat_sysfs_entry ioat_version_attr = __ATTR_RO(version); @@ -118,7 +118,7 @@ static ssize_t ring_size_show(struct dma_chan *c, char *page) { struct ioatdma_chan *ioat_chan = to_ioat_chan(c); - return sprintf(page, "%d\n", (1 << ioat_chan->alloc_order) & ~1); + return sysfs_emit(page, "%d\n", (1 << ioat_chan->alloc_order) & ~1); } static const struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size); @@ -127,7 +127,7 @@ static ssize_t ring_active_show(struct dma_chan *c, char *page) struct ioatdma_chan *ioat_chan = to_ioat_chan(c); /* ...taken outside the lock, no need to be precise */ - return sprintf(page, "%d\n", ioat_ring_active(ioat_chan)); + return sysfs_emit(page, "%d\n", ioat_ring_active(ioat_chan)); } static const struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active); @@ -135,7 +135,7 @@ static ssize_t intr_coalesce_show(struct dma_chan *c, char *page) { struct ioatdma_chan *ioat_chan = to_ioat_chan(c); - return sprintf(page, "%d\n", ioat_chan->intr_coalesce); + return sysfs_emit(page, "%d\n", ioat_chan->intr_coalesce); } static ssize_t intr_coalesce_store(struct dma_chan *c, const char *page, From f3017892457d8bb664ea4b912910dc254e2dd825 Mon Sep 17 00:00:00 2001 From: Logan Gunthorpe Date: Wed, 2 Sep 2026 00:21:52 -0600 Subject: [PATCH 088/149] dmaengine: plx_dma: fix NULL pointer deref in plx_dma_isr() plx_dma_create() registered the interrupt handler with request_irq() before initializing plxdev->bar. If the device raised an interrupt in that window, plx_dma_isr() would dereference the still-NULL bar. Move the bar assignment ahead of request_irq() so everything the handler can touch is initialized before it can run. Reported-by: Sangyun Kim Reported-by: Kyungwook Boo Link: https://lore.kernel.org/all/20260610112121.676561-1-jjy600901@snu.ac.kr Fixes: c2dbcaa8c672 ("dmaengine: plx-dma: Implement hardware initialization and cleanup") Reviewed-by: Frank Li Signed-off-by: Logan Gunthorpe Link: https://lore.kernel.org/all/20260610112121.676561-1-jjy600901@snu.ac.kr/T/#u Link: https://patch.msgid.link/20260902062153.31048-11-logang@deltatee.com Signed-off-by: Vinod Koul --- drivers/dma/plx_dma.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/dma/plx_dma.c b/drivers/dma/plx_dma.c index 84941a918b01..409898e92c32 100644 --- a/drivers/dma/plx_dma.c +++ b/drivers/dma/plx_dma.c @@ -504,17 +504,17 @@ static int plx_dma_create(struct pci_dev *pdev) if (!plxdev) return -ENOMEM; - rc = request_irq(pci_irq_vector(pdev, 0), plx_dma_isr, 0, - KBUILD_MODNAME, plxdev); - if (rc) - goto free_plx; - spin_lock_init(&plxdev->ring_lock); tasklet_setup(&plxdev->desc_task, plx_dma_desc_task); RCU_INIT_POINTER(plxdev->pdev, pdev); plxdev->bar = pcim_iomap_table(pdev)[0]; + rc = request_irq(pci_irq_vector(pdev, 0), plx_dma_isr, 0, + KBUILD_MODNAME, plxdev); + if (rc) + goto free_plx; + dma = &plxdev->dma_dev; INIT_LIST_HEAD(&dma->channels); dma_cap_set(DMA_MEMCPY, dma->cap_mask); From 9d79e5efaf7b908fd3eea1a6afb34fc06dfa1d7e Mon Sep 17 00:00:00 2001 From: Xianwei Zhao Date: Thu, 3 Sep 2026 07:38:28 +0000 Subject: [PATCH 089/149] dt-bindings: dma: Add Amlogic A9 SoC DMA Add documentation describing the Amlogic A9 SoC DMA. And add the properties specific values defines into a new include file. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Xianwei Zhao Link: https://patch.msgid.link/20260903-amlogic-dma-v12-1-f769bc344056@amlogic.com Signed-off-by: Vinod Koul --- .../bindings/dma/amlogic,a9-dma.yaml | 68 +++++++++++++++++++ include/dt-bindings/dma/amlogic,a9-dma.h | 8 +++ 2 files changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/amlogic,a9-dma.yaml create mode 100644 include/dt-bindings/dma/amlogic,a9-dma.h diff --git a/Documentation/devicetree/bindings/dma/amlogic,a9-dma.yaml b/Documentation/devicetree/bindings/dma/amlogic,a9-dma.yaml new file mode 100644 index 000000000000..3e1a4fba3047 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/amlogic,a9-dma.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/amlogic,a9-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic general DMA controller + +description: + This is a general-purpose peripheral DMA controller. It currently supports + major peripherals including I2C, I3C, PIO, and CAN-BUS. Transmit and receive + for the same peripheral use two separate channels, controlled by different + register sets. I2C and I3C transfer data in 1-byte units, while PIO and + CAN-BUS transfer data in 4-byte units. From the controller’s perspective, + there is no significant difference. + +maintainers: + - Xianwei Zhao + +properties: + compatible: + const: amlogic,a9-dma + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: sys + + '#dma-cells': + const: 2 + description: + The first cell is the DMA channel type(AMLOGIC_A9_DMA_TX or AMLOGIC_A9_DMA_RX). + The second cell is the DMA channel index. + + dma-channels: + maximum: 64 + +required: + - compatible + - reg + - interrupts + - clocks + - '#dma-cells' + - dma-channels + +allOf: + - $ref: dma-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + dma-controller@fe400000 { + compatible = "amlogic,a9-dma"; + reg = <0xfe400000 0x4000>; + interrupts = ; + clocks = <&clkc 45>; + #dma-cells = <2>; + dma-channels = <28>; + }; diff --git a/include/dt-bindings/dma/amlogic,a9-dma.h b/include/dt-bindings/dma/amlogic,a9-dma.h new file mode 100644 index 000000000000..ea7c90063572 --- /dev/null +++ b/include/dt-bindings/dma/amlogic,a9-dma.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ + +#ifndef __DT_BINDINGS_DMA_AMLOGIC_DMA_H__ +#define __DT_BINDINGS_DMA_AMLOGIC_DMA_H__ + +#define AMLOGIC_A9_DMA_TX 0 +#define AMLOGIC_A9_DMA_RX 1 +#endif /* __DT_BINDINGS_DMA_AMLOGIC_DMA_H__ */ From b84b5197e344e2d378a9edf5d782b6fbddff8d06 Mon Sep 17 00:00:00 2001 From: Xianwei Zhao Date: Thu, 3 Sep 2026 07:38:29 +0000 Subject: [PATCH 090/149] dmaengine: amlogic: Add general DMA driver for A9 Amlogic A9 SoCs include a general-purpose DMA controller that can be used by multiple peripherals, such as I2C PIO and I3C. Each peripheral group is associated with a dedicated DMA channel in hardware. Reviewed-by: Frank Li Signed-off-by: Xianwei Zhao Link: https://patch.msgid.link/20260903-amlogic-dma-v12-2-f769bc344056@amlogic.com Signed-off-by: Vinod Koul --- drivers/dma/Kconfig | 10 + drivers/dma/Makefile | 1 + drivers/dma/amlogic-dma.c | 737 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 748 insertions(+) create mode 100644 drivers/dma/amlogic-dma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index ae6a682c9f76..01f96a8257e5 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -85,6 +85,16 @@ config AMCC_PPC440SPE_ADMA help Enable support for the AMCC PPC440SPe RAID engines. +config AMLOGIC_DMA + tristate "Amlogic general DMA support" + depends on ARCH_MESON || COMPILE_TEST + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + select REGMAP_MMIO + help + Enable support for the Amlogic general DMA engines. THis DMA + controller is used some Amlogic SoCs, such as A9. + config APPLE_ADMAC tristate "Apple ADMAC support" depends on ARCH_APPLE || COMPILE_TEST diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 14aa086629d5..f62d12b08e15 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_DMATEST) += dmatest.o obj-$(CONFIG_ALTERA_MSGDMA) += altera-msgdma.o obj-$(CONFIG_AMBA_PL08X) += amba-pl08x.o obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc4xx/ +obj-$(CONFIG_AMLOGIC_DMA) += amlogic-dma.o obj-$(CONFIG_APPLE_ADMAC) += apple-admac.o obj-$(CONFIG_ARM_DMA350) += arm-dma350.o obj-$(CONFIG_AT_HDMAC) += at_hdmac.o diff --git a/drivers/dma/amlogic-dma.c b/drivers/dma/amlogic-dma.c new file mode 100644 index 000000000000..78ee2337ae71 --- /dev/null +++ b/drivers/dma/amlogic-dma.c @@ -0,0 +1,737 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright (C) 2026 Amlogic, Inc. All rights reserved + * Author: Xianwei Zhao + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "virt-dma.h" + +#define RCH_REG_BASE 0x0 +#define WCH_REG_BASE 0x2000 +/* + * Each rch (read from memory) REG offset Rch_offset 0x0 each channel total 0x40 + * rch addr = DMA_base + Rch_offset+ chan_id * 0x40 + reg_offset + */ +#define RCH_READY 0x0 +#define RCH_STATUS 0x4 +#define RCH_CFG 0x8 +#define CFG_CLEAR BIT(25) +#define CFG_PAUSE BIT(26) +#define CFG_ENABLE BIT(27) +#define CFG_DONE BIT(28) +#define RCH_ADDR 0xc +#define RCH_LEN 0x10 +#define RCH_RD_LEN 0x14 +#define RCH_PRT 0x18 +#define RCH_SYCN_STAT 0x1c +#define RCH_ADDR_LOW 0x20 +#define RCH_ADDR_HIGH 0x24 +/* if work on 64, it work with RCH_PRT */ +#define RCH_PTR_HIGH 0x28 + +/* + * Each wch (write to memory) REG offset Wch_offset 0x2000 each channel total 0x40 + * wch addr = DMA_base + Wch_offset+ chan_id * 0x40 + reg_offset + */ +#define WCH_READY 0x0 +#define WCH_TOTAL_LEN 0x4 +#define WCH_CFG 0x8 +#define WCH_ADDR 0xc +#define WCH_LEN 0x10 +#define WCH_RD_LEN 0x14 +#define WCH_PRT 0x18 +#define WCH_CMD_CNT 0x1c +#define WCH_ADDR_LOW 0x20 +#define WCH_ADDR_HIGH 0x24 +/* if work on 64, it work with RCH_PRT */ +#define WCH_PTR_HIGH 0x28 + +/* DMA controller reg */ +#define RCH_INT_MASK 0x1000 +#define WCH_INT_MASK 0x1004 +#define CLEAR_W_BATCH 0x1014 +#define CLEAR_RCH 0x1024 +#define CLEAR_WCH 0x1028 +#define RCH_ACTIVE 0x1038 +#define WCH_ACTIVE 0x103c +#define RCH_DONE 0x104c +#define WCH_DONE 0x1050 +#define RCH_ERR 0x1060 +#define RCH_LEN_ERR 0x1064 +#define WCH_ERR 0x1068 +#define DMA_BATCH_END 0x1078 +#define WCH_EOC_DONE 0x1088 +#define WDMA_RESP_ERR 0x1098 +#define UPT_PKT_SYNC 0x10a8 +#define RCHN_CFG 0x10ac +#define WCHN_CFG 0x10b0 +#define MEM_PD_CFG 0x10b4 +#define MEM_BUS_CFG 0x10b8 +#define DMA_GMV_CFG 0x10bc +#define DMA_GMR_CFG 0x10c0 + +#define MAX_CHAN_ID 32 +#define SG_MAX_LEN GENMASK(26, 2) +#define INT_MASK 0xffffffff + +struct aml_dma_sg_link { +#define LINK_LEN GENMASK(26, 0) +#define LINK_IRQ BIT(27) +#define LINK_EOC BIT(28) +#define LINK_LOOP BIT(29) +#define LINK_ERR BIT(30) +#define LINK_OWNER BIT(31) + __le32 ctl; + __le32 addr_low; + __le32 addr_high; + __le32 revered; +} __packed; + +/* 1 page for link 256*16 */ +#define DMA_MAX_LINK 256 +/* sizeof(struct aml_dma_sg_link) */ +#define DMA_LINK_SIZE 16 +#define DMA_LINK_MAX_SIZE (DMA_LINK_SIZE * DMA_MAX_LINK) + +struct aml_dma_desc { + struct virt_dma_desc vd; + struct aml_dma_sg_link *sg_link; + struct dma_device *dma_device; + dma_addr_t sg_link_phys; + size_t sg_link_size; + u32 data_len; + struct work_struct free_work; +}; + +struct aml_dma_chan { + struct virt_dma_chan vchan; + struct aml_dma_dev *aml_dma; + struct aml_dma_desc *cur_desc; + enum dma_status pre_status; + enum dma_status status; + enum dma_transfer_direction direction; + int chan_id; + /* reg_base (direction + chan_id) */ + int reg_offs; + /* When there are multiple consecutive transmission errors, this channel halt */ + int err_num; +}; + +struct aml_dma_dev { + struct dma_device dma_device; + void __iomem *base; + struct regmap *regmap; + struct clk *clk; + int irq; + struct platform_device *pdev; + struct aml_dma_chan *aml_rch[MAX_CHAN_ID]; + struct aml_dma_chan *aml_wch[MAX_CHAN_ID]; + struct workqueue_struct *free_wq; + unsigned int chan_nr; + unsigned int chan_used; + struct aml_dma_chan aml_chans[]__counted_by(chan_nr); +}; + +static inline struct aml_dma_chan *to_aml_dma_chan(struct dma_chan *chan) +{ + return container_of(chan, struct aml_dma_chan, vchan.chan); +} + +static inline struct aml_dma_desc *to_aml_dma_desc(struct virt_dma_desc *vd) +{ + return container_of(vd, struct aml_dma_desc, vd); +} + +static void aml_dma_free_desc_work(struct work_struct *work) +{ + struct aml_dma_desc *aml_desc = + container_of(work, struct aml_dma_desc, free_work); + + dma_free_coherent(aml_desc->dma_device->dev, + aml_desc->sg_link_size, + aml_desc->sg_link, + aml_desc->sg_link_phys); + kfree(aml_desc); +} + +static void aml_dma_free_desc(struct virt_dma_desc *vd) +{ + struct aml_dma_desc *aml_desc = to_aml_dma_desc(vd); + struct aml_dma_dev *aml_dev = container_of(aml_desc->dma_device, + struct aml_dma_dev, dma_device); + + queue_work(aml_dev->free_wq, &aml_desc->free_work); +} + +static int aml_dma_alloc_chan_resources(struct dma_chan *chan) +{ + struct aml_dma_chan *aml_chan = to_aml_dma_chan(chan); + struct aml_dma_dev *aml_dma = aml_chan->aml_dma; + + /* offset is the same RCH_CFG and WCH_CFG */ + regmap_set_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_CLEAR); + regmap_clear_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_PAUSE); + regmap_clear_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_CLEAR); + + aml_chan->status = DMA_COMPLETE; + aml_chan->cur_desc = NULL; + aml_chan->err_num = 0; + + return 0; +} + +static void aml_dma_free_chan_resources(struct dma_chan *chan) +{ + struct aml_dma_chan *aml_chan = to_aml_dma_chan(chan); + struct aml_dma_dev *aml_dma = aml_chan->aml_dma; + struct virt_dma_desc *cur_vd = NULL; + unsigned long flags; + + spin_lock_irqsave(&aml_chan->vchan.lock, flags); + regmap_set_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_PAUSE); + regmap_set_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_CLEAR); + if (aml_chan->cur_desc) + cur_vd = &aml_chan->cur_desc->vd; + aml_chan->cur_desc = NULL; + spin_unlock_irqrestore(&aml_chan->vchan.lock, flags); + if (cur_vd) + aml_dma_free_desc(cur_vd); + + vchan_free_chan_resources(&aml_chan->vchan); +} + +/* DMA transfer state update how many data reside it */ +static enum dma_status aml_dma_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct aml_dma_chan *aml_chan = to_aml_dma_chan(chan); + struct aml_dma_dev *aml_dma = aml_chan->aml_dma; + struct aml_dma_desc *aml_desc = NULL; + struct virt_dma_desc *vd; + u32 residue = 0, done = 0; + unsigned long flags; + enum dma_status ret; + + ret = dma_cookie_status(chan, cookie, txstate); + if (ret == DMA_COMPLETE) + return ret; + + if (aml_chan->status == DMA_PAUSED) + ret = DMA_PAUSED; + if (!txstate) + return ret; + + spin_lock_irqsave(&aml_chan->vchan.lock, flags); + vd = vchan_find_desc(&aml_chan->vchan, cookie); + if (vd) { + aml_desc = to_aml_dma_desc(vd); + residue = aml_desc->data_len; + } else if (aml_chan->cur_desc && aml_chan->cur_desc->vd.tx.cookie == cookie) { + aml_desc = aml_chan->cur_desc; + regmap_read(aml_dma->regmap, aml_chan->reg_offs + RCH_RD_LEN, &done); + residue = aml_desc->data_len - done; + } else { + dev_err(aml_dma->dma_device.dev, "cookie error\n"); + } + spin_unlock_irqrestore(&aml_chan->vchan.lock, flags); + dma_set_residue(txstate, residue); + + return ret; +} + +static struct dma_async_tx_descriptor *aml_dma_prep_slave_sg + (struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sg_len, enum dma_transfer_direction direction, + unsigned long flags, void *context) +{ + struct aml_dma_chan *aml_chan = to_aml_dma_chan(chan); + struct aml_dma_dev *aml_dma = aml_chan->aml_dma; + struct aml_dma_desc *aml_desc = NULL; + struct aml_dma_sg_link *sg_link = NULL; + struct scatterlist *sg = NULL; + u64 paddr; + u32 link_count, avail; + u32 i; + + if (aml_chan->direction != direction) { + dev_err(aml_dma->dma_device.dev, "direction not support\n"); + return NULL; + } + + link_count = sg_nents_for_dma(sgl, sg_len, SG_MAX_LEN); + if (link_count == 0) + return NULL; + + aml_desc = kzalloc_obj(*aml_desc, GFP_NOWAIT); + if (!aml_desc) + return NULL; + + INIT_WORK(&aml_desc->free_work, aml_dma_free_desc_work); + aml_desc->sg_link_size = link_count * sizeof(*sg_link); + aml_desc->sg_link = dma_alloc_coherent(aml_dma->dma_device.dev, aml_desc->sg_link_size, + &aml_desc->sg_link_phys, GFP_NOWAIT); + if (!aml_desc->sg_link) { + kfree(aml_desc); + return NULL; + } + aml_desc->dma_device = &aml_dma->dma_device; + + sg_link = aml_desc->sg_link; + for_each_sg(sgl, sg, sg_len, i) { + avail = sg_dma_len(sg); + if (avail == 0) + continue; + paddr = sg->dma_address; + while (avail > SG_MAX_LEN) { + /* set dma address and len to sglink*/ + sg_link->addr_low = cpu_to_le32(lower_32_bits(paddr)); + sg_link->addr_high = cpu_to_le32(upper_32_bits(paddr)); + sg_link->ctl = cpu_to_le32(FIELD_PREP(LINK_LEN, SG_MAX_LEN)); + paddr = paddr + SG_MAX_LEN; + avail = avail - SG_MAX_LEN; + sg_link++; + } + /* set dma address and len to sglink*/ + sg_link->addr_low = cpu_to_le32(lower_32_bits(paddr)); + sg_link->addr_high = cpu_to_le32(upper_32_bits(paddr)); + sg_link->ctl = cpu_to_le32(FIELD_PREP(LINK_LEN, avail)); + + aml_desc->data_len += sg_dma_len(sg); + sg_link++; + } + + /* the last sg set eoc flag */ + sg_link--; + sg_link->ctl |= LINK_EOC; + + return vchan_tx_prep(&aml_chan->vchan, &aml_desc->vd, flags); +} + +static int aml_dma_chan_pause(struct dma_chan *chan) +{ + struct aml_dma_chan *aml_chan = to_aml_dma_chan(chan); + struct aml_dma_dev *aml_dma = aml_chan->aml_dma; + unsigned long flags; + + spin_lock_irqsave(&aml_chan->vchan.lock, flags); + regmap_set_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_PAUSE); + aml_chan->pre_status = aml_chan->status; + aml_chan->status = DMA_PAUSED; + spin_unlock_irqrestore(&aml_chan->vchan.lock, flags); + + return 0; +} + +static int aml_dma_chan_resume(struct dma_chan *chan) +{ + struct aml_dma_chan *aml_chan = to_aml_dma_chan(chan); + struct aml_dma_dev *aml_dma = aml_chan->aml_dma; + unsigned long flags; + + spin_lock_irqsave(&aml_chan->vchan.lock, flags); + regmap_clear_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_PAUSE); + aml_chan->status = aml_chan->pre_status; + spin_unlock_irqrestore(&aml_chan->vchan.lock, flags); + + return 0; +} + +static int aml_dma_terminate_all(struct dma_chan *chan) +{ + struct aml_dma_chan *aml_chan = to_aml_dma_chan(chan); + struct aml_dma_dev *aml_dma = aml_chan->aml_dma; + int chan_id = aml_chan->chan_id; + struct virt_dma_desc *cur_vd; + unsigned long flags; + LIST_HEAD(head); + + spin_lock_irqsave(&aml_chan->vchan.lock, flags); + regmap_set_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_PAUSE); + regmap_set_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_CLEAR); + + if (aml_chan->direction == DMA_MEM_TO_DEV) + regmap_set_bits(aml_dma->regmap, RCH_INT_MASK, BIT(chan_id)); + else if (aml_chan->direction == DMA_DEV_TO_MEM) + regmap_set_bits(aml_dma->regmap, WCH_INT_MASK, BIT(chan_id)); + + regmap_clear_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_PAUSE); + regmap_clear_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_CLEAR); + + vchan_get_all_descriptors(&aml_chan->vchan, &head); + cur_vd = &aml_chan->cur_desc->vd; + aml_chan->cur_desc = NULL; + spin_unlock_irqrestore(&aml_chan->vchan.lock, flags); + if (cur_vd) + aml_dma_free_desc(cur_vd); + + vchan_dma_desc_free_list(&aml_chan->vchan, &head); + + aml_chan->status = DMA_COMPLETE; + aml_chan->err_num = 0; + + return 0; +} + +static void aml_dma_start(struct aml_dma_chan *aml_chan) +{ + struct virt_dma_desc *vd = vchan_next_desc(&aml_chan->vchan); + struct aml_dma_dev *aml_dma = aml_chan->aml_dma; + struct aml_dma_desc *aml_desc = NULL; + int chan_id = aml_chan->chan_id; + + if (aml_chan->status == DMA_ERROR) { + if (aml_chan->err_num > 5) { + dev_err(aml_dma->dma_device.dev, "hw error\n"); + return; + } + regmap_set_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_PAUSE); + regmap_set_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_CLEAR); + aml_chan->err_num++; + regmap_clear_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_PAUSE); + regmap_clear_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_CLEAR); + aml_chan->status = DMA_COMPLETE; + } else { + aml_chan->err_num = 0; + } + + if (!vd) + return; + + if (aml_chan->status != DMA_COMPLETE) + return; + + list_del(&vd->node); + aml_desc = to_aml_dma_desc(vd); + aml_chan->cur_desc = aml_desc; + + if (aml_chan->direction == DMA_MEM_TO_DEV) { + regmap_write(aml_dma->regmap, aml_chan->reg_offs + RCH_ADDR, + lower_32_bits(aml_desc->sg_link_phys)); + regmap_write(aml_dma->regmap, aml_chan->reg_offs + RCH_ADDR_HIGH, + upper_32_bits(aml_desc->sg_link_phys)); + regmap_write(aml_dma->regmap, aml_chan->reg_offs + RCH_LEN, aml_desc->data_len); + regmap_clear_bits(aml_dma->regmap, RCH_INT_MASK, BIT(chan_id)); + /* for rch (tx) need set cfg 0 to trigger start */ + regmap_write(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, 0); + } else if (aml_chan->direction == DMA_DEV_TO_MEM) { + regmap_write(aml_dma->regmap, aml_chan->reg_offs + WCH_ADDR, + lower_32_bits(aml_desc->sg_link_phys)); + regmap_write(aml_dma->regmap, aml_chan->reg_offs + WCH_ADDR_HIGH, + upper_32_bits(aml_desc->sg_link_phys)); + regmap_write(aml_dma->regmap, aml_chan->reg_offs + WCH_LEN, aml_desc->data_len); + regmap_clear_bits(aml_dma->regmap, WCH_INT_MASK, BIT(chan_id)); + } +} + +static void aml_dma_issue_pending(struct dma_chan *chan) +{ + struct aml_dma_chan *aml_chan = to_aml_dma_chan(chan); + unsigned long flags; + + spin_lock_irqsave(&aml_chan->vchan.lock, flags); + if (vchan_issue_pending(&aml_chan->vchan) && !aml_chan->cur_desc) + aml_dma_start(aml_chan); + spin_unlock_irqrestore(&aml_chan->vchan.lock, flags); +} + +static irqreturn_t aml_dma_interrupt_handler(int irq, void *dev_id) +{ + struct aml_dma_dev *aml_dma = dev_id; + struct aml_dma_chan *aml_chan; + struct aml_dma_desc *aml_desc; + u32 done, eoc_done, err, err_l, end; + u32 cpl_data; + int i = 0; + + /* deal with rch normal complete and error */ + regmap_read(aml_dma->regmap, RCH_DONE, &done); + regmap_read(aml_dma->regmap, RCH_ERR, &err); + regmap_read(aml_dma->regmap, RCH_LEN_ERR, &err_l); + err = err | err_l; + + done = done | err; + + while (done) { + i = ffs(done) - 1; + regmap_write(aml_dma->regmap, CLEAR_RCH, BIT(i)); + done &= ~BIT(i); + aml_chan = aml_dma->aml_rch[i]; + if (!aml_chan) { + dev_err(aml_dma->dma_device.dev, "idx %d rch not initialized\n", i); + continue; + } + spin_lock(&aml_chan->vchan.lock); + aml_chan->status = (err & BIT(i)) ? DMA_ERROR : DMA_COMPLETE; + aml_desc = aml_chan->cur_desc; + if (!aml_desc) { + spin_unlock(&aml_chan->vchan.lock); + continue; + } + if (aml_chan->status == DMA_ERROR) { + aml_desc->vd.tx_result.result = DMA_TRANS_READ_FAILED; + regmap_read(aml_dma->regmap, aml_chan->reg_offs + RCH_RD_LEN, &cpl_data); + aml_desc->vd.tx_result.residue = aml_desc->data_len - cpl_data; + } + vchan_cookie_complete(&aml_desc->vd); + aml_chan->cur_desc = NULL; + aml_dma_start(aml_chan); + spin_unlock(&aml_chan->vchan.lock); + } + + /* deal with wch normal complete and error */ + regmap_read(aml_dma->regmap, DMA_BATCH_END, &end); + if (end) + regmap_write(aml_dma->regmap, CLEAR_W_BATCH, end); + + regmap_read(aml_dma->regmap, WCH_DONE, &done); + regmap_read(aml_dma->regmap, WCH_EOC_DONE, &eoc_done); + done = done | eoc_done; + + regmap_read(aml_dma->regmap, WCH_ERR, &err); + regmap_read(aml_dma->regmap, WDMA_RESP_ERR, &err_l); + err = err | err_l; + + done = done | err; + i = 0; + while (done) { + i = ffs(done) - 1; + done &= ~BIT(i); + regmap_write(aml_dma->regmap, CLEAR_WCH, BIT(i)); + aml_chan = aml_dma->aml_wch[i]; + if (!aml_chan) { + dev_err(aml_dma->dma_device.dev, "idx %d wch not initialized\n", i); + continue; + } + spin_lock(&aml_chan->vchan.lock); + aml_chan->status = (err & BIT(i)) ? DMA_ERROR : DMA_COMPLETE; + aml_desc = aml_chan->cur_desc; + if (!aml_desc) { + spin_unlock(&aml_chan->vchan.lock); + continue; + } + if (aml_chan->status == DMA_ERROR) { + aml_desc->vd.tx_result.result = DMA_TRANS_WRITE_FAILED; + regmap_read(aml_dma->regmap, aml_chan->reg_offs + RCH_RD_LEN, &cpl_data); + aml_desc->vd.tx_result.residue = aml_desc->data_len - cpl_data; + } + vchan_cookie_complete(&aml_desc->vd); + aml_chan->cur_desc = NULL; + aml_dma_start(aml_chan); + spin_unlock(&aml_chan->vchan.lock); + } + + return IRQ_HANDLED; +} + +static struct dma_chan *aml_of_dma_xlate(struct of_phandle_args *dma_spec, struct of_dma *ofdma) +{ + struct aml_dma_dev *aml_dma = (struct aml_dma_dev *)ofdma->of_dma_data; + struct aml_dma_chan *aml_chan = NULL; + u32 type; + u32 phy_chan_id; + + if (dma_spec->args_count != 2) + return NULL; + + type = dma_spec->args[0]; + phy_chan_id = dma_spec->args[1]; + + if (phy_chan_id >= MAX_CHAN_ID) + return NULL; + + if (type == AMLOGIC_A9_DMA_TX) { + aml_chan = aml_dma->aml_rch[phy_chan_id]; + if (!aml_chan) { + if (aml_dma->chan_used >= aml_dma->chan_nr) { + dev_err(aml_dma->dma_device.dev, "some dma clients err used\n"); + return NULL; + } + aml_chan = &aml_dma->aml_chans[aml_dma->chan_used]; + aml_dma->chan_used++; + aml_chan->direction = DMA_MEM_TO_DEV; + aml_chan->chan_id = phy_chan_id; + aml_chan->reg_offs = RCH_REG_BASE + 0x40 * aml_chan->chan_id; + aml_dma->aml_rch[phy_chan_id] = aml_chan; + } + } else if (type == AMLOGIC_A9_DMA_RX) { + aml_chan = aml_dma->aml_wch[phy_chan_id]; + if (!aml_chan) { + if (aml_dma->chan_used >= aml_dma->chan_nr) { + dev_err(aml_dma->dma_device.dev, "some dma clients err used\n"); + return NULL; + } + aml_chan = &aml_dma->aml_chans[aml_dma->chan_used]; + aml_dma->chan_used++; + aml_chan->direction = DMA_DEV_TO_MEM; + aml_chan->chan_id = phy_chan_id; + aml_chan->reg_offs = WCH_REG_BASE + 0x40 * aml_chan->chan_id; + aml_dma->aml_wch[phy_chan_id] = aml_chan; + } + } else { + dev_err(aml_dma->dma_device.dev, "type %d not supported\n", type); + return NULL; + } + + return dma_get_slave_channel(&aml_chan->vchan.chan); +} + +static int aml_dma_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct dma_device *dma_dev; + struct aml_dma_dev *aml_dma; + int ret, i, len; + u32 chan_nr; + + const struct regmap_config aml_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 0x3000, + }; + + ret = of_property_read_u32(np, "dma-channels", &chan_nr); + if (ret) + return dev_err_probe(&pdev->dev, ret, "failed to read dma-channels\n"); + if (chan_nr > (MAX_CHAN_ID * 2)) + return dev_err_probe(&pdev->dev, -EINVAL, "dma-channels unusual\n"); + + len = sizeof(struct aml_dma_dev) + sizeof(struct aml_dma_chan) * chan_nr; + aml_dma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); + if (!aml_dma) + return -ENOMEM; + + aml_dma->free_wq = alloc_ordered_workqueue("aml_dma_free", 0); + if (!aml_dma->free_wq) + return -ENOMEM; + + aml_dma->chan_nr = chan_nr; + + aml_dma->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(aml_dma->base)) + return PTR_ERR(aml_dma->base); + + aml_dma->regmap = devm_regmap_init_mmio(&pdev->dev, aml_dma->base, + &aml_regmap_config); + if (IS_ERR_OR_NULL(aml_dma->regmap)) + return PTR_ERR(aml_dma->regmap); + + aml_dma->clk = devm_clk_get_enabled(&pdev->dev, NULL); + if (IS_ERR(aml_dma->clk)) + return PTR_ERR(aml_dma->clk); + + aml_dma->irq = platform_get_irq(pdev, 0); + + aml_dma->pdev = pdev; + aml_dma->dma_device.dev = &pdev->dev; + + dma_dev = &aml_dma->dma_device; + INIT_LIST_HEAD(&dma_dev->channels); + + /* Initialize channel parameters */ + for (i = 0; i < chan_nr; i++) { + struct aml_dma_chan *aml_chan = &aml_dma->aml_chans[i]; + + aml_chan->aml_dma = aml_dma; + aml_chan->vchan.desc_free = aml_dma_free_desc; + vchan_init(&aml_chan->vchan, &aml_dma->dma_device); + } + aml_dma->chan_used = 0; + + dma_set_max_seg_size(dma_dev->dev, SG_MAX_LEN); + dma_cap_set(DMA_SLAVE, dma_dev->cap_mask); + dma_dev->device_alloc_chan_resources = aml_dma_alloc_chan_resources; + dma_dev->device_free_chan_resources = aml_dma_free_chan_resources; + dma_dev->device_tx_status = aml_dma_tx_status; + dma_dev->device_prep_slave_sg = aml_dma_prep_slave_sg; + dma_dev->device_pause = aml_dma_chan_pause; + dma_dev->device_resume = aml_dma_chan_resume; + dma_dev->device_terminate_all = aml_dma_terminate_all; + dma_dev->device_issue_pending = aml_dma_issue_pending; + /* PIO 4 bytes and I2C 1 byte */ + dma_dev->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE); + dma_dev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); + dma_dev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; + + regmap_write(aml_dma->regmap, RCH_INT_MASK, INT_MASK); + regmap_write(aml_dma->regmap, WCH_INT_MASK, INT_MASK); + + ret = devm_request_irq(&pdev->dev, aml_dma->irq, aml_dma_interrupt_handler, + 0, dev_name(&pdev->dev), aml_dma); + if (ret) + return dev_err_probe(&pdev->dev, ret, "failed to register irq\n"); + + ret = dmaenginem_async_device_register(dma_dev); + if (ret) + return dev_err_probe(&pdev->dev, ret, "failed to register dmaenginem\n"); + + ret = of_dma_controller_register(np, aml_of_dma_xlate, aml_dma); + if (ret) + return dev_err_probe(&pdev->dev, ret, "failed to register xlate\n"); + + platform_set_drvdata(pdev, aml_dma); + + return 0; +} + +static void aml_dma_remove(struct platform_device *pdev) +{ + struct aml_dma_dev *aml_dma = platform_get_drvdata(pdev); + struct aml_dma_chan *aml_chan = NULL; + int i; + + of_dma_controller_free((&pdev->dev)->of_node); + + regmap_write(aml_dma->regmap, RCH_INT_MASK, INT_MASK); + regmap_write(aml_dma->regmap, WCH_INT_MASK, INT_MASK); + + for (i = 0; i < MAX_CHAN_ID; i++) { + aml_chan = aml_dma->aml_rch[i]; + if (aml_chan) + tasklet_kill(&aml_chan->vchan.task); + aml_chan = aml_dma->aml_wch[i]; + if (aml_chan) + tasklet_kill(&aml_chan->vchan.task); + } + destroy_workqueue(aml_dma->free_wq); +} + +static const struct of_device_id aml_dma_ids[] = { + { .compatible = "amlogic,a9-dma", }, + { } +}; +MODULE_DEVICE_TABLE(of, aml_dma_ids); + +static struct platform_driver aml_dma_driver = { + .probe = aml_dma_probe, + .remove = aml_dma_remove, + .driver = { + .name = "aml-dma", + .of_match_table = aml_dma_ids, + }, +}; + +module_platform_driver(aml_dma_driver); + +MODULE_DESCRIPTION("GENERAL DMA driver for Amlogic"); +MODULE_AUTHOR("Xianwei Zhao "); +MODULE_LICENSE("GPL"); From a5b2763df36b5c8ca0927f24ee97d9617e4eb6eb Mon Sep 17 00:00:00 2001 From: Xianwei Zhao Date: Thu, 3 Sep 2026 07:38:30 +0000 Subject: [PATCH 091/149] MAINTAINERS: Add an entry for Amlogic DMA driver Add Amlogic DMA controller entry to MAINTAINERS to clarify the maintainers. Signed-off-by: Xianwei Zhao Link: https://patch.msgid.link/20260903-amlogic-dma-v12-3-f769bc344056@amlogic.com Signed-off-by: Vinod Koul --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c31b81eb42d7..42f5165019ee 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1371,6 +1371,13 @@ F: Documentation/devicetree/bindings/perf/amlogic,g12-ddr-pmu.yaml F: drivers/perf/amlogic/ F: include/soc/amlogic/ +AMLOGIC DMA DRIVER +M: Xianwei Zhao +L: linux-amlogic@lists.infradead.org +S: Maintained +F: Documentation/devicetree/bindings/dma/amlogic,a9-dma.yaml +F: drivers/dma/amlogic-dma.c + AMLOGIC ISP DRIVER M: Keke Li L: linux-media@vger.kernel.org From 4bbfc1d7e56134336dd1f792f51ee88a600a27ad Mon Sep 17 00:00:00 2001 From: Diego Fernando Mancera Gomez Date: Sat, 5 Sep 2026 00:28:33 -0600 Subject: [PATCH 092/149] dmaengine: loongson2-apb-cmc: fix descriptor leak in prep_slave_sg() loongson2_cmc_dma_prep_slave_sg() allocates the descriptor with kzalloc_flex() before iterating over the scatterlist. If loongson2_cmc_dma_set_xfer_param() fails inside the loop, the function returns ERR_PTR(ret) without freeing the descriptor. At this point the descriptor has not been handed to vchan_tx_prep() yet, so nothing else will ever free it, leaking it on every failed ->device_prep_slave_sg() call (e.g. an unsupported transfer direction or bus width). The neighbouring error path for the num_items check already frees the descriptor before returning; do the same on the set_xfer_param() failure path. Fixes: 1c0028e725f1 ("dmaengine: loongson: New driver for the Loongson Multi-Channel DMA controller") Link: https://lore.kernel.org/all/20260818094957.7D2221F000E9@smtp.kernel.org/ Cc: stable@vger.kernel.org Signed-off-by: Diego Fernando Mancera Gomez Co-authored-by: Claude Opus 4.8 Claude-Session: https://claude.ai/code/session_012bUV3WshMSfTq61n1cgh1i Reviewed-by: Frank Li Link: https://patch.msgid.link/20260905062833.272484-1-diegomancera.dev@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/loongson/loongson2-apb-cmc-dma.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/dma/loongson/loongson2-apb-cmc-dma.c b/drivers/dma/loongson/loongson2-apb-cmc-dma.c index bc336947e31a..e440430bed80 100644 --- a/drivers/dma/loongson/loongson2-apb-cmc-dma.c +++ b/drivers/dma/loongson/loongson2-apb-cmc-dma.c @@ -399,8 +399,10 @@ loongson2_cmc_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, for_each_sg(sgl, sg, sg_len, i) { ret = loongson2_cmc_dma_set_xfer_param(lchan, direction, &buswidth, sg_dma_len(sg)); - if (ret) + if (ret) { + kfree(desc); return ERR_PTR(ret); + } num_items = DIV_ROUND_UP(sg_dma_len(sg), buswidth); if (num_items >= LOONSON2_CMCDMA_MAX_DATA_ITEMS) { From 7b6aa7904aae77275e4e8e8c69ce8826dc301fa8 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Fri, 11 Sep 2026 15:03:08 -0700 Subject: [PATCH 093/149] dmaengine: ppc4xx: change to %zu format specifiers for size_t arguments Several dev_err, dev_dbg, pr_debug, and printk calls use %d or %u format specifiers for size_t arguments (len, pool_size). Fix them to use %zu to avoid warnings on 64-bit builds. Assisted-by: LLM Signed-off-by: Rosen Penev Reviewed-by: Frank Li Link: https://patch.msgid.link/20260911220308.176962-1-rosenp@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/ppc4xx/adma.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/dma/ppc4xx/adma.c b/drivers/dma/ppc4xx/adma.c index 279a431ccae3..bcc54d584e2b 100644 --- a/drivers/dma/ppc4xx/adma.c +++ b/drivers/dma/ppc4xx/adma.c @@ -799,7 +799,7 @@ static int ppc440spe_chan_xor_slot_count(size_t len, int src_cnt, if (likely(len <= PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT)) return slot_cnt; - printk(KERN_ERR "%s: len %d > max %d !!\n", + printk(KERN_ERR "%s: len %zu > max %d !!\n", __func__, len, PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT); BUG(); return slot_cnt; @@ -1989,7 +1989,7 @@ static struct dma_async_tx_descriptor *ppc440spe_adma_prep_dma_memcpy( spin_lock_bh(&ppc440spe_chan->lock); dev_dbg(ppc440spe_chan->device->common.dev, - "ppc440spe adma%d: %s len: %u int_en %d\n", + "ppc440spe adma%d: %s len: %zu int_en %d\n", ppc440spe_chan->device->id, __func__, len, flags & DMA_PREP_INTERRUPT ? 1 : 0); slot_cnt = slots_per_op = 1; @@ -2030,7 +2030,7 @@ static struct dma_async_tx_descriptor *ppc440spe_adma_prep_dma_xor( BUG_ON(len > PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT); dev_dbg(ppc440spe_chan->device->common.dev, - "ppc440spe adma%d: %s src_cnt: %d len: %u int_en: %d\n", + "ppc440spe adma%d: %s src_cnt: %d len: %zu int_en: %d\n", ppc440spe_chan->device->id, __func__, src_cnt, len, flags & DMA_PREP_INTERRUPT ? 1 : 0); @@ -2279,7 +2279,7 @@ static struct ppc440spe_adma_desc_slot *ppc440spe_dma01_prep_pq( unsigned long op = 0; unsigned char mult = 1; - pr_debug("%s: dst_cnt %d, src_cnt %d, len %d\n", + pr_debug("%s: dst_cnt %d, src_cnt %d, len %zu\n", __func__, dst_cnt, src_cnt, len); /* select operations WXOR/RXOR depending on the * source addresses of operators and the number @@ -2553,7 +2553,7 @@ static struct dma_async_tx_descriptor *ppc440spe_adma_prep_dma_pq( BUG_ON(!dst_cnt); dev_dbg(ppc440spe_chan->device->common.dev, - "ppc440spe adma%d: %s src_cnt: %d len: %u int_en: %d\n", + "ppc440spe adma%d: %s src_cnt: %d len: %zu int_en: %d\n", ppc440spe_chan->device->id, __func__, src_cnt, len, flags & DMA_PREP_INTERRUPT ? 1 : 0); @@ -4077,7 +4077,7 @@ static int ppc440spe_adma_probe(struct platform_device *ofdev) adev->pool_size, &adev->dma_desc_pool, GFP_KERNEL); if (adev->dma_desc_pool_virt == NULL) { - dev_err(&ofdev->dev, "failed to allocate %d bytes of coherent " + dev_err(&ofdev->dev, "failed to allocate %zu bytes of coherent " "memory for hardware descriptors\n", adev->pool_size); initcode = PPC_ADMA_INIT_COHERENT; From f54701da5c0562cefadc8b638c3c141111c10579 Mon Sep 17 00:00:00 2001 From: Koichiro Den Date: Sun, 13 Sep 2026 02:40:21 +0900 Subject: [PATCH 094/149] dmaengine: Allow drivers to assign static channel IDs The dmaengine core assigns channel IDs in registration order. If a driver skips a hardware channel, chan_id can differ from the hardware numbering and a client cannot reliably correlate a requested channel with hardware resources. Let a driver request an exact channel ID before device registration. Reserve static IDs through the existing IDA so they remain unique, while retaining automatic IDA allocation as the default. For example, idma32 uses chan_id to select DMA_CTL_CH() and DMA_XBAR_SEL(), so it relies on ascending registration order to match chan_id with the hardware channel number. Use direction-flattened IDs for dw-edma channels. Unlike the direction-local hardware channel number, these IDs are unique within the DMA device. Suggested-by: Frank Li Reviewed-by: Frank Li Signed-off-by: Koichiro Den Link: https://lore.kernel.org/r/lm7tadnxsyrypu4mypptlkx5qkytex4qxsijdr5ydud2n3anvf@yakjfjg5ng4u/ Link: https://lore.kernel.org/r/20260813063757.3131865-2-den@valinux.co.jp/ Link: https://lore.kernel.org/r/an4TXwT37vWYEzCn@SMW015318/ Link: https://patch.msgid.link/20260912174023.1227397-2-den@valinux.co.jp Signed-off-by: Vinod Koul --- drivers/dma/dmaengine.c | 13 ++++++++----- drivers/dma/dw-edma/dw-edma-core.c | 1 + include/linux/dmaengine.h | 20 ++++++++++++++++++++ 3 files changed, 29 insertions(+), 5 deletions(-) diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c index bb30a9aa54d3..c5fef57b5adf 100644 --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c @@ -1078,6 +1078,7 @@ static int __dma_async_device_channel_register(struct dma_device *device, struct dma_chan *chan, const char *name) { + unsigned int id; int rc; chan->local = alloc_percpu(typeof(*chan->local)); @@ -1089,11 +1090,13 @@ static int __dma_async_device_channel_register(struct dma_device *device, goto err_free_local; } - /* - * When the chan_id is a negative value, we are dynamically adding - * the channel. Otherwise we are static enumerating. - */ - chan->chan_id = ida_alloc(&device->chan_ida, GFP_KERNEL); + if (chan->chan_id & DMA_CHAN_ID_STATIC) { + id = chan->chan_id & ~DMA_CHAN_ID_STATIC; + chan->chan_id = ida_alloc_range(&device->chan_ida, id, id, + GFP_KERNEL); + } else { + chan->chan_id = ida_alloc(&device->chan_ida, GFP_KERNEL); + } if (chan->chan_id < 0) { pr_err("%s: unable to alloc ida for chan: %d\n", __func__, chan->chan_id); diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c index e2eba6d72b53..4ed35e452d17 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -1119,6 +1119,7 @@ static int dw_edma_channel_setup(struct dw_edma *dw, u32 wr_alloc, u32 rd_alloc) &dw->chip->dt_region_rd[chan->id]; vchan_init(&chan->vc, dma); + dmaengine_set_static_chan_id(&chan->vc.chan, i); dw_edma_core_ch_config(chan); } diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index c3a49a33307c..0ada6fe66e80 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -377,6 +377,26 @@ struct dma_chan { void *private; }; +#define DMA_CHAN_ID_STATIC BIT(30) + +/** + * dmaengine_set_static_chan_id - request an exact DMA engine channel ID + * @chan: DMA channel + * @id: channel ID, unique within the DMA device + * + * Drivers may call this after initializing @chan and before registering its + * DMA device. The dmaengine core reserves @id from the device IDA instead of + * assigning the next available ID. + */ +static inline void dmaengine_set_static_chan_id(struct dma_chan *chan, + unsigned int id) +{ + if (WARN_ON_ONCE(id >= DMA_CHAN_ID_STATIC)) + return; + + chan->chan_id = DMA_CHAN_ID_STATIC | id; +} + /** * struct dma_chan_dev - relate sysfs device node to backing channel device * @chan: driver channel device From 9d31ad3b331d5d78bd6a247a9d35f35a6a9bbd59 Mon Sep 17 00:00:00 2001 From: Koichiro Den Date: Sun, 13 Sep 2026 02:40:22 +0900 Subject: [PATCH 095/149] dmaengine: dw-edma: Configure remote interrupt routing An endpoint function can reserve an endpoint-local channel while the RC programs it through an exposed register window. Such a channel must route interrupts remotely and ignore them on the endpoint. Use dma_slave_config to set per-channel interrupt routing on idle channels of a local eDMA or HDMA instance. Releasing a remote-routed channel quiesces the hardware and drains its local IRQ before restoring default routing. The eDMA quiesce may stop a complete direction. The caller must own every channel in that direction and stop remote programming first. Suggested-by: Frank Li Signed-off-by: Koichiro Den Reviewed-by: Frank Li Link: https://patch.msgid.link/20260912174023.1227397-3-den@valinux.co.jp Signed-off-by: Vinod Koul --- drivers/dma/dw-edma/dw-edma-core.c | 138 ++++++++++++++++++++++------- include/linux/dma/edma.h | 21 +++++ 2 files changed, 126 insertions(+), 33 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c index 4ed35e452d17..da14b6b9cbc6 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -309,48 +309,76 @@ dw_edma_get_default_irq_mode(struct dw_edma_chan *chan) DW_EDMA_CH_IRQ_REMOTE; } +static int dw_edma_device_config_irq_mode(struct dw_edma_chan *chan, + enum dw_edma_ch_irq_mode mode) +{ + if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) || + (mode != DW_EDMA_CH_IRQ_LOCAL && mode != DW_EDMA_CH_IRQ_REMOTE)) + return -EINVAL; + + guard(spinlock_irqsave)(&chan->vc.lock); + + if (chan->status != EDMA_ST_IDLE || chan->request != EDMA_REQ_NONE) + return -EBUSY; + + /* IRQ routing cannot change after the initial configuration. */ + if (chan->irq_mode == mode) + return 0; + + if (chan->configured) + return -EBUSY; + + chan->irq_mode = mode; + + return 0; +} + static int dw_edma_device_config(struct dma_chan *dchan, struct dma_slave_config *config) { + const struct dw_edma_chan_config *dw_config = config->peripheral_config; struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan); - bool cfg_non_ll; - int non_ll = 0; + bool non_ll = false; + u32 flags = 0; + int ret; - chan->non_ll = false; - if (chan->dw->chip->mf == EDMA_MF_HDMA_NATIVE) { - if (config->peripheral_config && - config->peripheral_size != sizeof(int)) { - dev_err(dchan->device->dev, - "config param peripheral size mismatch\n"); + if (dw_config) { + if (config->peripheral_size != sizeof(*dw_config) || + dw_config->flags & ~(DW_EDMA_CH_CONFIG_NON_LL | + DW_EDMA_CH_CONFIG_IRQ_MODE)) + return -EINVAL; + flags = dw_config->flags; + } + + /* + * When there is no valid LLP base address available then the + * default DMA ops will use the non-LL mode. + * + * When LL mode is the default, clients can request non-LL mode + * through DW_EDMA_CH_CONFIG_NON_LL. + */ + non_ll = chan->dw->chip->mf == EDMA_MF_HDMA_NATIVE && + chan->dw->chip->cfg_non_ll; + + if (flags & DW_EDMA_CH_CONFIG_NON_LL) { + if (chan->dw->chip->mf != EDMA_MF_HDMA_NATIVE) + return -EINVAL; + + if (chan->dw->chip->cfg_non_ll && !dw_config->non_ll) { + dev_err(dchan->device->dev, "invalid configuration\n"); return -EINVAL; } - /* - * When there is no valid LLP base address available then the - * default DMA ops will use the non-LL mode. - * - * Cases where LL mode is enabled and client wants to use the - * non-LL mode then also client can do so via providing the - * peripheral_config param. - */ - cfg_non_ll = chan->dw->chip->cfg_non_ll; - if (config->peripheral_config) { - non_ll = *(int *)config->peripheral_config; - - if (cfg_non_ll && !non_ll) { - dev_err(dchan->device->dev, "invalid configuration\n"); - return -EINVAL; - } - } - - if (cfg_non_ll || non_ll) - chan->non_ll = true; - } else if (config->peripheral_config) { - dev_err(dchan->device->dev, - "peripheral config param applicable only for HDMA\n"); - return -EINVAL; + non_ll = dw_config->non_ll; } + if (flags & DW_EDMA_CH_CONFIG_IRQ_MODE) { + ret = dw_edma_device_config_irq_mode(chan, dw_config->irq_mode); + if (ret) + return ret; + } + + chan->non_ll = non_ll; memcpy(&chan->config, config, sizeof(*config)); chan->configured = true; @@ -1014,11 +1042,53 @@ static void dw_edma_wait_termination(struct dma_chan *dchan) "timeout waiting for channel termination\n"); } +static void dw_edma_synchronize_chan_irq(struct dw_edma_chan *chan) +{ + struct dw_edma *dw = chan->dw; + unsigned long *mask; + int i; + + /* + * A shared handler may retain this channel's status across quiesce. + * With nr_irqs == 1, it scans both directions even if routing and + * delegation are direction-wide. Drain it before allowing a routing change. + */ + for (i = 0; i < dw->nr_irqs; i++) { + mask = chan->dir == EDMA_DIR_WRITE ? dw->irq[i].wr_mask : + dw->irq[i].rd_mask; + if (!test_bit(chan->id, mask)) + continue; + + synchronize_irq(dw->chip->ops->irq_vector(dw->chip->dev, i)); + return; + } +} + static void dw_edma_device_synchronize(struct dma_chan *dchan) { struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan); + bool remote; + + /* + * irq_mode is fixed after initial configuration. The free path + * restores it only after synchronization. + */ + remote = chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL && + chan->irq_mode == DW_EDMA_CH_IRQ_REMOTE; + + /* + * Peer-driven transfers bypass local descriptor tracking, so quiesce + * the hardware explicitly. + */ + if (remote && dw_edma_core_ch_quiesce(chan)) + dev_warn(chan->dw->chip->dev, + "failed to quiesce remote-routed %s channel %u\n", + chan->dir == EDMA_DIR_WRITE ? "write" : "read", + chan->id); dw_edma_wait_termination(dchan); + if (remote) + dw_edma_synchronize_chan_irq(chan); cancel_work_sync(&chan->irq_work); atomic_set(&chan->irq_pending, 0); vchan_synchronize(&chan->vc); @@ -1031,8 +1101,10 @@ static void dw_edma_free_chan_resources(struct dma_chan *dchan) dw_edma_device_terminate_all(dchan); dw_edma_device_synchronize(dchan); - scoped_guard(spinlock_irqsave, &chan->vc.lock) + scoped_guard(spinlock_irqsave, &chan->vc.lock) { chan->configured = false; + chan->irq_mode = dw_edma_get_default_irq_mode(chan); + } vchan_free_chan_resources(&chan->vc); } diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index affd896563a1..eead04b805e7 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -101,6 +101,27 @@ enum dw_edma_ch_irq_mode { DW_EDMA_CH_IRQ_REMOTE, }; +#define DW_EDMA_CH_CONFIG_NON_LL BIT(0) +#define DW_EDMA_CH_CONFIG_IRQ_MODE BIT(1) + +/** + * struct dw_edma_chan_config - dw-edma channel configuration + * @flags: fields selected by DW_EDMA_CH_CONFIG_* + * @non_ll: use HDMA non-linked-list mode + * @irq_mode: interrupt routing mode + * + * Pass this structure through dma_slave_config.peripheral_config. Before + * synchronizing a remote-routed channel, the client must stop remote + * programming and own every channel affected by the hardware quiesce: the + * entire direction for eDMA-compatible layouts, or the individual channel for + * native HDMA. + */ +struct dw_edma_chan_config { + u32 flags; + bool non_ll; + enum dw_edma_ch_irq_mode irq_mode; +}; + /** * struct dw_edma_chip - representation of DesignWare eDMA controller hardware * @dev: struct device of the eDMA controller From 742c2a8041e8c23ec4ac6688284ac12c623df1cc Mon Sep 17 00:00:00 2001 From: Koichiro Den Date: Sun, 13 Sep 2026 02:40:23 +0900 Subject: [PATCH 096/149] dmaengine: dw-edma: Account for the MSI vector offset get_cached_msi_msg() returns the base message shared by a multi-MSI descriptor. dw-edma currently derives per-channel data from its local IRQ index and does not adjust a common IRQ at all. Both assume eDMA starts at the descriptor's first vector. That is not true when eDMA receives a tail subset. Compose each message from the IRQ offset relative to the descriptor base in both paths. While at it, avoid reading PCI MSI attributes from descriptors owned by non-PCI devices. Reviewed-by: Frank Li Signed-off-by: Koichiro Den Link: https://patch.msgid.link/20260912174023.1227397-4-den@valinux.co.jp Signed-off-by: Vinod Koul --- drivers/dma/dw-edma/dw-edma-core.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c index da14b6b9cbc6..b08bb31657c9 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -1237,12 +1238,23 @@ static inline void dw_edma_dec_irq_alloc(int *nr_irqs, u32 *alloc, u16 cnt) } } +static void dw_edma_compose_msi(int irq, struct msi_msg *msi) +{ + struct msi_desc *desc = irq_get_msi_desc(irq); + + if (!desc) + return; + + get_cached_msi_msg(irq, msi); + if (dev_is_pci(desc->dev) && !desc->pci.msi_attrib.is_msix) + msi->data += irq - desc->irq; +} + static int dw_edma_irq_request(struct dw_edma *dw, u32 *wr_alloc, u32 *rd_alloc) { struct dw_edma_chip *chip = dw->chip; struct device *dev = dw->chip->dev; - struct msi_desc *msi_desc; int i, err = 0; u32 ch_cnt; int irq; @@ -1267,8 +1279,7 @@ static int dw_edma_irq_request(struct dw_edma *dw, return err; } - if (irq_get_msi_desc(irq)) - get_cached_msi_msg(irq, &dw->irq[0].msi); + dw_edma_compose_msi(irq, &dw->irq[0].msi); dw->nr_irqs = 1; } else { @@ -1291,12 +1302,7 @@ static int dw_edma_irq_request(struct dw_edma *dw, &dw->irq[i]); if (err) goto err_irq_free; - msi_desc = irq_get_msi_desc(irq); - if (msi_desc) { - get_cached_msi_msg(irq, &dw->irq[i].msi); - if (!msi_desc->pci.msi_attrib.is_msix) - dw->irq[i].msi.data = dw->irq[0].msi.data + i; - } + dw_edma_compose_msi(irq, &dw->irq[i].msi); } dw->nr_irqs = i; From ef399305a5bf64231059c63a53f3384eb59c2458 Mon Sep 17 00:00:00 2001 From: Bogdan Mahomet Date: Sat, 22 Aug 2026 03:15:30 +0300 Subject: [PATCH 097/149] docs: dmaengine: document ownership of the descriptor flags field The flags field of struct dma_async_tx_descriptor has carried a TODO since the provider documentation was added in 2014, asking whether a driver may modify the field itself or whether it must always hold the flags passed in the arguments. The field belongs to the client. dma_async_tx_descriptor_init() does not touch it, so the provider has to set it, and providers store the flags they were given verbatim; vchan_tx_prep() does this for every driver built on top of virt-dma. Afterwards providers only read the field: the DMA_PREP_* bits are consumed while the descriptor is being prepared, and DMA_CTRL_ACK and DMA_CTRL_REUSE are tested with async_tx_test_ack() and dmaengine_desc_test_reuse() before a descriptor is recycled or freed. Once a descriptor has been prepared, nothing in the tree changes the field except the client helpers in include/linux/dmaengine.h: async_tx_ack(), async_tx_clear_ack(), dmaengine_desc_set_reuse() and dmaengine_desc_clear_reuse(). Document that rule in place of the TODO. Signed-off-by: Bogdan Mahomet Reviewed-by: Frank Li Link: https://patch.msgid.link/20260822001536.29269-1-bogdan.mahomet.dev@gmail.com Signed-off-by: Vinod Koul --- Documentation/driver-api/dmaengine/provider.rst | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/driver-api/dmaengine/provider.rst b/Documentation/driver-api/dmaengine/provider.rst index 22d235fb478f..2897ade67b39 100644 --- a/Documentation/driver-api/dmaengine/provider.rst +++ b/Documentation/driver-api/dmaengine/provider.rst @@ -413,9 +413,11 @@ supported. - You'll also need to set following fields in this structure: - - flags: - TODO: Can it be modified by the driver itself, or - should it be always the flags passed in the arguments + - flags: this field belongs to the client. The driver stores the + flags passed in the arguments and must not modify them. It reads + the DMA_PREP_* bits while preparing the descriptor, and must only + test DMA_CTRL_ACK and DMA_CTRL_REUSE, which the client may change + after the descriptor has been prepared. - tx_submit: A pointer to a function you have to implement, that is supposed to push the current transaction descriptor to a From e2174129ddb293552ab7832439606848348f0370 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Monin?= Date: Wed, 16 Sep 2026 10:24:11 +0200 Subject: [PATCH 098/149] dmaengine: fsl-edma: Implement device_prep_peripheral_dma_vec MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add implementation of .device_prep_peripheral_dma_vec() callback to setup a scatter/gather DMA transfer from an array of dma_vec structures. Setup a cyclic transfer if the DMA_PREP_REPEAT flag is set. Reviewed-by: Frank Li Signed-off-by: Benoît Monin Link: https://patch.msgid.link/20260916-fsl-edma-dyn-sg-v11-1-02792de71b92@bootlin.com Signed-off-by: Vinod Koul --- drivers/dma/fsl-edma-common.c | 117 ++++++++++++++++++++++++++++++++++ drivers/dma/fsl-edma-common.h | 4 ++ drivers/dma/fsl-edma-main.c | 2 + 3 files changed, 123 insertions(+) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index bb7531c456df..8ba72b3d0e1a 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -3,6 +3,7 @@ // Copyright (c) 2013-2014 Freescale Semiconductor, Inc // Copyright (c) 2017 Sysam, Angelo Dureghello +#include #include #include #include @@ -673,6 +674,122 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); } +struct dma_async_tx_descriptor * +fsl_edma_prep_peripheral_dma_vec(struct dma_chan *chan, const struct dma_vec *vecs, + size_t nb, enum dma_transfer_direction direction, + unsigned long flags) +{ + struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); + dma_addr_t src_addr, dst_addr, last_sg; + struct fsl_edma_desc *fsl_desc; + u16 soff, doff, iter; + u32 nbytes; + int i; + + if (!is_slave_direction(direction)) + return NULL; + + if (!fsl_edma_prep_slave_dma(fsl_chan, direction)) + return NULL; + + fsl_desc = fsl_edma_alloc_desc(fsl_chan, nb); + if (!fsl_desc) + return NULL; + fsl_desc->iscyclic = flags & DMA_PREP_REPEAT; + fsl_desc->dirn = direction; + + if (direction == DMA_MEM_TO_DEV) { + if (!fsl_chan->cfg.src_addr_width) + fsl_chan->cfg.src_addr_width = fsl_chan->cfg.dst_addr_width; + fsl_chan->attr = + fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width, + fsl_chan->cfg.dst_addr_width); + nbytes = fsl_chan->cfg.dst_addr_width * fsl_chan->cfg.dst_maxburst; + } else { + if (!fsl_chan->cfg.dst_addr_width) + fsl_chan->cfg.dst_addr_width = fsl_chan->cfg.src_addr_width; + fsl_chan->attr = + fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width, + fsl_chan->cfg.dst_addr_width); + nbytes = fsl_chan->cfg.src_addr_width * fsl_chan->cfg.src_maxburst; + } + + for (i = 0; i < nb; i++) { + if (direction == DMA_MEM_TO_DEV) { + src_addr = vecs[i].addr; + dst_addr = fsl_chan->dma_dev_addr; + soff = fsl_chan->cfg.dst_addr_width; + doff = 0; + } else if (direction == DMA_DEV_TO_MEM) { + src_addr = fsl_chan->dma_dev_addr; + dst_addr = vecs[i].addr; + soff = 0; + doff = fsl_chan->cfg.src_addr_width; + } else { + /* DMA_DEV_TO_DEV */ + src_addr = fsl_chan->cfg.src_addr; + dst_addr = fsl_chan->cfg.dst_addr; + soff = 0; + doff = 0; + } + + /* + * Choose the suitable burst length if dma_vec length is not + * multiple of burst length so that the whole transfer length is + * multiple of minor loop(burst length). + */ + if (nbytes && vecs[i].len % nbytes) { + u32 width = (direction == DMA_DEV_TO_MEM) ? doff : soff; + u32 burst = (direction == DMA_DEV_TO_MEM) ? + fsl_chan->cfg.src_maxburst : + fsl_chan->cfg.dst_maxburst; + int j; + + for (j = burst; j > 1; j--) { + if (!(vecs[i].len % (j * width))) { + nbytes = j * width; + break; + } + } + /* Set burst size as 1 if there's no suitable one */ + if (j == 1) + nbytes = width; + } + + if (!nbytes || vecs[i].len / nbytes > FIELD_MAX(EDMA_TCD_ITER_MASK)) + goto err_free_desc; + + iter = vecs[i].len / nbytes; + if (i < nb - 1) { + last_sg = fsl_desc->tcd[(i + 1)].ptcd; + fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, + dst_addr, fsl_chan->attr, soff, + nbytes, 0, iter, iter, doff, last_sg, + false, false, true); + } else { + if (fsl_desc->iscyclic) { + last_sg = fsl_desc->tcd[0].ptcd; + fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, + dst_addr, fsl_chan->attr, soff, + nbytes, 0, iter, iter, doff, last_sg, + true, false, true); + } else { + last_sg = 0; + fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, + dst_addr, fsl_chan->attr, soff, + nbytes, 0, iter, iter, doff, last_sg, + true, true, false); + } + } + } + + return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); + +err_free_desc: + fsl_edma_free_desc(&fsl_desc->vdesc); + return NULL; +} + struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, enum dma_transfer_direction direction, diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index 205a96489094..0d028048701d 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -496,6 +496,10 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, size_t period_len, enum dma_transfer_direction direction, unsigned long flags); +struct dma_async_tx_descriptor *fsl_edma_prep_peripheral_dma_vec( + struct dma_chan *chan, const struct dma_vec *vecs, + size_t nb, enum dma_transfer_direction direction, + unsigned long flags); struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, enum dma_transfer_direction direction, diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index 6934ac882697..630285c85482 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -846,6 +846,8 @@ static int fsl_edma_probe(struct platform_device *pdev) fsl_edma->dma_dev.device_free_chan_resources = fsl_edma_free_chan_resources; fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status; + fsl_edma->dma_dev.device_prep_peripheral_dma_vec + = fsl_edma_prep_peripheral_dma_vec; fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg; fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic; fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy; From 2c9f5e95f41898b506b132d7698d270ed6a13583 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Monin?= Date: Wed, 16 Sep 2026 10:24:12 +0200 Subject: [PATCH 099/149] dmaengine: fsl-edma: Support dynamic scatter/gather chaining MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement dynamic linking of scatter/gather transfers to enable chaining multiple DMA descriptors without stopping the channel. This avoids waiting for the channel to go idle if there is another transaction already issued. Add fsl_edma_link_sg() to dynamically link the last TCD of a previously issued descriptor to the first TCD of a new descriptor by setting the scatter/gather address and the E_SG flag, and keeping the channel active by clearing the DREQ bit. Also in fsl_edma_link_sg(), assign a non-zero identifier to the new descriptor that is stored in the EDMA_TCD_CSR_LINKCH field of the CSR of each TCD, after checking that the descriptors are not using channel linking. The use of this field (MAJORLINKCH in the datasheet) as an identifier for dynamic scatter/gather is suggested in the i.MX93 datasheet. When the last issued descriptor is the one currently active on the channel and has a single TCD, the scatter/gather address and CSR are also written directly to the hardware registers to ensure the link takes effect immediately, unless the DMA controller requires the DONE bit to be cleared for the CSR change to take effect. Clearing the DONE bit would disrupt the interrupt handler. Linking is done in fsl_edma_issue_pending(), which iterates over the submitted descriptors, links each one to the previously issued descriptor via fsl_edma_link_sg(), and then moves it to the issued list. This ensures that transactions are linked in the order they were issued. Linking of a descriptor is limited to 31 outstanding descriptors on the issued list so the identifier fits in the LINKCH field of the CSR register. The value of zero is left to identify non-linked descriptors. Update fsl_edma_xfer_desc() to avoid re-initializing the hardware when a transfer is already in progress, allowing seamless chaining of descriptors. Modify the transfer completion handler to check the DONE flag in the channel CSR before marking the transfer complete. Since this flag is only available on SoC with the split registers layout, only link transactions for DMA controllers flagged with newly added FSL_EDMA_DRV_CSR_LINKCH. This flag is set for eDMA3 and EDMA4 controllers which are able to perform dynamic scatter/gather linking. The completion handler also reaps issued descriptors whose link channel ID (EDMA_TCD_CSR_LINKCH) has already been passed by the hardware, marking them as completed even if their corresponding interrupt has been missed. Add trace event for scatter/gather linking operations. Reviewed-by: Frank Li Signed-off-by: Benoît Monin Link: https://patch.msgid.link/20260916-fsl-edma-dyn-sg-v11-2-02792de71b92@bootlin.com Signed-off-by: Vinod Koul --- drivers/dma/fsl-edma-common.c | 138 ++++++++++++++++++++++++++++++++-- drivers/dma/fsl-edma-common.h | 11 ++- drivers/dma/fsl-edma-trace.h | 5 ++ 3 files changed, 146 insertions(+), 8 deletions(-) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index 8ba72b3d0e1a..513b0f4e5be2 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -56,10 +56,36 @@ void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan) } if (!fsl_chan->edesc->iscyclic) { - list_del(&fsl_chan->edesc->vdesc.node); - vchan_cookie_complete(&fsl_chan->edesc->vdesc); + u16 csr = edma_read_tcdreg(fsl_chan, csr); + u8 link_sg_id = FIELD_GET(EDMA_TCD_CSR_LINKCH, csr); + struct virt_dma_desc *vdesc, *tmp; + + /* Channel is DONE when a TCD with D_REQ set completes */ + if (!(fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_SPLIT_REG) || + (edma_readl_chreg(fsl_chan, ch_csr) & EDMA_V3_CH_CSR_DONE)) { + fsl_chan->status = DMA_COMPLETE; + } + + list_for_each_entry_safe(vdesc, tmp, &fsl_chan->vchan.desc_issued, node) { + struct fsl_edma_desc *fsl_desc = to_fsl_edma_desc(vdesc); + bool id_match = (link_sg_id == fsl_desc->link_sg_id); + + /* + * If the transfer is still running, + * don't mark as complete the current descriptor + */ + if (id_match && fsl_chan->status != DMA_COMPLETE) + break; + + list_del(&vdesc->node); + vchan_cookie_complete(vdesc); + + if (id_match) + break; + } + fsl_chan->edesc = NULL; - fsl_chan->status = DMA_COMPLETE; + } else { vchan_cyclic_callback(&fsl_chan->edesc->vdesc); } @@ -932,14 +958,99 @@ void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan) if (!vdesc) return; fsl_chan->edesc = to_fsl_edma_desc(vdesc); - fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); - fsl_edma_enable_request(fsl_chan); - fsl_chan->status = DMA_IN_PROGRESS; + + if (fsl_chan->status != DMA_IN_PROGRESS) { + fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); + fsl_edma_enable_request(fsl_chan); + fsl_chan->status = DMA_IN_PROGRESS; + } +} + +static void fsl_edma_link_sg(struct fsl_edma_chan *fsl_chan, struct fsl_edma_desc *fsl_desc) +{ + u32 flags = fsl_edma_drvflags(fsl_chan); + struct fsl_edma_hw_tcd *last_tcd; + struct fsl_edma_desc *prev_desc; + struct virt_dma_desc *vdesc; + u16 last_csr; + + lockdep_assert_held(&fsl_chan->vchan.lock); + + if (!(flags & FSL_EDMA_DRV_CSR_LINKCH) || fsl_desc->iscyclic) + return; + + vdesc = list_last_entry_or_null(&fsl_chan->vchan.desc_issued, + struct virt_dma_desc, node); + if (!vdesc) + return; + + prev_desc = to_fsl_edma_desc(vdesc); + if (prev_desc->iscyclic) + return; + + last_tcd = prev_desc->tcd[prev_desc->n_tcds - 1].vtcd; + last_csr = fsl_edma_get_tcd_to_cpu(fsl_chan, last_tcd, csr); + + for (unsigned int i = 0; i < fsl_desc->n_tcds; i++) { + struct fsl_edma_hw_tcd *tcd = fsl_desc->tcd[i].vtcd; + + if (fsl_edma_get_tcd_to_cpu(fsl_chan, tcd, csr) & EDMA_TCD_CSR_E_LINK) + return; + } + + if (!(last_csr & EDMA_TCD_CSR_D_REQ) || + last_csr & EDMA_TCD_CSR_E_LINK) + return; + + /* Set a non-zero linked SG identifier to all TCD of the new descriptor */ + fsl_chan->link_sg_id++; + if (fsl_chan->link_sg_id > FIELD_MAX(EDMA_TCD_CSR_LINKCH)) + fsl_chan->link_sg_id = 1; + + fsl_desc->link_sg_id = fsl_chan->link_sg_id; + + for (unsigned int i = 0; i < fsl_desc->n_tcds; i++) { + struct fsl_edma_hw_tcd *tcd = fsl_desc->tcd[i].vtcd; + u16 csr = fsl_edma_get_tcd_to_cpu(fsl_chan, tcd, csr); + + csr |= FIELD_PREP(EDMA_TCD_CSR_LINKCH, fsl_chan->link_sg_id); + fsl_edma_set_tcd_to_le(fsl_chan, tcd, csr, csr); + } + + /* + * Set DLAST_SGA before enabling E_SG in CSR: if the DMA engine + * only picks up the former, it updates DADDR at end of transfer, + * which is not reused. + */ + fsl_edma_set_tcd_to_le(fsl_chan, last_tcd, fsl_desc->tcd[0].ptcd, dlast_sga); + + dma_wmb(); + + last_csr &= ~EDMA_TCD_CSR_D_REQ; + last_csr |= EDMA_TCD_CSR_E_SG; + fsl_edma_set_tcd_to_le(fsl_chan, last_tcd, last_csr, csr); + + /* + * Update the registers if the engine already loaded the TCD, + * unless doing so requires clearing the DONE bit, as that could + * lead to lost completion. + */ + if (prev_desc == fsl_chan->edesc && + prev_desc->n_tcds == 1 && + !(flags & FSL_EDMA_DRV_CLEAR_DONE_E_SG)) { + edma_cp_tcd_to_reg(fsl_chan, last_tcd, dlast_sga); + edma_cp_tcd_to_reg(fsl_chan, last_tcd, csr); + } + + trace_edma_link_sg(fsl_chan, last_tcd); } void fsl_edma_issue_pending(struct dma_chan *chan) { struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); + struct virt_dma_desc *vdesc, *tmp; + size_t issued_count = 0; + struct list_head *pos; unsigned long flags; spin_lock_irqsave(&fsl_chan->vchan.lock, flags); @@ -950,6 +1061,21 @@ void fsl_edma_issue_pending(struct dma_chan *chan) return; } + /* Count the issued desc up to the maximum number of linked SG id */ + list_for_each(pos, &fsl_chan->vchan.desc_issued) { + if (++issued_count > FIELD_MAX(EDMA_TCD_CSR_LINKCH)) + break; + } + + /* Link the SG descriptors with the available identifiers */ + list_for_each_entry_safe(vdesc, tmp, &fsl_chan->vchan.desc_submitted, node) { + if (++issued_count > FIELD_MAX(EDMA_TCD_CSR_LINKCH)) + break; + fsl_edma_link_sg(fsl_chan, to_fsl_edma_desc(vdesc)); + list_move_tail(&vdesc->node, &fsl_chan->vchan.desc_issued); + } + + /* Issue the rest of the descriptors unlinked */ if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc) fsl_edma_xfer_desc(fsl_chan); diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index 0d028048701d..cbb077e98f55 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -42,6 +42,7 @@ #define EDMA_TCD_CSR_E_LINK BIT(5) #define EDMA_TCD_CSR_ACTIVE BIT(6) #define EDMA_TCD_CSR_DONE BIT(7) +#define EDMA_TCD_CSR_LINKCH GENMASK(12, 8) #define EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(x) ((x) & GENMASK(9, 0)) #define EDMA_V3_TCD_NBYTES_MLOFF(x) (x << 10) @@ -169,6 +170,7 @@ struct fsl_edma_chan { struct dma_slave_config cfg; u32 attr; bool is_sw; + u8 link_sg_id; struct dma_pool *tcd_pool; dma_addr_t dma_dev_addr; u32 dma_dev_size; @@ -199,6 +201,7 @@ struct fsl_edma_desc { struct virt_dma_desc vdesc; struct fsl_edma_chan *echan; bool iscyclic; + u8 link_sg_id; enum dma_transfer_direction dirn; unsigned int n_tcds; struct fsl_edma_sw_tcd tcd[]; @@ -225,6 +228,8 @@ struct fsl_edma_desc { #define FSL_EDMA_DRV_TCD64 BIT(15) /* All channel ERR IRQ share one IRQ line */ #define FSL_EDMA_DRV_ERRIRQ_SHARE BIT(16) +/* Major link channel in CSR used for linking SG descriptors */ +#define FSL_EDMA_DRV_CSR_LINKCH BIT(17) #define FSL_EDMA_DRV_EDMA3 (FSL_EDMA_DRV_SPLIT_REG | \ @@ -232,13 +237,15 @@ struct fsl_edma_desc { FSL_EDMA_DRV_DEV_TO_DEV | \ FSL_EDMA_DRV_ALIGN_64BYTE | \ FSL_EDMA_DRV_CLEAR_DONE_E_SG | \ - FSL_EDMA_DRV_CLEAR_DONE_E_LINK) + FSL_EDMA_DRV_CLEAR_DONE_E_LINK | \ + FSL_EDMA_DRV_CSR_LINKCH) #define FSL_EDMA_DRV_EDMA4 (FSL_EDMA_DRV_SPLIT_REG | \ FSL_EDMA_DRV_BUS_8BYTE | \ FSL_EDMA_DRV_DEV_TO_DEV | \ FSL_EDMA_DRV_ALIGN_64BYTE | \ - FSL_EDMA_DRV_CLEAR_DONE_E_LINK) + FSL_EDMA_DRV_CLEAR_DONE_E_LINK | \ + FSL_EDMA_DRV_CSR_LINKCH) struct fsl_edma_drvdata { u32 dmamuxs; /* only used before v3 */ diff --git a/drivers/dma/fsl-edma-trace.h b/drivers/dma/fsl-edma-trace.h index 45d964a3726d..f4b0021d2bd0 100644 --- a/drivers/dma/fsl-edma-trace.h +++ b/drivers/dma/fsl-edma-trace.h @@ -121,6 +121,11 @@ DEFINE_EVENT(edma_log_tcd, edma_fill_tcd, TP_ARGS(chan, tcd) ); +DEFINE_EVENT(edma_log_tcd, edma_link_sg, + TP_PROTO(struct fsl_edma_chan *chan, void *tcd), + TP_ARGS(chan, tcd) +); + #endif /* this part must be outside header guard */ From 6b0089d88669c87d69df6fa118c198024494a033 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 28 Sep 2026 07:44:46 -0500 Subject: [PATCH 100/149] dt-bindings: dma: Convert hisilicon,k3-dma-1.0 to DT schema Convert the hisilicon,k3-dma-1.0 binding to DT schema format. Add dma-channel-mask, dma-no-cci, dma-type and interrupt-names properties which were not documented. The "hisilicon,hisi-pcm-asp-dma-1.0" doesn't have clocks, so make it optional. Assisted-by: LLM Signed-off-by: Rob Herring (Arm) Acked-by: Wei Xu Link: https://patch.msgid.link/20260928124448.3754740-1-robh@kernel.org Signed-off-by: Vinod Koul --- .../bindings/dma/hisilicon,k3-dma-1.0.yaml | 87 +++++++++++++++++++ .../devicetree/bindings/dma/k3dma.txt | 47 ---------- 2 files changed, 87 insertions(+), 47 deletions(-) create mode 100644 Documentation/devicetree/bindings/dma/hisilicon,k3-dma-1.0.yaml delete mode 100644 Documentation/devicetree/bindings/dma/k3dma.txt diff --git a/Documentation/devicetree/bindings/dma/hisilicon,k3-dma-1.0.yaml b/Documentation/devicetree/bindings/dma/hisilicon,k3-dma-1.0.yaml new file mode 100644 index 000000000000..e60f2a572272 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/hisilicon,k3-dma-1.0.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/hisilicon,k3-dma-1.0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon K3 DMA controller + +maintainers: + - Wei Xu + +properties: + compatible: + items: + - enum: + - hisilicon,k3-dma-1.0 + - hisilicon,hisi-pcm-asp-dma-1.0 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#dma-cells': + const: 1 + + dma-channels: + description: Number of physical DMA channels supported. + maximum: 32 + + dma-requests: + description: Number of virtual DMA request lines supported. + maximum: 32 + + dma-channel-mask: + description: Bitmask of usable DMA channels. + + dma-no-cci: + type: boolean + description: DMA is not coherent with the CCI. + + dma-type: + $ref: /schemas/types.yaml#/definitions/string + description: SoC-specific DMA type name. + enum: + - hi3660_dma + - hi6220_dma + + interrupt-names: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - '#dma-cells' + - dma-channels + - dma-requests + +allOf: + - $ref: dma-controller.yaml# + - if: + properties: + compatible: + contains: + const: hisilicon,k3-dma-1.0 + then: + required: + - clocks + +additionalProperties: false + +examples: + - | + dma-controller@fcd02000 { + compatible = "hisilicon,k3-dma-1.0"; + reg = <0xfcd02000 0x1000>; + #dma-cells = <1>; + dma-channels = <16>; + dma-requests = <27>; + interrupts = <0 12 4>; + clocks = <&pclk>; + }; diff --git a/Documentation/devicetree/bindings/dma/k3dma.txt b/Documentation/devicetree/bindings/dma/k3dma.txt deleted file mode 100644 index 10a2f15b08a3..000000000000 --- a/Documentation/devicetree/bindings/dma/k3dma.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Hisilicon K3 DMA controller - -See dma.txt first - -Required properties: -- compatible: Must be one of -- "hisilicon,k3-dma-1.0" -- "hisilicon,hisi-pcm-asp-dma-1.0" -- reg: Should contain DMA registers location and length. -- interrupts: Should contain one interrupt shared by all channel -- #dma-cells: see dma.txt, should be 1, para number -- dma-channels: physical channels supported -- dma-requests: virtual channels supported, each virtual channel - have specific request line -- clocks: clock required - -Example: - -Controller: - dma0: dma@fcd02000 { - compatible = "hisilicon,k3-dma-1.0"; - reg = <0xfcd02000 0x1000>; - #dma-cells = <1>; - dma-channels = <16>; - dma-requests = <27>; - interrupts = <0 12 4>; - clocks = <&pclk>; - }; - -Client: -Use specific request line passing from dmax -For example, i2c0 read channel request line is 18, while write channel use 19 - - i2c0: i2c@fcb08000 { - compatible = "snps,designware-i2c"; - dmas = <&dma0 18 /* read channel */ - &dma0 19>; /* write channel */ - dma-names = "rx", "tx"; - }; - - i2c1: i2c@fcb09000 { - compatible = "snps,designware-i2c"; - dmas = <&dma0 20 /* read channel */ - &dma0 21>; /* write channel */ - dma-names = "rx", "tx"; - }; - From 5014a84aa577922593072719c048d526e5a37bf2 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Wed, 16 Sep 2026 17:21:29 +0200 Subject: [PATCH 101/149] dt-bindings: dma: qcom,gpi: Document the Nord GPI DMA engine Add the compatible string for the GPI DMA engine found on the Nord family of SoCs. Signed-off-by: Bartosz Golaszewski Reviewed-by: Shawn Guo Link: https://patch.msgid.link/20260916-nord-gpi-dt-bindings-v1-1-857bf9e84999@oss.qualcomm.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml index dfc4a3054b5d..dc7bdf7c4201 100644 --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -30,6 +30,7 @@ properties: - qcom,kaanapali-gpi-dma - qcom,maili-gpi-dma - qcom,milos-gpi-dma + - qcom,nord-gpi-dma - qcom,qcm2290-gpi-dma - qcom,qcs8300-gpi-dma - qcom,qdu1000-gpi-dma From 3a03a5866e82027c0fa96f6208721397e5a6ff78 Mon Sep 17 00:00:00 2001 From: Pawel Zalewski Date: Wed, 16 Sep 2026 16:27:54 +0100 Subject: [PATCH 102/149] dmaengine: dw: use designated initializers for acpi_device_id Use a named initializer for the acpi_device_id fields which makes the code more readable and consistent with how lists are initialized in the rest of the kernel code base. Signed-off-by: Pawel Zalewski Reviewed-by: Andy Shevchenko Reviewed-by: Frank Li Link: https://patch.msgid.link/20260916-acpi-dma-v3-1-0dac05654967@thegoodpenguin.co.uk Signed-off-by: Vinod Koul --- drivers/dma/dw/platform.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c index c63fa52036d7..5c1c97eb28a4 100644 --- a/drivers/dma/dw/platform.c +++ b/drivers/dma/dw/platform.c @@ -141,14 +141,14 @@ MODULE_DEVICE_TABLE(of, dw_dma_of_id_table); #ifdef CONFIG_ACPI static const struct acpi_device_id dw_dma_acpi_id_table[] = { - { "INTL9C60", (kernel_ulong_t)&dw_dma_chip_pdata }, - { "80862286", (kernel_ulong_t)&dw_dma_chip_pdata }, - { "808622C0", (kernel_ulong_t)&dw_dma_chip_pdata }, + { .id = "INTL9C60", .driver_data = (kernel_ulong_t)&dw_dma_chip_pdata }, + { .id = "80862286", .driver_data = (kernel_ulong_t)&dw_dma_chip_pdata }, + { .id = "808622C0", .driver_data = (kernel_ulong_t)&dw_dma_chip_pdata }, /* Elkhart Lake iDMA 32-bit (PSE DMA) */ - { "80864BB4", (kernel_ulong_t)&xbar_chip_pdata }, - { "80864BB5", (kernel_ulong_t)&xbar_chip_pdata }, - { "80864BB6", (kernel_ulong_t)&xbar_chip_pdata }, + { .id = "80864BB4", .driver_data = (kernel_ulong_t)&xbar_chip_pdata }, + { .id = "80864BB5", .driver_data = (kernel_ulong_t)&xbar_chip_pdata }, + { .id = "80864BB6", .driver_data = (kernel_ulong_t)&xbar_chip_pdata }, { } }; From b37c93bc1cfd0f5fb898b7943bd0c1797341a41d Mon Sep 17 00:00:00 2001 From: Pawel Zalewski Date: Wed, 16 Sep 2026 16:27:55 +0100 Subject: [PATCH 103/149] dmaengine: loongson: use named initializers for acpi_device_id Use a named initializer for the acpi_device_id fields which makes the code more readable and consistent with how lists are initialized in the rest of the kernel code base. Unify the list terminator to have a single space between the brackets and no trailing comma. Signed-off-by: Pawel Zalewski Reviewed-by: Binbin Zhou Reviewed-by: Andy Shevchenko Reviewed-by: Frank Li Link: https://patch.msgid.link/20260916-acpi-dma-v3-2-0dac05654967@thegoodpenguin.co.uk Signed-off-by: Vinod Koul --- drivers/dma/loongson/loongson2-apb-cmc-dma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma/loongson/loongson2-apb-cmc-dma.c b/drivers/dma/loongson/loongson2-apb-cmc-dma.c index e440430bed80..2037120b23ca 100644 --- a/drivers/dma/loongson/loongson2-apb-cmc-dma.c +++ b/drivers/dma/loongson/loongson2-apb-cmc-dma.c @@ -706,8 +706,8 @@ static const struct of_device_id loongson2_cmc_dma_of_match[] = { MODULE_DEVICE_TABLE(of, loongson2_cmc_dma_of_match); static const struct acpi_device_id loongson2_cmc_dma_acpi_match[] = { - { "LOON0014", .driver_data = (kernel_ulong_t)&ls2k3000_cmc_dma_config }, - { /* sentinel */ } + { .id = "LOON0014", .driver_data = (kernel_ulong_t)&ls2k3000_cmc_dma_config }, + { } }; MODULE_DEVICE_TABLE(acpi, loongson2_cmc_dma_acpi_match); From db09763394959442d91d86840717412073c41abc Mon Sep 17 00:00:00 2001 From: Pawel Zalewski Date: Wed, 16 Sep 2026 16:27:56 +0100 Subject: [PATCH 104/149] dmaengine: qcom: use named initializers for acpi_device_id Use a named initializer for the acpi_device_id fields which makes the code more readable and consistent with how lists are initialized in the rest of the kernel code base. Unify the list terminator to have a single space between the brackets and no trailing comma. Signed-off-by: Pawel Zalewski Reviewed-by: Andy Shevchenko Reviewed-by: Frank Li Link: https://patch.msgid.link/20260916-acpi-dma-v3-3-0dac05654967@thegoodpenguin.co.uk Signed-off-by: Vinod Koul --- drivers/dma/qcom/hidma.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/dma/qcom/hidma.c b/drivers/dma/qcom/hidma.c index c939635be21d..1349066b1544 100644 --- a/drivers/dma/qcom/hidma.c +++ b/drivers/dma/qcom/hidma.c @@ -935,10 +935,10 @@ static void hidma_remove(struct platform_device *pdev) #if IS_ENABLED(CONFIG_ACPI) static const struct acpi_device_id hidma_acpi_ids[] = { - {"QCOM8061"}, - {"QCOM8062", HIDMA_MSI_CAP}, - {"QCOM8063", (HIDMA_MSI_CAP | HIDMA_IDENTITY_CAP)}, - {}, + { .id = "QCOM8061" }, + { .id = "QCOM8062", .driver_data = HIDMA_MSI_CAP }, + { .id = "QCOM8063", .driver_data = (HIDMA_MSI_CAP | HIDMA_IDENTITY_CAP) }, + { } }; MODULE_DEVICE_TABLE(acpi, hidma_acpi_ids); #endif From b2c203a5878b0d3f95e4802fa01e320d317b82cf Mon Sep 17 00:00:00 2001 From: Pawel Zalewski Date: Wed, 16 Sep 2026 16:27:57 +0100 Subject: [PATCH 105/149] dmaengine: xgene-dma: use named initializers for acpi_device_id Use a designated initializer for the acpi_device_id fields which makes the code more readable and consistent with how lists are initialized in the rest of the kernel code base. Also drop explicitly setting fields to 0 where it is redundant. Unify the list terminator to have a single space between the brackets and no trailing comma. Signed-off-by: Pawel Zalewski Reviewed-by: Andy Shevchenko Reviewed-by: Frank Li Link: https://patch.msgid.link/20260916-acpi-dma-v3-4-0dac05654967@thegoodpenguin.co.uk Signed-off-by: Vinod Koul --- drivers/dma/xgene-dma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c index fa1173e49900..8d1c58ca0d48 100644 --- a/drivers/dma/xgene-dma.c +++ b/drivers/dma/xgene-dma.c @@ -1800,8 +1800,8 @@ static void xgene_dma_remove(struct platform_device *pdev) #ifdef CONFIG_ACPI static const struct acpi_device_id xgene_dma_acpi_match_ptr[] = { - {"APMC0D43", 0}, - {}, + { .id = "APMC0D43" }, + { } }; MODULE_DEVICE_TABLE(acpi, xgene_dma_acpi_match_ptr); #endif From 57946765c242005bdb16d17944c27662c8c5b013 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Fri, 18 Sep 2026 10:59:50 -0700 Subject: [PATCH 106/149] dmaengine: bestcomm: Enable compile testing Allow the BestComm DMA engine to be selected for PowerPC compile-test builds. The freescale ethernet and sound drivers now need a dependency on PPC_MPC52xx as they use headers/functions from that platform. Assisted-by: LLM Signed-off-by: Rosen Penev Reviewed-by: Frank Li Link: https://patch.msgid.link/20260918175950.21657-1-rosenp@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/bestcomm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/bestcomm/Kconfig b/drivers/dma/bestcomm/Kconfig index 5dd437295964..e23ba4982d7e 100644 --- a/drivers/dma/bestcomm/Kconfig +++ b/drivers/dma/bestcomm/Kconfig @@ -5,7 +5,7 @@ config PPC_BESTCOMM tristate "Bestcomm DMA engine support" - depends on PPC_MPC52xx + depends on PPC_MPC52xx || (PPC && COMPILE_TEST) default n select PPC_LIB_RHEAP help From 9db8e502b34bc1df8078abd0169a4fa0624de3bb Mon Sep 17 00:00:00 2001 From: Tommaso Merciai Date: Tue, 22 Sep 2026 12:20:37 +0300 Subject: [PATCH 107/149] dmaengine: sh: rz-dmac: Fix off-by-one in residue lmdesc lookup lmdesc->nxla is the address of the next descriptor, so comparing it against CRLA, which is the address of the current descriptor, finds the descriptor before the active one, not the active one. The residue loops below then summed one lmdesc too many on top of that. Compare each descriptor's own address to CRLA instead, and add tb after advancing to the next lmdesc. Fixes: 21323b118c16 ("dmaengine: sh: rz-dmac: Add device_tx_status() callback") Fixes: 172bfb57481c ("dmaengine: sh: rz-dmac: Add cyclic DMA support") Cc: stable@vger.kernel.org Suggested-by: Claudiu Beznea Signed-off-by: Tommaso Merciai Signed-off-by: Claudiu Beznea Reviewed-by: Frank Li Link: https://patch.msgid.link/20260922092037.224884-1-claudiu.beznea@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/sh/rz-dmac.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index ca76f1bb45c4..fdd7131e890a 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -937,7 +937,7 @@ static u32 rz_dmac_calculate_residue_bytes_in_vd(struct rz_dmac_chan *channel, struct rz_dmac *dmac = to_rz_dmac(chan->device); u32 residue = 0, i = 0; - while (lmdesc->nxla != crla) { + while (rz_dmac_lmdesc_addr(channel, lmdesc) != crla) { lmdesc = rz_dmac_get_next_lmdesc(channel->lmdesc.base, lmdesc); if (++i >= DMAC_NR_LMDESC) return 0; @@ -948,13 +948,13 @@ static u32 rz_dmac_calculate_residue_bytes_in_vd(struct rz_dmac_chan *channel, u32 start_lmdesc_addr = rz_dmac_lmdesc_addr(channel, desc->start_lmdesc); while (lmdesc->nxla != start_lmdesc_addr) { - residue += lmdesc->tb; lmdesc = rz_dmac_get_next_lmdesc(channel->lmdesc.base, lmdesc); + residue += lmdesc->tb; } } else { while (lmdesc->chcfg & CHCFG_DEM) { - residue += lmdesc->tb; lmdesc = rz_dmac_get_next_lmdesc(channel->lmdesc.base, lmdesc); + residue += lmdesc->tb; } } From 11101a8e3e42273a5910a149f6324040b88f4747 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:14 +0200 Subject: [PATCH 108/149] dmaengine: ste_dma40: Fix physical cyclic capability d40_dmaengine_init() configures dma_both for physical channels that can handle both slave and memcpy transfers. Physical DMA40 channel setup has supported cyclic LLIs since cyclic transfer support was added, but the DMA_CYCLIC capability is set on dma_slave a second time instead of dma_both. Set DMA_CYCLIC on dma_both so d40_ops_init() installs device_prep_dma_cyclic and physical channels advertise cyclic support. Fixes: 0c842b551063 ("dma40: cyclic xfer support") Reviewed-by: Frank Li Assisted-by: LLM Signed-off-by: Linus Walleij Link: https://patch.msgid.link/20260927-dma40-fixes-v7-1-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 05e797496cae..5f5549896922 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -2892,7 +2892,7 @@ static int __init d40_dmaengine_init(struct d40_base *base, dma_cap_zero(base->dma_both.cap_mask); dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask); dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask); - dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask); + dma_cap_set(DMA_CYCLIC, base->dma_both.cap_mask); d40_ops_init(base, &base->dma_both); err = dmaenginem_async_device_register(&base->dma_both); From c80edceff29ee212987c2d2c851b2cb2eb4b477a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:15 +0200 Subject: [PATCH 109/149] dmaengine: ste_dma40: Fix cyclic transfer residue DMA40 reads residue from the element count of the currently active LLI. For a cyclic transfer this reports at most one period, not the bytes remaining until the cyclic buffer wraps. Once DMA40 advertises burst granularity, DMAengine PCM uses this residue directly. For a four-period PCM buffer it consequently reports the hardware pointer near three periods after every period interrupt. ALSA eventually stops playback with -EIO although DMA period callbacks continue. Calculate cyclic residue from the current memory-side hardware pointer instead. Read the destination pointer for capture and the source pointer for playback. Sample the split logical channel pointer coherently and retain the last valid residue during relink transitions. Make at most three residue sampling attempts: one initial read plus two retries. The retries let transient split-register updates or LLI relink windows settle, while the limit prevents unbounded polling if hardware does not yield a valid pointer. This avoids counting terminal-count interrupts, which races with hardware advancing to the next LLI and cannot account for coalesced interrupt status. Also reject cyclic periods that expand into multiple LLIs because logical cyclic LLIs each request a terminal-count interrupt and would generate more than one callback per period. Reject invalid cyclic geometries before dividing or constructing the scatterlist as well. Reported-by: Frank Li Closes: https://lore.kernel.org/dmaengine/aq2wIPJW6viUxyy9@SMW015318/ Fixes: 15c606686541 ("dmaengine: ste_dma40: indicate granularity on channels") Assisted-by: LLM Reviewed-by: Frank Li Signed-off-by: Linus Walleij Link: https://patch.msgid.link/20260927-dma40-fixes-v7-2-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 106 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 101 insertions(+), 5 deletions(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 5f5549896922..8a99c0033048 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -65,6 +65,9 @@ struct stedma40_platform_data { /* Maximum iterations taken before giving up suspending a channel */ #define D40_SUSPEND_MAX_IT 500 +/* Maximum attempts to sample a stable cyclic residue position */ +#define D40_RESIDUE_MAX_ATTEMPTS 3 + /* Milliseconds */ #define DMA40_AUTOSUSPEND_DELAY 100 @@ -378,6 +381,9 @@ struct d40_lli_pool { * @lli_len: Number of llis of current descriptor. * @lli_current: Number of transferred llis. * @lcla_alloc: Number of LCLA entries allocated. + * @cyclic_dma_addr: Start address of the cyclic buffer. + * @cyclic_buf_len: Length of the cyclic buffer. + * @cyclic_residue: Last valid cyclic residue sample. * @txd: DMA engine struct. Used for among other things for communication * during a transfer. * @node: List entry. @@ -396,6 +402,9 @@ struct d40_desc { int lli_len; int lli_current; int lcla_alloc; + dma_addr_t cyclic_dma_addr; + size_t cyclic_buf_len; + size_t cyclic_residue; struct dma_async_tx_descriptor txd; struct list_head node; @@ -1415,6 +1424,64 @@ static u32 d40_residue(struct d40_chan *d40c) return num_elt * d40c->dma_cfg.dst_info.data_width; } +static bool d40_current_addr(struct d40_chan *d40c, dma_addr_t *addr) +{ + bool dst = d40c->dma_cfg.dir == DMA_DEV_TO_MEM; + void __iomem *high_reg; + void __iomem *low_reg; + u32 low; + u32 high; + u32 check; + int i; + + if (chan_is_physical(d40c)) { + *addr = readl(chan_base(d40c) + + (dst ? D40_CHAN_REG_SDPTR : D40_CHAN_REG_SSPTR)); + return true; + } + + if (dst) { + low_reg = &d40c->lcpa->lcsp2; + high_reg = &d40c->lcpa->lcsp3; + } else { + low_reg = &d40c->lcpa->lcsp0; + high_reg = &d40c->lcpa->lcsp1; + } + + for (i = 0; i < D40_RESIDUE_MAX_ATTEMPTS; i++) { + high = readl(high_reg) & D40_MEM_LCSP1_SPTR_MASK; + low = readl(low_reg) & D40_MEM_LCSP0_SPTR_MASK; + check = readl(high_reg) & D40_MEM_LCSP1_SPTR_MASK; + if (high == check) { + *addr = low | high; + return true; + } + } + + return false; +} + +static bool d40_cyclic_offset(struct d40_chan *d40c, struct d40_desc *d40d, + size_t *offset) +{ + dma_addr_t current_addr; + dma_addr_t current_offset; + int i; + + for (i = 0; i < D40_RESIDUE_MAX_ATTEMPTS; i++) { + if (!d40_current_addr(d40c, ¤t_addr)) + continue; + + current_offset = current_addr - d40d->cyclic_dma_addr; + if (current_offset <= d40d->cyclic_buf_len) { + *offset = current_offset; + return true; + } + } + + return false; +} + static bool d40_tx_is_linked(struct d40_chan *d40c) { bool is_link; @@ -2103,15 +2170,26 @@ static bool d40_is_paused(struct d40_chan *d40c) } -static u32 stedma40_residue(struct dma_chan *chan) +static u32 stedma40_residue(struct dma_chan *chan, dma_cookie_t cookie) { struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); + struct d40_desc *d40d; + size_t offset; u32 bytes_left; unsigned long flags; spin_lock_irqsave(&d40c->lock, flags); - bytes_left = d40_residue(d40c); + d40d = d40_first_active_get(d40c); + if (d40d && d40d->txd.cookie == cookie && d40d->cyclic && + d40d->cyclic_buf_len) { + if (d40_cyclic_offset(d40c, d40d, &offset)) + d40d->cyclic_residue = d40d->cyclic_buf_len - offset; + bytes_left = d40d->cyclic_residue; + } else { + bytes_left = d40_residue(d40c); + } + spin_unlock_irqrestore(&d40c->lock, flags); return bytes_left; @@ -2241,8 +2319,13 @@ d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src, if (desc == NULL) goto unlock; - if (sg_next(&sg_src[sg_len - 1]) == sg_src) + if (sg_next(&sg_src[sg_len - 1]) == sg_src) { desc->cyclic = true; + if (desc->lli_len != sg_len) { + chan_err(chan, "Cyclic periods must fit in one LLI\n"); + goto free_desc; + } + } src_dev_addr = 0; dst_dev_addr = 0; @@ -2519,11 +2602,18 @@ dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, size_t period_len, enum dma_transfer_direction direction, unsigned long flags) { - unsigned int periods = buf_len / period_len; + unsigned int periods; struct dma_async_tx_descriptor *txd; + struct d40_desc *desc; struct scatterlist *sg; + dma_addr_t buf_addr = dma_addr; int i; + if (!buf_len || !period_len || buf_len % period_len) + return NULL; + + periods = buf_len / period_len; + sg = kzalloc_objs(struct scatterlist, periods + 1, GFP_NOWAIT); if (!sg) return NULL; @@ -2538,6 +2628,12 @@ dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr, txd = d40_prep_sg(chan, sg, sg, periods, direction, DMA_PREP_INTERRUPT); + if (txd) { + desc = container_of(txd, struct d40_desc, txd); + desc->cyclic_dma_addr = buf_addr; + desc->cyclic_buf_len = buf_len; + desc->cyclic_residue = buf_len; + } kfree(sg); @@ -2558,7 +2654,7 @@ static enum dma_status d40_tx_status(struct dma_chan *chan, ret = dma_cookie_status(chan, cookie, txstate); if (ret != DMA_COMPLETE && txstate) - dma_set_residue(txstate, stedma40_residue(chan)); + dma_set_residue(txstate, stedma40_residue(chan, cookie)); if (d40_is_paused(d40c)) ret = DMA_PAUSED; From db28400d92cd97005065dad230b8a5d72ab121cb Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:16 +0200 Subject: [PATCH 110/149] dmaengine: ste_dma40: Recover coalesced cyclic callbacks DMA40 has one terminal-count status bit per channel, so cyclic period interrupts can coalesce. Use the memory-side pointer displacement to queue the minimum observable number of callbacks. If sampling fails, queue one callback and invalidate the saved position; the next successful sample resynchronizes without recounting it. The pointer is modulo the cyclic buffer: a displacement of d periods can mean d plus n complete iterations of the buffer. Report d, so the driver could have missed n iterations of the buffer; DMA40 has no counter to recover them. For an unchanged pointer, report one callback rather than risk a spurious full-buffer burst. This condition has not been seen in practice and is only a product of review comments that the buffer can miss interrupts. The preceding cyclic-residue fix ensures that every cyclic period fits in one LLI, so each boundary corresponds to one client callback. Fixes: 0c842b551063 ("dma40: cyclic xfer support") Assisted-by: LLM Signed-off-by: Linus Walleij Reviewed-by: Frank Li Link: https://patch.msgid.link/20260927-dma40-fixes-v7-3-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 69 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 8a99c0033048..45b4f4140a6f 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -384,11 +384,14 @@ struct d40_lli_pool { * @cyclic_dma_addr: Start address of the cyclic buffer. * @cyclic_buf_len: Length of the cyclic buffer. * @cyclic_residue: Last valid cyclic residue sample. + * @cyclic_period_len: Length of one cyclic period. + * @cyclic_callback_pos: Position after the callbacks already queued. * @txd: DMA engine struct. Used for among other things for communication * during a transfer. * @node: List entry. * @is_in_client_list: true if the client owns this descriptor. * @cyclic: true if this is a cyclic job + * @cyclic_callback_pos_valid: Whether cyclic_callback_pos is reliable. * * This descriptor is used for both logical and physical transfers. */ @@ -405,12 +408,15 @@ struct d40_desc { dma_addr_t cyclic_dma_addr; size_t cyclic_buf_len; size_t cyclic_residue; + size_t cyclic_period_len; + size_t cyclic_callback_pos; struct dma_async_tx_descriptor txd; struct list_head node; bool is_in_client_list; bool cyclic; + bool cyclic_callback_pos_valid; }; /** @@ -1482,6 +1488,61 @@ static bool d40_cyclic_offset(struct d40_chan *d40c, struct d40_desc *d40d, return false; } +static unsigned int d40_cyclic_periods_elapsed(struct d40_chan *d40c, + struct d40_desc *d40d) +{ + size_t current_pos; + size_t delta; + size_t offset; + unsigned int periods; + + if (!d40d->cyclic_period_len) + return 1; + + if (!d40_cyclic_offset(d40c, d40d, &offset)) { + d40d->cyclic_callback_pos_valid = false; + return 1; + } + + current_pos = rounddown(offset, d40d->cyclic_period_len); + if (!d40_residue(d40c) && current_pos != offset) + current_pos += d40d->cyclic_period_len; + if (current_pos == d40d->cyclic_buf_len) + current_pos = 0; + + if (!d40d->cyclic_callback_pos_valid) { + /* + * The previous interrupt was reported without a pointer + * sample. Resynchronize without using the stale position, + * which would count that callback again. + */ + d40d->cyclic_callback_pos = current_pos; + d40d->cyclic_callback_pos_valid = true; + return 1; + } + + /* + * The pointer wraps with the cyclic buffer, so its displacement is + * only the minimum number of elapsed periods. Complete buffer laps + * are not observable. + */ + delta = (current_pos + d40d->cyclic_buf_len - + d40d->cyclic_callback_pos) % d40d->cyclic_buf_len; + periods = delta / d40d->cyclic_period_len; + if (!periods) { + /* + * The TC status is a single latched bit. An unchanged pointer + * cannot distinguish a complete lap from a repeated interrupt, + * so do not amplify it into a buffer's worth of callbacks. + */ + periods = 1; + } + + d40d->cyclic_callback_pos = current_pos; + + return periods; +} + static bool d40_tx_is_linked(struct d40_chan *d40c) { bool is_link; @@ -1604,6 +1665,7 @@ static struct d40_desc *d40_queue_start(struct d40_chan *d40c) static void dma_tc_handle(struct d40_chan *d40c) { struct d40_desc *d40d; + unsigned int callbacks = 1; /* Get first active entry from list */ d40d = d40_first_active_get(d40c); @@ -1628,6 +1690,8 @@ static void dma_tc_handle(struct d40_chan *d40c) if (d40d->lli_current == d40d->lli_len) d40d->lli_current = 0; } + + callbacks = d40_cyclic_periods_elapsed(d40c, d40d); } else { d40_lcla_free_all(d40c, d40d); @@ -1648,7 +1712,7 @@ static void dma_tc_handle(struct d40_chan *d40c) d40_desc_done(d40c, d40d); } - d40c->pending_tx++; + d40c->pending_tx += callbacks; tasklet_schedule(&d40c->tasklet); } @@ -2633,6 +2697,9 @@ dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr, desc->cyclic_dma_addr = buf_addr; desc->cyclic_buf_len = buf_len; desc->cyclic_residue = buf_len; + desc->cyclic_period_len = period_len; + desc->cyclic_callback_pos = 0; + desc->cyclic_callback_pos_valid = true; } kfree(sg); From 8175ead5727173d4b96d1e830e696765d75ade71 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:17 +0200 Subject: [PATCH 111/149] dmaengine: ste_dma40: Fix failed start cleanup If d40_start() fails after a queued descriptor has been moved to the active list, d40_queue_start() currently returns NULL without unwinding the transfer state or clearing the channel busy flag. Fix this pre-existing error path by completing the descriptor through the normal tasklet path, clearing the busy flag, balancing the runtime PM reference and returning an error pointer to distinguish the failure from the no-work case. Do not free the descriptor directly, since it has already been submitted and has a DMA cookie. When starting the next queued transfer from the completion handler, put the completed descriptor on the done list first. This preserves FIFO completion order if the new transfer fails to start and prevents the completed cookie from moving backwards. Use done-list membership rather than the cyclic flag to identify terminal descriptors in the tasklet. A cyclic descriptor that failed to start is then completed and removed instead of remaining permanently at the head of the done list. Fixes: 7d83a854a1a4 ("dma40: remove "hardware link with previous jobs" code") Reported-by: sashiko-bot@kernel.org Closes: https://lore.kernel.org/dmaengine/20260618051539.15E201F000E9@smtp.kernel.org/ Reviewed-by: Frank Li Assisted-by: LLM Link: https://lore.kernel.org/dmaengine/20260618051539.15E201F000E9@smtp.kernel.org/ Signed-off-by: Linus Walleij Link: https://patch.msgid.link/20260927-dma40-fixes-v7-4-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 45b4f4140a6f..19f62de5ad3b 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -1654,8 +1654,15 @@ static struct d40_desc *d40_queue_start(struct d40_chan *d40c) /* Start dma job */ err = d40_start(d40c); - if (err) - return NULL; + if (err) { + d40_desc_remove(d40d); + d40_desc_done(d40c, d40d); + d40c->pending_tx++; + d40c->busy = false; + pm_runtime_put_autosuspend(d40c->base->dev); + tasklet_schedule(&d40c->tasklet); + return ERR_PTR(err); + } } return d40d; @@ -1702,14 +1709,14 @@ static void dma_tc_handle(struct d40_chan *d40c) return; } + d40_desc_remove(d40d); + d40_desc_done(d40c, d40d); + if (d40_queue_start(d40c) == NULL) { d40c->busy = false; pm_runtime_put_autosuspend(d40c->base->dev); } - - d40_desc_remove(d40d); - d40_desc_done(d40c, d40d); } d40c->pending_tx += callbacks; @@ -1723,20 +1730,22 @@ static void dma_tasklet(struct tasklet_struct *t) struct d40_desc *d40d; unsigned long flags; bool callback_active; + bool from_done; struct dmaengine_desc_callback cb; spin_lock_irqsave(&d40c->lock, flags); /* Get first entry from the done list */ d40d = d40_first_done(d40c); - if (d40d == NULL) { + from_done = !!d40d; + if (!from_done) { /* Check if we have reached here for cyclic job */ d40d = d40_first_active_get(d40c); if (d40d == NULL || !d40d->cyclic) goto check_pending_tx; } - if (!d40d->cyclic) + if (from_done) dma_cookie_complete(&d40d->txd); /* @@ -1752,7 +1761,7 @@ static void dma_tasklet(struct tasklet_struct *t) callback_active = !!(d40d->txd.flags & DMA_PREP_INTERRUPT); dmaengine_desc_get_callback(&d40d->txd, &cb); - if (!d40d->cyclic) { + if (from_done) { if (async_tx_test_ack(&d40d->txd)) { d40_desc_remove(d40d); d40_desc_free(d40c, d40d); From c6809b381e34f8966cc3d9e5d7d658775a408f83 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:18 +0200 Subject: [PATCH 112/149] dmaengine: ste_dma40: Fix probe runtime PM disable Some d40_probe() error paths jump to destroy_cache before runtime PM has been enabled for the DMA controller device. The label unconditionally calls pm_runtime_disable(), which increments disable_depth even though this probe attempt never enabled runtime PM. Use devm_pm_runtime_set_active_enabled() to mark the controller active, enable runtime PM and register balanced cleanup for probe failure. This avoids both the disable-depth imbalance and ad-hoc probe state tracking. The interrupt handler uses pm_runtime_get_if_active() and cannot acknowledge a pending interrupt while runtime PM is disabled. Request the IRQ only after enabling runtime PM so the handler cannot enter an unacknowledged interrupt loop during probe. Fixes: 0618c077a8c2 ("dmaengine: ste_dma40: Fix PM disable depth imbalance in d40_probe") Reported-by: sashiko-bot@kernel.org Closes: https://lore.kernel.org/dmaengine/20260618051539.15E201F000E9@smtp.kernel.org/ Assisted-by: LLM Reviewed-by: Frank Li Signed-off-by: Linus Walleij Link: https://patch.msgid.link/20260927-dma40-fixes-v7-5-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 19f62de5ad3b..e405ffd729b1 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -3752,12 +3752,6 @@ static int __init d40_probe(struct platform_device *pdev) goto destroy_cache; } - ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base); - if (ret) { - d40_err(dev, "No IRQ defined\n"); - goto destroy_cache; - } - if (base->plat_data->use_esram_lcla) { base->lcpa_regulator = regulator_get(base->dev, "lcla_esram"); @@ -3782,10 +3776,20 @@ static int __init d40_probe(struct platform_device *pdev) pm_runtime_irq_safe(base->dev); pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY); - pm_runtime_use_autosuspend(base->dev); pm_runtime_mark_last_busy(base->dev); - pm_runtime_set_active(base->dev); - pm_runtime_enable(base->dev); + + ret = devm_pm_runtime_set_active_enabled(base->dev); + if (ret) { + d40_err(dev, "Failed to enable runtime PM: %d\n", ret); + goto destroy_cache; + } + pm_runtime_use_autosuspend(base->dev); + + ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base); + if (ret) { + d40_err(dev, "No IRQ defined\n"); + goto destroy_cache; + } ret = d40_dmaengine_init(base, num_reserved_chans); if (ret) @@ -3821,7 +3825,6 @@ static int __init d40_probe(struct platform_device *pdev) regulator_disable(base->lcpa_regulator); regulator_put(base->lcpa_regulator); } - pm_runtime_disable(base->dev); report_failure: d40_err(dev, "probe failed\n"); From 12787e3f2f93f3af59769b08ee4fcb044531120b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:19 +0200 Subject: [PATCH 113/149] dmaengine: ste_dma40: Check runtime PM in IRQ d40_handle_interrupt() reads DMA40 interrupt registers unconditionally. A spurious interrupt can arrive while the device is runtime suspended, after dma40_runtime_suspend() has disabled the GCC clock. Avoid touching the registers unless the device is runtime active by taking a conditional runtime PM reference. Return IRQ_NONE when the device is suspended, and drop the reference after handling an active interrupt. When CONFIG_PM is disabled, pm_runtime_get_if_active() returns -EINVAL even though the registers remain accessible. Keep handling interrupts in that configuration and only drop the runtime PM reference when one was acquired. Fixes: 7fb3e75e1833 ("dmaengine/ste_dma40: support pm in dma40") Reported-by: sashiko-bot@kernel.org Closes: https://lore.kernel.org/dmaengine/20260819225114.AE1511F000E9@smtp.kernel.org/ Reviewed-by: Frank Li Assisted-by: LLM Signed-off-by: Linus Walleij Link: https://patch.msgid.link/20260927-dma40-fixes-v7-6-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index e405ffd729b1..279da2882a43 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -1802,6 +1802,11 @@ static irqreturn_t d40_handle_interrupt(int irq, void *data) u32 *regs = base->regs_interrupt; struct d40_interrupt_lookup *il = base->gen_dmac.il; u32 il_size = base->gen_dmac.il_size; + int ret; + + ret = pm_runtime_get_if_active(base->dev); + if (IS_ENABLED(CONFIG_PM) && ret <= 0) + return IRQ_NONE; spin_lock(&base->interrupt_lock); @@ -1850,6 +1855,9 @@ static irqreturn_t d40_handle_interrupt(int irq, void *data) spin_unlock(&base->interrupt_lock); + if (ret > 0) + pm_runtime_put_autosuspend(base->dev); + return IRQ_HANDLED; } From 55a35231b8ced2250a7743ec350a9566d553780e Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:20 +0200 Subject: [PATCH 114/149] dmaengine: ste_dma40: Handle runtime PM resume errors Several channel operations use pm_runtime_get_sync() and access DMA40 registers without checking whether runtime resume succeeded. If resume fails, the registers may be inaccessible. pm_runtime_get_sync() also increments the usage counter on failure, making error unwinding easy to unbalance. Use pm_runtime_resume_and_get() and avoid register access when resume fails. Acquire the runtime PM reference before allocating a channel so failure needs no channel-allocation rollback. If a queued transfer cannot be started because resume failed, retire all issued descriptors through the normal tasklet path. Since dma_async_issue_pending() cannot return an error, leaving them queued would make clients wait indefinitely for callbacks. Termination and channel release must also clean up software state when the controller cannot resume. d40_term_all() only releases descriptor state and does not access DMA40 registers, so it remains unconditional. Balance each transient runtime PM reference in its successful acquisition block, without bookkeeping flags. Release the outstanding busy reference and channel allocation state when freeing a channel. Skip only the hardware stop that requires register access. Fixes: 7fb3e75e1833 ("dmaengine/ste_dma40: support pm in dma40") Assisted-by: LLM Reviewed-by: Frank Li Signed-off-by: Linus Walleij Link: https://patch.msgid.link/20260927-dma40-fixes-v7-7-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 74 +++++++++++++++++++++++++++++------------ 1 file changed, 52 insertions(+), 22 deletions(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 279da2882a43..03c43116e3ec 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -1571,11 +1571,14 @@ static int d40_pause(struct dma_chan *chan) return 0; spin_lock_irqsave(&d40c->lock, flags); - pm_runtime_get_sync(d40c->base->dev); + res = pm_runtime_resume_and_get(d40c->base->dev); + if (res < 0) + goto unlock; res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ); pm_runtime_put_autosuspend(d40c->base->dev); + unlock: spin_unlock_irqrestore(&d40c->lock, flags); return res; } @@ -1595,13 +1598,16 @@ static int d40_resume(struct dma_chan *chan) return 0; spin_lock_irqsave(&d40c->lock, flags); - pm_runtime_get_sync(d40c->base->dev); + res = pm_runtime_resume_and_get(d40c->base->dev); + if (res < 0) + goto unlock; /* If bytes left to transfer or linked tx resume job */ if (d40_residue(d40c) || d40_tx_is_linked(d40c)) res = d40_channel_execute_command(d40c, D40_DMA_RUN); pm_runtime_put_autosuspend(d40c->base->dev); + unlock: spin_unlock_irqrestore(&d40c->lock, flags); return res; } @@ -1638,8 +1644,20 @@ static struct d40_desc *d40_queue_start(struct d40_chan *d40c) if (d40d != NULL) { if (!d40c->busy) { + err = pm_runtime_resume_and_get(d40c->base->dev); + if (err < 0) { + chan_err(d40c, "Failed to resume DMA: %d\n", + err); + do { + d40_desc_remove(d40d); + d40_desc_done(d40c, d40d); + d40c->pending_tx++; + d40d = d40_first_queued(d40c); + } while (d40d); + tasklet_schedule(&d40c->tasklet); + return ERR_PTR(err); + } d40c->busy = true; - pm_runtime_get_sync(d40c->base->dev); } /* Remove from queue */ @@ -2156,9 +2174,6 @@ static int d40_free_dma(struct d40_chan *d40c) struct d40_phy_res *phy = d40c->phy_chan; bool is_src; - /* Terminate all queued and active transfers */ - d40_term_all(d40c); - if (phy == NULL) { chan_err(d40c, "phy == null\n"); return -EINVAL; @@ -2180,11 +2195,18 @@ static int d40_free_dma(struct d40_chan *d40c) return -EINVAL; } - pm_runtime_get_sync(d40c->base->dev); - res = d40_channel_execute_command(d40c, D40_DMA_STOP); - if (res) { - chan_err(d40c, "stop failed\n"); - goto mark_last_busy; + /* Release descriptor state; this does not access DMA40 registers. */ + d40_term_all(d40c); + + res = pm_runtime_resume_and_get(d40c->base->dev); + if (res >= 0) { + res = d40_channel_execute_command(d40c, D40_DMA_STOP); + if (res) + chan_err(d40c, "stop failed\n"); + + pm_runtime_put_autosuspend(d40c->base->dev); + if (res) + return res; } d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0); @@ -2200,8 +2222,6 @@ static int d40_free_dma(struct d40_chan *d40c) d40c->busy = false; d40c->phy_chan = NULL; d40c->configured = false; - mark_last_busy: - pm_runtime_put_autosuspend(d40c->base->dev); return res; } @@ -2576,10 +2596,14 @@ static int d40_alloc_chan_resources(struct dma_chan *chan) err = d40_config_memcpy(d40c); if (err) { chan_err(d40c, "Failed to configure memcpy channel\n"); - goto mark_last_busy; + goto unlock; } } + err = pm_runtime_resume_and_get(d40c->base->dev); + if (err < 0) + goto unlock; + err = d40_allocate_channel(d40c, &is_free_phy); if (err) { chan_err(d40c, "Failed to allocate channel\n"); @@ -2587,8 +2611,6 @@ static int d40_alloc_chan_resources(struct dma_chan *chan) goto mark_last_busy; } - pm_runtime_get_sync(d40c->base->dev); - d40_set_prio_realtime(d40c); if (chan_is_logical(d40c)) { @@ -2620,6 +2642,7 @@ static int d40_alloc_chan_resources(struct dma_chan *chan) d40_config_write(d40c); mark_last_busy: pm_runtime_put_autosuspend(d40c->base->dev); + unlock: spin_unlock_irqrestore(&d40c->lock, flags); return err; } @@ -2780,19 +2803,26 @@ static int d40_terminate_all(struct dma_chan *chan) spin_lock_irqsave(&d40c->lock, flags); - pm_runtime_get_sync(d40c->base->dev); - ret = d40_channel_execute_command(d40c, D40_DMA_STOP); - if (ret) - chan_err(d40c, "Failed to stop channel\n"); + ret = pm_runtime_resume_and_get(d40c->base->dev); + if (ret >= 0) { + ret = d40_channel_execute_command(d40c, D40_DMA_STOP); + if (ret) + chan_err(d40c, "Failed to stop channel\n"); + pm_runtime_put_autosuspend(d40c->base->dev); + } + + /* + * Always release software state, even when the controller cannot + * resume. d40_term_all() does not access DMA40 registers. + */ d40_term_all(d40c); - pm_runtime_put_autosuspend(d40c->base->dev); if (d40c->busy) pm_runtime_put_autosuspend(d40c->base->dev); d40c->busy = false; spin_unlock_irqrestore(&d40c->lock, flags); - return 0; + return ret; } static int From b96967644c524d34b2fdd2e58c31e7b36e3469e6 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:21 +0200 Subject: [PATCH 115/149] dmaengine: ste_dma40: Return IRQ_NONE when no interrupt is pending d40_handle_interrupt() returns IRQ_HANDLED even when no terminal-count or error status bit is pending. IRQ_NONE is not only used to identify a device on a shared interrupt. The generic IRQ core also counts it as unhandled for spurious IRQ detection. DMA40 does not request this IRQ with IRQF_SHARED, so interrupt sharing is not the purpose of this change. If the line remains asserted without matching DMA40 status, returning IRQ_HANDLED hides the stuck interrupt and can leave the CPU servicing it indefinitely. Track whether any DMA40 status is pending and return IRQ_NONE when none is present, allowing the generic IRQ core to diagnose and eventually disable the faulty line. DMA40 channels can be owned by other SoC cores. Their status means that the interrupt is real, but Linux must not acknowledge it. Treat foreign status as handled and leave its acknowledgment to the owning core, while acknowledging and dispatching only registered Linux channels. Fixes: 8d318a50b3d7 ("DMAENGINE: Support for ST-Ericssons DMA40 block v3") Assisted-by: LLM Reviewed-by: Frank Li Signed-off-by: Linus Walleij Link: https://patch.msgid.link/20260927-dma40-fixes-v7-8-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 03c43116e3ec..fddafa8c4886 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -1811,6 +1811,7 @@ static void dma_tasklet(struct tasklet_struct *t) static irqreturn_t d40_handle_interrupt(int irq, void *data) { + irqreturn_t handled = IRQ_NONE; int i; u32 idx; u32 row; @@ -1844,6 +1845,12 @@ static irqreturn_t d40_handle_interrupt(int irq, void *data) row = chan / BITS_PER_LONG; idx = chan & (BITS_PER_LONG - 1); + /* + * Status for a channel owned by another core still explains + * the interrupt, but only ACK Linux-owned channels below. + */ + handled = IRQ_HANDLED; + if (il[row].offset == D40_PHY_CHAN) d40c = base->lookup_phy_chans[idx]; else @@ -1876,7 +1883,7 @@ static irqreturn_t d40_handle_interrupt(int irq, void *data) if (ret > 0) pm_runtime_put_autosuspend(base->dev); - return IRQ_HANDLED; + return handled; } static int d40_validate_conf(struct d40_chan *d40c, From ffd583a734dc4bdafb9e18d9aa48b6efafd1a628 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:22 +0200 Subject: [PATCH 116/149] dmaengine: ste_dma40: Init hardware before registration d40_probe() enables the interrupt handler and registers DMAengine devices before calling d40_hw_init(). An interrupt pending from the bootloader can therefore reach the handler while the hardware interrupt state is not initialized and channel lookup entries are empty. The handler deliberately does not acknowledge an interrupt for an unknown channel, so a level IRQ can retrigger continuously. Initialize the hardware and set the DMA segment limit before requesting the IRQ or registering DMAengine devices. d40_hw_init() clears pending logical and physical interrupt status, so request_irq() can enable the line normally after the hardware state is initialized. This ensures that the handler and clients only observe initialized hardware. Fixes: 8d318a50b3d7 ("DMAENGINE: Support for ST-Ericssons DMA40 block v3") Reported-by: sashiko-bot@kernel.org Closes: https://lore.kernel.org/dmaengine/20260819225215.5EA2F1F000E9@smtp.kernel.org/ Assisted-by: LLM Signed-off-by: Linus Walleij Reviewed-by: Frank Li Link: https://patch.msgid.link/20260927-dma40-fixes-v7-9-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index fddafa8c4886..1035bc7fa55d 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -3830,20 +3830,19 @@ static int __init d40_probe(struct platform_device *pdev) } pm_runtime_use_autosuspend(base->dev); + dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE); + + d40_hw_init(base); + ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base); if (ret) { d40_err(dev, "No IRQ defined\n"); goto destroy_cache; } - ret = d40_dmaengine_init(base, num_reserved_chans); if (ret) goto destroy_cache; - dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE); - - d40_hw_init(base); - ret = of_dma_controller_register(np, d40_xlate, NULL); if (ret) { dev_err(dev, From 7ca608cf6b842685bbbe131d4f7d638f7cdc2b5d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:23 +0200 Subject: [PATCH 117/149] dmaengine: ste_dma40: Fix probe IRQ leak d40_probe() registers the hardware interrupt before several later probe steps that can fail. Those error paths jump to destroy_cache without freeing the IRQ, leaving the handler registered after probe resources have been released. Route failures after a successful IRQ request through a dedicated cleanup label. Keep the request before DMAengine registration because that registration publishes channels to clients. Fixes: 8d318a50b3d7 ("DMAENGINE: Support for ST-Ericssons DMA40 block v3") Reported-by: sashiko-bot@kernel.org Closes: https://lore.kernel.org/dmaengine/20260618051539.15E201F000E9@smtp.kernel.org/ Assisted-by: LLM Signed-off-by: Linus Walleij Reviewed-by: Frank Li Link: https://patch.msgid.link/20260927-dma40-fixes-v7-10-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 1035bc7fa55d..57b60cf7194c 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -3841,18 +3841,20 @@ static int __init d40_probe(struct platform_device *pdev) } ret = d40_dmaengine_init(base, num_reserved_chans); if (ret) - goto destroy_cache; + goto release_irq; ret = of_dma_controller_register(np, d40_xlate, NULL); if (ret) { dev_err(dev, "could not register of_dma_controller\n"); - goto destroy_cache; + goto release_irq; } dev_info(base->dev, "initialized\n"); return 0; + release_irq: + free_irq(base->irq, base); destroy_cache: if (base->lcla_pool.dma_addr) dma_unmap_single(base->dev, base->lcla_pool.dma_addr, From f71ef686f913c8e9771a54466a76d653b83cd3dd Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:24 +0200 Subject: [PATCH 118/149] dmaengine: ste_dma40: Fix DMA registration unwind d40_dmaengine_init() registers DMAengine devices using devres-managed unregister actions. If probe fails after one of those registrations, the DMAengine devices stay visible until devres unwinds after d40_probe() returns. The channel tasklets are also initialized before each DMAengine device is registered. An interrupt can therefore have queued a tasklet by the time a later registration step fails, but unregistering the DMAengine devices does not drain that tasklet before probe-owned storage is released. Add tasklet cleanup actions to the DMAengine registration devres group. Install each action before publishing its DMAengine device. If action registration fails, those tasklets have never been exposed and cannot have been scheduled, so use devm_add_action() without immediate reset cleanup. On later failure, free the IRQ before releasing the group so no new tasklets can be scheduled, then unregister the DMAengine devices and drain their tasklets before freeing the remaining probe resources. Keep the managed registrations and cleanup actions in place on successful probe by removing only the temporary group markers. Fixes: 42ae6f1695be ("dmaengine: ste_dma40: Remove platform data") Reported-by: sashiko-bot@kernel.org Closes: https://lore.kernel.org/dmaengine/20260819225215.5EA2F1F000E9@smtp.kernel.org/ Assisted-by: LLM Signed-off-by: Linus Walleij Reviewed-by: Frank Li Link: https://patch.msgid.link/20260927-dma40-fixes-v7-11-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 45 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 43 insertions(+), 2 deletions(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 57b60cf7194c..ee6542491279 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -3034,6 +3034,18 @@ static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma, } } +static void d40_kill_tasklets(void *data) +{ + struct dma_device *dma = data; + struct d40_chan *d40c; + struct dma_chan *chan; + + list_for_each_entry(chan, &dma->channels, device_node) { + d40c = container_of(chan, struct d40_chan, chan); + tasklet_kill(&d40c->tasklet); + } +} + static void d40_ops_init(struct d40_base *base, struct dma_device *dev) { if (dma_has_cap(DMA_SLAVE, dev->cap_mask)) { @@ -3080,6 +3092,11 @@ static int __init d40_dmaengine_init(struct d40_base *base, d40_ops_init(base, &base->dma_slave); + err = devm_add_action(base->dev, d40_kill_tasklets, + &base->dma_slave); + if (err) + goto exit; + err = dmaenginem_async_device_register(&base->dma_slave); if (err) { @@ -3095,6 +3112,11 @@ static int __init d40_dmaengine_init(struct d40_base *base, d40_ops_init(base, &base->dma_memcpy); + err = devm_add_action(base->dev, d40_kill_tasklets, + &base->dma_memcpy); + if (err) + goto exit; + err = dmaenginem_async_device_register(&base->dma_memcpy); if (err) { @@ -3112,6 +3134,12 @@ static int __init d40_dmaengine_init(struct d40_base *base, dma_cap_set(DMA_CYCLIC, base->dma_both.cap_mask); d40_ops_init(base, &base->dma_both); + + err = devm_add_action(base->dev, d40_kill_tasklets, + &base->dma_both); + if (err) + goto exit; + err = dmaenginem_async_device_register(&base->dma_both); if (err) { @@ -3709,6 +3737,7 @@ static int __init d40_probe(struct platform_device *pdev) struct d40_base *base; struct resource *res; struct resource res_lcpa; + void *dmaenginem_reg_group; int num_reserved_chans; u32 val; int ret; @@ -3839,20 +3868,32 @@ static int __init d40_probe(struct platform_device *pdev) d40_err(dev, "No IRQ defined\n"); goto destroy_cache; } + + dmaenginem_reg_group = devres_open_group(dev, NULL, GFP_KERNEL); + if (!dmaenginem_reg_group) { + ret = -ENOMEM; + goto release_irq; + } + ret = d40_dmaengine_init(base, num_reserved_chans); if (ret) - goto release_irq; + goto release_dmaenginem; ret = of_dma_controller_register(np, d40_xlate, NULL); if (ret) { dev_err(dev, "could not register of_dma_controller\n"); - goto release_irq; + goto release_dmaenginem; } + devres_remove_group(dev, dmaenginem_reg_group); dev_info(base->dev, "initialized\n"); return 0; + release_dmaenginem: + free_irq(base->irq, base); + devres_release_group(dev, dmaenginem_reg_group); + goto destroy_cache; release_irq: free_irq(base->irq, base); destroy_cache: From 7d4dc355c574d414d2402ac481a2fc4ee51e2771 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:25 +0200 Subject: [PATCH 119/149] dmaengine: ste_dma40: Fix LCLA allocation order d40_lcla_allocate() calculates the number of pages needed for LCLA, but passes that raw page count as the allocation order to __get_free_pages(). The same value is later passed to free_pages(). Store the allocation order with get_order() instead, and use a separate byte size for allocation diagnostics, fallback kmalloc() sizing and DMA mapping. Fixes: 508849ade23c ("DMAENGINE: ste_dma40: allocate LCLA dynamically") Reported-by: sashiko-bot@kernel.org Closes: https://lore.kernel.org/dmaengine/20260819225114.AE1511F000E9@smtp.kernel.org/ Assisted-by: LLM Reviewed-by: Frank Li Signed-off-by: Linus Walleij Link: https://patch.msgid.link/20260927-dma40-fixes-v7-12-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 33 ++++++++++++++++----------------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index ee6542491279..f2d9b7fecb93 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -426,8 +426,8 @@ struct d40_desc { * @dma_addr: DMA address, if mapped * @base_unaligned: The original kmalloc pointer, if kmalloc is used. * This pointer is only there for clean-up on error. - * @pages: The number of pages needed for all physical channels. - * Only used later for clean-up on error + * @alloc_order: Order used for the LCLA page allocation. + * Only used later for clean-up on error. * @lock: Lock to protect the content in this struct. * @alloc_map: big map over which LCLA entry is own by which job. */ @@ -435,7 +435,7 @@ struct d40_lcla_pool { void *base; dma_addr_t dma_addr; void *base_unaligned; - int pages; + unsigned int alloc_order; spinlock_t lock; struct d40_desc **alloc_map; }; @@ -3598,6 +3598,7 @@ static void __init d40_hw_init(struct d40_base *base) static int __init d40_lcla_allocate(struct d40_base *base) { struct d40_lcla_pool *pool = &base->lcla_pool; + size_t lcla_size = SZ_1K * base->num_phy_chans; unsigned long *page_list; int i, j; int ret; @@ -3613,20 +3614,20 @@ static int __init d40_lcla_allocate(struct d40_base *base) if (!page_list) return -ENOMEM; - /* Calculating how many pages that are required */ - base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE; + base->lcla_pool.alloc_order = get_order(lcla_size); for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) { page_list[i] = __get_free_pages(GFP_KERNEL, - base->lcla_pool.pages); + base->lcla_pool.alloc_order); if (!page_list[i]) { - d40_err(base->dev, "Failed to allocate %d pages.\n", - base->lcla_pool.pages); + d40_err(base->dev, "Failed to allocate %zu bytes.\n", + lcla_size); ret = -ENOMEM; for (j = 0; j < i; j++) - free_pages(page_list[j], base->lcla_pool.pages); + free_pages(page_list[j], + base->lcla_pool.alloc_order); goto free_page_list; } @@ -3636,7 +3637,7 @@ static int __init d40_lcla_allocate(struct d40_base *base) } for (j = 0; j < i; j++) - free_pages(page_list[j], base->lcla_pool.pages); + free_pages(page_list[j], base->lcla_pool.alloc_order); if (i < MAX_LCLA_ALLOC_ATTEMPTS) { base->lcla_pool.base = (void *)page_list[i]; @@ -3646,10 +3647,9 @@ static int __init d40_lcla_allocate(struct d40_base *base) * alignment, try with allocating a big buffer. */ dev_warn(base->dev, - "[%s] Failed to get %d pages @ 18 bit align.\n", - __func__, base->lcla_pool.pages); - base->lcla_pool.base_unaligned = kmalloc(SZ_1K * - base->num_phy_chans + + "[%s] Failed to get %zu bytes @ 18 bit align.\n", + __func__, lcla_size); + base->lcla_pool.base_unaligned = kmalloc(lcla_size + LCLA_ALIGNMENT, GFP_KERNEL); if (!base->lcla_pool.base_unaligned) { @@ -3661,8 +3661,7 @@ static int __init d40_lcla_allocate(struct d40_base *base) LCLA_ALIGNMENT); } - pool->dma_addr = dma_map_single(base->dev, pool->base, - SZ_1K * base->num_phy_chans, + pool->dma_addr = dma_map_single(base->dev, pool->base, lcla_size, DMA_TO_DEVICE); if (dma_mapping_error(base->dev, pool->dma_addr)) { pool->dma_addr = 0; @@ -3904,7 +3903,7 @@ static int __init d40_probe(struct platform_device *pdev) if (!base->lcla_pool.base_unaligned && base->lcla_pool.base) free_pages((unsigned long)base->lcla_pool.base, - base->lcla_pool.pages); + base->lcla_pool.alloc_order); kfree(base->lcla_pool.base_unaligned); From 750dfcdb7a406bdd52d604099a631bbe96ddda91 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:26 +0200 Subject: [PATCH 120/149] dmaengine: ste_dma40: Fix probe LCLA free When LCLA is placed in ESRAM, d40_probe() stores a devm_ioremap() address in lcla_pool.base and leaves base_unaligned unset. The destroy_cache error path can then pass the ioremap address to free_pages(). Only free lcla_pool.base with free_pages() when the driver allocated the LCLA pool from normal memory. The ESRAM mapping is devm-managed. Fixes: 339f5041089a ("dmaengine: ste_dma40: Use managed resources") Reported-by: sashiko-bot@kernel.org Closes: https://lore.kernel.org/dmaengine/20260819225114.AE1511F000E9@smtp.kernel.org/ Assisted-by: LLM Reviewed-by: Frank Li Signed-off-by: Linus Walleij Link: https://patch.msgid.link/20260927-dma40-fixes-v7-13-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index f2d9b7fecb93..b2921305e076 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -3901,7 +3901,8 @@ static int __init d40_probe(struct platform_device *pdev) SZ_1K * base->num_phy_chans, DMA_TO_DEVICE); - if (!base->lcla_pool.base_unaligned && base->lcla_pool.base) + if (!base->plat_data->use_esram_lcla && + !base->lcla_pool.base_unaligned && base->lcla_pool.base) free_pages((unsigned long)base->lcla_pool.base, base->lcla_pool.alloc_order); From 9a3762b470421658214baeb6cce3eed7344bb435 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:27 +0200 Subject: [PATCH 121/149] dmaengine: ste_dma40: Put the LCPA SRAM node of_parse_phandle() takes a reference to the LCPA SRAM node, but d40_probe() does not release it after translating the node into a resource. This leaks the node reference for the lifetime of the system. Put the node immediately after of_address_to_resource() so both the success and error paths release the reference. Fixes: 5a1a3b9c19dd ("dmaengine: ste_dma40: Get LCPA SRAM from SRAM node") Assisted-by: LLM Reviewed-by: Frank Li Signed-off-by: Linus Walleij Link: https://patch.msgid.link/20260927-dma40-fixes-v7-14-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index b2921305e076..3885aca8a69e 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -3766,6 +3766,7 @@ static int __init d40_probe(struct platform_device *pdev) } /* This is no device so read the address directly from the node */ ret = of_address_to_resource(np_lcpa, 0, &res_lcpa); + of_node_put(np_lcpa); if (ret) { dev_err(dev, "no LCPA SRAM resource\n"); goto report_failure; From f2baf04a695de4f952513cb00ccf0338c6db2e00 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:28 +0200 Subject: [PATCH 122/149] dmaengine: ste_dma40: Fix memcpy channel parsing d40_of_probe() validates the memcpy-channels property against D40_MEMCPY_MAX_CHANS, but reads the property directly into a smaller global array. A long property can therefore overwrite adjacent data. The mutable global also lets a later DMA40 instance replace the memcpy channel mapping used for future allocations on an earlier instance. Store the mapping in the per-device platform data, validate the property against that storage, and check the property read result. The property is required and d40_probe() always populates the platform data, so remove the obsolete global mapping and fallback. Fixes: a7dacb68b35a ("dmaengine: ste_dma40: Allow memcpy channels to be configured from DT") Reported-by: sashiko-bot@kernel.org Closes: https://lore.kernel.org/dmaengine/20260819225215.5EA2F1F000E9@smtp.kernel.org/ Assisted-by: LLM Reviewed-by: Frank Li Signed-off-by: Linus Walleij Link: https://patch.msgid.link/20260927-dma40-fixes-v7-15-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 45 +++++++++++++---------------------------- 1 file changed, 14 insertions(+), 31 deletions(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 3885aca8a69e..8847bd60bbd9 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -28,6 +28,8 @@ #include "ste_dma40.h" #include "ste_dma40_ll.h" +#define D40_MEMCPY_MAX_CHANS 8 + /** * struct stedma40_platform_data - Configuration struct for the dma device. * @@ -41,6 +43,7 @@ * to use SoftLLI. * @use_esram_lcla: flag for mapping the lcla into esram region * @num_of_memcpy_chans: The number of channels reserved for memcpy. + * @memcpy_channels: The event lines used for memcpy. * @num_of_phy_chans: The number of physical channels implemented in HW. * 0 means reading the number of channels from DMA HW but this is only valid * for 'multiple of 4' channels, like 8. @@ -51,6 +54,7 @@ struct stedma40_platform_data { int num_of_soft_lli_chans; bool use_esram_lcla; int num_of_memcpy_chans; + u32 memcpy_channels[D40_MEMCPY_MAX_CHANS]; int num_of_phy_chans; }; @@ -89,25 +93,6 @@ struct stedma40_platform_data { #define D40_ALLOC_PHY BIT(30) #define D40_ALLOC_LOG_FREE 0 -#define D40_MEMCPY_MAX_CHANS 8 - -/* Reserved event lines for memcpy only. */ -#define DB8500_DMA_MEMCPY_EV_0 51 -#define DB8500_DMA_MEMCPY_EV_1 56 -#define DB8500_DMA_MEMCPY_EV_2 57 -#define DB8500_DMA_MEMCPY_EV_3 58 -#define DB8500_DMA_MEMCPY_EV_4 59 -#define DB8500_DMA_MEMCPY_EV_5 60 - -static int dma40_memcpy_channels[] = { - DB8500_DMA_MEMCPY_EV_0, - DB8500_DMA_MEMCPY_EV_1, - DB8500_DMA_MEMCPY_EV_2, - DB8500_DMA_MEMCPY_EV_3, - DB8500_DMA_MEMCPY_EV_4, - DB8500_DMA_MEMCPY_EV_5, -}; - /* Default configuration for physical memcpy */ static const struct stedma40_chan_cfg dma40_memcpy_conf_phy = { .mode = STEDMA40_MODE_PHYSICAL, @@ -2149,7 +2134,8 @@ static int d40_config_memcpy(struct d40_chan *d40c) if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) { d40c->dma_cfg = dma40_memcpy_conf_log; - d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id]; + d40c->dma_cfg.dev_type = + d40c->base->plat_data->memcpy_channels[d40c->chan.chan_id]; d40_log_cfg(&d40c->dma_cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); @@ -3429,12 +3415,7 @@ static int __init d40_hw_detect_init(struct platform_device *pdev, num_phy_chans = min(num_phy_chans, STEDMA40_MAX_PHYS); /* The number of channels used for memcpy */ - if (plat_data->num_of_memcpy_chans) - num_memcpy_chans = plat_data->num_of_memcpy_chans; - else - num_memcpy_chans = ARRAY_SIZE(dma40_memcpy_channels); - - num_memcpy_chans = min(num_memcpy_chans, D40_MEMCPY_MAX_CHANS); + num_memcpy_chans = plat_data->num_of_memcpy_chans; num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY; dev_info(dev, @@ -3683,6 +3664,7 @@ static int __init d40_of_probe(struct device *dev, struct stedma40_platform_data *pdata; int num_phy = 0, num_memcpy = 0, num_disabled = 0; const __be32 *list; + int ret; pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); if (!pdata) @@ -3696,18 +3678,19 @@ static int __init d40_of_probe(struct device *dev, list = of_get_property(np, "memcpy-channels", &num_memcpy); num_memcpy /= sizeof(*list); - if (num_memcpy > D40_MEMCPY_MAX_CHANS || num_memcpy <= 0) { + if (num_memcpy > ARRAY_SIZE(pdata->memcpy_channels) || + num_memcpy <= 0) { d40_err(dev, "Invalid number of memcpy channels specified (%d)\n", num_memcpy); return -EINVAL; } + ret = of_property_read_u32_array(np, "memcpy-channels", + pdata->memcpy_channels, num_memcpy); + if (ret) + return ret; pdata->num_of_memcpy_chans = num_memcpy; - of_property_read_u32_array(np, "memcpy-channels", - dma40_memcpy_channels, - num_memcpy); - list = of_get_property(np, "disabled-channels", &num_disabled); num_disabled /= sizeof(*list); From c96e9f056095825b5f8d4a11f4107fc174892f92 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:29 +0200 Subject: [PATCH 123/149] dmaengine: ste_dma40: Validate disabled channel indexes d40_of_probe() checks how many entries disabled-channels contains, but not the channel numbers themselves. d40_phy_res_init() later uses every value as an index into base->phy_res, whose size is the number of channels found in this DMA40 instance. An out-of-range value can therefore write beyond the allocation. Validate each disabled channel against the detected hardware channel count before allocating and initializing the channel resources. Fixes: 499c2bc3cc89 ("dmaengine: ste_dma40: Fetch disabled channels from DT") Assisted-by: LLM Reviewed-by: Frank Li Signed-off-by: Linus Walleij Link: https://patch.msgid.link/20260927-dma40-fixes-v7-16-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 8847bd60bbd9..08e9262dc8cd 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -3414,6 +3414,15 @@ static int __init d40_hw_detect_init(struct platform_device *pdev, num_phy_chans = min(num_phy_chans, STEDMA40_MAX_PHYS); + for (i = 0; plat_data->disabled_channels[i] != -1; i++) { + int chan = plat_data->disabled_channels[i]; + + if (chan < 0 || chan >= num_phy_chans) { + dev_err(dev, "Invalid disabled channel %d\n", chan); + return -EINVAL; + } + } + /* The number of channels used for memcpy */ num_memcpy_chans = plat_data->num_of_memcpy_chans; num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY; From 9f1064ebe17cf3ab65ac6eb166398e02678aea33 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:30 +0200 Subject: [PATCH 124/149] dmaengine: ste_dma40: Validate DMA specifier length The DMA40 binding requires three cells, but d40_xlate() reads args[0], args[1], and args[2] without checking args_count. A malformed provider node can specify fewer cells, leaving some of these values uninitialized when the OF DMA core invokes the translation callback. Reject specifiers that do not contain exactly three cells before reading the argument array. Fixes: fa332de5c6b3 ("dmaengine: ste_dma40: Supply full Device Tree parsing support") Assisted-by: LLM Reviewed-by: Frank Li Signed-off-by: Linus Walleij Link: https://patch.msgid.link/20260927-dma40-fixes-v7-17-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 08e9262dc8cd..0c183a34edea 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -2537,6 +2537,9 @@ static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec, dma_cap_mask_t cap; u32 flags; + if (dma_spec->args_count != 3) + return NULL; + memset(&cfg, 0, sizeof(struct stedma40_chan_cfg)); dma_cap_zero(cap); From 77ebc64f40717b8501793b5f5ee717a141e62e8e Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:31 +0200 Subject: [PATCH 125/149] dmaengine: ste_dma40: Reject direction changes after allocation Logical channel allocation uses the configured direction to select the source or destination allocation mask, derive the logical channel number, and choose the LCPA location. d40_set_runtime_config_write() nevertheless overwrites the configured direction when a transfer is prepared for the opposite direction. d40_free_dma() then clears the wrong allocation mask, leaking the original resource and potentially releasing one used by another client. Reject directions that differ from the direction used during allocation and propagate runtime configuration errors to callers. Skip slave runtime configuration for memcpy transfers, which also use d40_prep_sg() but do not require it. Fixes: 95e1400fa131 ("DMAENGINE: add runtime slave config to DMA40 v3") Reported-by: sashiko-bot@kernel.org Closes: https://lore.kernel.org/dmaengine/20260618051539.15E201F000E9@smtp.kernel.org/ Assisted-by: LLM Reviewed-by: Frank Li Signed-off-by: Linus Walleij Link: https://patch.msgid.link/20260927-dma40-fixes-v7-18-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 0c183a34edea..2c818fadeb2a 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -2405,7 +2405,13 @@ d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src, return NULL; } - d40_set_runtime_config_write(dchan, &chan->slave_config, direction); + if (direction != DMA_MEM_TO_MEM) { + ret = d40_set_runtime_config_write(dchan, + &chan->slave_config, + direction); + if (ret) + return NULL; + } spin_lock_irqsave(&chan->lock, flags); @@ -2881,6 +2887,13 @@ static int d40_set_runtime_config_write(struct dma_chan *chan, return -EINVAL; } + if (direction != cfg->dir) { + chan_err(d40c, + "transfer direction %d differs from allocated direction %d\n", + direction, cfg->dir); + return -EINVAL; + } + src_addr_width = config->src_addr_width; src_maxburst = config->src_maxburst; dst_addr_width = config->dst_addr_width; @@ -2889,13 +2902,6 @@ static int d40_set_runtime_config_write(struct dma_chan *chan, if (direction == DMA_DEV_TO_MEM) { config_addr = config->src_addr; - if (cfg->dir != DMA_DEV_TO_MEM) - dev_dbg(d40c->base->dev, - "channel was not configured for peripheral " - "to memory transfer (%d) overriding\n", - cfg->dir); - cfg->dir = DMA_DEV_TO_MEM; - /* Configure the memory side */ if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) dst_addr_width = src_addr_width; @@ -2905,13 +2911,6 @@ static int d40_set_runtime_config_write(struct dma_chan *chan, } else if (direction == DMA_MEM_TO_DEV) { config_addr = config->dst_addr; - if (cfg->dir != DMA_MEM_TO_DEV) - dev_dbg(d40c->base->dev, - "channel was not configured for memory " - "to peripheral transfer (%d) overriding\n", - cfg->dir); - cfg->dir = DMA_MEM_TO_DEV; - /* Configure the memory side */ if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) src_addr_width = dst_addr_width; From 57938e0c2a24f9f792fe9f611391ef6b58d1aa21 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:32 +0200 Subject: [PATCH 126/149] dmaengine: ste_dma40: Fix logical channel bounds check d40_validate_conf() checks the raw dev_type against num_log_chans, but d40_allocate_channel() derives the lookup_log_chans index as either 2 * dev_type or 2 * dev_type + 1. Validate the dev_type against the derived logical channel index limit so channel allocation cannot write past lookup_log_chans. Fixes: 26955c07dcf3 ("dmaengine: ste_dma40: Amalgamate DMA source and destination channel numbers") Reported-by: sashiko-bot@kernel.org Closes: https://lore.kernel.org/dmaengine/20260618051539.15E201F000E9@smtp.kernel.org/ Assisted-by: LLM Signed-off-by: Linus Walleij Reviewed-by: Frank Li Link: https://patch.msgid.link/20260927-dma40-fixes-v7-19-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 2c818fadeb2a..b2ea7a44b5f1 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -1876,15 +1876,26 @@ static int d40_validate_conf(struct d40_chan *d40c, { int res = 0; bool is_log = conf->mode == STEDMA40_MODE_LOGICAL; + bool invalid_dev_type = conf->dev_type < 0; if (!conf->dir) { chan_err(d40c, "Invalid direction.\n"); res = -EINVAL; } - if ((is_log && conf->dev_type > d40c->base->num_log_chans) || - (!is_log && conf->dev_type > d40c->base->num_phy_chans) || - (conf->dev_type < 0)) { + if (!invalid_dev_type && is_log) { + int max_dev_type; + + if (conf->dir == DMA_DEV_TO_MEM) + max_dev_type = DIV_ROUND_UP(d40c->base->num_log_chans, 2); + else + max_dev_type = d40c->base->num_log_chans / 2; + + invalid_dev_type = conf->dev_type >= max_dev_type; + } + + if (invalid_dev_type || + (!is_log && conf->dev_type > d40c->base->num_phy_chans)) { chan_err(d40c, "Invalid device type (%d)\n", conf->dev_type); res = -EINVAL; } From e66a9dbe04c71249cfb2a544c9c25d1b3b761fba Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:33 +0200 Subject: [PATCH 127/149] dmaengine: ste_dma40: Fix event group bounds The dev_type validation can allow values whose derived event group has no matching physical channel pair. d40_allocate_channel() then indexes phy_res with j + event_group * 2, and __d40_set_prio_rt() uses the same group to select priority and realtime registers. The physical-mode validation also compares dev_type with the number of physical channels. However, dev_type identifies an event line: DB8500 has eight physical channels but 64 source and 64 destination event lines. The event group determines which physical channel pair can serve an event, so the physical channel count is not a valid dev_type limit. Reject dev_type values outside the hardware event-group range, remove the incorrect physical channel count limit, and stop the physical-channel search before a partial final channel group can index past phy_res. Fixes: 26955c07dcf3 ("dmaengine: ste_dma40: Amalgamate DMA source and destination channel numbers") Reported-by: sashiko-bot@kernel.org Closes: https://lore.kernel.org/dmaengine/20260819225008.5F9651F000E9@smtp.kernel.org/ Assisted-by: LLM Link: https://lore.kernel.org/dmaengine/20260819225008.5F9651F000E9@smtp.kernel.org/ Signed-off-by: Linus Walleij Reviewed-by: Frank Li Link: https://patch.msgid.link/20260927-dma40-fixes-v7-20-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index b2ea7a44b5f1..0e1c0da058a0 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -82,6 +82,10 @@ struct stedma40_platform_data { #define D40_LCLA_LINK_PER_EVENT_GRP 128 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP +/* Number of event groups per hardware register layout */ +#define D40_EVENT_GROUPS_V4A 4 +#define D40_EVENT_GROUPS_V4B 5 + /* Max number of logical channels per physical channel */ #define D40_MAX_LOG_CHAN_PER_PHY 32 @@ -522,6 +526,7 @@ struct d40_chan { * @high_prio_clear: the high priority clear register * @interrupt_en: the interrupt enable register * @interrupt_clear: the interrupt clear register + * @num_event_groups: number of supported event groups * @il: the pointer to struct d40_interrupt_lookup * @il_size: the size of d40_interrupt_lookup array * @init_reg: the pointer to the struct d40_reg_val @@ -536,6 +541,7 @@ struct d40_gen_dmac { u32 high_prio_clear; u32 interrupt_en; u32 interrupt_clear; + u32 num_event_groups; struct d40_interrupt_lookup *il; u32 il_size; struct d40_reg_val *init_reg; @@ -1878,6 +1884,11 @@ static int d40_validate_conf(struct d40_chan *d40c, bool is_log = conf->mode == STEDMA40_MODE_LOGICAL; bool invalid_dev_type = conf->dev_type < 0; + if (!invalid_dev_type && + D40_TYPE_TO_GROUP(conf->dev_type) >= + d40c->base->gen_dmac.num_event_groups) + invalid_dev_type = true; + if (!conf->dir) { chan_err(d40c, "Invalid direction.\n"); res = -EINVAL; @@ -1894,8 +1905,7 @@ static int d40_validate_conf(struct d40_chan *d40c, invalid_dev_type = conf->dev_type >= max_dev_type; } - if (invalid_dev_type || - (!is_log && conf->dev_type > d40c->base->num_phy_chans)) { + if (invalid_dev_type) { chan_err(d40c, "Invalid device type (%d)\n", conf->dev_type); res = -EINVAL; } @@ -2060,8 +2070,12 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user) } } } else - for (j = 0; j < d40c->base->num_phy_chans; j += 8) { + for (j = 0; j < d40c->base->num_phy_chans; + j += D40_GROUP_SIZE) { int phy_num = j + event_group * 2; + if (phy_num + 1 >= num_phy_chans) + break; + for (i = phy_num; i < phy_num + 2; i++) { if (d40_alloc_mask_set(&phys[i], is_src, @@ -2081,8 +2095,10 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user) return -EINVAL; /* Find logical channel */ - for (j = 0; j < d40c->base->num_phy_chans; j += 8) { + for (j = 0; j < d40c->base->num_phy_chans; j += D40_GROUP_SIZE) { int phy_num = j + event_group * 2; + if (phy_num + 1 >= num_phy_chans) + break; if (d40c->dma_cfg.use_fixed_channel) { i = d40c->dma_cfg.phy_channel; @@ -3462,6 +3478,7 @@ static int __init d40_hw_detect_init(struct platform_device *pdev, base->log_chans = &base->phy_chans[num_phy_chans]; if (base->plat_data->num_of_phy_chans == 14) { + base->gen_dmac.num_event_groups = D40_EVENT_GROUPS_V4B; base->gen_dmac.backup = d40_backup_regs_v4b; base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4B; base->gen_dmac.interrupt_en = D40_DREG_CPCMIS; @@ -3475,6 +3492,7 @@ static int __init d40_hw_detect_init(struct platform_device *pdev, base->gen_dmac.init_reg = dma_init_reg_v4b; base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4b); } else { + base->gen_dmac.num_event_groups = D40_EVENT_GROUPS_V4A; if (base->rev >= 3) { base->gen_dmac.backup = d40_backup_regs_v4a; base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4A; From b36f8fce7314fed53563c60e683ff86deb8a51ae Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:34 +0200 Subject: [PATCH 128/149] dmaengine: ste_dma40: Fix V4B event group mapping DMA40 physical resources are connected in pairs to event groups. The mapping repeats after each complete set of groups. D40_GROUP_SIZE and D40_PHYS_TO_GROUP() encode the four-group V4A layout. On V4B, which has five groups, resources 8 and 9 are consequently offered both to event groups 0 and 4. The GCC clock bookkeeping also treats these resources as group 0 instead of group 4. Derive the physical-resource stride and reverse mapping from the variant-specific number of event groups. This preserves the V4A mapping and gives V4B a ten-resource stride: resources 8 and 9 belong only to group 4, while resources 10 and 11 repeat group 0. Fixes: 3cb645dc85a0 ("dmaengine: ste_dma40: support more than 128 event lines") Assisted-by: LLM Signed-off-by: Linus Walleij Reviewed-by: Frank Li Link: https://patch.msgid.link/20260927-dma40-fixes-v7-21-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 47 ++++++++++++++++++++++++++------------ drivers/dma/ste_dma40_ll.h | 2 -- 2 files changed, 33 insertions(+), 16 deletions(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 0e1c0da058a0..208e877d93d7 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -85,6 +85,7 @@ struct stedma40_platform_data { /* Number of event groups per hardware register layout */ #define D40_EVENT_GROUPS_V4A 4 #define D40_EVENT_GROUPS_V4B 5 +#define D40_PHYS_PER_EVENT_GROUP 2 /* Max number of logical channels per physical channel */ #define D40_MAX_LOG_CHAN_PER_PHY 32 @@ -2022,6 +2023,12 @@ static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src, return is_free; } +static int d40_phy_to_group(struct d40_base *base, int phy) +{ + return (phy / D40_PHYS_PER_EVENT_GROUP) % + base->gen_dmac.num_event_groups; +} + static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user) { int dev_type = d40c->dma_cfg.dev_type; @@ -2032,11 +2039,14 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user) int j; int log_num; int num_phy_chans; + int phy_group_stride; bool is_src; bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL; phys = d40c->base->phy_res; num_phy_chans = d40c->base->num_phy_chans; + phy_group_stride = D40_PHYS_PER_EVENT_GROUP * + d40c->base->gen_dmac.num_event_groups; if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) { log_num = 2 * dev_type; @@ -2070,13 +2080,18 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user) } } } else - for (j = 0; j < d40c->base->num_phy_chans; - j += D40_GROUP_SIZE) { - int phy_num = j + event_group * 2; - if (phy_num + 1 >= num_phy_chans) + for (j = 0; j < num_phy_chans; + j += phy_group_stride) { + int phy_num = j + event_group * + D40_PHYS_PER_EVENT_GROUP; + + if (phy_num + D40_PHYS_PER_EVENT_GROUP > + num_phy_chans) break; - for (i = phy_num; i < phy_num + 2; i++) { + for (i = phy_num; + i < phy_num + D40_PHYS_PER_EVENT_GROUP; + i++) { if (d40_alloc_mask_set(&phys[i], is_src, 0, @@ -2095,9 +2110,10 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user) return -EINVAL; /* Find logical channel */ - for (j = 0; j < d40c->base->num_phy_chans; j += D40_GROUP_SIZE) { - int phy_num = j + event_group * 2; - if (phy_num + 1 >= num_phy_chans) + for (j = 0; j < num_phy_chans; j += phy_group_stride) { + int phy_num = j + event_group * D40_PHYS_PER_EVENT_GROUP; + + if (phy_num + D40_PHYS_PER_EVENT_GROUP > num_phy_chans) break; if (d40c->dma_cfg.use_fixed_channel) { @@ -2124,14 +2140,17 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user) * channels. */ if (is_src) { - for (i = phy_num; i < phy_num + 2; i++) { + for (i = phy_num; + i < phy_num + D40_PHYS_PER_EVENT_GROUP; + i++) { if (d40_alloc_mask_set(&phys[i], is_src, event_line, is_log, first_phy_user)) goto found_log; } } else { - for (i = phy_num + 1; i >= phy_num; i--) { + for (i = phy_num + D40_PHYS_PER_EVENT_GROUP - 1; + i >= phy_num; i--) { if (d40_alloc_mask_set(&phys[i], is_src, event_line, is_log, first_phy_user)) @@ -3302,9 +3321,9 @@ static int __init d40_phy_res_init(struct d40_base *base) base->phy_res[i].allocated_src = D40_ALLOC_PHY; base->phy_res[i].allocated_dst = D40_ALLOC_PHY; base->phy_res[i].reserved = true; - gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i), + gcc |= D40_DREG_GCC_EVTGRP_ENA(d40_phy_to_group(base, i), D40_DREG_GCC_SRC); - gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i), + gcc |= D40_DREG_GCC_EVTGRP_ENA(d40_phy_to_group(base, i), D40_DREG_GCC_DST); @@ -3324,9 +3343,9 @@ static int __init d40_phy_res_init(struct d40_base *base) base->phy_res[chan].allocated_src = D40_ALLOC_PHY; base->phy_res[chan].allocated_dst = D40_ALLOC_PHY; base->phy_res[chan].reserved = true; - gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan), + gcc |= D40_DREG_GCC_EVTGRP_ENA(d40_phy_to_group(base, chan), D40_DREG_GCC_SRC); - gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan), + gcc |= D40_DREG_GCC_EVTGRP_ENA(d40_phy_to_group(base, chan), D40_DREG_GCC_DST); num_phy_chans_avail--; } diff --git a/drivers/dma/ste_dma40_ll.h b/drivers/dma/ste_dma40_ll.h index 2e30e9a94a1e..55090cb31057 100644 --- a/drivers/dma/ste_dma40_ll.h +++ b/drivers/dma/ste_dma40_ll.h @@ -16,8 +16,6 @@ #define D40_TYPE_TO_GROUP(type) (type / 16) #define D40_TYPE_TO_EVENT(type) (type % 16) -#define D40_GROUP_SIZE 8 -#define D40_PHYS_TO_GROUP(phys) ((phys & (D40_GROUP_SIZE - 1)) / 2) /* Most bits of the CFG register are the same in log as in phy mode */ #define D40_SREG_CFG_MST_POS 15 From 884e01160bc727509b4fdf04e763a86b936df464 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:36 +0200 Subject: [PATCH 129/149] dmaengine: ste_dma40: Validate fixed physical channel indexes Fixed physical memcpy allocation uses dma_cfg.phy_channel directly as an index into phy_res when use_fixed_channel is set. d40_validate_conf() validates dev_type but not the fixed physical channel, allowing an invalid configuration to access memory outside the array. Validate the fixed physical channel centrally before accepting the channel configuration. Fixes: f000df8c5a0e ("dmaengine: ste_dma40: support fixed physical channel allocation") Reported-by: sashiko-bot@kernel.org Closes: https://lore.kernel.org/dmaengine/20260819225008.5F9651F000E9@smtp.kernel.org/ Assisted-by: LLM Reviewed-by: Frank Li Signed-off-by: Linus Walleij Link: https://patch.msgid.link/20260927-dma40-fixes-v7-23-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 208e877d93d7..b809339f1776 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -1911,6 +1911,14 @@ static int d40_validate_conf(struct d40_chan *d40c, res = -EINVAL; } + if (conf->use_fixed_channel && + (conf->phy_channel < 0 || + conf->phy_channel >= d40c->base->num_phy_chans)) { + chan_err(d40c, "Invalid physical channel (%d)\n", + conf->phy_channel); + res = -EINVAL; + } + if (conf->dir == DMA_DEV_TO_DEV) { /* * DMAC HW supports it. Will be added to this driver, From 0ac4a90c4805b41013044fdefff051ae59a54302 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Sep 2026 11:03:37 +0200 Subject: [PATCH 130/149] dmaengine: ste_dma40: Validate memcpy configuration d40_config_memcpy() builds a default memcpy configuration without passing it through d40_validate_conf(). A dev_type supplied through the memcpy-channels device tree property can therefore bypass the bounds checks added for client configurations. The generic DMA direction enum assigns zero to DMA_MEM_TO_MEM, unlike DMA40's old private enum. Allow memory-to-memory directions in the validator so checking the generated configuration does not reject all memcpy channels. Validate the generated memcpy configuration before deriving logical channel registers or allocating the channel. Fixes: 2c2b62d5d911 ("dmaengine: ste_dma40: Replace ST-E's home-brew DMA direction defs with generic ones") Reported-by: sashiko-bot@kernel.org Closes: https://lore.kernel.org/dmaengine/20260819225008.5F9651F000E9@smtp.kernel.org/ Assisted-by: LLM Reviewed-by: Frank Li Signed-off-by: Linus Walleij Link: https://patch.msgid.link/20260927-dma40-fixes-v7-24-89f595e8851d@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index b809339f1776..0ffdfd9a1c9d 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -1890,7 +1890,8 @@ static int d40_validate_conf(struct d40_chan *d40c, d40c->base->gen_dmac.num_event_groups) invalid_dev_type = true; - if (!conf->dir) { + if (conf->dir != DMA_MEM_TO_MEM && + !is_slave_direction(conf->dir)) { chan_err(d40c, "Invalid direction.\n"); res = -EINVAL; } @@ -2185,12 +2186,17 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user) static int d40_config_memcpy(struct d40_chan *d40c) { dma_cap_mask_t cap = d40c->chan.device->cap_mask; + int ret; if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) { d40c->dma_cfg = dma40_memcpy_conf_log; d40c->dma_cfg.dev_type = d40c->base->plat_data->memcpy_channels[d40c->chan.chan_id]; + ret = d40_validate_conf(d40c, &d40c->dma_cfg); + if (ret) + return ret; + d40_log_cfg(&d40c->dma_cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); @@ -2198,6 +2204,10 @@ static int d40_config_memcpy(struct d40_chan *d40c) dma_has_cap(DMA_SLAVE, cap)) { d40c->dma_cfg = dma40_memcpy_conf_phy; + ret = d40_validate_conf(d40c, &d40c->dma_cfg); + if (ret) + return ret; + /* Generate interrupt at end of transfer or relink. */ d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS); From 38d97b1122e02f6b8859e660990aaeda1c32e00f Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 18 Sep 2026 17:46:45 +0200 Subject: [PATCH 131/149] dt-bindings: dma: dma40: Restore disabled-channels The conversion of the DMA40 binding to YAML omitted the optional disabled-channels property from the original text binding. The driver still parses this property, but additionalProperties: false rejects any device tree using it. Restore disabled-channels and constrain it to the physical channel range. Also constrain memcpy-channels to the limits enforced by the driver and reject duplicate channel entries in both properties. Fixes: 23fbc87c8ae6 ("dt-bindings: dma: Rewrite ST-Ericsson DMA40 to YAML") Assisted-by: LLM Signed-off-by: Linus Walleij Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260918-dma40-dt-disabled-channels-v1-1-0f691109d8d3@kernel.org Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/stericsson,dma40.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml b/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml index d8f92838f4c9..81b83603ea79 100644 --- a/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml +++ b/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml @@ -140,8 +140,22 @@ properties: - description: LCPA (Logical Channel Parameter Address) memory. - description: LCLA (Logical Channel Link base Address) memory. + disabled-channels: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 31 + uniqueItems: true + items: + maximum: 31 + description: Physical channels that cannot be used by the DMA engine. + memcpy-channels: $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + uniqueItems: true + items: + maximum: 63 description: Array of u32 elements indicating which channels on the DMA engine are eligible for memcpy transfers From 15728ab23d00b19013a6cf5f8ed28d4f2ee5410a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 6 Oct 2026 00:40:17 +0200 Subject: [PATCH 132/149] dmaengine: ste_dma40: Search all blocks for fixed logical channels Fixed logical channel allocation scans physical channels in blocks determined by the event-group layout. When the requested physical channel does not belong to the first block, d40_allocate_channel() returns -EINVAL instead of checking later blocks. Skip nonmatching blocks so controllers with multiple physical-channel blocks can allocate fixed logical channels from the later blocks. Fixes: 5cd326fd27da ("dmaengine/ste_dma40: allow fixed physical channel") Reported-by: sashiko-bot@kernel.org Closes: https://lore.kernel.org/dmaengine/20260819225008.5F9651F000E9@smtp.kernel.org/ Assisted-by: LLM Reviewed-by: Frank Li Signed-off-by: Linus Walleij Link: https://patch.msgid.link/20261006-dma40-fixes-v8-1-b0aadf804793@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 0ffdfd9a1c9d..d3cc2c512ccf 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -2128,11 +2128,8 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user) if (d40c->dma_cfg.use_fixed_channel) { i = d40c->dma_cfg.phy_channel; - if ((i != phy_num) && (i != phy_num + 1)) { - dev_err(dmaengine_chan_dev(&d40c->chan), - "invalid fixed phy channel %d\n", i); - return -EINVAL; - } + if (i != phy_num && i != phy_num + 1) + continue; if (d40_alloc_mask_set(&phys[i], is_src, event_line, is_log, first_phy_user)) From 53b32375c9caf793ff392f762236c90f2a062ae5 Mon Sep 17 00:00:00 2001 From: Hemanth Selam Date: Tue, 6 Oct 2026 14:17:02 +0530 Subject: [PATCH 133/149] dmaengine: ppc4xx: fix typo "contoller" in comment The comment above XOR_ENGINES_NUM is missing an "r" in "controller". Link: https://lore.kernel.org/all/asSzFW-ZJ16xhFnA@parshuram/ Signed-off-by: Hemanth Selam Link: https://patch.msgid.link/20261006084702.5748-1-hemanth.selam@gmail.com Signed-off-by: Vinod Koul --- drivers/dma/ppc4xx/xor.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/ppc4xx/xor.h b/drivers/dma/ppc4xx/xor.h index da1230df2817..0931e18cd0d3 100644 --- a/drivers/dma/ppc4xx/xor.h +++ b/drivers/dma/ppc4xx/xor.h @@ -12,7 +12,7 @@ #include -/* Number of XOR engines available on the contoller */ +/* Number of XOR engines available on the controller */ #define XOR_ENGINES_NUM 1 /* Number of operands supported in the h/w */ From 82eed160cfa7a296ae4eb5acb8dd8f493323eea7 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 8 Oct 2026 11:54:35 +0200 Subject: [PATCH 134/149] dmaengine: qcom: bam_dma: free interrupt before the clock in error path The BAM interrupt is requested with a devres helper and so on error it's freed after probe() returns. We disable the clock before freeing or masking it so it may still fire and we may end up reading BAM registers with clock disabled. Stop using devres for interrupts as we free it in remove() manually anyway. Add an appropriate label and free the interrupt before disabling the clock in error path and in remove(). Cc: stable@vger.kernel.org Fixes: e7c0fe2a5c84 ("dmaengine: add Qualcomm BAM dma driver") Reported-by: Sashiko Closes: https://sashiko.dev/#/patchset/20260427-qcom-qce-cmd-descr-v16-0-945fd1cafbbc%40oss.qualcomm.com?part=2 Reviewed-by: Manivannan Sadhasivam Signed-off-by: Bartosz Golaszewski Link: https://patch.msgid.link/20261008-bam-dma-free-irq-v28-1-5e5b10de441e@oss.qualcomm.com Signed-off-by: Vinod Koul --- drivers/dma/qcom/bam_dma.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c index 94cb957d4b18..f67a93a37d48 100644 --- a/drivers/dma/qcom/bam_dma.c +++ b/drivers/dma/qcom/bam_dma.c @@ -1332,8 +1332,8 @@ static int bam_dma_probe(struct platform_device *pdev) for (i = 0; i < bdev->num_channels; i++) bam_channel_init(bdev, &bdev->channels[i], i); - ret = devm_request_irq(bdev->dev, bdev->irq, bam_dma_irq, - IRQF_TRIGGER_NONE, "bam_dma", bdev); + ret = request_irq(bdev->irq, bam_dma_irq, IRQF_TRIGGER_NONE, + "bam_dma", bdev); if (ret) goto err_bam_channel_exit; @@ -1366,7 +1366,7 @@ static int bam_dma_probe(struct platform_device *pdev) ret = dma_async_device_register(&bdev->common); if (ret) { dev_err(bdev->dev, "failed to register dma async device\n"); - goto err_bam_channel_exit; + goto err_free_irq; } ret = of_dma_controller_register(pdev->dev.of_node, bam_dma_xlate, @@ -1385,6 +1385,8 @@ static int bam_dma_probe(struct platform_device *pdev) err_unregister_dma: dma_async_device_unregister(&bdev->common); +err_free_irq: + free_irq(bdev->irq, bdev); err_bam_channel_exit: for (i = 0; i < bdev->num_channels; i++) tasklet_kill(&bdev->channels[i].vc.task); @@ -1410,7 +1412,7 @@ static void bam_dma_remove(struct platform_device *pdev) /* mask all interrupts for this execution environment */ writel_relaxed(0, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); - devm_free_irq(bdev->dev, bdev->irq, bdev); + free_irq(bdev->irq, bdev); for (i = 0; i < bdev->num_channels; i++) { bam_dma_terminate_all(&bdev->channels[i].vc.chan); From a416b656798317f1c6eb69d7a034b4dc392b3781 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 9 Sep 2026 11:40:10 +0200 Subject: [PATCH 135/149] dmaengine: sh: rcar-dmac: fix style in struct initialization A new member will be added to the struct. Before that, adhere to coding style by using a single space when assigning values. Signed-off-by: Wolfram Sang Reviewed-by: Frank Li Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260909094009.2167-7-wsa+renesas@sang-engineering.com Signed-off-by: Vinod Koul --- drivers/dma/sh/rcar-dmac.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c index 44eab2d21d54..cf07c17847d0 100644 --- a/drivers/dma/sh/rcar-dmac.c +++ b/drivers/dma/sh/rcar-dmac.c @@ -1998,13 +1998,13 @@ static void rcar_dmac_shutdown(struct platform_device *pdev) } static const struct rcar_dmac_of_data rcar_dmac_data = { - .chan_offset_base = 0x8000, - .chan_offset_stride = 0x80, + .chan_offset_base = 0x8000, + .chan_offset_stride = 0x80, }; static const struct rcar_dmac_of_data rcar_gen4_dmac_data = { - .chan_offset_base = 0x0, - .chan_offset_stride = 0x1000, + .chan_offset_base = 0x0, + .chan_offset_stride = 0x1000, }; static const struct of_device_id rcar_dmac_of_ids[] = { From 73812307647a90234cbc1e474f2dec4bfa4ad34f Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 9 Sep 2026 11:40:11 +0200 Subject: [PATCH 136/149] dmaengine: sh: rcar-dmac: SMMU doesn't need IPMMU workaround R-Car Gen5 doesn't use an IPMMU anymore, but a SMMU. So, the workaround for the IPMMU becomes optional. Add a flag to distinguish. No functional change. Signed-off-by: Wolfram Sang Reviewed-by: Frank Li Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260909094009.2167-8-wsa+renesas@sang-engineering.com Signed-off-by: Vinod Koul --- drivers/dma/sh/rcar-dmac.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c index cf07c17847d0..4eca52aeec02 100644 --- a/drivers/dma/sh/rcar-dmac.c +++ b/drivers/dma/sh/rcar-dmac.c @@ -219,10 +219,12 @@ struct rcar_dmac { * struct rcar_dmac_of_data - This driver's OF data * @chan_offset_base: DMAC channels base offset * @chan_offset_stride: DMAC channels offset stride + * @broken_ipmmu_microTLB0: flag if the connected IPMMU has microTLB0 issues */ struct rcar_dmac_of_data { u32 chan_offset_base; u32 chan_offset_stride; + unsigned int broken_ipmmu_microTLB0:1; }; /* ----------------------------------------------------------------------------- @@ -1877,8 +1879,9 @@ static int rcar_dmac_probe(struct platform_device *pdev) * can't use it with the IPMMU. As the IOMMU API operates at the device * level we can't disable it selectively, so ignore channel 0 for now if * the device is part of an IOMMU group. + * Not applicable if system uses something else than IPMMU like SMMU. */ - if (device_iommu_mapped(&pdev->dev)) + if (data->broken_ipmmu_microTLB0 && device_iommu_mapped(&pdev->dev)) dmac->channels_mask &= ~BIT(0); dmac->channels = devm_kcalloc(&pdev->dev, dmac->n_channels, @@ -2000,11 +2003,14 @@ static void rcar_dmac_shutdown(struct platform_device *pdev) static const struct rcar_dmac_of_data rcar_dmac_data = { .chan_offset_base = 0x8000, .chan_offset_stride = 0x80, + .broken_ipmmu_microTLB0 = 1, }; static const struct rcar_dmac_of_data rcar_gen4_dmac_data = { .chan_offset_base = 0x0, .chan_offset_stride = 0x1000, + /* Set to play safe. Needs testing if Gen4 is really affected */ + .broken_ipmmu_microTLB0 = 1, }; static const struct of_device_id rcar_dmac_of_ids[] = { From 8d4237d153174af7cda2b3e45f4f47586a04dc95 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 9 Sep 2026 11:40:12 +0200 Subject: [PATCH 137/149] dt-bindings: renesas,rcar-dmac: Add support for R-Car X5H SoC Also add the familiy compatible because X5H is the first R-Car Gen5 SoC. Signed-off-by: Wolfram Sang Acked-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260909094009.2167-9-wsa+renesas@sang-engineering.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/renesas,rcar-dmac.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml index 04fc4a99a7cb..d3d521c927e1 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml @@ -49,6 +49,11 @@ properties: - renesas,dmac-r8a779h0 # R-Car V4M - const: renesas,rcar-gen4-dmac # R-Car Gen4 + - items: + - enum: + - renesas,dmac-r8a78000 # R-Car X5H + - const: renesas,rcar-gen5-dmac # R-Car Gen5 + reg: true interrupts: @@ -123,6 +128,7 @@ if: contains: enum: - renesas,rcar-gen4-dmac + - renesas,rcar-gen5-dmac then: properties: reg: From 1d8ae2003de08f61095e4e928b1b8cce6c23cabd Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 9 Sep 2026 11:40:13 +0200 Subject: [PATCH 138/149] dmaengine: sh: rcar-dmac: Add support for R-Car Gen5 SoCs Gen5 is very similar to Gen4. Of interest here is that it has a SMMU instead of an IPMMU, so there is no need to set the flag for a workaround. Make the module description more generic while here. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Reviewed-by: Frank Li Link: https://patch.msgid.link/20260909094009.2167-10-wsa+renesas@sang-engineering.com Signed-off-by: Vinod Koul --- drivers/dma/sh/rcar-dmac.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c index 4eca52aeec02..3ad8aba5dcd4 100644 --- a/drivers/dma/sh/rcar-dmac.c +++ b/drivers/dma/sh/rcar-dmac.c @@ -2013,6 +2013,11 @@ static const struct rcar_dmac_of_data rcar_gen4_dmac_data = { .broken_ipmmu_microTLB0 = 1, }; +static const struct rcar_dmac_of_data rcar_gen5_dmac_data = { + .chan_offset_base = 0x0, + .chan_offset_stride = 0x1000, +}; + static const struct of_device_id rcar_dmac_of_ids[] = { { .compatible = "renesas,rcar-dmac", @@ -2020,6 +2025,9 @@ static const struct of_device_id rcar_dmac_of_ids[] = { }, { .compatible = "renesas,rcar-gen4-dmac", .data = &rcar_gen4_dmac_data, + }, { + .compatible = "renesas,rcar-gen5-dmac", + .data = &rcar_gen5_dmac_data, }, { /* * Backward compatibility for between v5.12 - v5.19 @@ -2045,6 +2053,6 @@ static struct platform_driver rcar_dmac_driver = { module_platform_driver(rcar_dmac_driver); -MODULE_DESCRIPTION("R-Car Gen2 DMA Controller Driver"); +MODULE_DESCRIPTION("R-Car DMA Controller Driver"); MODULE_AUTHOR("Laurent Pinchart "); MODULE_LICENSE("GPL v2"); From 4bdb88eb5496cb09902b9778ca7f4628c43b0d77 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 5 Oct 2026 05:37:14 -0400 Subject: [PATCH 139/149] dmaengine: add dmaengine_prep_dma_(pq|pq_val|interrupt|xor)() API Add dmaengine_prep_dma_(pq|pq_val|interrupt|xor)() as an inline wrapper around the device_prep_dma_(pq|pq_val|interrupt|xor)() callback, consistent with how other dmaengine prep helpers like dmaengine_prep_dma_memcpy() are structured. Provide a clean public API that hides the direct callback access and add proper NULL-checks on chan, chan->device, and the callback pointer. Assisted-by: LLM Signed-off-by: Frank Li Link: https://patch.msgid.link/20261005-dmaengine_prep_dma_pq-v3-1-a4a241f26fa7@nxp.com Signed-off-by: Vinod Koul --- include/linux/dmaengine.h | 134 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 0ada6fe66e80..143e5127c8d1 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -1252,6 +1252,122 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memcpy( len, flags); } +/** + * dmaengine_prep_dma_xor - prepare a DMA XOR operation + * @chan: the channel to use for this operation + * @dst: destination buffer address + * @src: array of source buffer addresses + * @src_cnt: number of source buffers + * @len: length in bytes of each source and destination buffer + * @flags: DMA engine flags (e.g. DMA_PREP_INTERRUPT) + * + * Prepare an XOR parity generation transaction. The engine computes: + * dst = src[0] XOR src[1] XOR ... XOR src[src_cnt - 1] + * + * Returns a descriptor on success, or NULL if the channel does not support + * this operation or the request could not be queued. + */ +static inline struct dma_async_tx_descriptor * +dmaengine_prep_dma_xor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, + unsigned int src_cnt, size_t len, unsigned long flags) +{ + if (!chan || !chan->device || !chan->device->device_prep_dma_xor) + return NULL; + + return chan->device->device_prep_dma_xor(chan, dst, src, + src_cnt, len, flags); +} + +/** + * dmaengine_prep_dma_xor_val - prepare a DMA XOR zero-sum validation operation + * @chan: the channel to use for this operation + * @src: array of source buffer addresses + * @src_cnt: number of source buffers + * @len: length in bytes of each source buffer + * @result: output flag set to SUM_CHECK_P_RESULT if the XOR of all sources + * is non-zero (i.e. parity error), cleared otherwise + * @flags: DMA engine flags (e.g. DMA_PREP_INTERRUPT) + * + * Prepare an XOR zero-sum validation transaction. The engine XORs all + * source buffers and checks whether the result is zero. The outcome is + * written to @result on completion. + * + * Returns a descriptor on success, or NULL if the channel does not support + * this operation or the request could not be queued. + */ +static inline struct dma_async_tx_descriptor * +dmaengine_prep_dma_xor_val(struct dma_chan *chan, dma_addr_t *src, + unsigned int src_cnt, size_t len, + enum sum_check_flags *result, unsigned long flags) +{ + if (!chan || !chan->device || !chan->device->device_prep_dma_xor_val) + return NULL; + + return chan->device->device_prep_dma_xor_val(chan, src, src_cnt, + len, result, flags); +} + +/** + * dmaengine_prep_dma_pq - prepare a DMA PQ (RAID-6 P+Q) operation + * @chan: the channel to use for this operation + * @dst: array of two destination addresses: dst[0] for P, dst[1] for Q + * @src: array of source buffer addresses + * @src_cnt: number of source buffers + * @scf: array of scaling coefficients, one per source buffer + * @len: length in bytes of each source and destination buffer + * @flags: DMA engine flags (e.g. DMA_PREP_INTERRUPT) + * + * Prepare a P+Q parity generation transaction. The engine computes: + * P = XOR of all source buffers + * Q = Galois field sum of (scf[i] * src[i]) over all sources + * + * Returns a descriptor on success, or NULL if the channel does not support + * this operation or the request could not be queued. + */ +static inline struct dma_async_tx_descriptor * +dmaengine_prep_dma_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, + unsigned int src_cnt, const unsigned char *scf, + size_t len, unsigned long flags) +{ + if (!chan || !chan->device || !chan->device->device_prep_dma_pq) + return NULL; + + return chan->device->device_prep_dma_pq(chan, dst, src, + src_cnt, scf, len, flags); +} + +/** + * dmaengine_prep_dma_pq_val - prepare a DMA PQ validation operation + * @chan: the channel to use for this operation + * @pq: array of two addresses holding existing P and Q parity buffers + * @src: array of source buffer addresses + * @src_cnt: number of source buffers + * @scf: array of scaling coefficients, one per source buffer + * @len: length in bytes of each buffer + * @pqres: output flags indicating P and/or Q check results (SUM_CHECK_P_VALID, + * SUM_CHECK_Q_VALID) + * @flags: DMA engine flags (e.g. DMA_PREP_INTERRUPT) + * + * Prepare a PQ validation transaction. The engine recomputes P and Q from the + * source buffers and compares them against the existing parity stored at @pq. + * The result of each comparison is reported through @pqres. + * + * Returns a descriptor on success, or NULL if the channel does not support + * this operation or the request could not be queued. + */ +static inline struct dma_async_tx_descriptor * +dmaengine_prep_dma_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, + unsigned int src_cnt, const unsigned char *scf, + size_t len, enum sum_check_flags *pqres, unsigned long flags) +{ + if (!chan || !chan->device || !chan->device->device_prep_dma_pq_val) + return NULL; + + return chan->device->device_prep_dma_pq_val(chan, pq, src, + src_cnt, scf, len, + pqres, flags); +} + static inline bool dmaengine_is_metadata_mode_supported(struct dma_chan *chan, enum dma_desc_metadata_mode mode) { @@ -1605,6 +1721,24 @@ __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) #define for_each_dma_cap_mask(cap, mask) \ for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END) +/** + * dmaengine_prep_dma_interrupt() - Prepare a DMA interrupt descriptor. + * @chan: The channel to be used for this descriptor + * @flags: DMA engine flags + * + * Returns a descriptor for an interrupt transaction, or NULL if the + * channel does not support DMA_INTERRUPT. + */ +static inline struct dma_async_tx_descriptor * +dmaengine_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags) +{ + if (!chan || !chan->device || !chan->device->device_prep_dma_interrupt || + !dma_has_cap(DMA_INTERRUPT, chan->device->cap_mask)) + return NULL; + + return chan->device->device_prep_dma_interrupt(chan, flags); +} + /** * dma_async_issue_pending - flush pending transactions to HW * @chan: target DMA channel From 11e801ccaca78c9d92b1f3a9733772bf9d2c079c Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 5 Oct 2026 05:37:15 -0400 Subject: [PATCH 140/149] dmaengine: add dmaengine_is_*_aligned() helpers for DMA consumers DMA engine consumers typically hold a struct dma_chan pointer and should not need to reach into struct dma_device directly to check alignment requirements. Add dmaengine_is_copy_aligned(), dmaengine_is_xor_aligned(), dmaengine_is_pq_aligned() and dmaengine_is_fill_aligned() as channel-based counterparts to the existing is_dma_*_aligned() family. Each wrapper calls dmaengine_check_align() directly with the alignment value from chan->device, keeping struct dma_device opaque to consumers. Signed-off-by: Frank Li Link: https://patch.msgid.link/20261005-dmaengine_prep_dma_pq-v3-2-a4a241f26fa7@nxp.com Signed-off-by: Vinod Koul --- include/linux/dmaengine.h | 64 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 143e5127c8d1..07fe91bdd8d7 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -1557,6 +1557,70 @@ static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1, return dmaengine_check_align(dev->fill_align, off1, off2, len); } +/** + * dmaengine_is_copy_aligned - test copy alignment + * @chan: DMA channel + * @off1: first buffer offset + * @off2: second buffer offset + * @len: transfer length + * + * Return true if off1, off2 and len satisfy the copy alignment requirement of + * the DMA channel, false otherwise. + */ +static inline bool dmaengine_is_copy_aligned(struct dma_chan *chan, size_t off1, + size_t off2, size_t len) +{ + return dmaengine_check_align(chan->device->copy_align, off1, off2, len); +} + +/** + * dmaengine_is_xor_aligned - test xor alignment + * @chan: DMA channel + * @off1: first buffer offset + * @off2: second buffer offset + * @len: transfer length + * + * Return true if off1, off2 and len satisfy the xor alignment requirement of + * the DMA channel, false otherwise. + */ +static inline bool dmaengine_is_xor_aligned(struct dma_chan *chan, size_t off1, + size_t off2, size_t len) +{ + return dmaengine_check_align(chan->device->xor_align, off1, off2, len); +} + +/** + * dmaengine_is_pq_aligned - test pq alignment + * @chan: DMA channel + * @off1: first buffer offset + * @off2: second buffer offset + * @len: transfer length + * + * Return true if off1, off2 and len satisfy the pq alignment requirement of + * the DMA channel, false otherwise. + */ +static inline bool dmaengine_is_pq_aligned(struct dma_chan *chan, size_t off1, + size_t off2, size_t len) +{ + return dmaengine_check_align(chan->device->pq_align, off1, off2, len); +} + +/** + * dmaengine_is_fill_aligned - test fill alignment + * @chan: DMA channel + * @off1: first buffer offset + * @off2: second buffer offset + * @len: transfer length + * + * Return true if off1, off2 and len satisfy the fill alignment requirement of + * the DMA channel, false otherwise. + */ +static inline bool dmaengine_is_fill_aligned(struct dma_chan *chan, size_t off1, + size_t off2, size_t len) +{ + return dmaengine_check_align(chan->device->fill_align, off1, off2, len); +} + static inline void dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue) { From 072975a8a578a62ea68ec1ceb8d2d7dcfb5dfefa Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 5 Oct 2026 05:37:16 -0400 Subject: [PATCH 141/149] dmaengine: add dmaengine_get_copy_align() and related alignment getter helpers Add dmaengine_get_copy_align(), dmaengine_get_xor_align(), dmaengine_get_pq_align(), and dmaengine_get_fill_align() inline helpers to retrieve the alignment requirement of a DMA channel as a power-of-2 exponent. These complement the existing dmaengine_is_*_aligned() test helpers by providing direct access to the alignment value, which is useful when callers need to propagate or compare alignment constraints. Signed-off-by: Frank Li Link: https://patch.msgid.link/20261005-dmaengine_prep_dma_pq-v3-3-a4a241f26fa7@nxp.com Signed-off-by: Vinod Koul --- include/linux/dmaengine.h | 48 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 07fe91bdd8d7..efe421503501 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -1557,6 +1557,54 @@ static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1, return dmaengine_check_align(dev->fill_align, off1, off2, len); } +/** + * dmaengine_get_copy_align - get copy alignment requirement of a DMA channel + * @chan: DMA channel + * + * Return the copy alignment requirement of @chan as a power-of-2 exponent. + */ +static inline enum dmaengine_alignment +dmaengine_get_copy_align(struct dma_chan *chan) +{ + return chan->device->copy_align; +} + +/** + * dmaengine_get_xor_align - get xor alignment requirement of a DMA channel + * @chan: DMA channel + * + * Return the xor alignment requirement of @chan as a power-of-2 exponent. + */ +static inline enum dmaengine_alignment +dmaengine_get_xor_align(struct dma_chan *chan) +{ + return chan->device->xor_align; +} + +/** + * dmaengine_get_pq_align - get pq alignment requirement of a DMA channel + * @chan: DMA channel + * + * Return the pq alignment requirement of @chan as a power-of-2 exponent. + */ +static inline enum dmaengine_alignment +dmaengine_get_pq_align(struct dma_chan *chan) +{ + return chan->device->pq_align; +} + +/** + * dmaengine_get_fill_align - get fill alignment requirement of a DMA channel + * @chan: DMA channel + * + * Return the fill alignment requirement of @chan as a power-of-2 exponent. + */ +static inline enum dmaengine_alignment +dmaengine_get_fill_align(struct dma_chan *chan) +{ + return chan->device->fill_align; +} + /** * dmaengine_is_copy_aligned - test copy alignment * @chan: DMA channel From bbc109e0e686266d784483df108af206bc52e120 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 5 Oct 2026 05:37:17 -0400 Subject: [PATCH 142/149] dmaengine: add dmaengine_get_cap_mask() and dmaengine_has_cap() helpers Add two new inline helpers to query DMA channel capabilities without directly accessing the internal dma_device pointer: dmaengine_get_cap_mask(chan) - returns a const pointer to the capability mask of the DMA device backing the channel. dmaengine_has_cap(chan, tx_type) - returns true if the channel supports the given transaction type. These complement the existing dma_has_cap() macro which operates on a dma_cap_mask_t directly. Signed-off-by: Frank Li Link: https://patch.msgid.link/20261005-dmaengine_prep_dma_pq-v3-4-a4a241f26fa7@nxp.com Signed-off-by: Vinod Koul --- include/linux/dmaengine.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index efe421503501..4e4e1cc22b9a 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -1605,6 +1605,18 @@ dmaengine_get_fill_align(struct dma_chan *chan) return chan->device->fill_align; } +/** + * dmaengine_get_cap_mask - get capability mask of a DMA channel + * @chan: DMA channel + * + * Return a pointer to the capability mask of the DMA device backing @chan. + */ +static inline const dma_cap_mask_t * +dmaengine_get_cap_mask(struct dma_chan *chan) +{ + return &chan->device->cap_mask; +} + /** * dmaengine_is_copy_aligned - test copy alignment * @chan: DMA channel @@ -1830,6 +1842,19 @@ __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) return test_bit(tx_type, srcp->bits); } +/** + * dmaengine_has_cap - test whether a DMA channel supports a transaction type + * @chan: DMA channel + * @tx_type: transaction type to test + * + * Return true if @chan supports @tx_type, false otherwise. + */ +static inline bool +dmaengine_has_cap(struct dma_chan *chan, enum dma_transaction_type tx_type) +{ + return dma_has_cap(tx_type, chan->device->cap_mask); +} + #define for_each_dma_cap_mask(cap, mask) \ for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END) From bff69558d64a98bc8d03f373d1331223c3428a2c Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 5 Oct 2026 05:37:18 -0400 Subject: [PATCH 143/149] dmaengine: add dmaengine_get_max_xor() helper Add a new inline helper dmaengine_get_max_xor() that returns the maximum number of XOR source buffers supported by the DMA channel's device. Returns 0 if the channel is NULL or does not support XOR operations. Signed-off-by: Frank Li Link: https://patch.msgid.link/20261005-dmaengine_prep_dma_pq-v3-5-a4a241f26fa7@nxp.com Signed-off-by: Vinod Koul --- include/linux/dmaengine.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 4e4e1cc22b9a..713f3ad68330 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -1252,6 +1252,21 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memcpy( len, flags); } +/** + * dmaengine_get_max_xor - get the maximum number of XOR sources for a channel + * @chan: DMA channel + * + * Returns the maximum number of source buffers supported by the XOR engine + * behind @chan, or 0 if the channel does not support XOR operations. + */ +static inline unsigned int dmaengine_get_max_xor(struct dma_chan *chan) +{ + if (!chan || !chan->device) + return 0; + + return chan->device->max_xor; +} + /** * dmaengine_prep_dma_xor - prepare a DMA XOR operation * @chan: the channel to use for this operation From 61527d7e6998e87b3acd04f1cd2f4d6814385051 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 2 Oct 2026 16:23:40 -0400 Subject: [PATCH 144/149] dmaengine: add dmaengine_get_provider_device() API Add dmaengine_get_provider_device() API and kernel doc for dmaengine_get_dma_device() to describe the difference. dmaengine_get_dma_device() is used for DMA mapping because some DMA engines provide per-channel iommu mapping. dmaengine_get_provider_device() is used to find a DMA engine channel by a filter function. In most cases they return the same value, but they have different semantic meanings. Signed-off-by: Frank Li Link: https://patch.msgid.link/20261002202341.253152-1-Frank.Li@oss.nxp.com Signed-off-by: Vinod Koul --- include/linux/dma/imx-dma.h | 6 ++++-- include/linux/dmaengine.h | 21 ++++++++++++++++++++- 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/include/linux/dma/imx-dma.h b/include/linux/dma/imx-dma.h index 16e491f63883..7c678316b757 100644 --- a/include/linux/dma/imx-dma.h +++ b/include/linux/dma/imx-dma.h @@ -59,8 +59,10 @@ struct imx_dma_data { static inline int imx_dma_is_general_purpose(struct dma_chan *chan) { - return !strcmp(chan->device->dev->driver->name, "imx-sdma") || - !strcmp(chan->device->dev->driver->name, "imx-dma"); + struct device *dev = dmaengine_get_provider_device(chan); + + return !strcmp(dev->driver->name, "imx-sdma") || + !strcmp(dev->driver->name, "imx-dma"); } /** diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 713f3ad68330..1ee63fdb90a7 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -2122,12 +2122,31 @@ static inline struct device *dmaengine_chan_dev(struct dma_chan *chan) return &chan->chan_dev->device; } +/* + * dmaengine_get_provider_device() - Get DMA engine provider device. Typical + * use is to find a DMA channel by filter. + * @chan: DMA channel + * + * Return: Pointer to the DMA engine provider device. + */ +static inline struct device *dmaengine_get_provider_device(struct dma_chan *chan) +{ + return chan->device->dev; +} + +/* + * dmaengine_get_dma_device() - Get DMA device used for DMA mapping. Some + * DMA engines provide per-channel iommu mapping. + * @chan: DMA channel + * + * Return: Pointer to the device used for DMA mapping. + */ static inline struct device *dmaengine_get_dma_device(struct dma_chan *chan) { if (chan->chan_dev->chan_dma_dev) return dmaengine_chan_dev(chan); - return chan->device->dev; + return dmaengine_get_provider_device(chan); } #endif /* DMAENGINE_H */ From 562b6ed45db52934aaab9fbc856db3db79753155 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 2 Oct 2026 15:54:09 -0400 Subject: [PATCH 145/149] dmaengine: add dmaengine_desc_set_callback() helper Add a dmaengine_desc_set_callback() inline helper that sets the callback, callback_result, and callback_param fields of a dma_async_tx_descriptor together in a single call. Using this helper instead of open-coding the three field assignments ensures all three related fields are always updated consistently and makes call sites more readable. Signed-off-by: Frank Li Link: https://patch.msgid.link/20261002195410.213610-1-Frank.Li@oss.nxp.com Signed-off-by: Vinod Koul --- include/linux/dmaengine.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 1ee63fdb90a7..1639f8a0a824 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -2060,6 +2060,31 @@ static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc) return desc->desc_free(desc); } +/** + * dmaengine_desc_set_callback - set the callback, callback_result and + * parameter on a descriptor + * @tx: the descriptor to set the callback on + * @cb: the plain completion callback, or NULL + * @cb_result: the result-bearing completion callback, or NULL + * @cb_param: the parameter to pass to the callback + * + * Sets the completion callbacks and their shared parameter on a DMA + * transaction descriptor. Use this helper instead of assigning the fields + * directly to ensure all three related fields are updated consistently. + * Only one of @cb and @cb_result should be non-NULL; if both are provided + * @cb_result takes precedence in drivers that support it. + */ +static inline void +dmaengine_desc_set_callback(struct dma_async_tx_descriptor *tx, + dma_async_tx_callback cb, + dma_async_tx_callback_result cb_result, + void *cb_param) +{ + tx->callback = cb; + tx->callback_result = cb_result; + tx->callback_param = cb_param; +} + /* --- DMA device --- */ int dma_async_device_register(struct dma_device *device); From 511afae96d89847f753fcab6b3a597f0281be9d5 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 1 Oct 2026 10:39:53 -0400 Subject: [PATCH 146/149] dmaengine: move driver-private helpers out of include/linux/dmaengine.h Move the following functions and declarations from the public header include/linux/dmaengine.h into the driver-private header drivers/dma/dmaengine.h, since they are only used by DMA engine drivers and not by DMA engine consumers: - dma_async_device_register() - dmaenginem_async_device_register() - dma_async_device_unregister() - dma_async_device_channel_register() - dma_async_device_channel_unregister() - is_slave_direction() - dmaengine_get_direction_text() Signed-off-by: Frank Li Link: https://patch.msgid.link/20261001143955.2195063-1-Frank.Li@oss.nxp.com Signed-off-by: Vinod Koul --- drivers/dma/dmaengine.h | 32 ++++++++++++++++++++++++++++++++ drivers/dma/dw/dw.c | 1 + include/linux/dmaengine.h | 31 ------------------------------- 3 files changed, 33 insertions(+), 31 deletions(-) diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h index 53f16d3f0029..42a3cfa7e597 100644 --- a/drivers/dma/dmaengine.h +++ b/drivers/dma/dmaengine.h @@ -182,6 +182,38 @@ dmaengine_desc_callback_valid(struct dmaengine_desc_callback *cb) struct dma_chan *dma_get_slave_channel(struct dma_chan *chan); struct dma_chan *dma_get_any_slave_channel(struct dma_device *device); +static inline char * +dmaengine_get_direction_text(enum dma_transfer_direction dir) +{ + switch (dir) { + case DMA_DEV_TO_MEM: + return "DEV_TO_MEM"; + case DMA_MEM_TO_DEV: + return "MEM_TO_DEV"; + case DMA_MEM_TO_MEM: + return "MEM_TO_MEM"; + case DMA_DEV_TO_DEV: + return "DEV_TO_DEV"; + default: + return "invalid"; + } +} + +static inline bool is_slave_direction(enum dma_transfer_direction direction) +{ + return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM) || + (direction == DMA_DEV_TO_DEV); +} + +int dma_async_device_register(struct dma_device *device); +int dmaenginem_async_device_register(struct dma_device *device); +void dma_async_device_unregister(struct dma_device *device); +int dma_async_device_channel_register(struct dma_device *device, + struct dma_chan *chan, + const char *name); +void dma_async_device_channel_unregister(struct dma_device *device, + struct dma_chan *chan); + #ifdef CONFIG_DEBUG_FS #include diff --git a/drivers/dma/dw/dw.c b/drivers/dma/dw/dw.c index 6766142884b6..e56974e7d4af 100644 --- a/drivers/dma/dw/dw.c +++ b/drivers/dma/dw/dw.c @@ -9,6 +9,7 @@ #include #include +#include "../dmaengine.h" #include "internal.h" static void dw_dma_initialize_chan(struct dw_dma_chan *dwc) diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 1639f8a0a824..71cde09ff240 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -1009,12 +1009,6 @@ static inline int dmaengine_slave_config(struct dma_chan *chan, return -ENOSYS; } -static inline bool is_slave_direction(enum dma_transfer_direction direction) -{ - return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM) || - (direction == DMA_DEV_TO_DEV); -} - static inline struct dma_async_tx_descriptor * dmaengine_prep_config_single(struct dma_chan *chan, dma_addr_t buf, size_t len, enum dma_transfer_direction dir, @@ -2087,14 +2081,6 @@ dmaengine_desc_set_callback(struct dma_async_tx_descriptor *tx, /* --- DMA device --- */ -int dma_async_device_register(struct dma_device *device); -int dmaenginem_async_device_register(struct dma_device *device); -void dma_async_device_unregister(struct dma_device *device); -int dma_async_device_channel_register(struct dma_device *device, - struct dma_chan *chan, - const char *name); -void dma_async_device_channel_unregister(struct dma_device *device, - struct dma_chan *chan); void dma_run_dependencies(struct dma_async_tx_descriptor *tx); #define dma_request_channel(mask, x, y) \ __dma_request_channel(&(mask), x, y, NULL) @@ -2125,23 +2111,6 @@ static inline struct dma_chan return dma_request_channel(mask, fn, fn_param); } -static inline char * -dmaengine_get_direction_text(enum dma_transfer_direction dir) -{ - switch (dir) { - case DMA_DEV_TO_MEM: - return "DEV_TO_MEM"; - case DMA_MEM_TO_DEV: - return "MEM_TO_DEV"; - case DMA_MEM_TO_MEM: - return "MEM_TO_MEM"; - case DMA_DEV_TO_DEV: - return "DEV_TO_DEV"; - default: - return "invalid"; - } -} - static inline struct device *dmaengine_chan_dev(struct dma_chan *chan) { return &chan->chan_dev->device; From fa89be96e845de705eed6edd01ecb79d46ee21c7 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Fri, 9 Oct 2026 11:37:44 +0200 Subject: [PATCH 147/149] docs: dmaengine: clarify ordering rules around cookie completion Sashiko pointed in [1] about the cookie completion order. It is good to Document that for ensuring that dma buffer is flushed and no stale data is seeing by consumer, we need to make sure such action is taken before drivers invoke dma cookie completion. [1]: https://lore.kernel.org/r/20260917072507.5BDB61F000FF@smtp.kernel.org Reviewed-by: Frank Li Reviewed-by: Dave Jiang Reviewed-by: Wolfram Sang Link: https://patch.msgid.link/20261009093745.539924-1-vkoul@kernel.org Signed-off-by: Vinod Koul --- Documentation/driver-api/dmaengine/provider.rst | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/driver-api/dmaengine/provider.rst b/Documentation/driver-api/dmaengine/provider.rst index 2897ade67b39..be47852e5a0f 100644 --- a/Documentation/driver-api/dmaengine/provider.rst +++ b/Documentation/driver-api/dmaengine/provider.rst @@ -557,6 +557,11 @@ dma_cookie_t - Not really relevant any more since the introduction of ``virt-dma`` that abstracts it away. +- dmaengine drivers need to ensure buffers are flushed before invoking + vchan_cookie_complete() or dma_cookie_complete(). This would imply a call + to unmapping buffers or any such architecture calls to ensure caller seeing + buffers are flushed is done before invoking these calls. + dma_vec - A small structure that contains a DMA address and length. From 42c31fec1ca76b8b5f7759def122d418dff2cd4b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 10 Oct 2026 00:58:53 +0200 Subject: [PATCH 148/149] dmaengine: ste_dma40: Preserve the LCPA I/O address space The LCPA area is mapped with devm_ioremap(), but lcpa_base and the per-channel lcpa pointer lack __iomem annotations. This loses the I/O address space and makes sparse warn when d40_current_addr() assigns LCPA register addresses to its __iomem pointers. Annotate both pointers and the LCPA argument of d40_log_lli_lcpa_write() to preserve the I/O address space from the mapping to the register accessors. This also fixes the existing LCPA read and write warnings without changing the generated code. Fixes: c80edceff29e ("dmaengine: ste_dma40: Fix cyclic transfer residue") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202610090216.pjMRxhRL-lkp@intel.com/ Assisted-by: LLM Signed-off-by: Linus Walleij Reviewed-by: Frank Li Link: https://patch.msgid.link/20261010-dma40-smatch-fix-v1-1-26ca10043957@kernel.org Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 4 ++-- drivers/dma/ste_dma40_ll.c | 8 ++++---- drivers/dma/ste_dma40_ll.h | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index d3cc2c512ccf..74dd4cbdc3c0 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -509,7 +509,7 @@ struct d40_chan { u32 src_def_cfg; u32 dst_def_cfg; struct d40_def_lcsp log_def; - struct d40_log_lli_full *lcpa; + struct d40_log_lli_full __iomem *lcpa; /* Runtime reconfiguration */ dma_addr_t runtime_addr; enum dma_transfer_direction runtime_direction; @@ -617,7 +617,7 @@ struct d40_base { /* Physical half channels */ struct d40_phy_res *phy_res; struct d40_lcla_pool lcla_pool; - void *lcpa_base; + void __iomem *lcpa_base; dma_addr_t phy_lcpa; resource_size_t lcpa_size; struct kmem_cache *desc_slab; diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c index 4c489b126cb2..3be7f5b1abb0 100644 --- a/drivers/dma/ste_dma40_ll.c +++ b/drivers/dma/ste_dma40_ll.c @@ -333,10 +333,10 @@ static void d40_log_lli_link(struct d40_log_lli *lli_dst, (dlos << D40_MEM_LCSP1_SLOS_POS); } -void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa, - struct d40_log_lli *lli_dst, - struct d40_log_lli *lli_src, - int next, unsigned int flags) +void d40_log_lli_lcpa_write(struct d40_log_lli_full __iomem *lcpa, + struct d40_log_lli *lli_dst, + struct d40_log_lli *lli_src, + int next, unsigned int flags) { d40_log_lli_link(lli_dst, lli_src, next, flags); diff --git a/drivers/dma/ste_dma40_ll.h b/drivers/dma/ste_dma40_ll.h index 55090cb31057..ca9d07649361 100644 --- a/drivers/dma/ste_dma40_ll.h +++ b/drivers/dma/ste_dma40_ll.h @@ -455,7 +455,7 @@ int d40_log_sg_to_lli(struct scatterlist *sg, u32 lcsp13, /* src or dst*/ u32 data_width1, u32 data_width2); -void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa, +void d40_log_lli_lcpa_write(struct d40_log_lli_full __iomem *lcpa, struct d40_log_lli *lli_dst, struct d40_log_lli *lli_src, int next, unsigned int flags); From aff5e6a77fc69a7c490246465940d18422d7c631 Mon Sep 17 00:00:00 2001 From: Xianwei Zhao Date: Fri, 16 Oct 2026 03:00:17 +0000 Subject: [PATCH 149/149] dmaengine: amlogic: Fix regmap error check issue The func devm_regmap_init_mmio() only returns an error pointer on failure, Use IS_ERR() instead to make the intent clearer. And Fix the following compilation issue at the same time. Smatch warnings: drivers/dma/amlogic-dma.c:636 aml_dma_probe() warn: passing zero to 'PTR_ERR' Fixes: b84b5197e344 ("dmaengine: amlogic: Add general DMA driver for A9") Reported-by: kernel test robot Closes: https://lore.kernel.org/r/202610080953.C5TYlCaA-lkp@intel.com/ Reported-by: Dan Carpenter Signed-off-by: Xianwei Zhao Reviewed-by: Frank Li Link: https://patch.msgid.link/20261016-fix-a9-dma-complier-v1-1-024421d5b3c8@amlogic.com Signed-off-by: Vinod Koul --- drivers/dma/amlogic-dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/amlogic-dma.c b/drivers/dma/amlogic-dma.c index 78ee2337ae71..684121d13fca 100644 --- a/drivers/dma/amlogic-dma.c +++ b/drivers/dma/amlogic-dma.c @@ -632,7 +632,7 @@ static int aml_dma_probe(struct platform_device *pdev) aml_dma->regmap = devm_regmap_init_mmio(&pdev->dev, aml_dma->base, &aml_regmap_config); - if (IS_ERR_OR_NULL(aml_dma->regmap)) + if (IS_ERR(aml_dma->regmap)) return PTR_ERR(aml_dma->regmap); aml_dma->clk = devm_clk_get_enabled(&pdev->dev, NULL);