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ASoC: SDCA: fix the register to ctl value conversion for Q7.8 format

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The division calculation should be implemented using signed integer format.
This patch changes mc->shift from an unsigned type to a signed integer during the calculation.

Fixes: 501efdcb3b ("ASoC: SDCA: Pull the Q7.8 volume helpers out of soc-ops")
Signed-off-by: Shuming Fan <shumingf@realtek.com>
Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://patch.msgid.link/20260327082331.2277498-1-shumingf@realtek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Shuming Fan 2026-03-27 16:23:31 +08:00 committed by Mark Brown
parent 7caae0aed0
commit ae00200acb
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1 changed files with 1 additions and 1 deletions
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sound/soc/sdca/sdca_asoc.c
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@ -850,7 +850,7 @@ static int q78_read(struct snd_soc_component *component,
reg_val = snd_soc_component_read(component, reg);
val = (sign_extend32(reg_val, mc->sign_bit) / mc->shift) - mc->min;
val = (sign_extend32(reg_val, mc->sign_bit) / (int)mc->shift) - mc->min;
return val & GENMASK(mc->sign_bit, 0);
}