github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-28 17:13:52 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

drm/i915/ltphy: Modify the step that need to be skipped

Browse Source 
Bspec has changed the non tbt pll enable sequence now we skip
steps 5-17 if no config change has occurred.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-26-suraj.kandpal@intel.com
This commit is contained in:
Suraj Kandpal 2025-11-01 08:55:13 +05:30
parent e34c635694
commit ad7108f966
1 changed files with 33 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

63
drivers/gpu/drm/i915/display/intel_lt_phy.c
View File

@ -1677,40 +1677,43 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
drm_warn(display->drm, "PHY %c PLL MacCLK Ack assertion Timeout after %dus.\n",
phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);
/*
* 13. Ungate the forward clock by setting
* PORT_CLOCK_CTL[Forward Clock Ungate] = 1.
*/
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
XELPDP_FORWARD_CLOCK_UNGATE,
XELPDP_FORWARD_CLOCK_UNGATE);
/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
lane_phy_pulse_status,
lane_phy_pulse_status);
/*
* 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over
* PHY message bus for Owned PHY Lanes.
*/
rate_update = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_RATE_UPDATE);
rate_update &= ~LT_PHY_RATE_CONTROL_VDR_UPDATE;
intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_RATE_UPDATE,
rate_update, MB_WRITE_COMMITTED);
/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
lane_phy_pulse_status, lane_phy_pulse_status,
XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
/* 17. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
lane_phy_pulse_status,
lane_phy_pulse_status);
} else {
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), crtc_state->port_clock);
}
/* 13. Ungate the forward clock by setting PORT_CLOCK_CTL[Forward Clock Ungate] = 1. */
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
XELPDP_FORWARD_CLOCK_UNGATE,
XELPDP_FORWARD_CLOCK_UNGATE);
/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
lane_phy_pulse_status,
lane_phy_pulse_status);
/*
* 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over PHY message bus for
* Owned PHY Lanes.
*/
rate_update = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_RATE_UPDATE);
rate_update &= ~LT_PHY_RATE_CONTROL_VDR_UPDATE;
intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_RATE_UPDATE,
rate_update, MB_WRITE_COMMITTED);
/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
lane_phy_pulse_status, lane_phy_pulse_status,
XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
/* 17. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
lane_phy_pulse_status,
lane_phy_pulse_status);
/*
* 18. Follow the Display Voltage Frequency Switching - Sequence After Frequency Change.
* We handle this step in bxt_set_cdclk()