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PM / devfreq: rockchip_dmc: add support for rk3568
Change-Id: I64f11fefb6227805031e911910a0123e4c0f9d78 Signed-off-by: YouMin Chen <cym@rock-chips.com>
This commit is contained in:
YouMin Chen
Tao Huang
parent
8a4608928a
commit
ad4ff95560
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@ -795,6 +795,42 @@ static void of_get_rk3328_timings(struct device *dev,
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of_node_put(np_tim);
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}
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static void of_get_rk3568_timings(struct device *dev,
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struct device_node *np, uint32_t *timing)
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{
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struct device_node *np_tim;
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u32 *p;
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struct rk3568_ddr_dts_config_timing *dts_timing;
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int ret = 0;
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u32 i;
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dts_timing =
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(struct rk3568_ddr_dts_config_timing *)(timing +
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DTS_PAR_OFFSET / 4);
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np_tim = of_parse_phandle(np, "ddr_timing", 0);
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if (!np_tim) {
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ret = -EINVAL;
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goto end;
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}
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p = (u32 *)dts_timing;
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for (i = 0; i < ARRAY_SIZE(px30_dts_timing); i++) {
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ret |= of_property_read_u32(np_tim, px30_dts_timing[i],
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p + i);
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}
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end:
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if (!ret) {
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dts_timing->available = 1;
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} else {
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dts_timing->available = 0;
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dev_err(dev, "of_get_ddr_timings: fail\n");
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}
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of_node_put(np_tim);
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}
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static void of_get_rv1126_timings(struct device *dev,
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struct device_node *np, uint32_t *timing)
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{
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@ -1103,6 +1139,8 @@ static irqreturn_t wait_dcf_complete_irq(int irqno, void *dev_id)
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int rockchip_dmcfreq_wait_complete(void)
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{
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struct arm_smccc_res res;
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if (!wait_ctrl.wait_en) {
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pr_err("%s: Do not support time out!\n", __func__);
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return 0;
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@ -1119,6 +1157,12 @@ int rockchip_dmcfreq_wait_complete(void)
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if (wait_ctrl.dcf_en == 1) {
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/* start dcf */
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regmap_update_bits(wait_ctrl.regmap_dcf, 0x0, 0x1, 0x1);
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} else if (wait_ctrl.dcf_en == 2) {
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res = sip_smc_dram(0, 0, ROCKCHIP_SIP_CONFIG_MCU_START);
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if (res.a0) {
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pr_err("rockchip_sip_config_mcu_start error:%lx\n", res.a0);
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return -ENOMEM;
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}
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}
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wait_event_timeout(wait_ctrl.wait_wq, (wait_ctrl.wait_flag == 0),
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@ -1618,6 +1662,82 @@ static __maybe_unused int rk3399_dmc_init(struct platform_device *pdev,
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return 0;
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}
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static __maybe_unused int rk3568_dmc_init(struct platform_device *pdev,
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struct rockchip_dmcfreq *dmcfreq)
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{
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struct arm_smccc_res res;
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u32 size;
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int ret;
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int complt_irq;
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res = sip_smc_dram(0, 0,
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ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION);
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dev_notice(&pdev->dev, "current ATF version 0x%lx\n", res.a1);
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if (res.a0 || res.a1 < 0x100) {
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dev_err(&pdev->dev,
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"trusted firmware need to update or is invalid!\n");
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return -ENXIO;
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}
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/*
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* first 4KB is used for interface parameters
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* after 4KB * N is dts parameters
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*/
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size = sizeof(struct rk1808_ddr_dts_config_timing);
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res = sip_smc_request_share_mem(DIV_ROUND_UP(size, 4096) + 1,
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SHARE_PAGE_TYPE_DDR);
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if (res.a0 != 0) {
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dev_err(&pdev->dev, "no ATF memory for init\n");
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return -ENOMEM;
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}
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ddr_psci_param = (struct share_params *)res.a1;
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of_get_rk3568_timings(&pdev->dev, pdev->dev.of_node,
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(uint32_t *)ddr_psci_param);
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/* start mcu with sip_smc_dram */
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wait_ctrl.dcf_en = 2;
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init_waitqueue_head(&wait_ctrl.wait_wq);
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wait_ctrl.wait_en = 1;
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wait_ctrl.wait_time_out_ms = 17 * 5;
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complt_irq = platform_get_irq_byname(pdev, "complete");
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if (complt_irq < 0) {
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dev_err(&pdev->dev, "no IRQ for complt_irq: %d\n",
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complt_irq);
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return complt_irq;
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}
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wait_ctrl.complt_irq = complt_irq;
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ret = devm_request_irq(&pdev->dev, complt_irq, wait_dcf_complete_irq,
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0, dev_name(&pdev->dev), &wait_ctrl);
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if (ret < 0) {
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dev_err(&pdev->dev, "cannot request complt_irq\n");
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return ret;
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}
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disable_irq(complt_irq);
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if (of_property_read_u32(pdev->dev.of_node, "update_drv_odt_cfg",
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&ddr_psci_param->update_drv_odt_cfg))
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ddr_psci_param->update_drv_odt_cfg = 0;
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if (of_property_read_u32(pdev->dev.of_node, "update_deskew_cfg",
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&ddr_psci_param->update_deskew_cfg))
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ddr_psci_param->update_deskew_cfg = 0;
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res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
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ROCKCHIP_SIP_CONFIG_DRAM_INIT);
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if (res.a0) {
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dev_err(&pdev->dev, "rockchip_sip_config_dram_init error:%lx\n",
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res.a0);
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return -ENOMEM;
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}
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dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
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return 0;
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}
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static __maybe_unused int rv1126_dmc_init(struct platform_device *pdev,
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struct rockchip_dmcfreq *dmcfreq)
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{
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@ -1727,6 +1847,9 @@ static const struct of_device_id rockchip_dmcfreq_of_match[] = {
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#ifdef CONFIG_CPU_RK3399
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{ .compatible = "rockchip,rk3399-dmc", .data = rk3399_dmc_init },
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#endif
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#ifdef CONFIG_CPU_RK3568
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{ .compatible = "rockchip,rk3568-dmc", .data = rk3568_dmc_init },
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#endif
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#ifdef CONFIG_CPU_RV1126
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{ .compatible = "rockchip,rv1126-dmc", .data = rv1126_dmc_init },
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#endif
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@ -1003,6 +1003,82 @@ struct rk3399_dram_timing {
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unsigned int phy_lpddr4_odt;
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};
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struct rk3568_ddr_dts_config_timing {
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unsigned int ddr2_speed_bin;
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unsigned int ddr3_speed_bin;
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unsigned int ddr4_speed_bin;
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unsigned int pd_idle;
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unsigned int sr_idle;
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unsigned int sr_mc_gate_idle;
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unsigned int srpd_lite_idle;
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unsigned int standby_idle;
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unsigned int auto_pd_dis_freq;
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unsigned int auto_sr_dis_freq;
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/* for ddr2 only */
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unsigned int ddr2_dll_dis_freq;
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/* for ddr3 only */
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unsigned int ddr3_dll_dis_freq;
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/* for ddr4 only */
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unsigned int ddr4_dll_dis_freq;
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unsigned int phy_dll_dis_freq;
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unsigned int ddr2_odt_dis_freq;
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unsigned int phy_ddr2_odt_dis_freq;
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unsigned int ddr2_drv;
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unsigned int ddr2_odt;
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unsigned int phy_ddr2_ca_drv;
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unsigned int phy_ddr2_ck_drv;
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unsigned int phy_ddr2_dq_drv;
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unsigned int phy_ddr2_odt;
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unsigned int ddr3_odt_dis_freq;
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unsigned int phy_ddr3_odt_dis_freq;
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unsigned int ddr3_drv;
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unsigned int ddr3_odt;
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unsigned int phy_ddr3_ca_drv;
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unsigned int phy_ddr3_ck_drv;
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unsigned int phy_ddr3_dq_drv;
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unsigned int phy_ddr3_odt;
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unsigned int phy_lpddr2_odt_dis_freq;
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unsigned int lpddr2_drv;
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unsigned int phy_lpddr2_ca_drv;
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unsigned int phy_lpddr2_ck_drv;
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unsigned int phy_lpddr2_dq_drv;
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unsigned int phy_lpddr2_odt;
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unsigned int lpddr3_odt_dis_freq;
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unsigned int phy_lpddr3_odt_dis_freq;
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unsigned int lpddr3_drv;
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unsigned int lpddr3_odt;
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unsigned int phy_lpddr3_ca_drv;
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unsigned int phy_lpddr3_ck_drv;
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unsigned int phy_lpddr3_dq_drv;
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unsigned int phy_lpddr3_odt;
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unsigned int lpddr4_odt_dis_freq;
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unsigned int phy_lpddr4_odt_dis_freq;
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unsigned int lpddr4_drv;
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unsigned int lpddr4_dq_odt;
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unsigned int lpddr4_ca_odt;
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unsigned int phy_lpddr4_ca_drv;
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unsigned int phy_lpddr4_ck_cs_drv;
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unsigned int phy_lpddr4_dq_drv;
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unsigned int phy_lpddr4_odt;
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unsigned int ddr4_odt_dis_freq;
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unsigned int phy_ddr4_odt_dis_freq;
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unsigned int ddr4_drv;
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unsigned int ddr4_odt;
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unsigned int phy_ddr4_ca_drv;
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unsigned int phy_ddr4_ck_drv;
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unsigned int phy_ddr4_dq_drv;
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unsigned int phy_ddr4_odt;
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unsigned int available;
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};
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/* name rule: ddr4(pad_name)_ddr3_lpddr3_lpddr4_de-skew */
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static const char * const rv1126_dts_ca_timing[] = {
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"a0_a3_a3_cke1-a_de-skew",
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@ -27,5 +27,6 @@
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#define ROCKCHIP_SIP_CONFIG_DRAM_POST_SET_RATE 0x09
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#define ROCKCHIP_SIP_CONFIG_DRAM_SET_MSCH_RL 0x0a
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#define ROCKCHIP_SIP_CONFIG_DRAM_DEBUG 0x0b
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#define ROCKCHIP_SIP_CONFIG_MCU_START 0x0c
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#endif
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