diff --git a/arch/arm64/configs/vendor/pineapple_GKI.config b/arch/arm64/configs/vendor/pineapple_GKI.config index 7c6669120713..a3ce005a16fb 100644 --- a/arch/arm64/configs/vendor/pineapple_GKI.config +++ b/arch/arm64/configs/vendor/pineapple_GKI.config @@ -1,7 +1,9 @@ CONFIG_ARCH_PINEAPPLE=y +CONFIG_COMMON_CLK_QCOM=m CONFIG_LOCALVERSION="-gki" # CONFIG_MODULE_SIG_ALL is not set CONFIG_PINCTRL_MSM=m CONFIG_PINCTRL_PINEAPPLE=m CONFIG_QCOM_SCM=m # CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set +CONFIG_REGULATOR_STUB=m diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 1718c34d3551..533f56563cd3 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -15,6 +15,7 @@ clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o clk-qcom-y += clk-hfpll.o clk-qcom-y += reset.o clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o +obj-$(CONFIG_COMMON_CLK_QCOM) += clk-dummy.o # Keep alphabetically sorted by config obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o diff --git a/drivers/clk/qcom/clk-dummy.c b/drivers/clk/qcom/clk-dummy.c new file mode 100644 index 000000000000..7e624381773e --- /dev/null +++ b/drivers/clk/qcom/clk-dummy.c @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include "common.h" + +#define to_clk_dummy(_hw) container_of(_hw, struct clk_dummy, hw) + +#define RESET_MAX 100 + +static int dummy_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_dummy *dummy = to_clk_dummy(hw); + + dummy->rrate = rate; + + pr_debug("%s: rate %lu\n", __func__, rate); + + return 0; +} + +static long dummy_clk_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + return rate; +} + +static unsigned long dummy_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_dummy *dummy = to_clk_dummy(hw); + + pr_debug("%s: returning a clock rate of %lu\n", + __func__, dummy->rrate); + + return dummy->rrate; +} + +const struct clk_ops clk_dummy_ops = { + .set_rate = dummy_clk_set_rate, + .round_rate = dummy_clk_round_rate, + .recalc_rate = dummy_clk_recalc_rate, +}; +EXPORT_SYMBOL(clk_dummy_ops); + +static int dummy_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return 0; +} + +static int dummy_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return 0; +} + +static struct reset_control_ops dummy_reset_ops = { + .assert = dummy_reset_assert, + .deassert = dummy_reset_deassert, +}; + +/** + * clk_register_dummy - register dummy clock with the + * clock framework + * @dev: device that is registering this clock + * @name: name of this clock + * @flags: framework-specific flags + * @node: device node + */ +static struct clk *clk_register_dummy(struct device *dev, const char *name, + unsigned long flags, struct device_node *node) +{ + struct clk_dummy *dummy; + struct clk *clk; + struct clk_init_data init = {}; + + /* allocate dummy clock */ + dummy = devm_kzalloc(dev, sizeof(*dummy), GFP_KERNEL); + if (!dummy) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &clk_dummy_ops; + init.flags = flags; + init.num_parents = 0; + dummy->hw.init = &init; + + /* register the clock */ + clk = devm_clk_register(dev, &dummy->hw); + if (IS_ERR(clk)) + return clk; + + dummy->reset.of_node = node; + dummy->reset.ops = &dummy_reset_ops; + dummy->reset.nr_resets = RESET_MAX; + + if (devm_reset_controller_register(dev, &dummy->reset)) + pr_err("Failed to register reset controller for %s\n", name); + else + pr_info("Successfully registered dummy reset controller for %s\n", name); + + return clk; +} + +static int dummy_clk_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + const char *clk_name = "dummy_clk"; + struct clk *clk; + int ret; + + of_property_read_string(node, "clock-output-names", &clk_name); + + clk = clk_register_dummy(&pdev->dev, clk_name, 0, node); + if (!IS_ERR(clk)) { + ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (ret) + return ret; + } else { + ret = PTR_ERR(clk); + pr_err("Failed to register dummy clock controller for %s, ret=%d\n", + clk_name, ret); + return ret; + } + + dev_info(&pdev->dev, "Successfully registered dummy clock controller for %s\n", + clk_name); + return 0; +} + +static int dummy_clk_remove(struct platform_device *pdev) +{ + of_clk_del_provider(pdev->dev.of_node); + + return 0; +} + +static const struct of_device_id dummy_clk_match_table[] = { + { .compatible = "qcom,dummycc" }, + { } +}; +MODULE_DEVICE_TABLE(of, dummy_clk_match_table); + +static struct platform_driver dummy_clk_driver = { + .probe = dummy_clk_probe, + .remove = dummy_clk_remove, + .driver = { + .name = "clk-dummy", + .of_match_table = dummy_clk_match_table, + }, +}; + +static int __init dummy_clk_init(void) +{ + return platform_driver_register(&dummy_clk_driver); +} +arch_initcall(dummy_clk_init); + +static void __exit dummy_clk_exit(void) +{ + platform_driver_unregister(&dummy_clk_driver); +} +module_exit(dummy_clk_exit); + +MODULE_DESCRIPTION("QTI Dummy Clock Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h index 9c8f7b798d9f..3c672ae04258 100644 --- a/drivers/clk/qcom/common.h +++ b/drivers/clk/qcom/common.h @@ -1,9 +1,11 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2014, The Linux Foundation. All rights reserved. */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2014, 2018, The Linux Foundation. All rights reserved. */ #ifndef __QCOM_CLK_COMMON_H__ #define __QCOM_CLK_COMMON_H__ +#include + struct platform_device; struct regmap_config; struct clk_regmap; @@ -41,6 +43,12 @@ struct parent_map { u8 cfg; }; +struct clk_dummy { + struct clk_hw hw; + struct reset_controller_dev reset; + unsigned long rrate; +}; + extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate); extern const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f, @@ -65,5 +73,5 @@ extern int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc); extern int qcom_cc_probe_by_index(struct platform_device *pdev, int index, const struct qcom_cc_desc *desc); - +extern const struct clk_ops clk_dummy_ops; #endif diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 1c35fed20d34..3c8b91fe80f0 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -1432,4 +1432,14 @@ config REGULATOR_QCOM_LABIBB boost regulator and IBB can be used as a negative boost regulator for LCD display panel. +config REGULATOR_STUB + tristate "Stub Regulator" + help + This driver adds stub regulator support. It allows for consumers to + request their regulator devices and to use all of the standard + regulator functions. It is useful for bringing up new platforms when + the real hardware based regulator implementation is not yet available. + Consumers can use stub regulator device with proper constraint + checking while the real regulator driver is being developed. + endif diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 2e1b087489fa..f4d72be145e9 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -173,4 +173,6 @@ obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o obj-$(CONFIG_REGULATOR_WM8994) += wm8994-regulator.o +obj-$(CONFIG_REGULATOR_STUB) += stub-regulator.o + ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG diff --git a/drivers/regulator/stub-regulator.c b/drivers/regulator/stub-regulator.c new file mode 100644 index 000000000000..d9c198d5cd9f --- /dev/null +++ b/drivers/regulator/stub-regulator.c @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012, 2016, 2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct regulator_stub { + struct regulator_desc rdesc; + int voltage; + bool enabled; + unsigned int mode; + int hpm_min_load_uA; + int system_load_uA; +}; + +static int regulator_stub_set_voltage(struct regulator_dev *rdev, int min_uV, + int max_uV, unsigned int *selector) +{ + struct regulator_stub *vreg = rdev_get_drvdata(rdev); + + vreg->voltage = min_uV; + + return 0; +} + +static int regulator_stub_get_voltage(struct regulator_dev *rdev) +{ + struct regulator_stub *vreg = rdev_get_drvdata(rdev); + + return vreg->voltage; +} + +static int regulator_stub_list_voltage(struct regulator_dev *rdev, + unsigned int selector) +{ + struct regulation_constraints *constraints = rdev->constraints; + + if (selector >= 2) + return -EINVAL; + else if (selector == 0) + return constraints->min_uV; + else + return constraints->max_uV; +} + +static unsigned int regulator_stub_get_mode(struct regulator_dev *rdev) +{ + struct regulator_stub *vreg = rdev_get_drvdata(rdev); + + return vreg->mode; +} + +static int regulator_stub_set_mode(struct regulator_dev *rdev, + unsigned int mode) +{ + struct regulator_stub *vreg = rdev_get_drvdata(rdev); + + if (mode != REGULATOR_MODE_NORMAL && mode != REGULATOR_MODE_IDLE) { + dev_err(&rdev->dev, "%s: invalid mode requested %u\n", + __func__, mode); + return -EINVAL; + } + vreg->mode = mode; + + return 0; +} + +static unsigned int regulator_stub_get_optimum_mode(struct regulator_dev *rdev, + int input_uV, int output_uV, int load_uA) +{ + struct regulator_stub *vreg = rdev_get_drvdata(rdev); + unsigned int mode; + + if (load_uA + vreg->system_load_uA >= vreg->hpm_min_load_uA) + mode = REGULATOR_MODE_NORMAL; + else + mode = REGULATOR_MODE_IDLE; + + return mode; +} + +static int regulator_stub_enable(struct regulator_dev *rdev) +{ + struct regulator_stub *vreg = rdev_get_drvdata(rdev); + + vreg->enabled = true; + + return 0; +} + +static int regulator_stub_disable(struct regulator_dev *rdev) +{ + struct regulator_stub *vreg = rdev_get_drvdata(rdev); + + vreg->enabled = false; + + return 0; +} + +static int regulator_stub_is_enabled(struct regulator_dev *rdev) +{ + struct regulator_stub *vreg = rdev_get_drvdata(rdev); + + return vreg->enabled; +} + +static const struct regulator_ops regulator_stub_ops = { + .enable = regulator_stub_enable, + .disable = regulator_stub_disable, + .is_enabled = regulator_stub_is_enabled, + .set_voltage = regulator_stub_set_voltage, + .get_voltage = regulator_stub_get_voltage, + .list_voltage = regulator_stub_list_voltage, + .set_mode = regulator_stub_set_mode, + .get_mode = regulator_stub_get_mode, + .get_optimum_mode = regulator_stub_get_optimum_mode, +}; + +static int regulator_stub_probe(struct platform_device *pdev) +{ + struct regulator_config reg_config = {}; + struct regulator_init_data *init_data; + struct device *dev = &pdev->dev; + struct regulator_stub *vreg; + struct regulator_dev *rdev; + int rc; + + if (!dev->of_node) { + dev_err(dev, "%s: device node missing\n", __func__); + return -ENODEV; + } + + vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL); + if (!vreg) + return -ENOMEM; + + init_data = of_get_regulator_init_data(dev, dev->of_node, &vreg->rdesc); + if (!init_data) + return -ENOMEM; + + if (!init_data->constraints.name) { + dev_err(dev, "%s: regulator name not specified\n", __func__); + return -EINVAL; + } + + of_property_read_u32(dev->of_node, "qcom,system-load", + &vreg->system_load_uA); + of_property_read_u32(dev->of_node, "qcom,hpm-min-load", + &vreg->hpm_min_load_uA); + + vreg->voltage = init_data->constraints.min_uV; + if (vreg->system_load_uA >= vreg->hpm_min_load_uA) + vreg->mode = REGULATOR_MODE_NORMAL; + else + vreg->mode = REGULATOR_MODE_IDLE; + + init_data->constraints.input_uV = init_data->constraints.max_uV; + init_data->constraints.valid_ops_mask |= REGULATOR_CHANGE_MODE | + REGULATOR_CHANGE_DRMS; + init_data->constraints.valid_modes_mask + = REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE; + + /* + * Ensure that voltage set points are handled correctly for regulators + * which have a specified voltage constraint range, as well as those + * that do not. + */ + if (init_data->constraints.min_uV == 0 && + init_data->constraints.max_uV == 0) + vreg->rdesc.n_voltages = 0; + else + vreg->rdesc.n_voltages = 2; + + vreg->rdesc.name = devm_kstrdup(dev, init_data->constraints.name, + GFP_KERNEL); + if (!vreg->rdesc.name) + return -ENOMEM; + + vreg->rdesc.supply_name = "parent"; + vreg->rdesc.ops = ®ulator_stub_ops; + vreg->rdesc.owner = THIS_MODULE; + vreg->rdesc.type = REGULATOR_VOLTAGE; + + reg_config.dev = dev; + reg_config.init_data = init_data; + reg_config.driver_data = vreg; + reg_config.of_node = dev->of_node; + + rdev = devm_regulator_register(dev, &vreg->rdesc, ®_config); + if (IS_ERR(rdev)) { + rc = PTR_ERR(rdev); + if (rc != -EPROBE_DEFER) + dev_err(dev, "%s: regulator_register failed\n", + __func__); + return rc; + } + + return 0; +} + +static const struct of_device_id regulator_stub_match_table[] = { + { .compatible = "qcom,stub-regulator", }, + {} +}; + +static struct platform_driver regulator_stub_driver = { + .driver = { + .name = "stub-regulator", + .of_match_table = of_match_ptr(regulator_stub_match_table), + }, + .probe = regulator_stub_probe, +}; + +int __init regulator_stub_init(void) +{ + return platform_driver_register(®ulator_stub_driver); +} +postcore_initcall(regulator_stub_init); + +static void __exit regulator_stub_exit(void) +{ + platform_driver_unregister(®ulator_stub_driver); +} +module_exit(regulator_stub_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("stub regulator driver"); diff --git a/include/dt-bindings/clock/qcom,camcc-pineapple.h b/include/dt-bindings/clock/qcom,camcc-pineapple.h new file mode 100644 index 000000000000..8eb1ce5a294e --- /dev/null +++ b/include/dt-bindings/clock/qcom,camcc-pineapple.h @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_PINEAPPLE_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_PINEAPPLE_H + +/* CAM_CC clocks */ +#define CAM_CC_BPS_AHB_CLK 0 +#define CAM_CC_BPS_CLK 1 +#define CAM_CC_BPS_CLK_SRC 2 +#define CAM_CC_BPS_FAST_AHB_CLK 3 +#define CAM_CC_BPS_SHIFT_CLK 4 +#define CAM_CC_CAMNOC_AXI_NRT_CLK 5 +#define CAM_CC_CAMNOC_AXI_RT_CLK 6 +#define CAM_CC_CAMNOC_AXI_RT_CLK_SRC 7 +#define CAM_CC_CAMNOC_DCD_XO_CLK 8 +#define CAM_CC_CAMNOC_XO_CLK 9 +#define CAM_CC_CCI_0_CLK 10 +#define CAM_CC_CCI_0_CLK_SRC 11 +#define CAM_CC_CCI_1_CLK 12 +#define CAM_CC_CCI_1_CLK_SRC 13 +#define CAM_CC_CCI_2_CLK 14 +#define CAM_CC_CCI_2_CLK_SRC 15 +#define CAM_CC_CORE_AHB_CLK 16 +#define CAM_CC_CPAS_AHB_CLK 17 +#define CAM_CC_CPAS_BPS_CLK 18 +#define CAM_CC_CPAS_CRE_CLK 19 +#define CAM_CC_CPAS_FAST_AHB_CLK 20 +#define CAM_CC_CPAS_IFE_0_CLK 21 +#define CAM_CC_CPAS_IFE_1_CLK 22 +#define CAM_CC_CPAS_IFE_2_CLK 23 +#define CAM_CC_CPAS_IFE_LITE_CLK 24 +#define CAM_CC_CPAS_IPE_NPS_CLK 25 +#define CAM_CC_CPAS_SBI_CLK 26 +#define CAM_CC_CPAS_SFE_0_CLK 27 +#define CAM_CC_CPAS_SFE_1_CLK 28 +#define CAM_CC_CPAS_SFE_2_CLK 29 +#define CAM_CC_CPHY_RX_CLK_SRC 30 +#define CAM_CC_CRE_AHB_CLK 31 +#define CAM_CC_CRE_CLK 32 +#define CAM_CC_CRE_CLK_SRC 33 +#define CAM_CC_CSI0PHYTIMER_CLK 34 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 35 +#define CAM_CC_CSI1PHYTIMER_CLK 36 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 37 +#define CAM_CC_CSI2PHYTIMER_CLK 38 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 39 +#define CAM_CC_CSI3PHYTIMER_CLK 40 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 41 +#define CAM_CC_CSI4PHYTIMER_CLK 42 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 43 +#define CAM_CC_CSI5PHYTIMER_CLK 44 +#define CAM_CC_CSI5PHYTIMER_CLK_SRC 45 +#define CAM_CC_CSI6PHYTIMER_CLK 46 +#define CAM_CC_CSI6PHYTIMER_CLK_SRC 47 +#define CAM_CC_CSI7PHYTIMER_CLK 48 +#define CAM_CC_CSI7PHYTIMER_CLK_SRC 49 +#define CAM_CC_CSID_CLK 50 +#define CAM_CC_CSID_CLK_SRC 51 +#define CAM_CC_CSID_CSIPHY_RX_CLK 52 +#define CAM_CC_CSIPHY0_CLK 53 +#define CAM_CC_CSIPHY1_CLK 54 +#define CAM_CC_CSIPHY2_CLK 55 +#define CAM_CC_CSIPHY3_CLK 56 +#define CAM_CC_CSIPHY4_CLK 57 +#define CAM_CC_CSIPHY5_CLK 58 +#define CAM_CC_CSIPHY6_CLK 59 +#define CAM_CC_CSIPHY7_CLK 60 +#define CAM_CC_DRV_AHB_CLK 61 +#define CAM_CC_DRV_XO_CLK 62 +#define CAM_CC_FAST_AHB_CLK_SRC 63 +#define CAM_CC_GDSC_CLK 64 +#define CAM_CC_ICP_AHB_CLK 65 +#define CAM_CC_ICP_CLK 66 +#define CAM_CC_ICP_CLK_SRC 67 +#define CAM_CC_IFE_0_CLK 68 +#define CAM_CC_IFE_0_CLK_SRC 69 +#define CAM_CC_IFE_0_FAST_AHB_CLK 70 +#define CAM_CC_IFE_0_SHIFT_CLK 71 +#define CAM_CC_IFE_1_CLK 72 +#define CAM_CC_IFE_1_CLK_SRC 73 +#define CAM_CC_IFE_1_FAST_AHB_CLK 74 +#define CAM_CC_IFE_1_SHIFT_CLK 75 +#define CAM_CC_IFE_2_CLK 76 +#define CAM_CC_IFE_2_CLK_SRC 77 +#define CAM_CC_IFE_2_FAST_AHB_CLK 78 +#define CAM_CC_IFE_2_SHIFT_CLK 79 +#define CAM_CC_IFE_LITE_AHB_CLK 80 +#define CAM_CC_IFE_LITE_CLK 81 +#define CAM_CC_IFE_LITE_CLK_SRC 82 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 83 +#define CAM_CC_IFE_LITE_CSID_CLK 84 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 85 +#define CAM_CC_IPE_NPS_AHB_CLK 86 +#define CAM_CC_IPE_NPS_CLK 87 +#define CAM_CC_IPE_NPS_CLK_SRC 88 +#define CAM_CC_IPE_NPS_FAST_AHB_CLK 89 +#define CAM_CC_IPE_PPS_CLK 90 +#define CAM_CC_IPE_PPS_FAST_AHB_CLK 91 +#define CAM_CC_IPE_SHIFT_CLK 92 +#define CAM_CC_JPEG_1_CLK 93 +#define CAM_CC_JPEG_CLK 94 +#define CAM_CC_JPEG_CLK_SRC 95 +#define CAM_CC_MCLK0_CLK 96 +#define CAM_CC_MCLK0_CLK_SRC 97 +#define CAM_CC_MCLK1_CLK 98 +#define CAM_CC_MCLK1_CLK_SRC 99 +#define CAM_CC_MCLK2_CLK 100 +#define CAM_CC_MCLK2_CLK_SRC 101 +#define CAM_CC_MCLK3_CLK 102 +#define CAM_CC_MCLK3_CLK_SRC 103 +#define CAM_CC_MCLK4_CLK 104 +#define CAM_CC_MCLK4_CLK_SRC 105 +#define CAM_CC_MCLK5_CLK 106 +#define CAM_CC_MCLK5_CLK_SRC 107 +#define CAM_CC_MCLK6_CLK 108 +#define CAM_CC_MCLK6_CLK_SRC 109 +#define CAM_CC_MCLK7_CLK 110 +#define CAM_CC_MCLK7_CLK_SRC 111 +#define CAM_CC_PLL0 112 +#define CAM_CC_PLL0_OUT_EVEN 113 +#define CAM_CC_PLL0_OUT_ODD 114 +#define CAM_CC_PLL1 115 +#define CAM_CC_PLL10 116 +#define CAM_CC_PLL10_OUT_EVEN 117 +#define CAM_CC_PLL1_OUT_EVEN 118 +#define CAM_CC_PLL2 119 +#define CAM_CC_PLL3 120 +#define CAM_CC_PLL3_OUT_EVEN 121 +#define CAM_CC_PLL4 122 +#define CAM_CC_PLL4_OUT_EVEN 123 +#define CAM_CC_PLL5 124 +#define CAM_CC_PLL5_OUT_EVEN 125 +#define CAM_CC_PLL6 126 +#define CAM_CC_PLL6_OUT_EVEN 127 +#define CAM_CC_PLL7 128 +#define CAM_CC_PLL7_OUT_EVEN 129 +#define CAM_CC_PLL8 130 +#define CAM_CC_PLL8_OUT_EVEN 131 +#define CAM_CC_PLL9 132 +#define CAM_CC_PLL9_OUT_EVEN 133 +#define CAM_CC_QDSS_DEBUG_CLK 134 +#define CAM_CC_QDSS_DEBUG_CLK_SRC 135 +#define CAM_CC_QDSS_DEBUG_XO_CLK 136 +#define CAM_CC_SBI_CLK 137 +#define CAM_CC_SBI_FAST_AHB_CLK 138 +#define CAM_CC_SBI_SHIFT_CLK 139 +#define CAM_CC_SFE_0_CLK 140 +#define CAM_CC_SFE_0_CLK_SRC 141 +#define CAM_CC_SFE_0_FAST_AHB_CLK 142 +#define CAM_CC_SFE_0_SHIFT_CLK 143 +#define CAM_CC_SFE_1_CLK 144 +#define CAM_CC_SFE_1_CLK_SRC 145 +#define CAM_CC_SFE_1_FAST_AHB_CLK 146 +#define CAM_CC_SFE_1_SHIFT_CLK 147 +#define CAM_CC_SFE_2_CLK 148 +#define CAM_CC_SFE_2_CLK_SRC 149 +#define CAM_CC_SFE_2_FAST_AHB_CLK 150 +#define CAM_CC_SFE_2_SHIFT_CLK 151 +#define CAM_CC_SLEEP_CLK 152 +#define CAM_CC_SLEEP_CLK_SRC 153 +#define CAM_CC_SLOW_AHB_CLK_SRC 154 +#define CAM_CC_TITAN_TOP_SHIFT_CLK 155 +#define CAM_CC_XO_CLK_SRC 156 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_DRV_BCR 1 +#define CAM_CC_ICP_BCR 2 +#define CAM_CC_IFE_0_BCR 3 +#define CAM_CC_IFE_1_BCR 4 +#define CAM_CC_IFE_2_BCR 5 +#define CAM_CC_IPE_0_BCR 6 +#define CAM_CC_QDSS_DEBUG_BCR 7 +#define CAM_CC_SBI_BCR 8 +#define CAM_CC_SFE_0_BCR 9 +#define CAM_CC_SFE_1_BCR 10 +#define CAM_CC_SFE_2_BCR 11 + +#endif diff --git a/include/dt-bindings/clock/qcom,dispcc-pineapple.h b/include/dt-bindings/clock/qcom,dispcc-pineapple.h new file mode 100644 index 000000000000..73d2486edff6 --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-pineapple.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_PINEAPPLE_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_PINEAPPLE_H + +/* DISP_CC clocks */ +#define DISP_CC_MDSS_ACCU_CLK 0 +#define DISP_CC_MDSS_AHB1_CLK 1 +#define DISP_CC_MDSS_AHB_CLK 2 +#define DISP_CC_MDSS_AHB_CLK_SRC 3 +#define DISP_CC_MDSS_BYTE0_CLK 4 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 5 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 7 +#define DISP_CC_MDSS_BYTE1_CLK 8 +#define DISP_CC_MDSS_BYTE1_CLK_SRC 9 +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10 +#define DISP_CC_MDSS_BYTE1_INTF_CLK 11 +#define DISP_CC_MDSS_DPTX0_AUX_CLK 12 +#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13 +#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 14 +#define DISP_CC_MDSS_DPTX0_LINK_CLK 15 +#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 16 +#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 17 +#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 18 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 19 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 20 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 21 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 22 +#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 23 +#define DISP_CC_MDSS_DPTX1_AUX_CLK 24 +#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 25 +#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 26 +#define DISP_CC_MDSS_DPTX1_LINK_CLK 27 +#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 28 +#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 29 +#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 30 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 31 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 32 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 33 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 34 +#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 35 +#define DISP_CC_MDSS_DPTX2_AUX_CLK 36 +#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 37 +#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 38 +#define DISP_CC_MDSS_DPTX2_LINK_CLK 39 +#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 40 +#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 41 +#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 42 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 43 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 44 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 45 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 46 +#define DISP_CC_MDSS_DPTX3_AUX_CLK 47 +#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 48 +#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 49 +#define DISP_CC_MDSS_DPTX3_LINK_CLK 50 +#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 51 +#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 52 +#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 53 +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 54 +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 55 +#define DISP_CC_MDSS_ESC0_CLK 56 +#define DISP_CC_MDSS_ESC0_CLK_SRC 57 +#define DISP_CC_MDSS_ESC1_CLK 58 +#define DISP_CC_MDSS_ESC1_CLK_SRC 59 +#define DISP_CC_MDSS_MDP1_CLK 60 +#define DISP_CC_MDSS_MDP_CLK 61 +#define DISP_CC_MDSS_MDP_CLK_SRC 62 +#define DISP_CC_MDSS_MDP_LUT1_CLK 63 +#define DISP_CC_MDSS_MDP_LUT_CLK 64 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 65 +#define DISP_CC_MDSS_PCLK0_CLK 66 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 67 +#define DISP_CC_MDSS_PCLK1_CLK 68 +#define DISP_CC_MDSS_PCLK1_CLK_SRC 69 +#define DISP_CC_MDSS_RSCC_AHB_CLK 70 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 71 +#define DISP_CC_MDSS_VSYNC1_CLK 72 +#define DISP_CC_MDSS_VSYNC_CLK 73 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 74 +#define DISP_CC_PLL0 75 +#define DISP_CC_PLL1 76 +#define DISP_CC_SLEEP_CLK 77 +#define DISP_CC_SLEEP_CLK_SRC 78 +#define DISP_CC_XO_CLK 79 +#define DISP_CC_XO_CLK_SRC 80 + +/* DISP_CC resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_CORE_INT2_BCR 1 +#define DISP_CC_MDSS_RSCC_BCR 2 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-pineapple.h b/include/dt-bindings/clock/qcom,gcc-pineapple.h new file mode 100644 index 000000000000..60b803333532 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-pineapple.h @@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_PINEAPPLE_H +#define _DT_BINDINGS_CLK_QCOM_GCC_PINEAPPLE_H + +/* GCC clocks */ +#define GCC_AGGRE_NOC_PCIE_AXI_CLK 0 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 1 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 2 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3 +#define GCC_BOOT_ROM_AHB_CLK 4 +#define GCC_CAMERA_AHB_CLK 5 +#define GCC_CAMERA_HF_AXI_CLK 6 +#define GCC_CAMERA_SF_AXI_CLK 7 +#define GCC_CAMERA_XO_CLK 8 +#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 9 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 10 +#define GCC_CNOC_PCIE_SF_AXI_CLK 11 +#define GCC_CPUSS_UBWCP_CLK 12 +#define GCC_CPUSS_UBWCP_CLK_SRC 13 +#define GCC_DDRSS_GPU_AXI_CLK 14 +#define GCC_DDRSS_PCIE_SF_QTB_CLK 15 +#define GCC_DDRSS_UBWCP_CLK 16 +#define GCC_DISP_AHB_CLK 17 +#define GCC_DISP_HF_AXI_CLK 18 +#define GCC_DISP_XO_CLK 19 +#define GCC_GP1_CLK 20 +#define GCC_GP1_CLK_SRC 21 +#define GCC_GP2_CLK 22 +#define GCC_GP2_CLK_SRC 23 +#define GCC_GP3_CLK 24 +#define GCC_GP3_CLK_SRC 25 +#define GCC_GPLL0 26 +#define GCC_GPLL0_OUT_EVEN 27 +#define GCC_GPLL1 28 +#define GCC_GPLL3 29 +#define GCC_GPLL4 30 +#define GCC_GPLL6 31 +#define GCC_GPLL7 32 +#define GCC_GPLL9 33 +#define GCC_GPU_CFG_AHB_CLK 34 +#define GCC_GPU_GPLL0_CLK_SRC 35 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 36 +#define GCC_GPU_MEMNOC_GFX_CLK 37 +#define GCC_GPU_SNOC_DVM_GFX_CLK 38 +#define GCC_PCIE_0_AUX_CLK 39 +#define GCC_PCIE_0_AUX_CLK_SRC 40 +#define GCC_PCIE_0_CFG_AHB_CLK 41 +#define GCC_PCIE_0_MSTR_AXI_CLK 42 +#define GCC_PCIE_0_PHY_RCHNG_CLK 43 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 44 +#define GCC_PCIE_0_PIPE_CLK 45 +#define GCC_PCIE_0_PIPE_CLK_SRC 46 +#define GCC_PCIE_0_SLV_AXI_CLK 47 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48 +#define GCC_PCIE_1_AUX_CLK 49 +#define GCC_PCIE_1_AUX_CLK_SRC 50 +#define GCC_PCIE_1_CFG_AHB_CLK 51 +#define GCC_PCIE_1_MSTR_AXI_CLK 52 +#define GCC_PCIE_1_PHY_AUX_CLK 53 +#define GCC_PCIE_1_PHY_AUX_CLK_SRC 54 +#define GCC_PCIE_1_PHY_RCHNG_CLK 55 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 56 +#define GCC_PCIE_1_PIPE_CLK 57 +#define GCC_PCIE_1_PIPE_CLK_SRC 58 +#define GCC_PCIE_1_SLV_AXI_CLK 59 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 60 +#define GCC_PDM2_CLK 61 +#define GCC_PDM2_CLK_SRC 62 +#define GCC_PDM_AHB_CLK 63 +#define GCC_PDM_XO4_CLK 64 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 65 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 66 +#define GCC_QMIP_DISP_AHB_CLK 67 +#define GCC_QMIP_GPU_AHB_CLK 68 +#define GCC_QMIP_PCIE_AHB_CLK 69 +#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 70 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 71 +#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 72 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 73 +#define GCC_QUPV3_I2C_CORE_CLK 74 +#define GCC_QUPV3_I2C_S0_CLK 75 +#define GCC_QUPV3_I2C_S0_CLK_SRC 76 +#define GCC_QUPV3_I2C_S1_CLK 77 +#define GCC_QUPV3_I2C_S1_CLK_SRC 78 +#define GCC_QUPV3_I2C_S2_CLK 79 +#define GCC_QUPV3_I2C_S2_CLK_SRC 80 +#define GCC_QUPV3_I2C_S3_CLK 81 +#define GCC_QUPV3_I2C_S3_CLK_SRC 82 +#define GCC_QUPV3_I2C_S4_CLK 83 +#define GCC_QUPV3_I2C_S4_CLK_SRC 84 +#define GCC_QUPV3_I2C_S5_CLK 85 +#define GCC_QUPV3_I2C_S5_CLK_SRC 86 +#define GCC_QUPV3_I2C_S6_CLK 87 +#define GCC_QUPV3_I2C_S6_CLK_SRC 88 +#define GCC_QUPV3_I2C_S7_CLK 89 +#define GCC_QUPV3_I2C_S7_CLK_SRC 90 +#define GCC_QUPV3_I2C_S8_CLK 91 +#define GCC_QUPV3_I2C_S8_CLK_SRC 92 +#define GCC_QUPV3_I2C_S9_CLK 93 +#define GCC_QUPV3_I2C_S9_CLK_SRC 94 +#define GCC_QUPV3_I2C_S_AHB_CLK 95 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 96 +#define GCC_QUPV3_WRAP1_CORE_CLK 97 +#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 98 +#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 99 +#define GCC_QUPV3_WRAP1_S0_CLK 100 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 101 +#define GCC_QUPV3_WRAP1_S1_CLK 102 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 103 +#define GCC_QUPV3_WRAP1_S2_CLK 104 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 105 +#define GCC_QUPV3_WRAP1_S3_CLK 106 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 107 +#define GCC_QUPV3_WRAP1_S4_CLK 108 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 109 +#define GCC_QUPV3_WRAP1_S5_CLK 110 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 111 +#define GCC_QUPV3_WRAP1_S6_CLK 112 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 113 +#define GCC_QUPV3_WRAP1_S7_CLK 114 +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 115 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 116 +#define GCC_QUPV3_WRAP2_CORE_CLK 117 +#define GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC 118 +#define GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK 119 +#define GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK 120 +#define GCC_QUPV3_WRAP2_S0_CLK 121 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 122 +#define GCC_QUPV3_WRAP2_S1_CLK 123 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 124 +#define GCC_QUPV3_WRAP2_S2_CLK 125 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 126 +#define GCC_QUPV3_WRAP2_S3_CLK 127 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 128 +#define GCC_QUPV3_WRAP2_S4_CLK 129 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 130 +#define GCC_QUPV3_WRAP2_S5_CLK 131 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 132 +#define GCC_QUPV3_WRAP2_S6_CLK 133 +#define GCC_QUPV3_WRAP2_S6_CLK_SRC 134 +#define GCC_QUPV3_WRAP2_S7_CLK 135 +#define GCC_QUPV3_WRAP2_S7_CLK_SRC 136 +#define GCC_QUPV3_WRAP3_CORE_2X_CLK 137 +#define GCC_QUPV3_WRAP3_CORE_CLK 138 +#define GCC_QUPV3_WRAP3_QSPI_REF_CLK 139 +#define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC 140 +#define GCC_QUPV3_WRAP3_S0_CLK 141 +#define GCC_QUPV3_WRAP3_S0_CLK_SRC 142 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 143 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 144 +#define GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK 145 +#define GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK 146 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 147 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 148 +#define GCC_QUPV3_WRAP_3_M_AHB_CLK 149 +#define GCC_QUPV3_WRAP_3_S_AHB_CLK 150 +#define GCC_SDCC2_AHB_CLK 151 +#define GCC_SDCC2_APPS_CLK 152 +#define GCC_SDCC2_APPS_CLK_SRC 153 +#define GCC_SDCC4_AHB_CLK 154 +#define GCC_SDCC4_APPS_CLK 155 +#define GCC_SDCC4_APPS_CLK_SRC 156 +#define GCC_UFS_PHY_AHB_CLK 157 +#define GCC_UFS_PHY_AXI_CLK 158 +#define GCC_UFS_PHY_AXI_CLK_SRC 159 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 160 +#define GCC_UFS_PHY_ICE_CORE_CLK 161 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 162 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 163 +#define GCC_UFS_PHY_PHY_AUX_CLK 164 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 165 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 166 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 167 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 168 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 169 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 170 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 171 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 172 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 173 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 174 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 175 +#define GCC_USB30_PRIM_MASTER_CLK 176 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 177 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 178 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 179 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 180 +#define GCC_USB30_PRIM_SLEEP_CLK 181 +#define GCC_USB3_PRIM_PHY_AUX_CLK 182 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 183 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 184 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 185 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 186 +#define GCC_VIDEO_AHB_CLK 187 +#define GCC_VIDEO_AXI0_CLK 188 +#define GCC_VIDEO_AXI1_CLK 189 +#define GCC_VIDEO_XO_CLK 190 + +/* GCC resets */ +#define GCC_CAMERA_BCR 0 +#define GCC_DISPLAY_BCR 1 +#define GCC_GPU_BCR 2 +#define GCC_PCIE_0_BCR 3 +#define GCC_PCIE_0_LINK_DOWN_BCR 4 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5 +#define GCC_PCIE_0_PHY_BCR 6 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7 +#define GCC_PCIE_1_BCR 8 +#define GCC_PCIE_1_LINK_DOWN_BCR 9 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10 +#define GCC_PCIE_1_PHY_BCR 11 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12 +#define GCC_PCIE_PHY_BCR 13 +#define GCC_PCIE_PHY_CFG_AHB_BCR 14 +#define GCC_PCIE_PHY_COM_BCR 15 +#define GCC_PDM_BCR 16 +#define GCC_QUPV3_WRAPPER_1_BCR 17 +#define GCC_QUPV3_WRAPPER_2_BCR 18 +#define GCC_QUPV3_WRAPPER_3_BCR 19 +#define GCC_QUPV3_WRAPPER_I2C_BCR 20 +#define GCC_QUSB2PHY_PRIM_BCR 21 +#define GCC_QUSB2PHY_SEC_BCR 22 +#define GCC_SDCC2_BCR 23 +#define GCC_SDCC4_BCR 24 +#define GCC_UFS_PHY_BCR 25 +#define GCC_USB30_PRIM_BCR 26 +#define GCC_USB3_DP_PHY_PRIM_BCR 27 +#define GCC_USB3_DP_PHY_SEC_BCR 28 +#define GCC_USB3_PHY_PRIM_BCR 29 +#define GCC_USB3_PHY_SEC_BCR 30 +#define GCC_USB3PHY_PHY_PRIM_BCR 31 +#define GCC_USB3PHY_PHY_SEC_BCR 32 +#define GCC_VIDEO_AXI0_CLK_ARES 33 +#define GCC_VIDEO_AXI1_CLK_ARES 34 +#define GCC_VIDEO_BCR 35 + +#endif diff --git a/include/dt-bindings/clock/qcom,gpucc-pineapple.h b/include/dt-bindings/clock/qcom,gpucc-pineapple.h new file mode 100644 index 000000000000..310bf49c3a14 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-pineapple.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_PINEAPPLE_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_PINEAPPLE_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_ACCU_SHIFT_CLK 2 +#define GPU_CC_CX_FF_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_DEMET_CLK 7 +#define GPU_CC_DPM_CLK 8 +#define GPU_CC_FF_CLK_SRC 9 +#define GPU_CC_FREQ_MEASURE_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GX_ACCU_SHIFT_CLK 12 +#define GPU_CC_GX_FF_CLK 13 +#define GPU_CC_GX_GFX3D_CLK 14 +#define GPU_CC_GX_GFX3D_RDVM_CLK 15 +#define GPU_CC_GX_GMU_CLK 16 +#define GPU_CC_GX_VSENSE_CLK 17 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 18 +#define GPU_CC_HUB_AON_CLK 19 +#define GPU_CC_HUB_CLK_SRC 20 +#define GPU_CC_HUB_CX_INT_CLK 21 +#define GPU_CC_HUB_DIV_CLK_SRC 22 +#define GPU_CC_MEMNOC_GFX_CLK 23 +#define GPU_CC_PLL0 24 +#define GPU_CC_PLL1 25 +#define GPU_CC_SLEEP_CLK 26 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CX_BCR 1 +#define GPUCC_GPU_CC_FAST_HUB_BCR 2 +#define GPUCC_GPU_CC_FF_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 + +#endif diff --git a/include/dt-bindings/clock/qcom,tcsrcc-pineapple.h b/include/dt-bindings/clock/qcom,tcsrcc-pineapple.h new file mode 100644 index 000000000000..bc0829f47188 --- /dev/null +++ b/include/dt-bindings/clock/qcom,tcsrcc-pineapple.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_PINEAPPLE_H +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_PINEAPPLE_H + +/* TCSR_CC clocks */ +#define TCSR_PCIE_0_CLKREF_EN 0 +#define TCSR_PCIE_1_CLKREF_EN 1 +#define TCSR_UFS_CLKREF_EN 2 +#define TCSR_UFS_PAD_CLKREF_EN 3 +#define TCSR_USB2_CLKREF_EN 4 +#define TCSR_USB3_CLKREF_EN 5 + +#endif diff --git a/include/dt-bindings/clock/qcom,videocc-pineapple.h b/include/dt-bindings/clock/qcom,videocc-pineapple.h new file mode 100644 index 000000000000..25af039f8150 --- /dev/null +++ b/include/dt-bindings/clock/qcom,videocc-pineapple.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_PINEAPPLE_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_PINEAPPLE_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_AHB_CLK 0 +#define VIDEO_CC_AHB_CLK_SRC 1 +#define VIDEO_CC_MVS0_CLK 2 +#define VIDEO_CC_MVS0_CLK_SRC 3 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 4 +#define VIDEO_CC_MVS0_SHIFT_CLK 5 +#define VIDEO_CC_MVS0C_CLK 6 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 7 +#define VIDEO_CC_MVS0C_SHIFT_CLK 8 +#define VIDEO_CC_MVS1_CLK 9 +#define VIDEO_CC_MVS1_CLK_SRC 10 +#define VIDEO_CC_MVS1_DIV_CLK_SRC 11 +#define VIDEO_CC_MVS1_SHIFT_CLK 12 +#define VIDEO_CC_MVS1C_CLK 13 +#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 14 +#define VIDEO_CC_MVS1C_SHIFT_CLK 15 +#define VIDEO_CC_PLL0 16 +#define VIDEO_CC_PLL1 17 +#define VIDEO_CC_SLEEP_CLK 18 +#define VIDEO_CC_SLEEP_CLK_SRC 19 +#define VIDEO_CC_XO_CLK 20 +#define VIDEO_CC_XO_CLK_SRC 21 + +/* VIDEO_CC resets */ +#define VCODEC_VIDEO_CC_INTERFACE_BCR 0 +#define VCODEC_VIDEO_CC_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_CLK_ARES 2 +#define VCODEC_VIDEO_CC_MVS0C_BCR 3 +#define VCODEC_VIDEO_CC_MVS1_BCR 4 +#define VIDEO_CC_MVS1C_CLK_ARES 5 +#define VCODEC_VIDEO_CC_MVS1C_BCR 6 + +#endif diff --git a/modules.list.msm.pineapple b/modules.list.msm.pineapple index f05ababeb324..549dea25c0c0 100644 --- a/modules.list.msm.pineapple +++ b/modules.list.msm.pineapple @@ -1,3 +1,5 @@ qcom-scm.ko pinctrl-msm.ko pinctrl-pineapple.ko +clk-dummy.ko +stub-regulator.ko