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media: qcom: camss: Fix RDI streaming for CSID GEN3

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Fix streaming from CSIDn RDI1 and RDI2 to VFEn RDI1 and RDI2. A pattern we
have replicated throughout CAMSS where we use the VC number to populate
both the VC fields and port fields of the CSID means that in practice only
VC = 0 on CSIDn:RDI0 to VFEn:RDI0 works.

Fix that for CSID gen3 by separating VC and port. Fix to VC zero as a
bugfix we will look to properly populate the VC field with follow on
patches later.

Fixes: d96fe1808d ("media: qcom: camss: Add CSID 780 support")
Cc: stable@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
This commit is contained in:
Bryan O'Donoghue 2026-04-07 11:34:54 +01:00 committed by Bryan O'Donoghue
parent 618765634c
commit ad136e5263
1 changed files with 14 additions and 14 deletions
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28
drivers/media/platform/qcom/camss/camss-csid-gen3.c
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@ -157,12 +157,12 @@ static void __csid_configure_wrapper(struct csid_device *csid)
writel(val, csid->camss->csid_wrapper_base + CSID_IO_PATH_CFG0(csid->id));
}
static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 vc)
static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 port, u8 vc)
{
u32 val;
u8 lane_cnt = csid->phy.lane_cnt;
/* Source pads matching RDI channels on hardware. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. */
struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc];
struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + port];
const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
csid->res->formats->nformats,
input_format->code);
@ -175,14 +175,14 @@ static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8
* the four least significant bits of the five bit VC
* bitfield to generate an internal CID value.
*
* CSID_RDI_CFG0(vc)
* CSID_RDI_CFG0(port)
* DT_ID : 28:27
* VC : 26:22
* DT : 21:16
*
* CID : VC 3:0 << 2 | DT_ID 1:0
*/
u8 dt_id = vc & 0x03;
u8 dt_id = port & 0x03;
val = RDI_CFG0_TIMESTAMP_EN;
val |= RDI_CFG0_TIMESTAMP_STB_SEL;
@ -192,7 +192,7 @@ static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8
val |= format->data_type << RDI_CFG0_DT;
val |= dt_id << RDI_CFG0_DT_ID;
writel(val, csid->base + CSID_RDI_CFG0(vc));
writel(val, csid->base + CSID_RDI_CFG0(port));
val = RDI_CFG1_PACKING_FORMAT_MIPI;
val |= RDI_CFG1_PIX_STORE;
@ -201,22 +201,22 @@ static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8
val |= RDI_CFG1_CROP_H_EN;
val |= RDI_CFG1_CROP_V_EN;
writel(val, csid->base + CSID_RDI_CFG1(vc));
writel(val, csid->base + CSID_RDI_CFG1(port));
val = 0;
writel(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PERIOD(vc));
writel(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PERIOD(port));
val = 1;
writel(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PATTERN(vc));
writel(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PATTERN(port));
val = 0;
writel(val, csid->base + CSID_RDI_CTRL(vc));
writel(val, csid->base + CSID_RDI_CTRL(port));
val = readl(csid->base + CSID_RDI_CFG0(vc));
val = readl(csid->base + CSID_RDI_CFG0(port));
if (enable)
val |= RDI_CFG0_EN;
writel(val, csid->base + CSID_RDI_CFG0(vc));
writel(val, csid->base + CSID_RDI_CFG0(port));
}
static void csid_configure_stream(struct csid_device *csid, u8 enable)
@ -225,11 +225,11 @@ static void csid_configure_stream(struct csid_device *csid, u8 enable)
__csid_configure_wrapper(csid);
/* Loop through all enabled VCs and configure stream for each */
/* Loop through all enabled ports and configure a stream for each */
for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++)
if (csid->phy.en_vc & BIT(i)) {
__csid_configure_rdi_stream(csid, enable, i);
__csid_configure_rx(csid, &csid->phy, i);
__csid_configure_rdi_stream(csid, enable, i, 0);
__csid_configure_rx(csid, &csid->phy, 0);
__csid_ctrl_rdi(csid, enable, i);
}
}