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riscv: dts: microchip: add a device tree for Discovery Kit
Add a minimal device tree for the Microchip PolarFire SoC Discovery Kit. The Discovery Kit is a cost-optimized board based on PolarFire SoC MPFS095T and features: - 1 GB DDR4x16 - 1x Gigabit Ethernet - 3x UARTs - Raspberry Pi connector - mikroBus connector - microSD card connector Link: https://www.microchip.com/en-us/development-tool/mpfs-disco-kit Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Valentina Fernandez
Conor Dooley
parent
d6d9d9be2a
commit
acc211539c
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@ -1,5 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-beaglev-fire.dtb
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dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-disco-kit.dtb
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dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
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dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit-prod.dtb
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dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb
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58
arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi
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58
arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi
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@ -0,0 +1,58 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2020-2025 Microchip Technology Inc */
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/ {
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core_pwm0: pwm@40000000 {
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compatible = "microchip,corepwm-rtl-v4";
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reg = <0x0 0x40000000 0x0 0xF0>;
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microchip,sync-update-mask = /bits/ 32 <0>;
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#pwm-cells = <3>;
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clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
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status = "disabled";
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};
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i2c2: i2c@40000200 {
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compatible = "microchip,corei2c-rtl-v7";
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reg = <0x0 0x40000200 0x0 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
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interrupt-parent = <&plic>;
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interrupts = <122>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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ihc: mailbox {
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compatible = "microchip,sbi-ipc";
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interrupt-parent = <&plic>;
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interrupts = <180>, <179>, <178>, <177>;
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interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
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#mbox-cells = <1>;
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status = "disabled";
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};
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mailbox@50000000 {
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compatible = "microchip,miv-ihc-rtl-v2";
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reg = <0x0 0x50000000 0x0 0x1c000>;
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interrupt-parent = <&plic>;
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interrupts = <180>, <179>, <178>, <177>;
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interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
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#mbox-cells = <1>;
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microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
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status = "disabled";
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};
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refclk_ccc: clock-cccref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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&ccc_sw {
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clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
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<&refclk_ccc>, <&refclk_ccc>;
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clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
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"dll0_ref", "dll1_ref";
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status = "okay";
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};
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190
arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts
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190
arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2020-2025 Microchip Technology Inc */
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/dts-v1/;
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#include "mpfs.dtsi"
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#include "mpfs-disco-kit-fabric.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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/ {
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model = "Microchip PolarFire-SoC Discovery Kit";
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compatible = "microchip,mpfs-disco-kit-reference-rtl-v2507",
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"microchip,mpfs-disco-kit",
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"microchip,mpfs";
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aliases {
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ethernet0 = &mac0;
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serial4 = &mmuart4;
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};
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chosen {
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stdout-path = "serial4:115200n8";
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};
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leds {
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compatible = "gpio-leds";
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led-1 {
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gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_AMBER>;
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label = "led1";
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};
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led-2 {
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gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_RED>;
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label = "led2";
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};
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led-3 {
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gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_AMBER>;
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label = "led3";
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};
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led-4 {
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gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_RED>;
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label = "led4";
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};
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led-5 {
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gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_AMBER>;
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label = "led5";
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};
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led-6 {
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gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_RED>;
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label = "led6";
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};
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led-7 {
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gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_AMBER>;
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label = "led7";
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};
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led-8 {
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gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_RED>;
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label = "led8";
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};
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};
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ddrc_cache_lo: memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x40000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hss_payload: region@bfc00000 {
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reg = <0x0 0xbfc00000 0x0 0x400000>;
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no-map;
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};
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};
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};
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&core_pwm0 {
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status = "okay";
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};
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&gpio1 {
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interrupts = <27>, <28>, <29>, <30>,
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<31>, <32>, <33>, <47>,
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<35>, <36>, <37>, <38>,
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<39>, <40>, <41>, <42>,
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<43>, <44>, <45>, <46>,
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<47>, <48>, <49>, <50>;
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status = "okay";
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};
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&gpio2 {
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interrupts = <53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>;
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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};
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&i2c2 {
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status = "okay";
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};
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&ihc {
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status = "okay";
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};
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&mac0 {
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phy-mode = "sgmii";
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phy-handle = <&phy0>;
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status = "okay";
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phy0: ethernet-phy@b {
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reg = <0xb>;
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};
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};
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&mbox {
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status = "okay";
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};
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&mmc {
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bus-width = <4>;
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disable-wp;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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no-1-8-v;
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status = "okay";
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};
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&mmuart1 {
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status = "okay";
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};
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&mmuart4 {
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status = "okay";
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};
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&refclk {
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clock-frequency = <125000000>;
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};
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&refclk_ccc {
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clock-frequency = <50000000>;
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};
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&rtc {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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};
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&spi1 {
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status = "okay";
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};
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&syscontroller {
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status = "okay";
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};
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