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x86/thermal: Add bit definitions for Intel Directed Package Thermal Interrupt

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Add CPUID and MSR bit definitions required to support Intel Directed
Package Thermal Interrupt.

A CPU requests directed package-level thermal interrupts by setting bit 25
in IA32_THERM_INTERRUPT. Hardware acknowledges by setting bit 25 in
IA32_PACKAGE_THERM_STATUS, indicating that only CPUs that opted in will
receive the interrupt. If no CPU in the package requests it, delivery
falls back to broadcast.

Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
Link: https://patch.msgid.link/20260613-rneri-directed-therm-intr-v3-2-3a26d1e47fc8@linux.intel.com
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This commit is contained in:
Ricardo Neri 2026-06-13 15:17:48 -07:00 committed by Rafael J. Wysocki
parent 8cdeaa50ea
commit ac5cc691eb
2 changed files with 4 additions and 0 deletions
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2
arch/x86/include/asm/cpufeatures.h
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@ -365,6 +365,8 @@
#define X86_FEATURE_HWP_HIGHEST_PERF_CHANGE (14*32+15) /* HWP Highest perf change */
#define X86_FEATURE_HFI (14*32+19) /* "hfi" Hardware Feedback Interface */
#define X86_FEATURE_DPTI (14*32+24) /* Intel Directed Package Thermal Interrupt */
/* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */
#define X86_FEATURE_NPT (15*32+ 0) /* "npt" Nested Page Table support */
#define X86_FEATURE_LBRV (15*32+ 1) /* "lbrv" LBR Virtualization support */

2
arch/x86/include/asm/msr-index.h
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@ -1007,6 +1007,7 @@
#define THERM_INT_HIGH_ENABLE (1 << 0)
#define THERM_INT_LOW_ENABLE (1 << 1)
#define THERM_INT_PLN_ENABLE (1 << 24)
#define THERM_INT_DPTI_ENABLE (1 << 25)
#define MSR_IA32_THERM_STATUS 0x0000019c
@ -1036,6 +1037,7 @@
#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
#define PACKAGE_THERM_STATUS_DPTI_ACK (1 << 25)
#define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26)
#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2