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video: rockchip: vop: 3399: add support rk3399
Change-Id: Icbccfdd4fb841df67c0ade1cfd141fb574d837f0 Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
This commit is contained in:
Huang Jiachai
Huang, Tao
parent
60c4848c4d
commit
ac5406c5aa
File diff suppressed because it is too large
Load Diff
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@ -169,10 +169,14 @@
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* LINE_FLAG: Line flag config register
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* VOP_STATUS: vop status register
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* BLANKING_VALUE: Register0000 Abstract
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* MCU_BYPASS_PORT: Mcu bypass value
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* WIN0_DSP_BG: Win0 layer background color
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* WIN1_DSP_BG: Win1 layer background color
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* WIN2_DSP_BG: Win2 layer background color
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* WIN3_DSP_BG: Win3 layer background color
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* YUV2YUV_WIN: YUV to YUV win
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* YUV2YUV_POST: Post YUV to YUV
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* AUTO_GATING_EN: Auto gating enable
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* DBG_PERF_LATENCY_CTRL0: Axi performance latency module contrl register0
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* DBG_PERF_RD_MAX_LATENCY_NUM0: Read max latency number
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* DBG_PERF_RD_LATENCY_THR_NUM0: The number of bigger than configed
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@ -201,7 +205,7 @@
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* DBG_PRE_REG0: Vop debug pre register0
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* DBG_PRE_RESERVED: Vop debug pre register1 reserved
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* DBG_POST_REG0: Vop debug post register0
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* DBG_POST_RESERVED: Vop debug post register1 reserved
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* DBG_POST_REG1: Vop debug
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* DBG_DATAO: debug data output path
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* DBG_DATAO_2: debug data output path 2
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* WIN2_LUT_ADDR: Win2 lut base address
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@ -250,10 +254,14 @@ static inline u64 val_mask(int val, u64 msk, int shift)
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#define V_EDP_OUT_EN(x) VAL_MASK(x, 1, 14)
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#define V_MIPI_OUT_EN(x) VAL_MASK(x, 1, 15)
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#define V_OVERLAY_MODE(x) VAL_MASK(x, 1, 16)
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/* rk322x only */
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#define V_FS_SAME_ADDR_MASK_EN(x) VAL_MASK(x, 1, 17)
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#define V_POST_LB_MODE(x) VAL_MASK(x, 1, 18)
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#define V_WIN23_PRI_OPT_MODE(x) VAL_MASK(x, 1, 19)
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/* rk322x only */
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#define V_VOP_MMU_EN(x) VAL_MASK(x, 1, 20)
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/* rk3399 only */
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#define V_VOP_FIELD_TVE_TIMING_POL(x) VAL_MASK(x, 1, 20)
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#define V_VOP_DMA_STOP(x) VAL_MASK(x, 1, 21)
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#define V_VOP_STANDBY_EN(x) VAL_MASK(x, 1, 22)
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#define V_AUTO_GATING_EN(x) VAL_MASK(x, 1, 23)
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@ -280,7 +288,10 @@ static inline u64 val_mask(int val, u64 msk, int shift)
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#define DSP_CTRL0 0x00000010
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#define V_DSP_OUT_MODE(x) VAL_MASK(x, 4, 0)
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#define V_SW_CORE_DCLK_SEL(x) VAL_MASK(x, 1, 4)
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/* rk322x */
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#define V_SW_HDMI_CLK_I_SEL(x) VAL_MASK(x, 1, 5)
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/* rk3399 */
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#define V_P2I_EN(x) VAL_MASK(x, 1, 5)
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#define V_DSP_DCLK_DDR(x) VAL_MASK(x, 1, 8)
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#define V_DSP_DDR_PHASE(x) VAL_MASK(x, 1, 9)
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#define V_DSP_INTERLACE(x) VAL_MASK(x, 1, 10)
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@ -297,6 +308,8 @@ static inline u64 val_mask(int val, u64 msk, int shift)
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#define V_DSP_YUV_CLIP(x) VAL_MASK(x, 1, 21)
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#define V_DSP_X_MIR_EN(x) VAL_MASK(x, 1, 22)
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#define V_DSP_Y_MIR_EN(x) VAL_MASK(x, 1, 23)
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/* rk3399 only */
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#define V_SW_TVE_OUTPUT_SEL(x) VAL_MASK(x, 1, 25)
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#define V_DSP_FIELD(x) VAL_MASK(x, 1, 31)
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#define DSP_CTRL1 0x00000014
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#define V_DSP_LUT_EN(x) VAL_MASK(x, 1, 0)
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@ -374,6 +387,8 @@ static inline u64 val_mask(int val, u64 msk, int shift)
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#define V_WIN0_MID_SWAP(x) VAL_MASK(x, 1, 14)
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#define V_WIN0_UV_SWAP(x) VAL_MASK(x, 1, 15)
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#define V_WIN0_HW_PRE_MUL_EN(x) VAL_MASK(x, 1, 16)
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/* rk3399 only */
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#define V_WIN0_YUYV(x) VAL_MASK(x, 1, 17)
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#define V_WIN0_YRGB_DEFLICK(x) VAL_MASK(x, 1, 18)
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#define V_WIN0_CBR_DEFLICK(x) VAL_MASK(x, 1, 19)
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#define V_WIN0_YUV_CLIP(x) VAL_MASK(x, 1, 20)
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@ -469,6 +484,8 @@ static inline u64 val_mask(int val, u64 msk, int shift)
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#define V_WIN1_MID_SWAP(x) VAL_MASK(x, 1, 14)
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#define V_WIN1_UV_SWAP(x) VAL_MASK(x, 1, 15)
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#define V_WIN1_HW_PRE_MUL_EN(x) VAL_MASK(x, 1, 16)
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/* rk3399 only */
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#define V_WIN1_YUYV(x) VAL_MASK(x, 1, 17)
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#define V_WIN1_YRGB_DEFLICK(x) VAL_MASK(x, 1, 18)
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#define V_WIN1_CBR_DEFLICK(x) VAL_MASK(x, 1, 19)
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#define V_WIN1_YUV_CLIP(x) VAL_MASK(x, 1, 20)
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@ -551,7 +568,7 @@ static inline u64 val_mask(int val, u64 msk, int shift)
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#define WIN2_CTRL0 0x000000b0
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#define V_WIN2_EN(x) VAL_MASK(x, 1, 0)
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#define V_WIN2_INTERLACE_READ(x) VAL_MASK(x, 1, 1)
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#define V_WIN2_CSC_MODE(x) VAL_MASK(x, 1, 2)
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#define V_WIN2_CSC_MODE(x) VAL_MASK(x, 2, 2)
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#define V_WIN2_MST0_EN(x) VAL_MASK(x, 1, 4)
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#define V_WIN2_DATA_FMT0(x) VAL_MASK(x, 2, 5)
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#define V_WIN2_MST1_EN(x) VAL_MASK(x, 1, 8)
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@ -643,7 +660,7 @@ static inline u64 val_mask(int val, u64 msk, int shift)
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#define WIN3_CTRL0 0x00000100
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#define V_WIN3_EN(x) VAL_MASK(x, 1, 0)
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#define V_WIN3_INTERLACE_READ(x) VAL_MASK(x, 1, 1)
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#define V_WIN3_CSC_MODE(x) VAL_MASK(x, 1, 2)
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#define V_WIN3_CSC_MODE(x) VAL_MASK(x, 2, 2)
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#define V_WIN3_MST0_EN(x) VAL_MASK(x, 1, 4)
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#define V_WIN3_DATA_FMT0(x) VAL_MASK(x, 2, 5)
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#define V_WIN3_MST1_EN(x) VAL_MASK(x, 1, 8)
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@ -738,7 +755,7 @@ static inline u64 val_mask(int val, u64 msk, int shift)
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#define V_HWC_MODE(x) VAL_MASK(x, 1, 4)
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#define V_HWC_SIZE(x) VAL_MASK(x, 2, 5)
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#define V_HWC_INTERLACE_READ(x) VAL_MASK(x, 1, 8)
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#define V_HWC_CSC_MODE(x) VAL_MASK(x, 1, 10)
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#define V_HWC_CSC_MODE(x) VAL_MASK(x, 2, 10)
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#define V_HWC_RB_SWAP(x) VAL_MASK(x, 1, 12)
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#define V_HWC_ALPHA_SWAP(x) VAL_MASK(x, 1, 13)
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#define V_HWC_ENDIAN_SWAP(x) VAL_MASK(x, 1, 14)
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@ -859,6 +876,8 @@ static inline u64 val_mask(int val, u64 msk, int shift)
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#define V_CABC_STAGE_DOWN(x) VAL_MASK(x, 8, 0)
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#define V_CABC_STAGE_UP(x) VAL_MASK(x, 9, 8)
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#define V_CABC_STAGE_UP_MODE(x) VAL_MASK(x, 1, 19)
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#define V_MAX_SCALE_CFG_VALUE(x) VAL_MASK(x, 9, 20)
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#define V_MAX_SCALE_CFG_ENABLE(x) VAL_MASK(x, 1, 31)
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#define CABC_CTRL3 0x000001cc
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#define V_CABC_GLOBAL_DN(x) VAL_MASK(x, 8, 0)
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#define V_CABC_GLOBAL_DN_LIMIT_EN(x) VAL_MASK(x, 1, 8)
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@ -992,6 +1011,9 @@ static inline u64 val_mask(int val, u64 msk, int shift)
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#define V_INTR_EN_WIN3_EMPTY(x) VAL_MASK(x, 1, 9)
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#define V_INTR_EN_HWC_EMPTY(x) VAL_MASK(x, 1, 10)
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#define V_INTR_EN_POST_BUF_EMPTY(x) VAL_MASK(x, 1, 11)
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/* rk3399 only */
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#define V_INTR_EN_FS_FIELD(x) VAL_MASK(x, 1, 12)
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/* rk322x only */
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#define V_INTR_EN_PWM_GEN(x) VAL_MASK(x, 1, 12)
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#define V_INTR_EN_DSP_HOLD_VALID(x) VAL_MASK(x, 1, 13)
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#define V_INTR_EN_MMU(x) VAL_MASK(x, 1, 14)
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@ -1010,6 +1032,9 @@ static inline u64 val_mask(int val, u64 msk, int shift)
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#define V_INT_CLR_WIN3_EMPTY(x) VAL_MASK(x, 1, 9)
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#define V_INT_CLR_HWC_EMPTY(x) VAL_MASK(x, 1, 10)
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#define V_INT_CLR_POST_BUF_EMPTY(x) VAL_MASK(x, 1, 11)
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/* rk3399 only */
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#define V_INT_CLR_FS_FIELD(x) VAL_MASK(x, 1, 12)
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/* rk322x only */
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#define V_INT_CLR_PWM_GEN(x) VAL_MASK(x, 1, 12)
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#define V_INT_CLR_DSP_HOLD_VALID(x) VAL_MASK(x, 1, 13)
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#define V_INT_CLR_MMU(x) VAL_MASK(x, 1, 14)
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@ -1028,6 +1053,9 @@ static inline u64 val_mask(int val, u64 msk, int shift)
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#define V_INT_STATUS_WIN3_EMPTY(x) VAL_MASK(x, 1, 9)
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#define V_INT_STATUS_HWC_EMPTY(x) VAL_MASK(x, 1, 10)
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#define V_INT_STATUS_POST_BUF_EMPTY(x) VAL_MASK(x, 1, 11)
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/* rk3399 only */
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#define V_INT_STATUS_FS_FIELD(x) VAL_MASK(x, 1, 12)
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/* rk322x only */
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#define V_INT_STATUS_PWM_GEN(x) VAL_MASK(x, 1, 12)
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#define V_INT_STATUS_DSP_HOLD_VALID(x) VAL_MASK(x, 1, 13)
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#define V_INT_STATUS_MMU(x) VAL_MASK(x, 1, 14)
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@ -1045,6 +1073,9 @@ static inline u64 val_mask(int val, u64 msk, int shift)
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#define V_INT_RAW_STATUS_WIN3_EMPTY(x) VAL_MASK(x, 1, 9)
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#define V_INT_RAW_STATUS_HWC_EMPTY(x) VAL_MASK(x, 1, 10)
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#define V_INT_RAW_STATUS_POST_BUF_EMPTY(x) VAL_MASK(x, 1, 11)
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/* rk3399 only */
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#define V_INT_RAW_STATUS_FS_FIELD(x) VAL_MASK(x, 1, 12)
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/* rk322x only */
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#define V_INT_RAW_STATUS_PWM_GEN(x) VAL_MASK(x, 1, 12)
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#define V_INT_RAW_STATUS_DSP_HOLD_VALID(x) VAL_MASK(x, 1, 13)
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#define V_INT_RAW_STATUS_MMU(x) VAL_MASK(x, 1, 14)
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@ -1080,6 +1111,9 @@ static inline u64 val_mask(int val, u64 msk, int shift)
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#define V_INT_CLR_AFBCD2_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 9)
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#define V_INT_CLR_AFBCD3_HREG_DEC_RESP(x) VAL_MASK(x, 1, 10)
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#define V_INT_CLR_AFBCD3_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 11)
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#define V_INT_CLR_WB_YRGB_FIFO_FULL(x) VAL_MASK(x, 1, 12)
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#define V_INT_CLR_WB_UV_FIFO_FULL(x) VAL_MASK(x, 1, 13)
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#define V_INT_CLR_WB_DMA_FINISH(x) VAL_MASK(x, 1, 14)
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#define V_INT_CLR_VFP(x) VAL_MASK(x, 1, 15)
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#define INTR_STATUS1 0x00000298
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#define V_INT_STATUS_FBCD0(x) VAL_MASK(x, 1, 0)
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@ -1094,6 +1128,9 @@ static inline u64 val_mask(int val, u64 msk, int shift)
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#define V_INT_STATUS_AFBCD2_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 9)
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#define V_INT_STATUS_AFBCD3_HREG_DEC_RESP(x) VAL_MASK(x, 1, 10)
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#define V_INT_STATUS_AFBCD4_HREG_DEC_RESP(x) VAL_MASK(x, 1, 11)
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#define V_INT_STATUS_WB_YRGB_FIFO_FULL(x) VAL_MASK(x, 1, 12)
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#define V_INT_STATUS_WB_UV_FIFO_FULL(x) VAL_MASK(x, 1, 13)
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#define V_INT_STATUS_WB_DMA_FINISH(x) VAL_MASK(x, 1, 14)
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#define V_INT_STATUS_VFP(x) VAL_MASK(x, 1, 15)
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#define INTR_RAW_STATUS1 0x0000029c
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#define V_INT_RAW_STATUS_FBCD0(x) VAL_MASK(x, 1, 0)
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@ -1108,6 +1145,9 @@ static inline u64 val_mask(int val, u64 msk, int shift)
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#define V_INT_RAW_STATUS_AFBCD2_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 9)
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#define V_INT_RAW_STATUS_AFBCD3_HREG_DEC_RESP(x) VAL_MASK(x, 1, 10)
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#define V_INT_RAW_STATUS_AFBCD3_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 11)
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#define V_INT_RAW_STATUS_WB_YRGB_FIFO_FULL(x) VAL_MASK(x, 1, 12)
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#define V_INT_RAW_STATUS_WB_UV_FIFO_FULL(x) VAL_MASK(x, 1, 13)
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#define V_INT_RAW_STATUS_WB_DMA_FINISH(x) VAL_MASK(x, 1, 14)
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#define V_INT_RAW_STATUS_VFP(x) VAL_MASK(x, 1, 15)
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#define LINE_FLAG 0x000002a0
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#define V_DSP_LINE_FLAG_NUM_0(x) VAL_MASK(x, 13, 0)
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@ -1241,6 +1281,18 @@ static inline u64 val_mask(int val, u64 msk, int shift)
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#define POST_YUV2YUV_Y2R_COE 0x00000480
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#define POST_YUV2YUV_3x3_COE 0x000004a0
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#define POST_YUV2YUV_R2Y_COE 0x000004c0
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#define WIN0_YUV2YUV_Y2R 0x000004e0
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#define WIN0_YUV2YUV_3x3 0x00000500
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#define WIN0_YUV2YUV_R2Y 0x00000520
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#define WIN1_YUV2YUV_Y2R 0x00000540
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#define WIN1_YUV2YUV_3x3 0x00000560
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#define WIN1_YUV2YUV_R2Y 0x00000580
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#define WIN2_YUV2YUV_Y2R 0x000005a0
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#define WIN2_YUV2YUV_3x3 0x000005c0
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#define WIN2_YUV2YUV_R2Y 0x000005e0
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#define WIN3_YUV2YUV_Y2R 0x00000600
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#define WIN3_YUV2YUV_3x3 0x00000620
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#define WIN3_YUV2YUV_R2Y 0x00000640
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#define WIN2_LUT_ADDR 0x00001000
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#define V_WIN2_LUT_ADDR(x) VAL_MASK(x, 32, 0)
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#define WIN3_LUT_ADDR 0x00001400
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@ -1265,7 +1317,10 @@ static inline u64 val_mask(int val, u64 msk, int shift)
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#define INTR_WIN3_EMPTY (1 << 9)
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#define INTR_HWC_EMPTY (1 << 10)
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#define INTR_POST_BUF_EMPTY (1 << 11)
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/* rk322x */
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#define INTR_PWM_GEN (1 << 12)
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/* rk3399 */
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#define INTR_FS_FIELD (1 << 12)
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#define INTR_DSP_HOLD_VALID (1 << 13)
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#define INTR_MMU (1 << 14)
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#define INTR_DMA_FINISH (1 << 15)
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@ -1296,17 +1351,47 @@ static inline u64 val_mask(int val, u64 msk, int shift)
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#define OUT_CCIR656_MODE_1 6
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#define OUT_CCIR656_MODE_2 7
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enum cabc_stage_mode {
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LAST_FRAME_PWM_VAL = 0x0,
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CUR_FRAME_PWM_VAL = 0x1,
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STAGE_BY_STAGE = 0x2
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};
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enum {
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VOP_RK322X,
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VOP_RK3399,
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};
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enum {
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VOP_WIN0,
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VOP_WIN1,
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VOP_WIN2,
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VOP_WIN3,
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VOP_HWC,
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VOP_WIN_MAX,
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};
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struct vop_data {
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int chip_type;
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struct rk_lcdc_win *win;
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int n_wins;
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};
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struct vop_device {
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int id;
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const struct vop_data *data;
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struct rk_lcdc_driver driver;
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struct device *dev;
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struct rk_screen *screen;
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struct regmap *grf_base;
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void __iomem *regs;
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void *regsbak;
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u32 reg_phy_base;
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u32 len;
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int __iomem *dsp_lut_addr_base;
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int __iomem *cabc_lut_addr_base;
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/* one time only one process allowed to config the register */
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spinlock_t reg_lock;
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@ -1317,6 +1402,8 @@ struct vop_device {
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bool clk_on;
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/*active layer counter,when atv_layer_cnt = 0,disable lcdc*/
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u8 atv_layer_cnt;
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/* point write back status */
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bool wb_on;
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unsigned int irq;
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@ -1391,7 +1478,7 @@ static inline void vop_clr_bit(struct vop_device *vop_dev, u32 offset, u64 v)
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writel_relaxed(*_pv, vop_dev->regs + offset);
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}
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static inline void vop_msk_reg(struct vop_device *vop_dev, u32 offset, u64 v)
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static inline void vop_msk_reg(struct vop_device *vop_dev, u32 offset, u64 v)
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{
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u32 *_pv = (u32 *)vop_dev->regsbak;
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@ -1401,6 +1488,15 @@ static inline void vop_msk_reg(struct vop_device *vop_dev, u32 offset, u64 v)
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writel_relaxed(*_pv, vop_dev->regs + offset);
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}
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static inline void vop_msk_reg_nobak(struct vop_device *vop_dev,
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u32 offset, u64 v)
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{
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u32 *_pv = (u32 *)vop_dev->regsbak;
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_pv += (offset >> 2);
|
||||
writel_relaxed((*_pv & (~(v >> 32))) | (u32)v, vop_dev->regs + offset);
|
||||
}
|
||||
|
||||
static inline void vop_mask_writel(struct vop_device *vop_dev, u32 offset,
|
||||
u32 mask, u32 v)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user