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Amlogic ARM64 DT for v6.18:

Browse Source 
- Add cache information to the Amlogic SoCs
 - Add RTC node for Amlogic C3 SoC
 - Fix PWM node for Amlogic C3 SoC
 - Remove UHS capability for Odroid-C2 SDCard
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Merge tag 'amlogic-arm64-dt-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt

Amlogic ARM64 DT for v6.18:
- Add cache information to the Amlogic SoCs
- Add RTC node for Amlogic C3 SoC
- Fix PWM node for Amlogic C3 SoC
- Remove UHS capability for Odroid-C2 SDCard

* tag 'amlogic-arm64-dt-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux:
  arm64: dts: amlogic: gxbb-odroidc2: remove UHS capability for SD card
  dts: arm: amlogic: fix pwm node for c3
  arm64: dts: amlogic: sm1-bananapi: lower SD card speed for stability
  arm64: dts: amlogic: Add cache information to the Amlogic T7 SoC
  arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC
  arm64: dts: amlogic: Add cache information to the Amlogic S7 SoC
  arm64: dts: amlogic: Add cache information to the Amlogic C3 SoC
  arm64: dts: amlogic: Add cache information to the Amlogic A4 SoC
  arm64: dts: amlogic: Add cache information to the Amlogic A1 SoC
  arm64: dts: amlogic: Add cache information to the Amlogic GXM SoCS
  arm64: dts: amlogic: Add cache information to the Amlogic AXG SoCS
  arm64: dts: amlogic: Add cache information to the Amlogic G12A SoCS
  arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC
  arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL SoC
  arm64: dts: amlogic: C3: Add RTC controller node

Link: https://lore.kernel.org/r/d40e7e96-4a7c-4e4f-b36f-750c6525b95c@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-09-23 22:28:42 +02:00
commit abfbfb98ac
13 changed files with 385 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
View File

@ -17,6 +17,13 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
@ -24,6 +31,13 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
};
cpu2: cpu@2 {
@ -31,6 +45,13 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
};
cpu3: cpu@3 {
@ -38,6 +59,22 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
};
l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x80000>; /* L2. 512 KB */
cache-line-size = <64>;
cache-sets = <512>;
};
};

41
arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi
View File

@ -23,6 +23,13 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a35";
reg = <0x0 0x0>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
@ -30,6 +37,22 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a35";
reg = <0x0 0x1>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
};
l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x7d000>; /* L2. 512 KB */
cache-line-size = <64>;
cache-sets = <512>;
};
};
@ -53,6 +76,13 @@ xtal: xtal-clk {
#clock-cells = <0>;
};
xtal_32k: xtal-clk-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "xtal_32k";
#clock-cells = <0>;
};
sm: secure-monitor {
compatible = "amlogic,meson-gxbb-sm";
@ -792,7 +822,7 @@ spicc1: spi@52000 {
pwm_mn: pwm@54000 {
compatible = "amlogic,c3-pwm",
"amlogic,meson-s4-pwm";
reg = <0x0 54000 0x0 0x24>;
reg = <0x0 0x54000 0x0 0x24>;
clocks = <&clkc_periphs CLKID_PWM_M>,
<&clkc_periphs CLKID_PWM_N>;
#pwm-cells = <3>;
@ -967,6 +997,15 @@ nand: nand-controller@8d000 {
clock-names = "core", "device";
status = "disabled";
};
rtc@9a000 {
compatible = "amlogic,c3-rtc",
"amlogic,a5-rtc";
reg = <0x0 0x9a000 0x0 0x38>;
interrupts = <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal_32k>, <&clkc_periphs CLKID_SYS_RTC>;
clock-names = "osc", "sys";
};
};
ethmac: ethernet@fdc00000 {

36
arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
View File

@ -18,6 +18,13 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
};
cpu1: cpu@100 {
@ -25,6 +32,13 @@ cpu1: cpu@100 {
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
};
cpu2: cpu@200 {
@ -32,6 +46,13 @@ cpu2: cpu@200 {
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
};
cpu3: cpu@300 {
@ -39,8 +60,23 @@ cpu3: cpu@300 {
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
};
l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x40000>; /* L2. 256 KB */
cache-line-size = <64>;
cache-sets = <512>;
};
};
timer {

74
arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
View File

@ -53,6 +53,13 @@ cpu100: cpu@100 {
compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2_cache_l>;
};
cpu101: cpu@101 {
@ -60,6 +67,13 @@ cpu101: cpu@101 {
compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2_cache_l>;
};
cpu102: cpu@102 {
@ -67,6 +81,13 @@ cpu102: cpu@102 {
compatible = "arm,cortex-a53";
reg = <0x0 0x102>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2_cache_l>;
};
cpu103: cpu@103 {
@ -74,6 +95,13 @@ cpu103: cpu@103 {
compatible = "arm,cortex-a53";
reg = <0x0 0x103>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2_cache_l>;
};
cpu0: cpu@0 {
@ -81,6 +109,13 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a73";
reg = <0x0 0x0>;
enable-method = "psci";
d-cache-line-size = <64>;
d-cache-size = <0x10000>;
d-cache-sets = <64>;
i-cache-line-size = <64>;
i-cache-size = <0x10000>;
i-cache-sets = <64>;
next-level-cache = <&l2_cache_b>;
};
cpu1: cpu@1 {
@ -88,6 +123,13 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a73";
reg = <0x0 0x1>;
enable-method = "psci";
d-cache-line-size = <64>;
d-cache-size = <0x10000>;
d-cache-sets = <64>;
i-cache-line-size = <64>;
i-cache-size = <0x10000>;
i-cache-sets = <64>;
next-level-cache = <&l2_cache_b>;
};
cpu2: cpu@2 {
@ -95,6 +137,13 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a73";
reg = <0x0 0x2>;
enable-method = "psci";
d-cache-line-size = <64>;
d-cache-size = <0x10000>;
d-cache-sets = <64>;
i-cache-line-size = <64>;
i-cache-size = <0x10000>;
i-cache-sets = <64>;
next-level-cache = <&l2_cache_b>;
};
cpu3: cpu@3 {
@ -102,6 +151,31 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a73";
reg = <0x0 0x3>;
enable-method = "psci";
d-cache-line-size = <64>;
d-cache-size = <0x10000>;
d-cache-sets = <64>;
i-cache-line-size = <64>;
i-cache-size = <0x10000>;
i-cache-sets = <64>;
next-level-cache = <&l2_cache_b>;
};
l2_cache_l: l2-cache-cluster0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x40000>; /* L2. 256 KB */
cache-line-size = <64>;
cache-sets = <512>;
};
l2_cache_b: l2-cache-cluster1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x100000>; /* L2. 1 Mb */
cache-line-size = <64>;
cache-sets = <512>;
};
};

15
arch/arm64/boot/dts/amlogic/meson-a1.dtsi
View File

@ -27,6 +27,12 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a35";
reg = <0x0 0x0>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@ -36,6 +42,12 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a35";
reg = <0x0 0x1>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@ -44,6 +56,9 @@ l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x80000>; /* L2. 512 KB */
cache-line-size = <64>;
cache-sets = <512>;
};
};

21
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
View File

@ -83,6 +83,12 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
dynamic-power-coefficient = <140>;
@ -94,6 +100,12 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
dynamic-power-coefficient = <140>;
@ -105,6 +117,12 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
dynamic-power-coefficient = <140>;
@ -115,6 +133,9 @@ l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x80000>; /* L2. 512 KB */
cache-line-size = <64>;
cache-sets = <512>;
};
};

27
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
View File

@ -17,6 +17,12 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@ -26,6 +32,12 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@ -35,6 +47,12 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@ -44,6 +62,12 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@ -52,6 +76,9 @@ l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x80000>; /* L2. 512 KB */
cache-line-size = <64>;
cache-sets = <512>;
};
};

62
arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
View File

@ -49,7 +49,13 @@ cpu0: cpu@0 {
reg = <0x0 0x0>;
enable-method = "psci";
capacity-dmips-mhz = <592>;
next-level-cache = <&l2>;
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2_cache_l>;
#cooling-cells = <2>;
};
@ -59,7 +65,13 @@ cpu1: cpu@1 {
reg = <0x0 0x1>;
enable-method = "psci";
capacity-dmips-mhz = <592>;
next-level-cache = <&l2>;
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2_cache_l>;
#cooling-cells = <2>;
};
@ -69,7 +81,13 @@ cpu100: cpu@100 {
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>;
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2_cache_l>;
#cooling-cells = <2>;
};
@ -79,7 +97,13 @@ cpu101: cpu@101 {
reg = <0x0 0x101>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>;
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2_cache_l>;
#cooling-cells = <2>;
};
@ -89,7 +113,13 @@ cpu102: cpu@102 {
reg = <0x0 0x102>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>;
d-cache-line-size = <64>;
d-cache-size = <0x10000>;
d-cache-sets = <64>;
i-cache-line-size = <64>;
i-cache-size = <0x10000>;
i-cache-sets = <64>;
next-level-cache = <&l2_cache_b>;
#cooling-cells = <2>;
};
@ -99,14 +129,32 @@ cpu103: cpu@103 {
reg = <0x0 0x103>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>;
d-cache-line-size = <64>;
d-cache-size = <0x10000>;
d-cache-sets = <64>;
i-cache-line-size = <64>;
i-cache-size = <0x10000>;
i-cache-sets = <64>;
next-level-cache = <&l2_cache_b>;
#cooling-cells = <2>;
};
l2: l2-cache0 {
l2_cache_l: l2-cache-cluster0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x40000>; /* L2. 256 KB */
cache-line-size = <64>;
cache-sets = <512>;
};
l2_cache_b: l2-cache-cluster1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x100000>; /* L2. 1MB */
cache-line-size = <64>;
cache-sets = <512>;
};
};
};

27
arch/arm64/boot/dts/amlogic/meson-gx.dtsi
View File

@ -95,6 +95,12 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
#cooling-cells = <2>;
@ -105,6 +111,12 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
#cooling-cells = <2>;
@ -115,6 +127,12 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
#cooling-cells = <2>;
@ -125,6 +143,12 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
#cooling-cells = <2>;
@ -134,6 +158,9 @@ l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x80000>; /* L2. 512 KB */
cache-line-size = <64>;
cache-sets = <512>;
};
};

4
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
View File

@ -348,10 +348,6 @@ &sd_emmc_b {
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-ddr50;
max-frequency = <100000000>;
disable-wp;

24
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
View File

@ -64,6 +64,12 @@ cpu4: cpu@100 {
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
@ -75,6 +81,12 @@ cpu5: cpu@101 {
reg = <0x0 0x101>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
@ -86,6 +98,12 @@ cpu6: cpu@102 {
reg = <0x0 0x102>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
@ -97,6 +115,12 @@ cpu7: cpu@103 {
reg = <0x0 0x103>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;

5
arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
View File

@ -380,11 +380,10 @@ &sd_emmc_b {
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <50000000>;
/* Boot failures are observed at 50MHz */
max-frequency = <35000000>;
disable-wp;
/* TOFIX: SD card is barely usable in SDR modes */
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
vmmc-supply = <&tflash_vdd>;
vqmmc-supply = <&vddio_c>;

27
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
View File

@ -55,6 +55,12 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@ -64,6 +70,12 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a55";
reg = <0x0 0x1>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@ -73,6 +85,12 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a55";
reg = <0x0 0x2>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@ -82,6 +100,12 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a55";
reg = <0x0 0x3>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@ -90,6 +114,9 @@ l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x40000>; /* L2. 256 KB */
cache-line-size = <64>;
cache-sets = <256>;
};
};