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net/mlx5: Manage ICM type of SW encap

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Support allocate/deallocate the new SW encap ICM type memory.
The new ICM type is used for encap context allocation managed by SW,
instead FW. It can increase encap context maximum number and allocation
speed

Signed-off-by: Shun Hao <shunh@nvidia.com>
Link: https://lore.kernel.org/r/bed5121255918eb132a1334141c76a0594df8143.1701871118.git.leon@kernel.org
Signed-off-by: Leon Romanovsky <leon@kernel.org>
This commit is contained in:
Shun Hao 2023-12-06 16:01:36 +02:00 committed by Leon Romanovsky
parent a429ec96c0
commit abf8e8f29a
1 changed files with 37 additions and 1 deletions
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38
drivers/net/ethernet/mellanox/mlx5/core/lib/dm.c
View File

@ -13,11 +13,13 @@ struct mlx5_dm {
unsigned long *steering_sw_icm_alloc_blocks;
unsigned long *header_modify_sw_icm_alloc_blocks;
unsigned long *header_modify_pattern_sw_icm_alloc_blocks;
unsigned long *header_encap_sw_icm_alloc_blocks;
};
struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev)
{
u64 header_modify_pattern_icm_blocks = 0;
u64 header_sw_encap_icm_blocks = 0;
u64 header_modify_icm_blocks = 0;
u64 steering_icm_blocks = 0;
struct mlx5_dm *dm;
@ -54,6 +56,17 @@ struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev)
goto err_modify_hdr;
}
if (MLX5_CAP_DEV_MEM(dev, log_indirect_encap_sw_icm_size)) {
header_sw_encap_icm_blocks =
BIT(MLX5_CAP_DEV_MEM(dev, log_indirect_encap_sw_icm_size) -
MLX5_LOG_SW_ICM_BLOCK_SIZE(dev));
dm->header_encap_sw_icm_alloc_blocks =
bitmap_zalloc(header_sw_encap_icm_blocks, GFP_KERNEL);
if (!dm->header_encap_sw_icm_alloc_blocks)
goto err_pattern;
}
support_v2 = MLX5_CAP_FLOWTABLE_NIC_RX(dev, sw_owner_v2) &&
MLX5_CAP_FLOWTABLE_NIC_TX(dev, sw_owner_v2) &&
MLX5_CAP64_DEV_MEM(dev, header_modify_pattern_sw_icm_start_address);
@ -66,11 +79,14 @@ struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev)
dm->header_modify_pattern_sw_icm_alloc_blocks =
bitmap_zalloc(header_modify_pattern_icm_blocks, GFP_KERNEL);
if (!dm->header_modify_pattern_sw_icm_alloc_blocks)
goto err_pattern;
goto err_sw_encap;
}
return dm;
err_sw_encap:
bitmap_free(dm->header_encap_sw_icm_alloc_blocks);
err_pattern:
bitmap_free(dm->header_modify_sw_icm_alloc_blocks);
@ -105,6 +121,14 @@ void mlx5_dm_cleanup(struct mlx5_core_dev *dev)
bitmap_free(dm->header_modify_sw_icm_alloc_blocks);
}
if (dm->header_encap_sw_icm_alloc_blocks) {
WARN_ON(!bitmap_empty(dm->header_encap_sw_icm_alloc_blocks,
BIT(MLX5_CAP_DEV_MEM(dev,
log_indirect_encap_sw_icm_size) -
MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))));
bitmap_free(dm->header_encap_sw_icm_alloc_blocks);
}
if (dm->header_modify_pattern_sw_icm_alloc_blocks) {
WARN_ON(!bitmap_empty(dm->header_modify_pattern_sw_icm_alloc_blocks,
BIT(MLX5_CAP_DEV_MEM(dev,
@ -164,6 +188,13 @@ int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
log_header_modify_pattern_sw_icm_size);
block_map = dm->header_modify_pattern_sw_icm_alloc_blocks;
break;
case MLX5_SW_ICM_TYPE_SW_ENCAP:
icm_start_addr = MLX5_CAP64_DEV_MEM(dev,
indirect_encap_sw_icm_start_address);
log_icm_size = MLX5_CAP_DEV_MEM(dev,
log_indirect_encap_sw_icm_size);
block_map = dm->header_encap_sw_icm_alloc_blocks;
break;
default:
return -EINVAL;
}
@ -242,6 +273,11 @@ int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type
header_modify_pattern_sw_icm_start_address);
block_map = dm->header_modify_pattern_sw_icm_alloc_blocks;
break;
case MLX5_SW_ICM_TYPE_SW_ENCAP:
icm_start_addr = MLX5_CAP64_DEV_MEM(dev,
indirect_encap_sw_icm_start_address);
block_map = dm->header_encap_sw_icm_alloc_blocks;
break;
default:
return -EINVAL;
}