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media: iris: implement the boot sequence of the firmware

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Set the memory region on the firmware and implement the boot sequence.

Tested-by: Stefan Schmidt <stefan.schmidt@linaro.org> # x1e80100 (Dell XPS 13 9345)
Reviewed-by: Stefan Schmidt <stefan.schmidt@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
This commit is contained in:
Dikshita Agarwal 2025-02-07 13:24:46 +05:30 committed by Hans Verkuil
parent d19b163356
commit abf5bac63f
6 changed files with 114 additions and 0 deletions
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1
drivers/media/platform/qcom/iris/Makefile
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@ -6,5 +6,6 @@ iris-objs += iris_core.o \
iris_platform_sm8550.o \
iris_probe.o \
iris_vidc.o \
iris_vpu_common.o \
obj-$(CONFIG_VIDEO_QCOM_IRIS) += iris.o

7
drivers/media/platform/qcom/iris/iris_core.c
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@ -6,6 +6,7 @@
#include "iris_core.h"
#include "iris_firmware.h"
#include "iris_state.h"
#include "iris_vpu_common.h"
void iris_core_deinit(struct iris_core *core)
{
@ -39,10 +40,16 @@ int iris_core_init(struct iris_core *core)
if (ret)
goto error_queue_deinit;
ret = iris_vpu_boot_firmware(core);
if (ret)
goto error_unload_fw;
mutex_unlock(&core->lock);
return 0;
error_unload_fw:
iris_fw_unload(core);
error_queue_deinit:
iris_hfi_queues_deinit(core);
error:

1
drivers/media/platform/qcom/iris/iris_platform_common.h
View File

@ -44,6 +44,7 @@ struct iris_platform_data {
const char *fwname;
u32 pas_id;
struct tz_cp_config *tz_cp_config_data;
u32 core_arch;
};
#endif

3
drivers/media/platform/qcom/iris/iris_platform_sm8550.c
View File

@ -7,6 +7,8 @@
#include "iris_hfi_gen2.h"
#include "iris_platform_common.h"
#define VIDEO_ARCH_LX 1
static const struct icc_info sm8550_icc_table[] = {
{ "cpu-cfg", 1000, 1000 },
{ "video-mem", 1000, 15000000 },
@ -48,4 +50,5 @@ struct iris_platform_data sm8550_data = {
.fwname = "qcom/vpu/vpu30_p4.mbn",
.pas_id = IRIS_PAS_ID,
.tz_cp_config_data = &tz_cp_config_sm8550,
.core_arch = VIDEO_ARCH_LX,
};

89
drivers/media/platform/qcom/iris/iris_vpu_common.c Normal file
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@ -0,0 +1,89 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/iopoll.h>
#include "iris_core.h"
#include "iris_vpu_common.h"
#define CPU_BASE_OFFS 0x000A0000
#define CPU_CS_BASE_OFFS (CPU_BASE_OFFS)
#define CTRL_INIT (CPU_CS_BASE_OFFS + 0x48)
#define CTRL_STATUS (CPU_CS_BASE_OFFS + 0x4C)
#define CTRL_ERROR_STATUS__M 0xfe
#define QTBL_INFO (CPU_CS_BASE_OFFS + 0x50)
#define QTBL_ENABLE BIT(0)
#define QTBL_ADDR (CPU_CS_BASE_OFFS + 0x54)
#define CPU_CS_SCIACMDARG3 (CPU_CS_BASE_OFFS + 0x58)
#define SFR_ADDR (CPU_CS_BASE_OFFS + 0x5C)
#define UC_REGION_ADDR (CPU_CS_BASE_OFFS + 0x64)
#define UC_REGION_SIZE (CPU_CS_BASE_OFFS + 0x68)
#define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148)
#define HOST2XTENSA_INTR_ENABLE BIT(0)
#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
static void iris_vpu_setup_ucregion_memory_map(struct iris_core *core)
{
u32 queue_size, value;
/* Iris hardware requires 4K queue alignment */
queue_size = ALIGN(sizeof(struct iris_hfi_queue_table_header) +
(IFACEQ_QUEUE_SIZE * IFACEQ_NUMQ), SZ_4K);
value = (u32)core->iface_q_table_daddr;
writel(value, core->reg_base + UC_REGION_ADDR);
/* Iris hardware requires 1M queue alignment */
value = ALIGN(SFR_SIZE + queue_size, SZ_1M);
writel(value, core->reg_base + UC_REGION_SIZE);
value = (u32)core->iface_q_table_daddr;
writel(value, core->reg_base + QTBL_ADDR);
writel(QTBL_ENABLE, core->reg_base + QTBL_INFO);
if (core->sfr_daddr) {
value = (u32)core->sfr_daddr + core->iris_platform_data->core_arch;
writel(value, core->reg_base + SFR_ADDR);
}
}
int iris_vpu_boot_firmware(struct iris_core *core)
{
u32 ctrl_init = BIT(0), ctrl_status = 0, count = 0, max_tries = 1000;
iris_vpu_setup_ucregion_memory_map(core);
writel(ctrl_init, core->reg_base + CTRL_INIT);
writel(0x1, core->reg_base + CPU_CS_SCIACMDARG3);
while (!ctrl_status && count < max_tries) {
ctrl_status = readl(core->reg_base + CTRL_STATUS);
if ((ctrl_status & CTRL_ERROR_STATUS__M) == 0x4) {
dev_err(core->dev, "invalid setting for uc_region\n");
break;
}
usleep_range(50, 100);
count++;
}
if (count >= max_tries) {
dev_err(core->dev, "error booting up iris firmware\n");
return -ETIME;
}
writel(HOST2XTENSA_INTR_ENABLE, core->reg_base + CPU_CS_H2XSOFTINTEN);
writel(0x0, core->reg_base + CPU_CS_X2RPMH);
return 0;
}

13
drivers/media/platform/qcom/iris/iris_vpu_common.h Normal file
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@ -0,0 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __IRIS_VPU_COMMON_H__
#define __IRIS_VPU_COMMON_H__
struct iris_core;
int iris_vpu_boot_firmware(struct iris_core *core);
#endif