From 96d5a545374eac8fbd29b23bcd0d624c37e0ab9d Mon Sep 17 00:00:00 2001 From: Franklin S Cooper Jr Date: Tue, 3 May 2016 10:56:48 -0500 Subject: [PATCH 01/42] ARM: dts: am437x: Add missing compatibles to PWM binding documents There are several SOC specific compatibles for ECAP, EHRPWM and PWMMS that are in use but aren't properly documented. Therefore, fix this by adding the compatibles to the appropriate binding documents. While at it make minor corrections to the binding document. Signed-off-by: Franklin S Cooper Jr Acked-by: Rob Herring Signed-off-by: Tony Lindgren --- .../devicetree/bindings/pwm/pwm-tiecap.txt | 12 +++++++++-- .../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 12 +++++++++-- .../devicetree/bindings/pwm/pwm-tipwmss.txt | 21 +++++++++++++++++-- 3 files changed, 39 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt index fb81179dce37..788da6cf7074 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt @@ -2,8 +2,9 @@ TI SOC ECAP based APWM controller Required properties: - compatible: Must be "ti,-ecap". - for am33xx - compatible = "ti,am33xx-ecap"; - for da850 - compatible = "ti,da850-ecap", "ti,am33xx-ecap"; + for am33xx - compatible = "ti,am33xx-ecap"; + for am4372 - compatible = "ti,am4372-ecap", "ti,am33xx-ecap"; + for da850 - compatible = "ti,da850-ecap", "ti,am33xx-ecap"; - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The PWM channel index ranges from 0 to 4. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. @@ -22,6 +23,13 @@ ecap0: ecap@0 { /* ECAP on am33xx */ ti,hwmods = "ecap0"; }; +ecap0: ecap@0 { /* ECAP on am4372 */ + compatible = "ti,am4372-ecap", "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48300100 0x80>; + ti,hwmods = "ecap0"; +}; + ecap0: ecap@0 { /* ECAP on da850 */ compatible = "ti,da850-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt index 9c100b2c5b23..99b544f75f96 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt @@ -2,8 +2,9 @@ TI SOC EHRPWM based PWM controller Required properties: - compatible: Must be "ti,-ehrpwm". - for am33xx - compatible = "ti,am33xx-ehrpwm"; - for da850 - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; + for am33xx - compatible = "ti,am33xx-ehrpwm"; + for am4372 - compatible = "ti,am4372-ehrpwm", "ti,am33xx-ehrpwm"; + for da850 - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. @@ -22,6 +23,13 @@ ehrpwm0: ehrpwm@0 { /* EHRPWM on am33xx */ ti,hwmods = "ehrpwm0"; }; +ehrpwm0: ehrpwm@0 { /* EHRPWM on am4372 */ + compatible = "ti,am4372-ehrpwm", "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48300200 0x80>; + ti,hwmods = "ehrpwm0"; +}; + ehrpwm0: ehrpwm@0 { /* EHRPWM on da850 */ compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; diff --git a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt index f7eae77f8354..fd8e87c16a44 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt @@ -1,7 +1,10 @@ TI SOC based PWM Subsystem Required properties: -- compatible: Must be "ti,am33xx-pwmss"; +- compatible: Must be "ti,-pwmss". + for am33xx - compatible = "ti,am33xx-pwmss"; + for am4372 - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + - reg: physical base address and size of the registers map. - address-cells: Specify the number of u32 entries needed in child nodes. Should set to 1. @@ -16,7 +19,7 @@ Required properties: Also child nodes should also populated under PWMSS DT node. Example: -pwmss0: pwmss@48300000 { +epwmss0: epwmss@48300000 { /* PWMSS for am33xx */ compatible = "ti,am33xx-pwmss"; reg = <0x48300000 0x10>; ti,hwmods = "epwmss0"; @@ -29,3 +32,17 @@ pwmss0: pwmss@48300000 { /* child nodes go here */ }; + +epwmss0: epwmss@48300000 { /* PWMSS for am4372 */ + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss" + reg = <0x48300000 0x10>; + ti,hwmods = "epwmss0"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0x48300100 0x48300100 0x80 /* ECAP */ + 0x48300180 0x48300180 0x80 /* EQEP */ + 0x48300200 0x48300200 0x80>; /* EHRPWM */ + + /* child nodes go here */ +}; From 956abfe38cf51f8710bc1289333c0135129cf5fd Mon Sep 17 00:00:00 2001 From: Franklin S Cooper Jr Date: Tue, 3 May 2016 10:56:49 -0500 Subject: [PATCH 02/42] pwm: pwm-tiehrpwm: Update dt binding document to use generic node name Now that the node name has been changed from ehrpwm to pwm the document should show this proper usage. Change the unit address in the example from 0 to the proper physical address value that should be used. Also insure that the unit address matches to the reg property. Signed-off-by: Franklin S Cooper Jr Acked-by: Rob Herring Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt index 99b544f75f96..f3bc09e92d4c 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt @@ -16,22 +16,22 @@ Optional properties: Example: -ehrpwm0: ehrpwm@0 { /* EHRPWM on am33xx */ +ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */ compatible = "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x100>; ti,hwmods = "ehrpwm0"; }; -ehrpwm0: ehrpwm@0 { /* EHRPWM on am4372 */ +ehrpwm0: pwm@48300200 { /* EHRPWM on am4372 */ compatible = "ti,am4372-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x80>; ti,hwmods = "ehrpwm0"; }; -ehrpwm0: ehrpwm@0 { /* EHRPWM on da850 */ +ehrpwm0: pwm@1f00000 { /* EHRPWM on da850 */ compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; - reg = <0x300000 0x2000>; + reg = <0x1f00000 0x2000>; }; From 7d68a7f8fed9925437eacf067654ee8e753f8c49 Mon Sep 17 00:00:00 2001 From: Franklin S Cooper Jr Date: Tue, 3 May 2016 10:56:50 -0500 Subject: [PATCH 03/42] pwm: pwm-tiecap: Update dt binding document to use proper unit address Replace unit address from 0 to the proper physical address. Also insure that the unit address matches the reg property address. Signed-off-by: Franklin S Cooper Jr Acked-by: Rob Herring Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/pwm/pwm-tiecap.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt index 788da6cf7074..0d47354b72f4 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt @@ -16,22 +16,22 @@ Optional properties: Example: -ecap0: ecap@0 { /* ECAP on am33xx */ +ecap0: ecap@48300100 { /* ECAP on am33xx */ compatible = "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; ti,hwmods = "ecap0"; }; -ecap0: ecap@0 { /* ECAP on am4372 */ +ecap0: ecap@48300100 { /* ECAP on am4372 */ compatible = "ti,am4372-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; ti,hwmods = "ecap0"; }; -ecap0: ecap@0 { /* ECAP on da850 */ +ecap0: ecap@1f06000 { /* ECAP on da850 */ compatible = "ti,da850-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; - reg = <0x306000 0x80>; + reg = <0x1f06000 0x80>; }; From 229110c1aa69134a1ca1e3118cae08fac9d843ad Mon Sep 17 00:00:00 2001 From: Franklin S Cooper Jr Date: Tue, 3 May 2016 10:56:51 -0500 Subject: [PATCH 04/42] ARM: dts: am437x/am33xx/da850: Add new ECAP and EPWM bindings Switch to a new ECAP and EPWM bindings that doesn't depend on hwmod to provide the various required clocks. For AM437 and AM335x, add the required clocks explicitly to DT. The hwmod entries for ECAP and EPWM will be removed and this will prevent anything from breaking. Signed-off-by: Franklin S Cooper Jr Acked-by: Rob Herring Signed-off-by: Tony Lindgren --- .../devicetree/bindings/pwm/pwm-tiecap.txt | 18 ++++--- .../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 18 ++++--- arch/arm/boot/dts/am33xx.dtsi | 30 ++++++++--- arch/arm/boot/dts/am4372.dtsi | 54 +++++++++++++++---- 4 files changed, 93 insertions(+), 27 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt index 0d47354b72f4..ee0a8bd34701 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt @@ -2,9 +2,9 @@ TI SOC ECAP based APWM controller Required properties: - compatible: Must be "ti,-ecap". - for am33xx - compatible = "ti,am33xx-ecap"; - for am4372 - compatible = "ti,am4372-ecap", "ti,am33xx-ecap"; - for da850 - compatible = "ti,da850-ecap", "ti,am33xx-ecap"; + for am33xx - compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; + for am4372 - compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; + for da850 - compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The PWM channel index ranges from 0 to 4. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. @@ -13,25 +13,31 @@ Required properties: Optional properties: - ti,hwmods: Name of the hwmod associated to the ECAP: "ecap", being the 0-based instance number from the HW spec +- clocks: Handle to the ECAP's functional clock. +- clock-names: Must be set to "fck". Example: ecap0: ecap@48300100 { /* ECAP on am33xx */ - compatible = "ti,am33xx-ecap"; + compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; ti,hwmods = "ecap0"; + clocks = <&l4ls_gclk>; + clock-names = "fck"; }; ecap0: ecap@48300100 { /* ECAP on am4372 */ - compatible = "ti,am4372-ecap", "ti,am33xx-ecap"; + compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; ti,hwmods = "ecap0"; + clocks = <&l4ls_gclk>; + clock-names = "fck"; }; ecap0: ecap@1f06000 { /* ECAP on da850 */ - compatible = "ti,da850-ecap", "ti,am33xx-ecap"; + compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x1f06000 0x80>; }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt index f3bc09e92d4c..e9a156b56bd5 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt @@ -2,9 +2,9 @@ TI SOC EHRPWM based PWM controller Required properties: - compatible: Must be "ti,-ehrpwm". - for am33xx - compatible = "ti,am33xx-ehrpwm"; - for am4372 - compatible = "ti,am4372-ehrpwm", "ti,am33xx-ehrpwm"; - for da850 - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; + for am33xx - compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; + for am4372 - compatible = "ti,am4372-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm"; + for da850 - compatible = "ti,da850-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm"; - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. @@ -13,25 +13,31 @@ Required properties: Optional properties: - ti,hwmods: Name of the hwmod associated to the EHRPWM: "ehrpwm", being the 0-based instance number from the HW spec +- clocks: Handle to the PWM's time-base and functional clock. +- clock-names: Must be set to "tbclk" and "fck". Example: ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */ - compatible = "ti,am33xx-ehrpwm"; + compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x100>; + clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; ti,hwmods = "ehrpwm0"; }; ehrpwm0: pwm@48300200 { /* EHRPWM on am4372 */ - compatible = "ti,am4372-ehrpwm", "ti,am33xx-ehrpwm"; + compatible = "ti,am4372-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x80>; + clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; ti,hwmods = "ehrpwm0"; }; ehrpwm0: pwm@1f00000 { /* EHRPWM on da850 */ - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; + compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x1f00000 0x2000>; }; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 52be48bbd2dd..999ba2f1a8b7 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -679,9 +679,12 @@ epwmss0: epwmss@48300000 { 0x48300200 0x48300200 0x80>; /* EHRPWM */ ecap0: ecap@48300100 { - compatible = "ti,am33xx-ecap"; + compatible = "ti,am3352-ecap", + "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; interrupts = <31>; interrupt-names = "ecap0"; ti,hwmods = "ecap0"; @@ -689,10 +692,13 @@ ecap0: ecap@48300100 { }; ehrpwm0: pwm@48300200 { - compatible = "ti,am33xx-ehrpwm"; + compatible = "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x80>; ti,hwmods = "ehrpwm0"; + clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; status = "disabled"; }; }; @@ -709,9 +715,12 @@ epwmss1: epwmss@48302000 { 0x48302200 0x48302200 0x80>; /* EHRPWM */ ecap1: ecap@48302100 { - compatible = "ti,am33xx-ecap"; + compatible = "ti,am3352-ecap", + "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48302100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; interrupts = <47>; interrupt-names = "ecap1"; ti,hwmods = "ecap1"; @@ -719,10 +728,13 @@ ecap1: ecap@48302100 { }; ehrpwm1: pwm@48302200 { - compatible = "ti,am33xx-ehrpwm"; + compatible = "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48302200 0x80>; ti,hwmods = "ehrpwm1"; + clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; status = "disabled"; }; }; @@ -739,9 +751,12 @@ epwmss2: epwmss@48304000 { 0x48304200 0x48304200 0x80>; /* EHRPWM */ ecap2: ecap@48304100 { - compatible = "ti,am33xx-ecap"; + compatible = "ti,am3352-ecap", + "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48304100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; interrupts = <61>; interrupt-names = "ecap2"; ti,hwmods = "ecap2"; @@ -749,10 +764,13 @@ ecap2: ecap@48304100 { }; ehrpwm2: pwm@48304200 { - compatible = "ti,am33xx-ehrpwm"; + compatible = "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48304200 0x80>; ti,hwmods = "ehrpwm2"; + clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 12fcde4d4d2e..e8584606d56f 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -672,18 +672,26 @@ epwmss0: epwmss@48300000 { status = "disabled"; ecap0: ecap@48300100 { - compatible = "ti,am4372-ecap","ti,am33xx-ecap"; + compatible = "ti,am4372-ecap", + "ti,am3352-ecap", + "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; ti,hwmods = "ecap0"; + clocks = <&l4ls_gclk>; + clock-names = "fck"; status = "disabled"; }; ehrpwm0: pwm@48300200 { - compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x80>; ti,hwmods = "ehrpwm0"; + clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; status = "disabled"; }; }; @@ -698,18 +706,26 @@ epwmss1: epwmss@48302000 { status = "disabled"; ecap1: ecap@48302100 { - compatible = "ti,am4372-ecap","ti,am33xx-ecap"; + compatible = "ti,am4372-ecap", + "ti,am3352-ecap", + "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48302100 0x80>; ti,hwmods = "ecap1"; + clocks = <&l4ls_gclk>; + clock-names = "fck"; status = "disabled"; }; ehrpwm1: pwm@48302200 { - compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48302200 0x80>; ti,hwmods = "ehrpwm1"; + clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; status = "disabled"; }; }; @@ -724,18 +740,26 @@ epwmss2: epwmss@48304000 { status = "disabled"; ecap2: ecap@48304100 { - compatible = "ti,am4372-ecap","ti,am33xx-ecap"; + compatible = "ti,am4372-ecap", + "ti,am3352-ecap", + "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48304100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; ti,hwmods = "ecap2"; status = "disabled"; }; ehrpwm2: pwm@48304200 { - compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48304200 0x80>; ti,hwmods = "ehrpwm2"; + clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; status = "disabled"; }; }; @@ -750,10 +774,14 @@ epwmss3: epwmss@48306000 { status = "disabled"; ehrpwm3: pwm@48306200 { - compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48306200 0x80>; ti,hwmods = "ehrpwm3"; + clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; status = "disabled"; }; }; @@ -768,10 +796,14 @@ epwmss4: epwmss@48308000 { status = "disabled"; ehrpwm4: pwm@48308200 { - compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48308200 0x80>; ti,hwmods = "ehrpwm4"; + clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; status = "disabled"; }; }; @@ -786,9 +818,13 @@ epwmss5: epwmss@4830a000 { status = "disabled"; ehrpwm5: pwm@4830a200 { - compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x4830a200 0x80>; + clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; ti,hwmods = "ehrpwm5"; status = "disabled"; }; From 58bfbea5b1c6826953d54ee470ab560aba55afce Mon Sep 17 00:00:00 2001 From: Franklin S Cooper Jr Date: Tue, 3 May 2016 10:56:53 -0500 Subject: [PATCH 05/42] ARM: dts: am437x/am33xx: Remove hwmod entries for ECAP and EPWM nodes Previous patches switched the ECAP and EPWM to use the new bindings. These bindings explicitly adds the various required clocks via DT rather than depending on hwmod. Therefore, it is safe to remove the hwmod entries since they are no longer needed. Signed-off-by: Franklin S Cooper Jr Acked-by: Rob Herring Acked-by: Paul Walmsley Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/pwm/pwm-tiecap.txt | 3 --- Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt | 3 --- arch/arm/boot/dts/am33xx.dtsi | 6 ------ arch/arm/boot/dts/am4372.dtsi | 9 --------- 4 files changed, 21 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt index ee0a8bd34701..f2a9a7cbea34 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt @@ -11,8 +11,6 @@ Required properties: - reg: physical base address and size of the registers map. Optional properties: -- ti,hwmods: Name of the hwmod associated to the ECAP: - "ecap", being the 0-based instance number from the HW spec - clocks: Handle to the ECAP's functional clock. - clock-names: Must be set to "fck". @@ -22,7 +20,6 @@ ecap0: ecap@48300100 { /* ECAP on am33xx */ compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; - ti,hwmods = "ecap0"; clocks = <&l4ls_gclk>; clock-names = "fck"; }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt index e9a156b56bd5..41a2bd4b9fe3 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt @@ -11,8 +11,6 @@ Required properties: - reg: physical base address and size of the registers map. Optional properties: -- ti,hwmods: Name of the hwmod associated to the EHRPWM: - "ehrpwm", being the 0-based instance number from the HW spec - clocks: Handle to the PWM's time-base and functional clock. - clock-names: Must be set to "tbclk" and "fck". @@ -24,7 +22,6 @@ ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */ reg = <0x48300200 0x100>; clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; - ti,hwmods = "ehrpwm0"; }; ehrpwm0: pwm@48300200 { /* EHRPWM on am4372 */ diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 999ba2f1a8b7..2661accdcd92 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -687,7 +687,6 @@ ecap0: ecap@48300100 { clock-names = "fck"; interrupts = <31>; interrupt-names = "ecap0"; - ti,hwmods = "ecap0"; status = "disabled"; }; @@ -696,7 +695,6 @@ ehrpwm0: pwm@48300200 { "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x80>; - ti,hwmods = "ehrpwm0"; clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; @@ -723,7 +721,6 @@ ecap1: ecap@48302100 { clock-names = "fck"; interrupts = <47>; interrupt-names = "ecap1"; - ti,hwmods = "ecap1"; status = "disabled"; }; @@ -732,7 +729,6 @@ ehrpwm1: pwm@48302200 { "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48302200 0x80>; - ti,hwmods = "ehrpwm1"; clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; @@ -759,7 +755,6 @@ ecap2: ecap@48304100 { clock-names = "fck"; interrupts = <61>; interrupt-names = "ecap2"; - ti,hwmods = "ecap2"; status = "disabled"; }; @@ -768,7 +763,6 @@ ehrpwm2: pwm@48304200 { "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48304200 0x80>; - ti,hwmods = "ehrpwm2"; clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index e8584606d56f..cfdd4b77f714 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -677,7 +677,6 @@ ecap0: ecap@48300100 { "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; - ti,hwmods = "ecap0"; clocks = <&l4ls_gclk>; clock-names = "fck"; status = "disabled"; @@ -689,7 +688,6 @@ ehrpwm0: pwm@48300200 { "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x80>; - ti,hwmods = "ehrpwm0"; clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; @@ -711,7 +709,6 @@ ecap1: ecap@48302100 { "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48302100 0x80>; - ti,hwmods = "ecap1"; clocks = <&l4ls_gclk>; clock-names = "fck"; status = "disabled"; @@ -723,7 +720,6 @@ ehrpwm1: pwm@48302200 { "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48302200 0x80>; - ti,hwmods = "ehrpwm1"; clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; @@ -747,7 +743,6 @@ ecap2: ecap@48304100 { reg = <0x48304100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; - ti,hwmods = "ecap2"; status = "disabled"; }; @@ -757,7 +752,6 @@ ehrpwm2: pwm@48304200 { "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48304200 0x80>; - ti,hwmods = "ehrpwm2"; clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; @@ -779,7 +773,6 @@ ehrpwm3: pwm@48306200 { "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48306200 0x80>; - ti,hwmods = "ehrpwm3"; clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; @@ -801,7 +794,6 @@ ehrpwm4: pwm@48308200 { "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48308200 0x80>; - ti,hwmods = "ehrpwm4"; clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; @@ -825,7 +817,6 @@ ehrpwm5: pwm@4830a200 { reg = <0x4830a200 0x80>; clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; - ti,hwmods = "ehrpwm5"; status = "disabled"; }; }; From 34370142331953146efd1be573696785957a2fa9 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Tue, 3 May 2016 10:56:55 -0500 Subject: [PATCH 06/42] ARM: dts: DRA7: Add dt nodes for PWMSS Add PWMSS device tree nodes for DRA7 SoC family and add documentation for dt bindings. Signed-off-by: Vignesh R [fcooper@ti.com: Add eCAP and use updated bindings for PWMSS and ePWM] Signed-off-by: Franklin S Cooper Jr Acked-by: Rob Herring Signed-off-by: Tony Lindgren --- .../devicetree/bindings/pwm/pwm-tiecap.txt | 9 ++ .../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 9 ++ .../devicetree/bindings/pwm/pwm-tipwmss.txt | 12 +++ arch/arm/boot/dts/dra7.dtsi | 90 +++++++++++++++++++ 4 files changed, 120 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt index f2a9a7cbea34..8007e839a716 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt @@ -5,6 +5,7 @@ Required properties: for am33xx - compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; for am4372 - compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; for da850 - compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; + for dra746 - compatible = "ti,dra746-ecap", "ti,am3352-ecap"; - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The PWM channel index ranges from 0 to 4. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. @@ -38,3 +39,11 @@ ecap0: ecap@1f06000 { /* ECAP on da850 */ #pwm-cells = <3>; reg = <0x1f06000 0x80>; }; + +ecap0: ecap@4843e100 { + compatible = "ti,dra746-ecap", "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x4843e100 0x80>; + clocks = <&l4_root_clk_div>; + clock-names = "fck"; +}; diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt index 41a2bd4b9fe3..944fe356bb45 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt @@ -5,6 +5,7 @@ Required properties: for am33xx - compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; for am4372 - compatible = "ti,am4372-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm"; for da850 - compatible = "ti,da850-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm"; + for dra746 - compatible = "ti,dra746-ehrpwm", "ti-am3352-ehrpwm"; - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. @@ -38,3 +39,11 @@ ehrpwm0: pwm@1f00000 { /* EHRPWM on da850 */ #pwm-cells = <3>; reg = <0x1f00000 0x2000>; }; + +ehrpwm0: pwm@4843e200 { /* EHRPWM on dra746 */ + compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x4843e200 0x80>; + clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; + clock-names = "tbclk", "fck"; +}; diff --git a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt index fd8e87c16a44..1a5d7b71db89 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt @@ -4,6 +4,7 @@ Required properties: - compatible: Must be "ti,-pwmss". for am33xx - compatible = "ti,am33xx-pwmss"; for am4372 - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + for dra746 - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss" - reg: physical base address and size of the registers map. - address-cells: Specify the number of u32 entries needed in child nodes. @@ -46,3 +47,14 @@ epwmss0: epwmss@48300000 { /* PWMSS for am4372 */ /* child nodes go here */ }; + +epwmss0: epwmss@4843e000 { /* PWMSS for DRA7xx */ + compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; + reg = <0x4843e000 0x30>; + ti,hwmods = "epwmss0"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* child nodes go here */ +}; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index e0074014385a..5a21e46ce487 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1743,6 +1743,96 @@ hdmi: encoder@58060000 { clock-names = "fck", "sys_clk"; }; }; + + epwmss0: epwmss@4843e000 { + compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; + reg = <0x4843e000 0x30>; + ti,hwmods = "epwmss0"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges; + + ehrpwm0: pwm@4843e200 { + compatible = "ti,dra746-ehrpwm", + "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x4843e200 0x80>; + clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + ecap0: ecap@4843e100 { + compatible = "ti,dra746-ecap", + "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x4843e100 0x80>; + clocks = <&l4_root_clk_div>; + clock-names = "fck"; + status = "disabled"; + }; + }; + + epwmss1: epwmss@48440000 { + compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; + reg = <0x48440000 0x30>; + ti,hwmods = "epwmss1"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges; + + ehrpwm1: pwm@48440200 { + compatible = "ti,dra746-ehrpwm", + "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48440200 0x80>; + clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + ecap1: ecap@48440100 { + compatible = "ti,dra746-ecap", + "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x48440100 0x80>; + clocks = <&l4_root_clk_div>; + clock-names = "fck"; + status = "disabled"; + }; + }; + + epwmss2: epwmss@48442000 { + compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; + reg = <0x48442000 0x30>; + ti,hwmods = "epwmss2"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges; + + ehrpwm2: pwm@48442200 { + compatible = "ti,dra746-ehrpwm", + "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48442200 0x80>; + clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + ecap2: ecap@48442100 { + compatible = "ti,dra746-ecap", + "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x48442100 0x80>; + clocks = <&l4_root_clk_div>; + clock-names = "fck"; + status = "disabled"; + }; + }; }; thermal_zones: thermal-zones { From a5fa09b6943f3304c2a7b2670c896c485fba8cf4 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Tue, 10 May 2016 14:49:41 -0500 Subject: [PATCH 07/42] ARM: dts: dra7: Add ocmcram nodes Add all ocmcram nodes to dra7.dtsi using the generic mmio-sram driver. DRA7xx and AM57xx families of SoCs can contain three ocmcram regions of SRAM, one of 512kb and also an optional two additional of 1Mb each. Mark the two additional 1MB regions of SRAM as disabled as only ocmcmram1 is on all variants of the SoCs, then depending on which specific variant is in use the ocmcram2 and ocmcram3 nodes can be enabled in the board dts file if the data manual for that part number indicates the ocmcram region is available. Signed-off-by: Dave Gerlach Reviewed-by: Andreas Dannenberg Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 5a21e46ce487..4847ef9780cc 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -304,6 +304,38 @@ pcie2_intc: interrupt-controller { }; }; + ocmcram1: ocmcram@40300000 { + compatible = "mmio-sram"; + reg = <0x40300000 0x80000>; + ranges = <0x0 0x40300000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + /* + * NOTE: ocmcram2 and ocmcram3 are not available on all + * DRA7xx and AM57xx variants. Confirm availability in + * the data manual for the exact part number in use + * before enabling these nodes in the board dts file. + */ + ocmcram2: ocmcram@40400000 { + status = "disabled"; + compatible = "mmio-sram"; + reg = <0x40400000 0x100000>; + ranges = <0x0 0x40400000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + ocmcram3: ocmcram@40500000 { + status = "disabled"; + compatible = "mmio-sram"; + reg = <0x40500000 0x100000>; + ranges = <0x0 0x40500000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + }; + bandgap: bandgap@4a0021e0 { reg = <0x4a0021e0 0xc 0x4a00232c 0xc From fae3a9f023b7903be3d84ae81014b061508480f9 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Tue, 10 May 2016 14:49:42 -0500 Subject: [PATCH 08/42] ARM: dts: dra7: Add ti,secure-ram node to ocmcram1 node Secure variants of DRA7xx and AM57xx SoCs may need to reserve a region of the SRAM for use by secure software. To account for this, add a child node to the ocmcram1 node that will act as a placeholder at the start of the SRAM for the reserved region of memory that may be required by secure services. The node is added with size 0 so that by default parts will have the full space available but the bootloader or board dts file is able to resize the node as needed depending on how much reserved space is needed, if any, so end users of the ocmcram1 region on HS parts must be aware that a smaller amount of SRAM than expected may be available. Signed-off-by: Dave Gerlach Reviewed-by: Andreas Dannenberg Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 4847ef9780cc..d8c0dd1024f0 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -310,6 +310,21 @@ ocmcram1: ocmcram@40300000 { ranges = <0x0 0x40300000 0x80000>; #address-cells = <1>; #size-cells = <1>; + /* + * This is a placeholder for an optional reserved + * region for use by secure software. The size + * of this region is not known until runtime so it + * is set as zero to either be updated to reserve + * space or left unchanged to leave all SRAM for use. + * On HS parts that that require the reserved region + * either the bootloader can update the size to + * the required amount or the node can be overridden + * from the board dts file for the secure platform. + */ + sram-hs@0 { + compatible = "ti,secure-ram"; + reg = <0x0 0x0>; + }; }; /* From e7c8682143db9771bad62626793201eb809cfaf2 Mon Sep 17 00:00:00 2001 From: Ivaylo Dimitrov Date: Mon, 16 May 2016 22:34:14 +0300 Subject: [PATCH 09/42] ARM: dts: n900: enable lirc-rx51 driver Add the needed DT data to enable IR TX driver Signed-off-by: Ivaylo Dimitrov Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-n900.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index d9e2d9c6e999..0ceff5d285b2 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -143,6 +143,18 @@ battery: n900-battery { io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>; io-channel-names = "temp", "bsi", "vbat"; }; + + pwm9: dmtimer-pwm@9 { + compatible = "ti,omap-dmtimer-pwm"; + #pwm-cells = <3>; + ti,timers = <&timer9>; + ti,clock-source = <0x00>; /* timer_sys_ck */ + }; + + ir: n900-ir { + compatible = "nokia,n900-ir"; + pwms = <&pwm9 0 26316 0>; /* 38000 Hz */ + }; }; &omap3_pmx_core { From 28a1b403b28e34e4a4e6ff29925e66d358499622 Mon Sep 17 00:00:00 2001 From: Marek Belisko Date: Tue, 17 May 2016 21:48:47 +0200 Subject: [PATCH 10/42] ARM: dts: omap3-gta04: Add backlight support Define pwm backlight node which is using dmtimer pwm. Signed-off-by: Marek Belisko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-gta04.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index ab9fb8f49ff3..cef8b23a6b19 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -100,6 +100,22 @@ lcd_in: endpoint { }; }; + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm11 0 2000000 0>; + pwm-names = "backlight"; + brightness-levels = <0 11 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <9>; /* => 90 */ + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + }; + + pwm11: dmtimer-pwm@11 { + compatible = "ti,omap-dmtimer-pwm"; + ti,timers = <&timer11>; + #pwm-cells = <3>; + }; + hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; @@ -190,6 +206,12 @@ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_d >; }; + backlight_pins: backlight_pins_pimnux { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20ba, MUX_MODE3) /* gpt11/gpio57 */ + >; + }; + dss_dpi_pins: pinmux_dss_dpi_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ From ee327111953b841280af501c65c976f253884587 Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Tue, 17 May 2016 21:48:48 +0200 Subject: [PATCH 11/42] ARM: dts: omap3-gta04: Define and use bma180 irq pin Add pinmux and usage of bma180 irq pin. Signed-off-by: H. Nikolaus Schaller Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-gta04.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index cef8b23a6b19..e0520cf0f45c 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -250,6 +250,12 @@ hdq_pins: hdq_pins { OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.hdq */ >; }; + + bma180_pins: pinmux_bma180_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x213a, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio115 */ + >; + }; }; &omap3_pmx_core2 { @@ -320,6 +326,8 @@ bmp085@77 { bma180@41 { compatible = "bosch,bma180"; reg = <0x41>; + pinctrl-names = "default"; + pintcrl-0 = <&bma180_pins>; interrupt-parent = <&gpio4>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_115 */ }; From f6cbf6106ad0fb7f25b39714b30c0e083dbc5612 Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Tue, 17 May 2016 21:48:49 +0200 Subject: [PATCH 12/42] ARM: dta: omap3-gta04: Define and use itg3200 irq pin Define pinmux and usage if irq pin + fix irq edge. Signed-off-by: H. Nikolaus Schaller Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-gta04.dtsi | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index e0520cf0f45c..094e5e14fb3d 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -256,6 +256,12 @@ bma180_pins: pinmux_bma180_pins { OMAP3_CORE1_IOPAD(0x213a, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio115 */ >; }; + + itg3200_pins: pinmux_itg3200_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio56 */ + >; + }; }; &omap3_pmx_core2 { @@ -336,8 +342,10 @@ bma180@41 { itg3200@68 { compatible = "invensense,itg3200"; reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&itg3200_pins>; interrupt-parent = <&gpio2>; - interrupts = <24 0>; /* GPIO_56 */ + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* GPIO_56 */ }; /* leds */ From e14927e265f0d2f50617c87259d5e08f30477d20 Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Tue, 17 May 2016 21:48:50 +0200 Subject: [PATCH 13/42] ARM: dta: omap3-gta04: Define and use hmc5843 irq pin Define pinmux and usage if irq pin. Signed-off-by: H. Nikolaus Schaller Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-gta04.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 094e5e14fb3d..55b6b884dd3b 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -262,6 +262,12 @@ itg3200_pins: pinmux_itg3200_pins { OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio56 */ >; }; + + hmc5843_pins: pinmux_hmc5843_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2134, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio112 */ + >; + }; }; &omap3_pmx_core2 { @@ -389,6 +395,10 @@ wifi_reset: wifi_reset@6 { hmc5843@1e { compatible = "honeywell,hmc5883l"; reg = <0x1e>; + pinctrl-names = "default"; + pinctrl-0 = <&hmc5843_pins>; + interrupt-parent = <&gpio4>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; /* gpio112 */ }; /* touchscreen */ From c2df98c000523789b799cf25798d3c5d6363fa0e Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Tue, 17 May 2016 21:48:51 +0200 Subject: [PATCH 14/42] ARM: dts: omap3-gat04: Fix wifi handling Without that change wifi card isn't probed because pwrseq is necessary for libertas chip. Signed-off-by: H. Nikolaus Schaller Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-gta04.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 55b6b884dd3b..634925770998 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -155,6 +155,11 @@ opa_out: endpoint@0 { }; }; }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&tca6507 0 GPIO_ACTIVE_LOW>; /* W2CBW003 reset through tca6507 */ + }; }; &omap3_pmx_core { @@ -354,8 +359,8 @@ itg3200@68 { interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* GPIO_56 */ }; - /* leds */ - tca6507@45 { + /* leds + gpios */ + tca6507: tca6507@45 { compatible = "ti,tca6507"; #address-cells = <1>; #size-cells = <0>; @@ -446,6 +451,7 @@ &mmc2 { bus-width = <4>; ti,non-removable; cap-power-off-card; + mmc-pwrseq = <&wifi_pwrseq>; }; &mmc3 { From fb515b8e384d8b1a46c664c1ff6c57fdf4dcbd6c Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 18 May 2016 18:36:26 -0500 Subject: [PATCH 15/42] ARM: dts: am335x: Update MPU regulator range for TI boards Now that we are moving to OPPv2 bindings and able to add 1GHz OPP for MPU, let's update the max MPU voltage range to align with the maximum possible value allowed in the operating-points table, which is max target voltage of 132500 uV + 2%. Signed-off-by: Dave Gerlach Acked-by: Viresh Kumar Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-bone-common.dtsi | 2 +- arch/arm/boot/dts/am335x-evm.dts | 2 +- arch/arm/boot/dts/am335x-evmsk.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 0cc150b87b86..13133f3587b8 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -318,7 +318,7 @@ dcdc2_reg: regulator@1 { /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1325000>; + regulator-max-microvolt = <1351500>; regulator-boot-on; regulator-always-on; }; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 516673bb023d..5d28712ad253 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -640,7 +640,7 @@ vdd1_reg: regulator@2 { /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1312500>; + regulator-max-microvolt = <1351500>; regulator-boot-on; regulator-always-on; }; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 282fe1b37095..09308d66645b 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -560,7 +560,7 @@ vdd1_reg: regulator@2 { /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1312500>; + regulator-max-microvolt = <1351500>; regulator-boot-on; regulator-always-on; }; From 4317be1162108bcdf50dc53dfb48eac94dcff25c Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 18 May 2016 18:36:27 -0500 Subject: [PATCH 16/42] ARM: dts: am33xx: Move to operating-points-v2 table and ti-cpufreq driver Drop the operating-points table present in am33xx.dtsi and add an operating-points-v2 table with all OPPs available for all silicon revisions along with necessary data for use by ti-cpufreq to selectively enable the appropriate OPPs at runtime. Also, drop the voltage-tolerance value and provide voltages for each OPP using the format instead. Information from AM335x Data Manual, SPRS717i, Revised December 2015, Table 5-7. Signed-off-by: Dave Gerlach Acked-by: Viresh Kumar Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx.dtsi | 88 +++++++++++++++++++++++++++++------ 1 file changed, 75 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 2661accdcd92..2625414b805a 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -45,19 +45,9 @@ cpu@0 { device_type = "cpu"; reg = <0>; - /* - * To consider voltage drop between PMIC and SoC, - * tolerance value is reduced to 2% from 4% and - * voltage value is increased as a precaution. - */ - operating-points = < - /* kHz uV */ - 720000 1285000 - 600000 1225000 - 500000 1125000 - 275000 1125000 - >; - voltage-tolerance = <2>; /* 2 percentage */ + operating-points-v2 = <&cpu0_opp_table>; + ti,syscon-efuse = <&scm_conf 0x7fc 0x1fff 0>; + ti,syscon-rev = <&scm_conf 0x600>; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; @@ -66,6 +56,78 @@ cpu@0 { }; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + /* + * The three following nodes are marked with opp-suspend + * because the can not be enabled simultaneously on a + * single SoC. + */ + opp50@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <950000 931000 969000>; + opp-supported-hw = <0x06 0x0010>; + opp-suspend; + }; + + opp100@275000000 { + opp-hz = /bits/ 64 <275000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x01 0x00FF>; + opp-suspend; + }; + + opp100@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x06 0x0020>; + opp-suspend; + }; + + opp100@500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + opp100@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x06 0x0040>; + }; + + opp120@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + opp120@720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0x06 0x0080>; + }; + + oppturbo@720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + oppturbo@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0x06 0x0100>; + }; + + oppnitro@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1325000 1298500 1351500>; + opp-supported-hw = <0x04 0x0200>; + }; + }; + pmu { compatible = "arm,cortex-a8-pmu"; interrupts = <3>; From c36e6ec904876de1935b1d74d2d711e6f5ceb572 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 18 May 2016 18:36:28 -0500 Subject: [PATCH 17/42] ARM: dts: am335x-boneblack: Enable 1GHz OPP for cpu Although all PG2.0 silicon may not support 1GHz OPP for the MPU, older Beaglebone Blacks may have PG2.0 silicon populated and these particular parts are guaranteed to support the OPP, so enable it for PG2.0 on am335x-boneblack only. Signed-off-by: Dave Gerlach Acked-by: Viresh Kumar Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-boneblack.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts index 55c0e954b146..ca721670bd91 100644 --- a/arch/arm/boot/dts/am335x-boneblack.dts +++ b/arch/arm/boot/dts/am335x-boneblack.dts @@ -33,6 +33,17 @@ &mmc2 { status = "okay"; }; +&cpu0_opp_table { + /* + * All PG 2.0 silicon may not support 1GHz but some of the early + * BeagleBone Blacks have PG 2.0 silicon which is guaranteed + * to support 1GHz OPP so enable it for PG 2.0 on this board. + */ + oppnitro@1000000000 { + opp-supported-hw = <0x06 0x0100>; + }; +}; + &am33xx_pinmux { nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { pinctrl-single,pins = < From 6da9c792b309bd34f5870943a16ee849975f4e10 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 18 May 2016 18:36:29 -0500 Subject: [PATCH 18/42] ARM: dts: am4372: Add operating-points-v2 table Add an operating-points-v2 table with all OPPs available for all silicon revisions along with necessary data for use by ti-cpufreq to selectively enable the appropriate OPPs at runtime. Information from AM437x Data Manual, SPRS851B, Revised April 2015, Table 5-2. Signed-off-by: Dave Gerlach Acked-by: Viresh Kumar Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 39 +++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index cfdd4b77f714..5a065b8eb4b6 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -44,10 +44,49 @@ cpu: cpu@0 { clocks = <&dpll_mpu_ck>; clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + ti,syscon-efuse = <&scm_conf 0x610 0x3f 0>; + ti,syscon-rev = <&scm_conf 0x600>; + clock-latency = <300000>; /* From omap-cpufreq driver */ }; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp50@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <950000 931000 969000>; + opp-supported-hw = <0xFF 0x01>; + opp-suspend; + }; + + opp100@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0xFF 0x04>; + }; + + opp120@720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0xFF 0x08>; + }; + + oppturbo@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0xFF 0x10>; + }; + + oppnitro@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1325000 1298500 1351500>; + opp-supported-hw = <0xFF 0x20>; + }; + }; + gic: interrupt-controller@48241000 { compatible = "arm,cortex-a9-gic"; interrupt-controller; From 2af84bdd12502f8d61682d7b230cc67aa8ba1499 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 18 May 2016 18:36:30 -0500 Subject: [PATCH 19/42] ARM: dts: am437x-gp-evm: Hook dcdc2 as the cpu0-supply Hook dcdc2 as the cpu0-supply. Signed-off-by: Dave Gerlach Acked-by: Viresh Kumar Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 5bcd3aa025bc..84832bf26b39 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -975,3 +975,7 @@ &rtc { clock-names = "ext-clk", "int-clk"; status = "okay"; }; + +&cpu { + cpu0-supply = <&dcdc2>; +}; From 62e4feed0b0b9bc73d0aa843a6a6d259cb5197e4 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 18 May 2016 18:36:31 -0500 Subject: [PATCH 20/42] ARM: dts: dra7: Add dt node for the syscon control module wkup Create a system control module node for the control module portion that resides under l4_wkup. Signed-off-by: Dave Gerlach Acked-by: Viresh Kumar Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index d8c0dd1024f0..cc4cb76431f6 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -233,6 +233,11 @@ prm_clocks: clocks { prm_clockdomains: clockdomains { }; }; + + scm_wkup: scm_conf@c000 { + compatible = "syscon"; + reg = <0xc000 0x1000>; + }; }; axi@0 { From b82ffb337b69947bf82d936827fe5c6e2ad6abdd Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 18 May 2016 18:36:32 -0500 Subject: [PATCH 21/42] ARM: dts: dra7: Move cpus node to parent dts for dra74x and dra72x Nearly all of the information in the cpus node, especially for cpu0, is the same between dra74x and dra72x so move the common information to the parent dra7.dtsi to avoid duplication of data. Signed-off-by: Dave Gerlach Acked-by: Viresh Kumar Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 27 +++++++++++++++++++++++++++ arch/arm/boot/dts/dra72x.dtsi | 16 ---------------- arch/arm/boot/dts/dra74x.dtsi | 24 ------------------------ 3 files changed, 27 insertions(+), 40 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index cc4cb76431f6..b1e9f5c0fb79 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -73,6 +73,33 @@ wakeupgen: interrupt-controller@48281000 { interrupt-parent = <&gic>; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + + operating-points = < + /* kHz uV */ + 1000000 1060000 + 1176000 1160000 + >; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + + /* cooling options */ + cooling-min-level = <0>; + cooling-max-level = <2>; + #cooling-cells = <2>; /* min followed by max */ + }; + }; + /* * The soc node represents the soc top level view. It is used for IPs * that are not memory mapped in the MPU view or for the MPU itself. diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi index 70a217050a4c..67107605fb4c 100644 --- a/arch/arm/boot/dts/dra72x.dtsi +++ b/arch/arm/boot/dts/dra72x.dtsi @@ -12,22 +12,6 @@ / { compatible = "ti,dra722", "ti,dra72", "ti,dra7"; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - - /* cooling options */ - cooling-min-level = <0>; - cooling-max-level = <2>; - #cooling-cells = <2>; /* min followed by max */ - }; - }; - pmu { compatible = "arm,cortex-a15-pmu"; interrupt-parent = <&wakeupgen>; diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index 4220eeffc65a..0c31db3a8919 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -13,30 +13,6 @@ / { compatible = "ti,dra742", "ti,dra74", "ti,dra7"; cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1176000 1160000 - >; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - - /* cooling options */ - cooling-min-level = <0>; - cooling-max-level = <2>; - #cooling-cells = <2>; /* min followed by max */ - }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; From f80bc97fd0a9711ef11bdb3e63c2c01115a82c47 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 18 May 2016 18:36:33 -0500 Subject: [PATCH 22/42] ARM: dts: dra7: Move to operating-points-v2 table Add an operating-points-v2 table with all OPPs available for all silicon revisions along with necessary data for use by ti-opp driver to selectively enable the appropriate OPPs at runtime and handle voltage transitions As we now need to define voltage ranges for each OPP, we define the minimum and maximum voltage to match the ranges possible for AVS class0 voltage as defined by the DRA7/AM57 Data Manual, with the exception of using a range for OPP_OD based on historical data to ensure that SoCs from older lots still continue to boot, even though more optimal voltages are now the standard. Once an AVS Class0 driver is in place it will be possible for these OPP voltages to be adjusted to any voltage within the provided range. Information from SPRS953, Revised December 2015. Signed-off-by: Dave Gerlach Acked-by: Viresh Kumar Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 26 +++++++++++++++++++++----- arch/arm/boot/dts/dra74x.dtsi | 1 + 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index b1e9f5c0fb79..c3e67eeee8e0 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -82,11 +82,9 @@ cpu0: cpu@0 { compatible = "arm,cortex-a15"; reg = <0>; - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1176000 1160000 - >; + operating-points-v2 = <&cpu0_opp_table>; + ti,syscon-efuse = <&scm_wkup 0x20c 0xf80000 19>; + ti,syscon-rev = <&scm_wkup 0x204>; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; @@ -100,6 +98,24 @@ cpu0: cpu@0 { }; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp_nom@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1060000 850000 1150000>; + opp-supported-hw = <0xFF 0x01>; + opp-suspend; + }; + + opp_od@1176000000 { + opp-hz = /bits/ 64 <1176000000>; + opp-microvolt = <1160000 885000 1160000>; + opp-supported-hw = <0xFF 0x02>; + }; + }; + /* * The soc node represents the soc top level view. It is used for IPs * that are not memory mapped in the MPU view or for the MPU itself. diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index 0c31db3a8919..0a8a5eee5dd0 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -17,6 +17,7 @@ cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; + operating-points-v2 = <&cpu0_opp_table>; }; }; From eaa03e4251196ad9cb70613fb577134814c31f1e Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Thu, 19 May 2016 12:17:30 +0530 Subject: [PATCH 23/42] ARM: dts: am335x-icev2: Add DT node for TI PCA9536 AM335x ICE board has a TI PCA9536 chip connected to I2C0 at address 0x41. Add DT entry for the same. Signed-off-by: Vignesh R Acked-by: Kristofer Martinez Acked-by: Linus Walleij Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-icev2.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts index e271013e78a6..7d8b8fefdf08 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -206,6 +206,13 @@ tpic2810: gpio@60 { gpio-controller; #gpio-cells = <2>; }; + + pca9536: gpio@41 { + compatible = "ti,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + }; }; #include "tps65910.dtsi" From 7172e745d5980ace6e068f6037b834922a3eba64 Mon Sep 17 00:00:00 2001 From: Misael Lopez Cruz Date: Tue, 24 May 2016 15:00:40 -0500 Subject: [PATCH 24/42] ARM: dts: dra72-evm: Rename 3.3V regulator tag Rename the tag of the 3.3 V regulator used in the DRA72 EVM in order to have a consistent tag name with the DRA7 EVM. This is useful when the regulator needs to be referenced in common dtsi files (i.e. for common companion boards like JAMR3 [1]). [1] http://www.ti.com.cn/cn/lit/ug/sprui52/sprui52.pdf Signed-off-by: Misael Lopez Cruz Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra72-evm-common.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index 093538ea5b5f..9d3cf50ca37e 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -18,7 +18,7 @@ aliases { display0 = &hdmi0; }; - evm_3v3: fixedregulator-evm_3v3 { + evm_3v3_sw: fixedregulator-evm_3v3 { compatible = "regulator-fixed"; regulator-name = "evm_3v3"; regulator-min-microvolt = <3300000>; @@ -29,7 +29,7 @@ aic_dvdd: fixedregulator-aic_dvdd { /* TPS77018DBVT */ compatible = "regulator-fixed"; regulator-name = "aic_dvdd"; - vin-supply = <&evm_3v3>; + vin-supply = <&evm_3v3_sw>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; @@ -414,9 +414,9 @@ tlv320aic3106: tlv320aic3106@19 { status = "okay"; /* Regulators */ - AVDD-supply = <&evm_3v3>; - IOVDD-supply = <&evm_3v3>; - DRVDD-supply = <&evm_3v3>; + AVDD-supply = <&evm_3v3_sw>; + IOVDD-supply = <&evm_3v3_sw>; + DRVDD-supply = <&evm_3v3_sw>; DVDD-supply = <&aic_dvdd>; }; }; @@ -597,7 +597,7 @@ &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins_default>; - vmmc-supply = <&evm_3v3>; + vmmc-supply = <&evm_3v3_sw>; bus-width = <8>; ti,non-removable; max-frequency = <192000000>; From a5206553bab2a7d5777e0fdfb5ac8c534a28f15a Mon Sep 17 00:00:00 2001 From: "Robert P. J. Day" Date: Tue, 24 May 2016 17:20:28 -0400 Subject: [PATCH 25/42] ARM: dts: Correct misspelling, "emda3" -> "edma3" Correct misspelling, "emda3" -> "edma3". Reported-by: Adam J Allison Signed-off-by: Robert P. J. Day Acked-by: Rob Herring Acked-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/dma/ti-edma.txt | 4 ++-- arch/arm/boot/dts/am33xx.dtsi | 2 +- arch/arm/boot/dts/am4372.dtsi | 2 +- arch/arm/boot/dts/dm814x.dtsi | 2 +- arch/arm/boot/dts/dra7.dtsi | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt index 079b42a81d7c..18090e7226b4 100644 --- a/Documentation/devicetree/bindings/dma/ti-edma.txt +++ b/Documentation/devicetree/bindings/dma/ti-edma.txt @@ -15,7 +15,7 @@ Required properties: - reg: Memory map of eDMA CC - reg-names: "edma3_cc" - interrupts: Interrupt lines for CCINT, MPERR and CCERRINT. -- interrupt-names: "edma3_ccint", "emda3_mperr" and "edma3_ccerrint" +- interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint" - ti,tptcs: List of TPTCs associated with the eDMA in the following form: <&tptc_phandle TC_priority_number>. The highest priority is 0. @@ -48,7 +48,7 @@ edma: edma@49000000 { reg = <0x49000000 0x10000>; reg-names = "edma3_cc"; interrupts = <12 13 14>; - interrupt-names = "edma3_ccint", "emda3_mperr", "edma3_ccerrint"; + interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint"; dma-requests = <64>; #dma-cells = <2>; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 2625414b805a..af18c4738bef 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -249,7 +249,7 @@ edma: edma@49000000 { reg = <0x49000000 0x10000>; reg-names = "edma3_cc"; interrupts = <12 13 14>; - interrupt-names = "edma3_ccint", "emda3_mperr", + interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint"; dma-requests = <64>; #dma-cells = <2>; diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 5a065b8eb4b6..03514665a5f5 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -238,7 +238,7 @@ edma: edma@49000000 { interrupts = , , ; - interrupt-names = "edma3_ccint", "emda3_mperr", + interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint"; dma-requests = <64>; #dma-cells = <2>; diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index d4537dc61497..a6e0aebc617b 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -448,7 +448,7 @@ edma: edma@49000000 { reg = <0x49000000 0x10000>; reg-names = "edma3_cc"; interrupts = <12 13 14>; - interrupt-names = "edma3_ccint", "emda3_mperr", + interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint"; dma-requests = <64>; #dma-cells = <2>; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index c3e67eeee8e0..5f1e0296b3fd 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -436,7 +436,7 @@ edma: edma@43300000 { interrupts = , , ; - interrupt-names = "edma3_ccint", "emda3_mperr", + interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint"; dma-requests = <64>; #dma-cells = <2>; From 759bc77b9a9ca661ef3edca1554f3edf6c5a5615 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Fri, 27 May 2016 13:17:42 -0500 Subject: [PATCH 26/42] ARM: dts: am437x-idk-evm: Mark MAC as having only one PHY Currently am4372.dtsi declares the MAC controller to have two slave ports, on this board we only use one, so set the slave count to one. This eliminates a console error message when the non-existent PHY is not detected. Signed-off-by: Andrew F. Davis Reviewed-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-idk-evm.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts index 76dcfc6d5f0d..12a69518383e 100644 --- a/arch/arm/boot/dts/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/am437x-idk-evm.dts @@ -382,6 +382,7 @@ partition@6 { }; &mac { + slaves = <1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; From fd4eeada1bf1264f7ff21fb5368ff1d17703af96 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Fri, 27 May 2016 13:17:43 -0500 Subject: [PATCH 27/42] ARM: dts: am335x-bone-common: Mark MAC as having only one PHY Currently am33xx.dtsi declares the MAC controller to have two slave ports, on these boards we only use one, so set the slave count to one. This eliminates a console error message when the non-existent PHY is not detected. Signed-off-by: Andrew F. Davis Reviewed-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-bone-common.dtsi | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 13133f3587b8..6b0609617c30 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -359,12 +359,8 @@ &cpsw_emac0 { phy-mode = "mii"; }; -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "mii"; -}; - &mac { + slaves = <1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; From 138e996c214b83a8bcc730cb9e52584b278f5204 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 30 May 2016 11:23:44 +0300 Subject: [PATCH 28/42] ARM: dts: omap3: Add clocks to McBSP nodes Add clock properties to the McBSP nodes. McBSP2 and 3 need to have ick also since the Sidetone block of these modules are operating using the McBSP interface clock. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 9fbda38528dc..4c3c471d2a83 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -493,6 +493,8 @@ mcbsp1: mcbsp@48074000 { dmas = <&sdma 31>, <&sdma 32>; dma-names = "tx", "rx"; + clocks = <&mcbsp1_fck>; + clock-names = "fck"; status = "disabled"; }; @@ -511,6 +513,8 @@ mcbsp2: mcbsp@49022000 { dmas = <&sdma 33>, <&sdma 34>; dma-names = "tx", "rx"; + clocks = <&mcbsp2_fck>, <&mcbsp2_ick>; + clock-names = "fck", "ick"; status = "disabled"; }; @@ -529,6 +533,8 @@ mcbsp3: mcbsp@49024000 { dmas = <&sdma 17>, <&sdma 18>; dma-names = "tx", "rx"; + clocks = <&mcbsp3_fck>, <&mcbsp3_ick>; + clock-names = "fck", "ick"; status = "disabled"; }; @@ -545,6 +551,8 @@ mcbsp4: mcbsp@49026000 { dmas = <&sdma 19>, <&sdma 20>; dma-names = "tx", "rx"; + clocks = <&mcbsp4_fck>; + clock-names = "fck"; status = "disabled"; }; @@ -561,6 +569,8 @@ mcbsp5: mcbsp@48096000 { dmas = <&sdma 21>, <&sdma 22>; dma-names = "tx", "rx"; + clocks = <&mcbsp5_fck>; + clock-names = "fck"; status = "disabled"; }; From 9e21c75d9265925718e7ae491443825869a2f30e Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 30 May 2016 11:55:14 +0300 Subject: [PATCH 29/42] ARM: dts: omap5-board-common: Add pdmclk binding for audio The twl6040 codec is generating the pdmclk, which is used by the McPDM as functional clock. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-board-common.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index dc759a3028b7..b95b221170e9 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi @@ -594,6 +594,7 @@ palmas_power_button: palmas_power_button { twl6040: twl@4b { compatible = "ti,twl6040"; + #clock-cells = <0>; reg = <0x4b>; pinctrl-names = "default"; @@ -614,6 +615,10 @@ twl6040: twl@4b { &mcpdm { pinctrl-names = "default"; pinctrl-0 = <&mcpdm_pins>; + + clocks = <&twl6040>; + clock-names = "pdmclk"; + status = "okay"; }; From 2ab60a38accebadc2bf531b6c56e12c38b8fa91d Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 30 May 2016 11:55:15 +0300 Subject: [PATCH 30/42] ARM: dts: omap4-panda-common: Add pdmclk binding for audio The twl6040 codec is generating the pdmclk, which is used by the McPDM as functional clock. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-panda-common.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index df2e356ec089..e1d606f64cb7 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -376,6 +376,7 @@ twl: twl@48 { twl6040: twl@4b { compatible = "ti,twl6040"; + #clock-cells = <0>; reg = <0x4b>; pinctrl-names = "default"; @@ -479,6 +480,10 @@ &mcbsp1 { &mcpdm { pinctrl-names = "default"; pinctrl-0 = <&mcpdm_pins>; + + clocks = <&twl6040>; + clock-names = "pdmclk"; + status = "okay"; }; From 3cec531b47fd6b99f9ecaac807ece06369d5aa88 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 30 May 2016 11:55:16 +0300 Subject: [PATCH 31/42] ARM: dts: omap4-sdp: Add pdmclk binding for audio The twl6040 codec is generating the pdmclk, which is used by the McPDM as functional clock. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-sdp.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index aae513265dc2..7e6cd2d8ed5d 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -367,6 +367,7 @@ twl: twl@48 { twl6040: twl@4b { compatible = "ti,twl6040"; + #clock-cells = <0>; reg = <0x4b>; pinctrl-names = "default"; @@ -620,6 +621,10 @@ &dmic { &mcpdm { pinctrl-names = "default"; pinctrl-0 = <&mcpdm_pins>; + + clocks = <&twl6040>; + clock-names = "pdmclk"; + status = "okay"; }; From 26b87e04dedb55801a817dd5fb18609e9207eaf3 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 30 May 2016 11:55:17 +0300 Subject: [PATCH 32/42] ARM: dts: omap4-var-som-om44: Add pdmclk binding for audio The twl6040 codec is generating the pdmclk, which is used by the McPDM as functional clock. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-var-som-om44.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/omap4-var-som-om44.dtsi index a17997f4e9aa..873cfc87260c 100644 --- a/arch/arm/boot/dts/omap4-var-som-om44.dtsi +++ b/arch/arm/boot/dts/omap4-var-som-om44.dtsi @@ -189,6 +189,7 @@ twl: twl@48 { twl6040: twl@4b { compatible = "ti,twl6040"; + #clock-cells = <0>; reg = <0x4b>; pinctrl-names = "default"; @@ -252,6 +253,10 @@ &i2c4 { &mcpdm { pinctrl-names = "default"; pinctrl-0 = <&mcpdm_pins>; + + clocks = <&twl6040>; + clock-names = "pdmclk"; + status = "okay"; }; From d471c277f495a864c7ca9538513e0f701eb82e39 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 30 May 2016 11:55:18 +0300 Subject: [PATCH 33/42] ARM: dts: omap4-duovero: Add pdmclk binding for audio The twl6040 codec is generating the pdmclk, which is used by the McPDM as functional clock. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-duovero.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi index f2a94fa62552..a90b582e4c3f 100644 --- a/arch/arm/boot/dts/omap4-duovero.dtsi +++ b/arch/arm/boot/dts/omap4-duovero.dtsi @@ -177,6 +177,7 @@ twl: twl@48 { twl6040: twl@4b { compatible = "ti,twl6040"; + #clock-cells = <0>; reg = <0x4b>; interrupts = ; /* IRQ_SYS_2N cascaded to gic */ ti,audpwron-gpio = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* gpio_160 */ @@ -207,6 +208,10 @@ &mcbsp1 { &mcpdm { pinctrl-names = "default"; pinctrl-0 = <&mcpdm_pins>; + + clocks = <&twl6040>; + clock-names = "pdmclk"; + status = "okay"; }; From 4393dd4ecaa729204d2c7eebb970b1412af195ec Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Sat, 4 Jun 2016 14:05:55 +0200 Subject: [PATCH 34/42] ARM: dts: omap3-gta04: Add RFID eeprom node Define RFID eeprom node which is present on gta04 device. Signed-off-by: H. Nikolaus Schaller Signed-off-by: Marek Belisko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-gta04.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 634925770998..3eb53bc493dd 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -415,6 +415,12 @@ tsc2007@48 { gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; ti,x-plate-ohms = <600>; }; + + /* RFID EEPROM */ + m24lr64@50 { + compatible = "at,24c64"; + reg = <0x50>; + }; }; &i2c3 { From 605b3d302dc6cdeeed95fb9294b7a010b562b1fb Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 9 Jun 2016 20:43:55 +0530 Subject: [PATCH 35/42] ARM: dts: DRA7: fix unit address of second PCIe instance The unit address of the second PCIe instance is set to be same as that of the first instance (copy-paste error). Fix it. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 5f1e0296b3fd..3c34a0c3ff7a 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -324,7 +324,7 @@ axi@1 { ranges = <0x51800000 0x51800000 0x3000 0x0 0x30000000 0x10000000>; status = "disabled"; - pcie@51000000 { + pcie@51800000 { compatible = "ti,dra7-pcie"; reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; reg-names = "rc_dbics", "ti_conf", "config"; From f03a881a8a8de26b09949b89d6a7177afbc5754d Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 17 Jun 2016 13:10:10 +0200 Subject: [PATCH 36/42] ARM: dts: am335x-bone-common: use stdout-path in Beaglebone boards. This commit adds the stdout-path propety in /chosen for all Beaglebone boards. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-bone-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 6b0609617c30..e247c15e5176 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -18,6 +18,10 @@ memory { reg = <0x80000000 0x10000000>; /* 256 MB */ }; + chosen { + stdout-path = &uart0; + }; + leds { pinctrl-names = "default"; pinctrl-0 = <&user_leds_s0>; From bac9d0b847a18ff9a0bb77711a8ad1db7400a948 Mon Sep 17 00:00:00 2001 From: Joel Fernandes Date: Wed, 1 Jun 2016 12:06:41 +0300 Subject: [PATCH 37/42] ARM: dts: DRA7: Add DT node for DES IP DRA7xx SoCs have a DES3DES IP. Add DT data for the same. Signed-off-by: Joel Fernandes Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 3c34a0c3ff7a..f5a83c4d133e 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1928,6 +1928,17 @@ ecap2: ecap@48442100 { status = "disabled"; }; }; + + des: des@480a5000 { + compatible = "ti,omap4-des"; + ti,hwmods = "des"; + reg = <0x480a5000 0xa0>; + interrupts = ; + dmas = <&sdma_xbar 117>, <&sdma_xbar 116>; + dma-names = "tx", "rx"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; }; thermal_zones: thermal-zones { From e7fd15c1d0580e1c5b35f808d064e5460bdaa7fc Mon Sep 17 00:00:00 2001 From: Joel Fernandes Date: Wed, 1 Jun 2016 12:06:42 +0300 Subject: [PATCH 38/42] ARM: dts: DRA7: Add DT nodes for AES IP DRA7 SoC has the same AES IP as OMAP4. Add DT entries for both AES cores. Signed-off-by: Joel Fernandes Signed-off-by: Lokesh Vutla [t-kristo@ti.com: squashed in the change to use EDMA, squashed in support for two AES cores] Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index f5a83c4d133e..18090963999b 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1929,6 +1929,28 @@ ecap2: ecap@48442100 { }; }; + aes1: aes@4b500000 { + compatible = "ti,omap4-aes"; + ti,hwmods = "aes1"; + reg = <0x4b500000 0xa0>; + interrupts = ; + dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; + dma-names = "tx", "rx"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; + + aes2: aes@4b700000 { + compatible = "ti,omap4-aes"; + ti,hwmods = "aes2"; + reg = <0x4b700000 0xa0>; + interrupts = ; + dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; + dma-names = "tx", "rx"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; + des: des@480a5000 { compatible = "ti,omap4-des"; ti,hwmods = "des"; From da34609df5bc4cfac28154970d9191fbcac17fab Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Wed, 1 Jun 2016 12:06:43 +0300 Subject: [PATCH 39/42] ARM: dts: DRA7: Add support for SHA IP DRA7 SoC has the same SHA IP as OMAP5. Add DT entry for the same. Signed-off-by: Lokesh Vutla [t-kristo@ti.com: changed SHA to use EDMA instead of SDMA] Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 18090963999b..b603e92634c0 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1961,6 +1961,17 @@ des: des@480a5000 { clocks = <&l3_iclk_div>; clock-names = "fck"; }; + + sham: sham@53100000 { + compatible = "ti,omap5-sham"; + ti,hwmods = "sham"; + reg = <0x4b101000 0x300>; + interrupts = ; + dmas = <&edma_xbar 119 0>; + dma-names = "rx"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; }; thermal_zones: thermal-zones { From 610e9c4aec6acdb44230e9bd96d12393650333ff Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Wed, 1 Jun 2016 12:06:44 +0300 Subject: [PATCH 40/42] ARM: dts: DRA7: Add DT node for RNG IP Adding dt node for hardware random number generator IP. Signed-off-by: Lokesh Vutla Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index b603e92634c0..60680a1b4f1d 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1972,6 +1972,15 @@ sham: sham@53100000 { clocks = <&l3_iclk_div>; clock-names = "fck"; }; + + rng: rng@48090000 { + compatible = "ti,omap4-rng"; + ti,hwmods = "rng"; + reg = <0x48090000 0x2000>; + interrupts = ; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; }; thermal_zones: thermal-zones { From 8ed607a7490172733936a50a2231509dbde4f3b9 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Wed, 1 Jun 2016 12:06:45 +0300 Subject: [PATCH 41/42] ARM: dts: AM43xx: clk: Add RNG clk node Add clk node for RNG module. Signed-off-by: Lokesh Vutla Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am43xx-clocks.dtsi | 8 ++++++++ drivers/clk/ti/clk-43xx.c | 1 + 2 files changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index 7630ba1d89e4..d1d73b725f47 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -104,6 +104,14 @@ aes0_fck: aes0_fck { clock-div = <1>; }; + rng_fck: rng_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + ehrpwm0_tbclk: ehrpwm0_tbclk@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c index 097fc90bf19a..3f157a40bbd1 100644 --- a/drivers/clk/ti/clk-43xx.c +++ b/drivers/clk/ti/clk-43xx.c @@ -58,6 +58,7 @@ static struct ti_dt_clk am43xx_clks[] = { DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"), DT_CLK(NULL, "sha0_fck", "sha0_fck"), DT_CLK(NULL, "aes0_fck", "aes0_fck"), + DT_CLK(NULL, "rng_fck", "rng_fck"), DT_CLK(NULL, "timer1_fck", "timer1_fck"), DT_CLK(NULL, "timer2_fck", "timer2_fck"), DT_CLK(NULL, "timer3_fck", "timer3_fck"), From 52c7c91319e469142628199548852198bcc3150f Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Wed, 1 Jun 2016 12:06:46 +0300 Subject: [PATCH 42/42] ARM: dts: AM43xx: Add node for RNG Adding DT node for hardware random number generator. Signed-off-by: Lokesh Vutla Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 03514665a5f5..e7b53ef923a1 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -909,6 +909,13 @@ des: des@53701000 { dma-names = "tx", "rx"; }; + rng: rng@48310000 { + compatible = "ti,omap4-rng"; + ti,hwmods = "rng"; + reg = <0x48310000 0x2000>; + interrupts = ; + }; + mcasp0: mcasp@48038000 { compatible = "ti,am33xx-mcasp-audio"; ti,hwmods = "mcasp0";