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perf vendor events intel: Update sapphirerapids events from 1.36 to 1.39

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The updated events and metrics were published in:

  0718b78555
  42fe96774f

Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andreas Färber <afaerber@suse.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Falcon <thomas.falcon@intel.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ian Rogers 2026-05-28 21:51:53 -07:00 committed by Arnaldo Carvalho de Melo
parent 4aa006c38d
commit ab85585e38
2 changed files with 28 additions and 1 deletions
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2
tools/perf/pmu-events/arch/x86/mapfile.csv
View File

@ -29,7 +29,7 @@ GenuineIntel-6-2E,v4,nehalemex,core
GenuineIntel-6-(CC|D5),v1.05,pantherlake,core
GenuineIntel-6-A7,v1.04,rocketlake,core
GenuineIntel-6-2A,v19,sandybridge,core
GenuineIntel-6-8F,v1.36,sapphirerapids,core
GenuineIntel-6-8F,v1.39,sapphirerapids,core
GenuineIntel-6-AF,v1.15,sierraforest,core
GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core
GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v59,skylake,core

1 Family-model Version Filename EventType
29 GenuineIntel-6-(CC|D5) v1.05 pantherlake core
30 GenuineIntel-6-A7 v1.04 rocketlake core
31 GenuineIntel-6-2A v19 sandybridge core
32 GenuineIntel-6-8F v1.36 v1.39 sapphirerapids core
33 GenuineIntel-6-AF v1.15 sierraforest core
34 GenuineIntel-6-(37|4A|4C|4D|5A) v15 silvermont core
35 GenuineIntel-6-(4E|5E|8E|9E|A5|A6) v59 skylake core

27
tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json
View File

@ -181,6 +181,15 @@
"SampleAfterValue": "200003",
"UMask": "0xff"
},
{
"BriefDescription": "All requests that hit L2 cache [This event is alias to L2_RQSTS.HIT]",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_REQUEST.HIT",
"PublicDescription": "Counts all requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]",
"SampleAfterValue": "200003",
"UMask": "0xdf"
},
{
"BriefDescription": "Read requests with true-miss in L2 cache. [This event is alias to L2_RQSTS.MISS]",
"Counter": "0,1,2,3",
@ -279,6 +288,15 @@
"SampleAfterValue": "200003",
"UMask": "0x21"
},
{
"BriefDescription": "All requests that hit L2 cache [This event is alias to L2_REQUEST.HIT]",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.HIT",
"PublicDescription": "Counts all requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT]",
"SampleAfterValue": "200003",
"UMask": "0xdf"
},
{
"BriefDescription": "L2_RQSTS.HWPF_MISS",
"Counter": "0,1,2,3",
@ -350,6 +368,15 @@
"SampleAfterValue": "200003",
"UMask": "0x40"
},
{
"BriefDescription": "Cycles when L1D is locked",
"Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
"PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
"Counter": "0,1,2,3,4,5,6,7",